[people/ms/u-boot.git] / drivers / mmc / sunxi_mmc.c

/*
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Aaron <leafy.myeh@allwinnertech.com>
 *
 * MMC driver for allwinner sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm-generic/gpio.h>

struct sunxi_mmc_host {
	unsigned mmc_no;
	uint32_t *mclkreg;
	unsigned fatal_err;
	struct sunxi_mmc *reg;
	struct mmc_config cfg;
};

/* support 4 mmc hosts */
struct sunxi_mmc_host mmc_host[4];

static int sunxi_mmc_getcd_gpio(int sdc_no)
{
	switch (sdc_no) {
	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
	}
	return -EINVAL;
}

static int mmc_resource_init(int sdc_no)
{
	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	int cd_pin, ret = 0;

	debug("init mmc %d resource\n", sdc_no);

	switch (sdc_no) {
	case 0:
		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
		mmchost->mclkreg = &ccm->sd0_clk_cfg;
		break;
	case 1:
		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
		mmchost->mclkreg = &ccm->sd1_clk_cfg;
		break;
	case 2:
		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
		mmchost->mclkreg = &ccm->sd2_clk_cfg;
		break;
	case 3:
		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
		mmchost->mclkreg = &ccm->sd3_clk_cfg;
		break;
	default:
		printf("Wrong mmc number %d\n", sdc_no);
		return -1;
	}
	mmchost->mmc_no = sdc_no;

	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
	if (cd_pin >= 0) {
		ret = gpio_request(cd_pin, "mmc_cd");
		if (!ret) {
			sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
			ret = gpio_direction_input(cd_pin);
		}
	}

	return ret;
}

static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
{
	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;

	if (hz <= 24000000) {
		pll = CCM_MMC_CTRL_OSCM24;
		pll_hz = 24000000;
	} else {
#ifdef CONFIG_MACH_SUN9I
		pll = CCM_MMC_CTRL_PLL_PERIPH0;
		pll_hz = clock_get_pll4_periph0();
#else
		pll = CCM_MMC_CTRL_PLL6;
		pll_hz = clock_get_pll6();
#endif
	}

	div = pll_hz / hz;
	if (pll_hz % hz)
		div++;

	n = 0;
	while (div > 16) {
		n++;
		div = (div + 1) / 2;
	}

	if (n > 3) {
		printf("mmc %u error cannot set clock to %u\n",
		       mmchost->mmc_no, hz);
		return -1;
	}

	/* determine delays */
	if (hz <= 400000) {
		oclk_dly = 0;
		sclk_dly = 0;
	} else if (hz <= 25000000) {
		oclk_dly = 0;
		sclk_dly = 5;
#ifdef CONFIG_MACH_SUN9I
	} else if (hz <= 50000000) {
		oclk_dly = 5;
		sclk_dly = 4;
	} else {
		/* hz > 50000000 */
		oclk_dly = 2;
		sclk_dly = 4;
#else
	} else if (hz <= 50000000) {
		oclk_dly = 3;
		sclk_dly = 4;
	} else {
		/* hz > 50000000 */
		oclk_dly = 1;
		sclk_dly = 4;
#endif
	}

	writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
	       CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
	       CCM_MMC_CTRL_M(div), mmchost->mclkreg);

	debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
	      mmchost->mmc_no, hz, pll_hz, 1u << n, div,
	      pll_hz / (1u << n) / div);

	return 0;
}

static int mmc_clk_io_on(int sdc_no)
{
	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	debug("init mmc %d clock and io\n", sdc_no);

	/* config ahb clock */
	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));

#ifdef CONFIG_SUNXI_GEN_SUN6I
	/* unassert reset */
	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
#endif
#if defined(CONFIG_MACH_SUN9I)
	/* sun9i has a mmc-common module, also set the gate and reset there */
	writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
	       SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
#endif

	return mmc_set_mod_clk(mmchost, 24000000);
}

static int mmc_update_clk(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	unsigned int cmd;
	unsigned timeout_msecs = 2000;

	cmd = SUNXI_MMC_CMD_START |
	      SUNXI_MMC_CMD_UPCLK_ONLY |
	      SUNXI_MMC_CMD_WAIT_PRE_OVER;
	writel(cmd, &mmchost->reg->cmd);
	while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
		if (!timeout_msecs--)
			return -1;
		udelay(1000);
	}

	/* clock update sets various irq status bits, clear these */
	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);

	return 0;
}

static int mmc_config_clock(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	unsigned rval = readl(&mmchost->reg->clkcr);

	/* Disable Clock */
	rval &= ~SUNXI_MMC_CLK_ENABLE;
	writel(rval, &mmchost->reg->clkcr);
	if (mmc_update_clk(mmc))
		return -1;

	/* Set mod_clk to new rate */
	if (mmc_set_mod_clk(mmchost, mmc->clock))
		return -1;

	/* Clear internal divider */
	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
	writel(rval, &mmchost->reg->clkcr);

	/* Re-enable Clock */
	rval |= SUNXI_MMC_CLK_ENABLE;
	writel(rval, &mmchost->reg->clkcr);
	if (mmc_update_clk(mmc))
		return -1;

	return 0;
}

static void sunxi_mmc_set_ios(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;

	debug("set ios: bus_width: %x, clock: %d\n",
	      mmc->bus_width, mmc->clock);

	/* Change clock first */
	if (mmc->clock && mmc_config_clock(mmc) != 0) {
		mmchost->fatal_err = 1;
		return;
	}

	/* Change bus width */
	if (mmc->bus_width == 8)
		writel(0x2, &mmchost->reg->width);
	else if (mmc->bus_width == 4)
		writel(0x1, &mmchost->reg->width);
	else
		writel(0x0, &mmchost->reg->width);
}

static int sunxi_mmc_core_init(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;

	/* Reset controller */
	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
	udelay(1000);

	return 0;
}

static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	const int reading = !!(data->flags & MMC_DATA_READ);
	const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
					      SUNXI_MMC_STATUS_FIFO_FULL;
	unsigned i;
	unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
	unsigned byte_cnt = data->blocksize * data->blocks;
	unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
	if (timeout_usecs < 2000000)
		timeout_usecs = 2000000;

	/* Always read / write data through the CPU */
	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);

	for (i = 0; i < (byte_cnt >> 2); i++) {
		while (readl(&mmchost->reg->status) & status_bit) {
			if (!timeout_usecs--)
				return -1;
			udelay(1);
		}

		if (reading)
			buff[i] = readl(&mmchost->reg->fifo);
		else
			writel(buff[i], &mmchost->reg->fifo);
	}

	return 0;
}

static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
			 unsigned int done_bit, const char *what)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	unsigned int status;

	do {
		status = readl(&mmchost->reg->rint);
		if (!timeout_msecs-- ||
		    (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
			debug("%s timeout %x\n", what,
			      status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
			return TIMEOUT;
		}
		udelay(1000);
	} while (!(status & done_bit));

	return 0;
}

static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	unsigned int cmdval = SUNXI_MMC_CMD_START;
	unsigned int timeout_msecs;
	int error = 0;
	unsigned int status = 0;
	unsigned int bytecnt = 0;

	if (mmchost->fatal_err)
		return -1;
	if (cmd->resp_type & MMC_RSP_BUSY)
		debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
	if (cmd->cmdidx == 12)
		return 0;

	if (!cmd->cmdidx)
		cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
	if (cmd->resp_type & MMC_RSP_PRESENT)
		cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
	if (cmd->resp_type & MMC_RSP_136)
		cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
	if (cmd->resp_type & MMC_RSP_CRC)
		cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;

	if (data) {
		if ((u32)(long)data->dest & 0x3) {
			error = -1;
			goto out;
		}

		cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
		if (data->flags & MMC_DATA_WRITE)
			cmdval |= SUNXI_MMC_CMD_WRITE;
		if (data->blocks > 1)
			cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
		writel(data->blocksize, &mmchost->reg->blksz);
		writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
	}

	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
	      cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
	writel(cmd->cmdarg, &mmchost->reg->arg);

	if (!data)
		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);

	/*
	 * transfer data and check status
	 * STATREG[2] : FIFO empty
	 * STATREG[3] : FIFO full
	 */
	if (data) {
		int ret = 0;

		bytecnt = data->blocksize * data->blocks;
		debug("trans data %d bytes\n", bytecnt);
		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
		ret = mmc_trans_data_by_cpu(mmc, data);
		if (ret) {
			error = readl(&mmchost->reg->rint) & \
				SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
			error = TIMEOUT;
			goto out;
		}
	}

	error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
	if (error)
		goto out;

	if (data) {
		timeout_msecs = 120;
		debug("cacl timeout %x msec\n", timeout_msecs);
		error = mmc_rint_wait(mmc, timeout_msecs,
				      data->blocks > 1 ?
				      SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
				      SUNXI_MMC_RINT_DATA_OVER,
				      "data");
		if (error)
			goto out;
	}

	if (cmd->resp_type & MMC_RSP_BUSY) {
		timeout_msecs = 2000;
		do {
			status = readl(&mmchost->reg->status);
			if (!timeout_msecs--) {
				debug("busy timeout\n");
				error = TIMEOUT;
				goto out;
			}
			udelay(1000);
		} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
	}

	if (cmd->resp_type & MMC_RSP_136) {
		cmd->response[0] = readl(&mmchost->reg->resp3);
		cmd->response[1] = readl(&mmchost->reg->resp2);
		cmd->response[2] = readl(&mmchost->reg->resp1);
		cmd->response[3] = readl(&mmchost->reg->resp0);
		debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
		      cmd->response[3], cmd->response[2],
		      cmd->response[1], cmd->response[0]);
	} else {
		cmd->response[0] = readl(&mmchost->reg->resp0);
		debug("mmc resp 0x%08x\n", cmd->response[0]);
	}
out:
	if (error < 0) {
		writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
		mmc_update_clk(mmc);
	}
	writel(0xffffffff, &mmchost->reg->rint);
	writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
	       &mmchost->reg->gctrl);

	return error;
}

static int sunxi_mmc_getcd(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	int cd_pin;

	cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
	if (cd_pin < 0)
		return 1;

	return !gpio_get_value(cd_pin);
}

static const struct mmc_ops sunxi_mmc_ops = {
	.send_cmd	= sunxi_mmc_send_cmd,
	.set_ios	= sunxi_mmc_set_ios,
	.init		= sunxi_mmc_core_init,
	.getcd		= sunxi_mmc_getcd,
};

struct mmc *sunxi_mmc_init(int sdc_no)
{
	struct mmc_config *cfg = &mmc_host[sdc_no].cfg;

	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));

	cfg->name = "SUNXI SD/MMC";
	cfg->ops  = &sunxi_mmc_ops;

	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
	cfg->host_caps = MMC_MODE_4BIT;
#ifdef CONFIG_MACH_SUN50I
	if (sdc_no == 2)
		cfg->host_caps = MMC_MODE_8BIT;
#endif
	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	cfg->f_min = 400000;
	cfg->f_max = 52000000;

	if (mmc_resource_init(sdc_no) != 0)
		return NULL;

	mmc_clk_io_on(sdc_no);

	return mmc_create(cfg, &mmc_host[sdc_no]);
}
Commit	Line	Data
e24ea55c IC	1	/*
	2	* (C) Copyright 2007-2011
	3	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	4	* Aaron <leafy.myeh@allwinnertech.com>
	5	*
	6	* MMC driver for allwinner sunxi platform.
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
90641f82	12	#include <errno.h>
e24ea55c IC	13	#include <malloc.h>
	14	#include <mmc.h>
	15	#include <asm/io.h>
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/cpu.h>
cd82113a	18	#include <asm/arch/gpio.h>
e24ea55c	19	#include <asm/arch/mmc.h>
cd82113a	20	#include <asm-generic/gpio.h>
e24ea55c	21
e24ea55c IC	22	struct sunxi_mmc_host {
	23	unsigned mmc_no;
	24	uint32_t *mclkreg;
e24ea55c	25	unsigned fatal_err;
e24ea55c IC	26	struct sunxi_mmc *reg;
	27	struct mmc_config cfg;
	28	};
	29
	30	/* support 4 mmc hosts */
	31	struct sunxi_mmc_host mmc_host[4];
	32
967325fe HG	33	static int sunxi_mmc_getcd_gpio(int sdc_no)
	34	{
	35	switch (sdc_no) {
	36	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
	37	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
	38	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
	39	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
	40	}
90641f82	41	return -EINVAL;
967325fe HG	42	}
967325fe HG	43
e24ea55c IC	44	static int mmc_resource_init(int sdc_no)
	45	{
	46	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
	47	struct sunxi_ccm_reg ccm = (struct sunxi_ccm_reg )SUNXI_CCM_BASE;
967325fe	48	int cd_pin, ret = 0;
e24ea55c IC	49
	50	debug("init mmc %d resource\n", sdc_no);
	51
	52	switch (sdc_no) {
	53	case 0:
	54	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
	55	mmchost->mclkreg = &ccm->sd0_clk_cfg;
	56	break;
	57	case 1:
	58	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
	59	mmchost->mclkreg = &ccm->sd1_clk_cfg;
	60	break;
	61	case 2:
	62	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
	63	mmchost->mclkreg = &ccm->sd2_clk_cfg;
	64	break;
	65	case 3:
	66	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
	67	mmchost->mclkreg = &ccm->sd3_clk_cfg;
	68	break;
	69	default:
	70	printf("Wrong mmc number %d\n", sdc_no);
	71	return -1;
	72	}
e24ea55c IC	73	mmchost->mmc_no = sdc_no;
e24ea55c IC	74
967325fe	75	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
90641f82	76	if (cd_pin >= 0) {
967325fe	77	ret = gpio_request(cd_pin, "mmc_cd");
1c09fa38 HG	78	if (!ret) {
1c09fa38 HG	79	sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
b0c4ae1a	80	ret = gpio_direction_input(cd_pin);
1c09fa38	81	}
b0c4ae1a	82	}
967325fe HG	83
967325fe HG	84	return ret;
e24ea55c IC	85	}
e24ea55c IC	86
fc3a8325 HG	87	static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
	88	{
	89	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
	90
	91	if (hz <= 24000000) {
	92	pll = CCM_MMC_CTRL_OSCM24;
	93	pll_hz = 24000000;
	94	} else {
daf22636 HG	95	#ifdef CONFIG_MACH_SUN9I
	96	pll = CCM_MMC_CTRL_PLL_PERIPH0;
	97	pll_hz = clock_get_pll4_periph0();
	98	#else
fc3a8325 HG	99	pll = CCM_MMC_CTRL_PLL6;
fc3a8325 HG	100	pll_hz = clock_get_pll6();
daf22636	101	#endif
fc3a8325 HG	102	}
	103
	104	div = pll_hz / hz;
	105	if (pll_hz % hz)
	106	div++;
	107
	108	n = 0;
	109	while (div > 16) {
	110	n++;
	111	div = (div + 1) / 2;
	112	}
	113
	114	if (n > 3) {
	115	printf("mmc %u error cannot set clock to %u\n",
	116	mmchost->mmc_no, hz);
	117	return -1;
	118	}
	119
	120	/* determine delays */
	121	if (hz <= 400000) {
	122	oclk_dly = 0;
be90974c	123	sclk_dly = 0;
fc3a8325 HG	124	} else if (hz <= 25000000) {
	125	oclk_dly = 0;
	126	sclk_dly = 5;
be90974c	127	#ifdef CONFIG_MACH_SUN9I
fc3a8325	128	} else if (hz <= 50000000) {
be90974c HG	129	oclk_dly = 5;
be90974c HG	130	sclk_dly = 4;
fc3a8325 HG	131	} else {
	132	/* hz > 50000000 */
	133	oclk_dly = 2;
	134	sclk_dly = 4;
be90974c HG	135	#else
	136	} else if (hz <= 50000000) {
	137	oclk_dly = 3;
	138	sclk_dly = 4;
	139	} else {
	140	/* hz > 50000000 */
	141	oclk_dly = 1;
	142	sclk_dly = 4;
	143	#endif
fc3a8325 HG	144	}
	145
	146	writel(CCM_MMC_CTRL_ENABLE \| pll \| CCM_MMC_CTRL_SCLK_DLY(sclk_dly) \|
	147	CCM_MMC_CTRL_N(n) \| CCM_MMC_CTRL_OCLK_DLY(oclk_dly) \|
	148	CCM_MMC_CTRL_M(div), mmchost->mclkreg);
	149
	150	debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
	151	mmchost->mmc_no, hz, pll_hz, 1u << n, div,
	152	pll_hz / (1u << n) / div);
	153
	154	return 0;
	155	}
	156
e24ea55c IC	157	static int mmc_clk_io_on(int sdc_no)
e24ea55c IC	158	{
e24ea55c IC	159	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
	160	struct sunxi_ccm_reg ccm = (struct sunxi_ccm_reg )SUNXI_CCM_BASE;
	161
	162	debug("init mmc %d clock and io\n", sdc_no);
	163
	164	/* config ahb clock */
	165	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
	166
44d8ae5b	167	#ifdef CONFIG_SUNXI_GEN_SUN6I
1d1bd42e HG	168	/* unassert reset */
	169	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
	170	#endif
daf22636 HG	171	#if defined(CONFIG_MACH_SUN9I)
	172	/* sun9i has a mmc-common module, also set the gate and reset there */
	173	writel(SUNXI_MMC_COMMON_CLK_GATE \| SUNXI_MMC_COMMON_RESET,
	174	SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
	175	#endif
1d1bd42e	176
fc3a8325	177	return mmc_set_mod_clk(mmchost, 24000000);
e24ea55c IC	178	}
	179
	180	static int mmc_update_clk(struct mmc *mmc)
	181	{
	182	struct sunxi_mmc_host *mmchost = mmc->priv;
	183	unsigned int cmd;
	184	unsigned timeout_msecs = 2000;
	185
	186	cmd = SUNXI_MMC_CMD_START \|
	187	SUNXI_MMC_CMD_UPCLK_ONLY \|
	188	SUNXI_MMC_CMD_WAIT_PRE_OVER;
	189	writel(cmd, &mmchost->reg->cmd);
	190	while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
	191	if (!timeout_msecs--)
	192	return -1;
	193	udelay(1000);
	194	}
	195
	196	/* clock update sets various irq status bits, clear these */
	197	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
	198
	199	return 0;
	200	}
	201
fc3a8325	202	static int mmc_config_clock(struct mmc *mmc)
e24ea55c IC	203	{
	204	struct sunxi_mmc_host *mmchost = mmc->priv;
	205	unsigned rval = readl(&mmchost->reg->clkcr);
	206
	207	/* Disable Clock */
	208	rval &= ~SUNXI_MMC_CLK_ENABLE;
	209	writel(rval, &mmchost->reg->clkcr);
	210	if (mmc_update_clk(mmc))
	211	return -1;
	212
fc3a8325 HG	213	/* Set mod_clk to new rate */
	214	if (mmc_set_mod_clk(mmchost, mmc->clock))
	215	return -1;
	216
	217	/* Clear internal divider */
e24ea55c	218	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
e24ea55c	219	writel(rval, &mmchost->reg->clkcr);
fc3a8325	220
e24ea55c IC	221	/* Re-enable Clock */
	222	rval \|= SUNXI_MMC_CLK_ENABLE;
	223	writel(rval, &mmchost->reg->clkcr);
e24ea55c IC	224	if (mmc_update_clk(mmc))
	225	return -1;
	226
	227	return 0;
	228	}
	229
5abdb156	230	static void sunxi_mmc_set_ios(struct mmc *mmc)
e24ea55c IC	231	{
e24ea55c IC	232	struct sunxi_mmc_host *mmchost = mmc->priv;
e24ea55c	233
fc3a8325 HG	234	debug("set ios: bus_width: %x, clock: %d\n",
fc3a8325 HG	235	mmc->bus_width, mmc->clock);
e24ea55c IC	236
e24ea55c IC	237	/* Change clock first */
fc3a8325 HG	238	if (mmc->clock && mmc_config_clock(mmc) != 0) {
	239	mmchost->fatal_err = 1;
	240	return;
e24ea55c IC	241	}
	242
	243	/* Change bus width */
	244	if (mmc->bus_width == 8)
	245	writel(0x2, &mmchost->reg->width);
	246	else if (mmc->bus_width == 4)
	247	writel(0x1, &mmchost->reg->width);
	248	else
	249	writel(0x0, &mmchost->reg->width);
	250	}
	251
5abdb156	252	static int sunxi_mmc_core_init(struct mmc *mmc)
e24ea55c IC	253	{
	254	struct sunxi_mmc_host *mmchost = mmc->priv;
	255
	256	/* Reset controller */
	257	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
b6ae6765	258	udelay(1000);
e24ea55c IC	259
	260	return 0;
	261	}
	262
	263	static int mmc_trans_data_by_cpu(struct mmc mmc, struct mmc_data data)
	264	{
	265	struct sunxi_mmc_host *mmchost = mmc->priv;
	266	const int reading = !!(data->flags & MMC_DATA_READ);
	267	const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
	268	SUNXI_MMC_STATUS_FIFO_FULL;
	269	unsigned i;
e24ea55c	270	unsigned buff = (unsigned int )(reading ? data->dest : data->src);
28f69b9a	271	unsigned byte_cnt = data->blocksize * data->blocks;
26c0c157 TD	272	unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
	273	if (timeout_usecs < 2000000)
	274	timeout_usecs = 2000000;
e24ea55c	275
b6ae6765 HG	276	/* Always read / write data through the CPU */
	277	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
	278
e24ea55c IC	279	for (i = 0; i < (byte_cnt >> 2); i++) {
e24ea55c IC	280	while (readl(&mmchost->reg->status) & status_bit) {
26c0c157	281	if (!timeout_usecs--)
e24ea55c	282	return -1;
26c0c157	283	udelay(1);
e24ea55c IC	284	}
	285
	286	if (reading)
1d1bd42e	287	buff[i] = readl(&mmchost->reg->fifo);
e24ea55c	288	else
1d1bd42e	289	writel(buff[i], &mmchost->reg->fifo);
e24ea55c IC	290	}
	291
	292	return 0;
	293	}
	294
e24ea55c IC	295	static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
	296	unsigned int done_bit, const char *what)
	297	{
	298	struct sunxi_mmc_host *mmchost = mmc->priv;
	299	unsigned int status;
	300
	301	do {
	302	status = readl(&mmchost->reg->rint);
	303	if (!timeout_msecs-- \|\|
	304	(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
	305	debug("%s timeout %x\n", what,
	306	status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
	307	return TIMEOUT;
	308	}
	309	udelay(1000);
	310	} while (!(status & done_bit));
	311
	312	return 0;
	313	}
	314
5abdb156 SS	315	static int sunxi_mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
5abdb156 SS	316	struct mmc_data *data)
e24ea55c IC	317	{
	318	struct sunxi_mmc_host *mmchost = mmc->priv;
	319	unsigned int cmdval = SUNXI_MMC_CMD_START;
	320	unsigned int timeout_msecs;
	321	int error = 0;
	322	unsigned int status = 0;
e24ea55c IC	323	unsigned int bytecnt = 0;
	324
	325	if (mmchost->fatal_err)
	326	return -1;
	327	if (cmd->resp_type & MMC_RSP_BUSY)
	328	debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
	329	if (cmd->cmdidx == 12)
	330	return 0;
	331
	332	if (!cmd->cmdidx)
	333	cmdval \|= SUNXI_MMC_CMD_SEND_INIT_SEQ;
	334	if (cmd->resp_type & MMC_RSP_PRESENT)
	335	cmdval \|= SUNXI_MMC_CMD_RESP_EXPIRE;
	336	if (cmd->resp_type & MMC_RSP_136)
	337	cmdval \|= SUNXI_MMC_CMD_LONG_RESPONSE;
	338	if (cmd->resp_type & MMC_RSP_CRC)
	339	cmdval \|= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
	340
	341	if (data) {
0ea5a04f	342	if ((u32)(long)data->dest & 0x3) {
e24ea55c IC	343	error = -1;
	344	goto out;
	345	}
	346
	347	cmdval \|= SUNXI_MMC_CMD_DATA_EXPIRE\|SUNXI_MMC_CMD_WAIT_PRE_OVER;
	348	if (data->flags & MMC_DATA_WRITE)
	349	cmdval \|= SUNXI_MMC_CMD_WRITE;
	350	if (data->blocks > 1)
	351	cmdval \|= SUNXI_MMC_CMD_AUTO_STOP;
	352	writel(data->blocksize, &mmchost->reg->blksz);
	353	writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
	354	}
	355
	356	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
	357	cmd->cmdidx, cmdval \| cmd->cmdidx, cmd->cmdarg);
	358	writel(cmd->cmdarg, &mmchost->reg->arg);
	359
	360	if (!data)
	361	writel(cmdval \| cmd->cmdidx, &mmchost->reg->cmd);
	362
	363	/*
	364	* transfer data and check status
	365	* STATREG[2] : FIFO empty
	366	* STATREG[3] : FIFO full
	367	*/
	368	if (data) {
	369	int ret = 0;
	370
	371	bytecnt = data->blocksize * data->blocks;
	372	debug("trans data %d bytes\n", bytecnt);
b6ae6765 HG	373	writel(cmdval \| cmd->cmdidx, &mmchost->reg->cmd);
b6ae6765 HG	374	ret = mmc_trans_data_by_cpu(mmc, data);
e24ea55c IC	375	if (ret) {
	376	error = readl(&mmchost->reg->rint) & \
	377	SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
	378	error = TIMEOUT;
	379	goto out;
	380	}
	381	}
	382
5b8d7fb4	383	error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
e24ea55c IC	384	if (error)
	385	goto out;
	386
	387	if (data) {
b6ae6765	388	timeout_msecs = 120;
e24ea55c IC	389	debug("cacl timeout %x msec\n", timeout_msecs);
	390	error = mmc_rint_wait(mmc, timeout_msecs,
	391	data->blocks > 1 ?
	392	SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
	393	SUNXI_MMC_RINT_DATA_OVER,
	394	"data");
	395	if (error)
	396	goto out;
	397	}
	398
	399	if (cmd->resp_type & MMC_RSP_BUSY) {
	400	timeout_msecs = 2000;
	401	do {
	402	status = readl(&mmchost->reg->status);
	403	if (!timeout_msecs--) {
	404	debug("busy timeout\n");
	405	error = TIMEOUT;
	406	goto out;
	407	}
	408	udelay(1000);
	409	} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
	410	}
	411
	412	if (cmd->resp_type & MMC_RSP_136) {
	413	cmd->response[0] = readl(&mmchost->reg->resp3);
	414	cmd->response[1] = readl(&mmchost->reg->resp2);
	415	cmd->response[2] = readl(&mmchost->reg->resp1);
	416	cmd->response[3] = readl(&mmchost->reg->resp0);
	417	debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
	418	cmd->response[3], cmd->response[2],
	419	cmd->response[1], cmd->response[0]);
	420	} else {
	421	cmd->response[0] = readl(&mmchost->reg->resp0);
	422	debug("mmc resp 0x%08x\n", cmd->response[0]);
	423	}
	424	out:
e24ea55c IC	425	if (error < 0) {
	426	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
	427	mmc_update_clk(mmc);
	428	}
	429	writel(0xffffffff, &mmchost->reg->rint);
	430	writel(readl(&mmchost->reg->gctrl) \| SUNXI_MMC_GCTRL_FIFO_RESET,
	431	&mmchost->reg->gctrl);
	432
	433	return error;
	434	}
	435
cd82113a HG	436	static int sunxi_mmc_getcd(struct mmc *mmc)
	437	{
	438	struct sunxi_mmc_host *mmchost = mmc->priv;
967325fe	439	int cd_pin;
cd82113a	440
967325fe	441	cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
90641f82	442	if (cd_pin < 0)
cd82113a HG	443	return 1;
cd82113a HG	444
b0c4ae1a	445	return !gpio_get_value(cd_pin);
cd82113a HG	446	}
cd82113a HG	447
e24ea55c	448	static const struct mmc_ops sunxi_mmc_ops = {
5abdb156 SS	449	.send_cmd = sunxi_mmc_send_cmd,
	450	.set_ios = sunxi_mmc_set_ios,
	451	.init = sunxi_mmc_core_init,
cd82113a	452	.getcd = sunxi_mmc_getcd,
e24ea55c IC	453	};
e24ea55c IC	454
e79c7c88	455	struct mmc *sunxi_mmc_init(int sdc_no)
e24ea55c IC	456	{
	457	struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
	458
	459	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
	460
	461	cfg->name = "SUNXI SD/MMC";
	462	cfg->ops = &sunxi_mmc_ops;
	463
	464	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
	465	cfg->host_caps = MMC_MODE_4BIT;
d96ebc46 SS	466	#ifdef CONFIG_MACH_SUN50I
	467	if (sdc_no == 2)
	468	cfg->host_caps = MMC_MODE_8BIT;
	469	#endif
5a20397b	470	cfg->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
e24ea55c IC	471	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
	472
	473	cfg->f_min = 400000;
	474	cfg->f_max = 52000000;
	475
967325fe HG	476	if (mmc_resource_init(sdc_no) != 0)
	477	return NULL;
	478
e24ea55c IC	479	mmc_clk_io_on(sdc_no);
e24ea55c IC	480
e79c7c88	481	return mmc_create(cfg, &mmc_host[sdc_no]);
e24ea55c	482	}