[people/ms/u-boot.git] / drivers / mmc / sunxi_mmc.c

/*
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Aaron <leafy.myeh@allwinnertech.com>
 *
 * MMC driver for allwinner sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm-generic/gpio.h>

struct sunxi_mmc_host {
	unsigned mmc_no;
	uint32_t *mclkreg;
	unsigned fatal_err;
	struct sunxi_mmc *reg;
	struct mmc_config cfg;
};

/* support 4 mmc hosts */
struct sunxi_mmc_host mmc_host[4];

static int sunxi_mmc_getcd_gpio(int sdc_no)
{
	switch (sdc_no) {
	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
	}
	return -EINVAL;
}

static int mmc_resource_init(int sdc_no)
{
	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	int cd_pin, ret = 0;

	debug("init mmc %d resource\n", sdc_no);

	switch (sdc_no) {
	case 0:
		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
		mmchost->mclkreg = &ccm->sd0_clk_cfg;
		break;
	case 1:
		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
		mmchost->mclkreg = &ccm->sd1_clk_cfg;
		break;
	case 2:
		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
		mmchost->mclkreg = &ccm->sd2_clk_cfg;
		break;
	case 3:
		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
		mmchost->mclkreg = &ccm->sd3_clk_cfg;
		break;
	default:
		printf("Wrong mmc number %d\n", sdc_no);
		return -1;
	}
	mmchost->mmc_no = sdc_no;

	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
	if (cd_pin >= 0) {
		ret = gpio_request(cd_pin, "mmc_cd");
		if (!ret)
			ret = gpio_direction_input(cd_pin);
	}

	return ret;
}

static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
{
	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;

	if (hz <= 24000000) {
		pll = CCM_MMC_CTRL_OSCM24;
		pll_hz = 24000000;
	} else {
#ifdef CONFIG_MACH_SUN9I
		pll = CCM_MMC_CTRL_PLL_PERIPH0;
		pll_hz = clock_get_pll4_periph0();
#else
		pll = CCM_MMC_CTRL_PLL6;
		pll_hz = clock_get_pll6();
#endif
	}

	div = pll_hz / hz;
	if (pll_hz % hz)
		div++;

	n = 0;
	while (div > 16) {
		n++;
		div = (div + 1) / 2;
	}

	if (n > 3) {
		printf("mmc %u error cannot set clock to %u\n",
		       mmchost->mmc_no, hz);
		return -1;
	}

	/* determine delays */
	if (hz <= 400000) {
		oclk_dly = 0;
		sclk_dly = 7;
	} else if (hz <= 25000000) {
		oclk_dly = 0;
		sclk_dly = 5;
	} else if (hz <= 50000000) {
		oclk_dly = 3;
		sclk_dly = 5;
	} else {
		/* hz > 50000000 */
		oclk_dly = 2;
		sclk_dly = 4;
	}

	writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
	       CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
	       CCM_MMC_CTRL_M(div), mmchost->mclkreg);

	debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
	      mmchost->mmc_no, hz, pll_hz, 1u << n, div,
	      pll_hz / (1u << n) / div);

	return 0;
}

static int mmc_clk_io_on(int sdc_no)
{
	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	debug("init mmc %d clock and io\n", sdc_no);

	/* config ahb clock */
	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));

#ifdef CONFIG_SUNXI_GEN_SUN6I
	/* unassert reset */
	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
#endif
#if defined(CONFIG_MACH_SUN9I)
	/* sun9i has a mmc-common module, also set the gate and reset there */
	writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
	       SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
#endif

	return mmc_set_mod_clk(mmchost, 24000000);
}

static int mmc_update_clk(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	unsigned int cmd;
	unsigned timeout_msecs = 2000;

	cmd = SUNXI_MMC_CMD_START |
	      SUNXI_MMC_CMD_UPCLK_ONLY |
	      SUNXI_MMC_CMD_WAIT_PRE_OVER;
	writel(cmd, &mmchost->reg->cmd);
	while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
		if (!timeout_msecs--)
			return -1;
		udelay(1000);
	}

	/* clock update sets various irq status bits, clear these */
	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);

	return 0;
}

static int mmc_config_clock(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	unsigned rval = readl(&mmchost->reg->clkcr);

	/* Disable Clock */
	rval &= ~SUNXI_MMC_CLK_ENABLE;
	writel(rval, &mmchost->reg->clkcr);
	if (mmc_update_clk(mmc))
		return -1;

	/* Set mod_clk to new rate */
	if (mmc_set_mod_clk(mmchost, mmc->clock))
		return -1;

	/* Clear internal divider */
	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
	writel(rval, &mmchost->reg->clkcr);

	/* Re-enable Clock */
	rval |= SUNXI_MMC_CLK_ENABLE;
	writel(rval, &mmchost->reg->clkcr);
	if (mmc_update_clk(mmc))
		return -1;

	return 0;
}

static void sunxi_mmc_set_ios(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;

	debug("set ios: bus_width: %x, clock: %d\n",
	      mmc->bus_width, mmc->clock);

	/* Change clock first */
	if (mmc->clock && mmc_config_clock(mmc) != 0) {
		mmchost->fatal_err = 1;
		return;
	}

	/* Change bus width */
	if (mmc->bus_width == 8)
		writel(0x2, &mmchost->reg->width);
	else if (mmc->bus_width == 4)
		writel(0x1, &mmchost->reg->width);
	else
		writel(0x0, &mmchost->reg->width);
}

static int sunxi_mmc_core_init(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;

	/* Reset controller */
	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
	udelay(1000);

	return 0;
}

static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	const int reading = !!(data->flags & MMC_DATA_READ);
	const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
					      SUNXI_MMC_STATUS_FIFO_FULL;
	unsigned i;
	unsigned byte_cnt = data->blocksize * data->blocks;
	unsigned timeout_msecs = 2000;
	unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);

	/* Always read / write data through the CPU */
	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);

	for (i = 0; i < (byte_cnt >> 2); i++) {
		while (readl(&mmchost->reg->status) & status_bit) {
			if (!timeout_msecs--)
				return -1;
			udelay(1000);
		}

		if (reading)
			buff[i] = readl(&mmchost->reg->fifo);
		else
			writel(buff[i], &mmchost->reg->fifo);
	}

	return 0;
}

static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
			 unsigned int done_bit, const char *what)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	unsigned int status;

	do {
		status = readl(&mmchost->reg->rint);
		if (!timeout_msecs-- ||
		    (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
			debug("%s timeout %x\n", what,
			      status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
			return TIMEOUT;
		}
		udelay(1000);
	} while (!(status & done_bit));

	return 0;
}

static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	unsigned int cmdval = SUNXI_MMC_CMD_START;
	unsigned int timeout_msecs;
	int error = 0;
	unsigned int status = 0;
	unsigned int bytecnt = 0;

	if (mmchost->fatal_err)
		return -1;
	if (cmd->resp_type & MMC_RSP_BUSY)
		debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
	if (cmd->cmdidx == 12)
		return 0;

	if (!cmd->cmdidx)
		cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
	if (cmd->resp_type & MMC_RSP_PRESENT)
		cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
	if (cmd->resp_type & MMC_RSP_136)
		cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
	if (cmd->resp_type & MMC_RSP_CRC)
		cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;

	if (data) {
		if ((u32) data->dest & 0x3) {
			error = -1;
			goto out;
		}

		cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
		if (data->flags & MMC_DATA_WRITE)
			cmdval |= SUNXI_MMC_CMD_WRITE;
		if (data->blocks > 1)
			cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
		writel(data->blocksize, &mmchost->reg->blksz);
		writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
	}

	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
	      cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
	writel(cmd->cmdarg, &mmchost->reg->arg);

	if (!data)
		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);

	/*
	 * transfer data and check status
	 * STATREG[2] : FIFO empty
	 * STATREG[3] : FIFO full
	 */
	if (data) {
		int ret = 0;

		bytecnt = data->blocksize * data->blocks;
		debug("trans data %d bytes\n", bytecnt);
		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
		ret = mmc_trans_data_by_cpu(mmc, data);
		if (ret) {
			error = readl(&mmchost->reg->rint) & \
				SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
			error = TIMEOUT;
			goto out;
		}
	}

	error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
	if (error)
		goto out;

	if (data) {
		timeout_msecs = 120;
		debug("cacl timeout %x msec\n", timeout_msecs);
		error = mmc_rint_wait(mmc, timeout_msecs,
				      data->blocks > 1 ?
				      SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
				      SUNXI_MMC_RINT_DATA_OVER,
				      "data");
		if (error)
			goto out;
	}

	if (cmd->resp_type & MMC_RSP_BUSY) {
		timeout_msecs = 2000;
		do {
			status = readl(&mmchost->reg->status);
			if (!timeout_msecs--) {
				debug("busy timeout\n");
				error = TIMEOUT;
				goto out;
			}
			udelay(1000);
		} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
	}

	if (cmd->resp_type & MMC_RSP_136) {
		cmd->response[0] = readl(&mmchost->reg->resp3);
		cmd->response[1] = readl(&mmchost->reg->resp2);
		cmd->response[2] = readl(&mmchost->reg->resp1);
		cmd->response[3] = readl(&mmchost->reg->resp0);
		debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
		      cmd->response[3], cmd->response[2],
		      cmd->response[1], cmd->response[0]);
	} else {
		cmd->response[0] = readl(&mmchost->reg->resp0);
		debug("mmc resp 0x%08x\n", cmd->response[0]);
	}
out:
	if (error < 0) {
		writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
		mmc_update_clk(mmc);
	}
	writel(0xffffffff, &mmchost->reg->rint);
	writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
	       &mmchost->reg->gctrl);

	return error;
}

static int sunxi_mmc_getcd(struct mmc *mmc)
{
	struct sunxi_mmc_host *mmchost = mmc->priv;
	int cd_pin;

	cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
	if (cd_pin < 0)
		return 1;

	return !gpio_get_value(cd_pin);
}

static const struct mmc_ops sunxi_mmc_ops = {
	.send_cmd	= sunxi_mmc_send_cmd,
	.set_ios	= sunxi_mmc_set_ios,
	.init		= sunxi_mmc_core_init,
	.getcd		= sunxi_mmc_getcd,
};

struct mmc *sunxi_mmc_init(int sdc_no)
{
	struct mmc_config *cfg = &mmc_host[sdc_no].cfg;

	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));

	cfg->name = "SUNXI SD/MMC";
	cfg->ops  = &sunxi_mmc_ops;

	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
	cfg->host_caps = MMC_MODE_4BIT;
	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	cfg->f_min = 400000;
	cfg->f_max = 52000000;

	if (mmc_resource_init(sdc_no) != 0)
		return NULL;

	mmc_clk_io_on(sdc_no);

	return mmc_create(cfg, &mmc_host[sdc_no]);
}
Commit	Line	Data
e24ea55c IC	1	/*
	2	* (C) Copyright 2007-2011
	3	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	4	* Aaron <leafy.myeh@allwinnertech.com>
	5	*
	6	* MMC driver for allwinner sunxi platform.
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
90641f82	12	#include <errno.h>
e24ea55c IC	13	#include <malloc.h>
	14	#include <mmc.h>
	15	#include <asm/io.h>
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/cpu.h>
cd82113a	18	#include <asm/arch/gpio.h>
e24ea55c	19	#include <asm/arch/mmc.h>
cd82113a	20	#include <asm-generic/gpio.h>
e24ea55c	21
e24ea55c IC	22	struct sunxi_mmc_host {
	23	unsigned mmc_no;
	24	uint32_t *mclkreg;
e24ea55c	25	unsigned fatal_err;
e24ea55c IC	26	struct sunxi_mmc *reg;
	27	struct mmc_config cfg;
	28	};
	29
	30	/* support 4 mmc hosts */
	31	struct sunxi_mmc_host mmc_host[4];
	32
967325fe HG	33	static int sunxi_mmc_getcd_gpio(int sdc_no)
	34	{
	35	switch (sdc_no) {
	36	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
	37	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
	38	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
	39	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
	40	}
90641f82	41	return -EINVAL;
967325fe HG	42	}
967325fe HG	43
e24ea55c IC	44	static int mmc_resource_init(int sdc_no)
	45	{
	46	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
	47	struct sunxi_ccm_reg ccm = (struct sunxi_ccm_reg )SUNXI_CCM_BASE;
967325fe	48	int cd_pin, ret = 0;
e24ea55c IC	49
	50	debug("init mmc %d resource\n", sdc_no);
	51
	52	switch (sdc_no) {
	53	case 0:
	54	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
	55	mmchost->mclkreg = &ccm->sd0_clk_cfg;
	56	break;
	57	case 1:
	58	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
	59	mmchost->mclkreg = &ccm->sd1_clk_cfg;
	60	break;
	61	case 2:
	62	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
	63	mmchost->mclkreg = &ccm->sd2_clk_cfg;
	64	break;
	65	case 3:
	66	mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
	67	mmchost->mclkreg = &ccm->sd3_clk_cfg;
	68	break;
	69	default:
	70	printf("Wrong mmc number %d\n", sdc_no);
	71	return -1;
	72	}
e24ea55c IC	73	mmchost->mmc_no = sdc_no;
e24ea55c IC	74
967325fe	75	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
90641f82	76	if (cd_pin >= 0) {
967325fe	77	ret = gpio_request(cd_pin, "mmc_cd");
b0c4ae1a AL	78	if (!ret)
	79	ret = gpio_direction_input(cd_pin);
	80	}
967325fe HG	81
967325fe HG	82	return ret;
e24ea55c IC	83	}
e24ea55c IC	84
fc3a8325 HG	85	static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
	86	{
	87	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
	88
	89	if (hz <= 24000000) {
	90	pll = CCM_MMC_CTRL_OSCM24;
	91	pll_hz = 24000000;
	92	} else {
daf22636 HG	93	#ifdef CONFIG_MACH_SUN9I
	94	pll = CCM_MMC_CTRL_PLL_PERIPH0;
	95	pll_hz = clock_get_pll4_periph0();
	96	#else
fc3a8325 HG	97	pll = CCM_MMC_CTRL_PLL6;
fc3a8325 HG	98	pll_hz = clock_get_pll6();
daf22636	99	#endif
fc3a8325 HG	100	}
	101
	102	div = pll_hz / hz;
	103	if (pll_hz % hz)
	104	div++;
	105
	106	n = 0;
	107	while (div > 16) {
	108	n++;
	109	div = (div + 1) / 2;
	110	}
	111
	112	if (n > 3) {
	113	printf("mmc %u error cannot set clock to %u\n",
	114	mmchost->mmc_no, hz);
	115	return -1;
	116	}
	117
	118	/* determine delays */
	119	if (hz <= 400000) {
	120	oclk_dly = 0;
	121	sclk_dly = 7;
	122	} else if (hz <= 25000000) {
	123	oclk_dly = 0;
	124	sclk_dly = 5;
	125	} else if (hz <= 50000000) {
	126	oclk_dly = 3;
	127	sclk_dly = 5;
	128	} else {
	129	/* hz > 50000000 */
	130	oclk_dly = 2;
	131	sclk_dly = 4;
	132	}
	133
	134	writel(CCM_MMC_CTRL_ENABLE \| pll \| CCM_MMC_CTRL_SCLK_DLY(sclk_dly) \|
	135	CCM_MMC_CTRL_N(n) \| CCM_MMC_CTRL_OCLK_DLY(oclk_dly) \|
	136	CCM_MMC_CTRL_M(div), mmchost->mclkreg);
	137
	138	debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
	139	mmchost->mmc_no, hz, pll_hz, 1u << n, div,
	140	pll_hz / (1u << n) / div);
	141
	142	return 0;
	143	}
	144
e24ea55c IC	145	static int mmc_clk_io_on(int sdc_no)
e24ea55c IC	146	{
e24ea55c IC	147	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
	148	struct sunxi_ccm_reg ccm = (struct sunxi_ccm_reg )SUNXI_CCM_BASE;
	149
	150	debug("init mmc %d clock and io\n", sdc_no);
	151
	152	/* config ahb clock */
	153	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
	154
44d8ae5b	155	#ifdef CONFIG_SUNXI_GEN_SUN6I
1d1bd42e HG	156	/* unassert reset */
	157	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
	158	#endif
daf22636 HG	159	#if defined(CONFIG_MACH_SUN9I)
	160	/* sun9i has a mmc-common module, also set the gate and reset there */
	161	writel(SUNXI_MMC_COMMON_CLK_GATE \| SUNXI_MMC_COMMON_RESET,
	162	SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
	163	#endif
1d1bd42e	164
fc3a8325	165	return mmc_set_mod_clk(mmchost, 24000000);
e24ea55c IC	166	}
	167
	168	static int mmc_update_clk(struct mmc *mmc)
	169	{
	170	struct sunxi_mmc_host *mmchost = mmc->priv;
	171	unsigned int cmd;
	172	unsigned timeout_msecs = 2000;
	173
	174	cmd = SUNXI_MMC_CMD_START \|
	175	SUNXI_MMC_CMD_UPCLK_ONLY \|
	176	SUNXI_MMC_CMD_WAIT_PRE_OVER;
	177	writel(cmd, &mmchost->reg->cmd);
	178	while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
	179	if (!timeout_msecs--)
	180	return -1;
	181	udelay(1000);
	182	}
	183
	184	/* clock update sets various irq status bits, clear these */
	185	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
	186
	187	return 0;
	188	}
	189
fc3a8325	190	static int mmc_config_clock(struct mmc *mmc)
e24ea55c IC	191	{
	192	struct sunxi_mmc_host *mmchost = mmc->priv;
	193	unsigned rval = readl(&mmchost->reg->clkcr);
	194
	195	/* Disable Clock */
	196	rval &= ~SUNXI_MMC_CLK_ENABLE;
	197	writel(rval, &mmchost->reg->clkcr);
	198	if (mmc_update_clk(mmc))
	199	return -1;
	200
fc3a8325 HG	201	/* Set mod_clk to new rate */
	202	if (mmc_set_mod_clk(mmchost, mmc->clock))
	203	return -1;
	204
	205	/* Clear internal divider */
e24ea55c	206	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
e24ea55c	207	writel(rval, &mmchost->reg->clkcr);
fc3a8325	208
e24ea55c IC	209	/* Re-enable Clock */
	210	rval \|= SUNXI_MMC_CLK_ENABLE;
	211	writel(rval, &mmchost->reg->clkcr);
e24ea55c IC	212	if (mmc_update_clk(mmc))
	213	return -1;
	214
	215	return 0;
	216	}
	217
5abdb156	218	static void sunxi_mmc_set_ios(struct mmc *mmc)
e24ea55c IC	219	{
e24ea55c IC	220	struct sunxi_mmc_host *mmchost = mmc->priv;
e24ea55c	221
fc3a8325 HG	222	debug("set ios: bus_width: %x, clock: %d\n",
fc3a8325 HG	223	mmc->bus_width, mmc->clock);
e24ea55c IC	224
e24ea55c IC	225	/* Change clock first */
fc3a8325 HG	226	if (mmc->clock && mmc_config_clock(mmc) != 0) {
	227	mmchost->fatal_err = 1;
	228	return;
e24ea55c IC	229	}
	230
	231	/* Change bus width */
	232	if (mmc->bus_width == 8)
	233	writel(0x2, &mmchost->reg->width);
	234	else if (mmc->bus_width == 4)
	235	writel(0x1, &mmchost->reg->width);
	236	else
	237	writel(0x0, &mmchost->reg->width);
	238	}
	239
5abdb156	240	static int sunxi_mmc_core_init(struct mmc *mmc)
e24ea55c IC	241	{
	242	struct sunxi_mmc_host *mmchost = mmc->priv;
	243
	244	/* Reset controller */
	245	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
b6ae6765	246	udelay(1000);
e24ea55c IC	247
	248	return 0;
	249	}
	250
	251	static int mmc_trans_data_by_cpu(struct mmc mmc, struct mmc_data data)
	252	{
	253	struct sunxi_mmc_host *mmchost = mmc->priv;
	254	const int reading = !!(data->flags & MMC_DATA_READ);
	255	const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
	256	SUNXI_MMC_STATUS_FIFO_FULL;
	257	unsigned i;
	258	unsigned byte_cnt = data->blocksize * data->blocks;
	259	unsigned timeout_msecs = 2000;
	260	unsigned buff = (unsigned int )(reading ? data->dest : data->src);
	261
b6ae6765 HG	262	/* Always read / write data through the CPU */
	263	setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
	264
e24ea55c IC	265	for (i = 0; i < (byte_cnt >> 2); i++) {
	266	while (readl(&mmchost->reg->status) & status_bit) {
	267	if (!timeout_msecs--)
	268	return -1;
	269	udelay(1000);
	270	}
	271
	272	if (reading)
1d1bd42e	273	buff[i] = readl(&mmchost->reg->fifo);
e24ea55c	274	else
1d1bd42e	275	writel(buff[i], &mmchost->reg->fifo);
e24ea55c IC	276	}
	277
	278	return 0;
	279	}
	280
e24ea55c IC	281	static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
	282	unsigned int done_bit, const char *what)
	283	{
	284	struct sunxi_mmc_host *mmchost = mmc->priv;
	285	unsigned int status;
	286
	287	do {
	288	status = readl(&mmchost->reg->rint);
	289	if (!timeout_msecs-- \|\|
	290	(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
	291	debug("%s timeout %x\n", what,
	292	status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
	293	return TIMEOUT;
	294	}
	295	udelay(1000);
	296	} while (!(status & done_bit));
	297
	298	return 0;
	299	}
	300
5abdb156 SS	301	static int sunxi_mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
5abdb156 SS	302	struct mmc_data *data)
e24ea55c IC	303	{
	304	struct sunxi_mmc_host *mmchost = mmc->priv;
	305	unsigned int cmdval = SUNXI_MMC_CMD_START;
	306	unsigned int timeout_msecs;
	307	int error = 0;
	308	unsigned int status = 0;
e24ea55c IC	309	unsigned int bytecnt = 0;
	310
	311	if (mmchost->fatal_err)
	312	return -1;
	313	if (cmd->resp_type & MMC_RSP_BUSY)
	314	debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
	315	if (cmd->cmdidx == 12)
	316	return 0;
	317
	318	if (!cmd->cmdidx)
	319	cmdval \|= SUNXI_MMC_CMD_SEND_INIT_SEQ;
	320	if (cmd->resp_type & MMC_RSP_PRESENT)
	321	cmdval \|= SUNXI_MMC_CMD_RESP_EXPIRE;
	322	if (cmd->resp_type & MMC_RSP_136)
	323	cmdval \|= SUNXI_MMC_CMD_LONG_RESPONSE;
	324	if (cmd->resp_type & MMC_RSP_CRC)
	325	cmdval \|= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
	326
	327	if (data) {
	328	if ((u32) data->dest & 0x3) {
	329	error = -1;
	330	goto out;
	331	}
	332
	333	cmdval \|= SUNXI_MMC_CMD_DATA_EXPIRE\|SUNXI_MMC_CMD_WAIT_PRE_OVER;
	334	if (data->flags & MMC_DATA_WRITE)
	335	cmdval \|= SUNXI_MMC_CMD_WRITE;
	336	if (data->blocks > 1)
	337	cmdval \|= SUNXI_MMC_CMD_AUTO_STOP;
	338	writel(data->blocksize, &mmchost->reg->blksz);
	339	writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
	340	}
	341
	342	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
	343	cmd->cmdidx, cmdval \| cmd->cmdidx, cmd->cmdarg);
	344	writel(cmd->cmdarg, &mmchost->reg->arg);
	345
	346	if (!data)
	347	writel(cmdval \| cmd->cmdidx, &mmchost->reg->cmd);
	348
	349	/*
	350	* transfer data and check status
	351	* STATREG[2] : FIFO empty
	352	* STATREG[3] : FIFO full
	353	*/
	354	if (data) {
	355	int ret = 0;
	356
	357	bytecnt = data->blocksize * data->blocks;
	358	debug("trans data %d bytes\n", bytecnt);
b6ae6765 HG	359	writel(cmdval \| cmd->cmdidx, &mmchost->reg->cmd);
b6ae6765 HG	360	ret = mmc_trans_data_by_cpu(mmc, data);
e24ea55c IC	361	if (ret) {
	362	error = readl(&mmchost->reg->rint) & \
	363	SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
	364	error = TIMEOUT;
	365	goto out;
	366	}
	367	}
	368
5b8d7fb4	369	error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
e24ea55c IC	370	if (error)
	371	goto out;
	372
	373	if (data) {
b6ae6765	374	timeout_msecs = 120;
e24ea55c IC	375	debug("cacl timeout %x msec\n", timeout_msecs);
	376	error = mmc_rint_wait(mmc, timeout_msecs,
	377	data->blocks > 1 ?
	378	SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
	379	SUNXI_MMC_RINT_DATA_OVER,
	380	"data");
	381	if (error)
	382	goto out;
	383	}
	384
	385	if (cmd->resp_type & MMC_RSP_BUSY) {
	386	timeout_msecs = 2000;
	387	do {
	388	status = readl(&mmchost->reg->status);
	389	if (!timeout_msecs--) {
	390	debug("busy timeout\n");
	391	error = TIMEOUT;
	392	goto out;
	393	}
	394	udelay(1000);
	395	} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
	396	}
	397
	398	if (cmd->resp_type & MMC_RSP_136) {
	399	cmd->response[0] = readl(&mmchost->reg->resp3);
	400	cmd->response[1] = readl(&mmchost->reg->resp2);
	401	cmd->response[2] = readl(&mmchost->reg->resp1);
	402	cmd->response[3] = readl(&mmchost->reg->resp0);
	403	debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
	404	cmd->response[3], cmd->response[2],
	405	cmd->response[1], cmd->response[0]);
	406	} else {
	407	cmd->response[0] = readl(&mmchost->reg->resp0);
	408	debug("mmc resp 0x%08x\n", cmd->response[0]);
	409	}
	410	out:
e24ea55c IC	411	if (error < 0) {
	412	writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
	413	mmc_update_clk(mmc);
	414	}
	415	writel(0xffffffff, &mmchost->reg->rint);
	416	writel(readl(&mmchost->reg->gctrl) \| SUNXI_MMC_GCTRL_FIFO_RESET,
	417	&mmchost->reg->gctrl);
	418
	419	return error;
	420	}
	421
cd82113a HG	422	static int sunxi_mmc_getcd(struct mmc *mmc)
	423	{
	424	struct sunxi_mmc_host *mmchost = mmc->priv;
967325fe	425	int cd_pin;
cd82113a	426
967325fe	427	cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
90641f82	428	if (cd_pin < 0)
cd82113a HG	429	return 1;
cd82113a HG	430
b0c4ae1a	431	return !gpio_get_value(cd_pin);
cd82113a HG	432	}
cd82113a HG	433
e24ea55c	434	static const struct mmc_ops sunxi_mmc_ops = {
5abdb156 SS	435	.send_cmd = sunxi_mmc_send_cmd,
	436	.set_ios = sunxi_mmc_set_ios,
	437	.init = sunxi_mmc_core_init,
cd82113a	438	.getcd = sunxi_mmc_getcd,
e24ea55c IC	439	};
e24ea55c IC	440
e79c7c88	441	struct mmc *sunxi_mmc_init(int sdc_no)
e24ea55c IC	442	{
	443	struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
	444
	445	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
	446
	447	cfg->name = "SUNXI SD/MMC";
	448	cfg->ops = &sunxi_mmc_ops;
	449
	450	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
	451	cfg->host_caps = MMC_MODE_4BIT;
5a20397b	452	cfg->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
e24ea55c IC	453	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
	454
	455	cfg->f_min = 400000;
	456	cfg->f_max = 52000000;
	457
967325fe HG	458	if (mmc_resource_init(sdc_no) != 0)
	459	return NULL;
	460
e24ea55c IC	461	mmc_clk_io_on(sdc_no);
e24ea55c IC	462
e79c7c88	463	return mmc_create(cfg, &mmc_host[sdc_no]);
e24ea55c	464	}