]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mmc/uniphier-sd.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: uniphier-sd: Add support for 64bit controller
[people/ms/u-boot.git] / drivers / mmc / uniphier-sd.c
CommitLineData
a111bfbf 1/*
4e3d8406
MY		 2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
a111bfbf
MY		 4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <fdtdec.h>
a111bfbf 11#include <mmc.h>
9d922450 12#include <dm.h>
a111bfbf 13#include <linux/compat.h>
b27af399 14#include <linux/dma-direction.h>
a111bfbf 15#include <linux/io.h>
4f80501b 16#include <linux/sizes.h>
a111bfbf 17#include <asm/unaligned.h>
a111bfbf
MY		 18
19DECLARE_GLOBAL_DATA_PTR;
20
21#define UNIPHIER_SD_CMD 0x000 /* command */
22#define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
23#define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */
24#define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */
25#define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */
26#define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
27#define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
28#define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */
29#define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
30#define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
31#define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
32#define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
33#define UNIPHIER_SD_ARG 0x008 /* command argument */
34#define UNIPHIER_SD_STOP 0x010 /* stop action control */
35#define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */
36#define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */
37#define UNIPHIER_SD_SECCNT 0x014 /* sector counter */
38#define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */
39#define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */
40#define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */
41#define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */
42#define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */
43#define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */
44#define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */
45#define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */
46#define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */
47#define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */
48#define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */
49#define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
50#define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */
51#define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */
52#define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */
53#define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
54#define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */
55#define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
56#define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
57#define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */
58#define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */
59#define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
60#define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
61#define UNIPHIER_SD_INFO1_MASK 0x040
62#define UNIPHIER_SD_INFO2_MASK 0x044
63#define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */
64#define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
65#define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
66#define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
67#define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
68#define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
69#define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
70#define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
71#define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
72#define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
73#define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
74#define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
75#define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
76#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
77#define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
78#define UNIPHIER_SD_SIZE 0x04c /* block size */
79#define UNIPHIER_SD_OPTION 0x050
80#define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
81#define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
82#define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
83#define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
84#define UNIPHIER_SD_BUF 0x060 /* read/write buffer */
85#define UNIPHIER_SD_EXTMODE 0x1b0
86#define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
87#define UNIPHIER_SD_SOFT_RST 0x1c0
88#define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
89#define UNIPHIER_SD_VERSION 0x1c4 /* version register */
90#define UNIPHIER_SD_VERSION_IP 0xff /* IP version */
91#define UNIPHIER_SD_HOST_MODE 0x1c8
92#define UNIPHIER_SD_IF_MODE 0x1cc
93#define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */
94#define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */
95#define UNIPHIER_SD_VOLT_MASK (3 << 0)
96#define UNIPHIER_SD_VOLT_OFF (0 << 0)
97#define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */
98#define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */
99#define UNIPHIER_SD_DMA_MODE 0x410
100#define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
101#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
102#define UNIPHIER_SD_DMA_CTL 0x414
103#define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
104#define UNIPHIER_SD_DMA_RST 0x418
105#define UNIPHIER_SD_DMA_RST_RD BIT(9)
106#define UNIPHIER_SD_DMA_RST_WR BIT(8)
107#define UNIPHIER_SD_DMA_INFO1 0x420
108#define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
109#define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
110#define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
111#define UNIPHIER_SD_DMA_INFO1_MASK 0x424
112#define UNIPHIER_SD_DMA_INFO2 0x428
113#define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
114#define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
115#define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
116#define UNIPHIER_SD_DMA_ADDR_L 0x440
117#define UNIPHIER_SD_DMA_ADDR_H 0x444
118
119/* alignment required by the DMA engine of this controller */
120#define UNIPHIER_SD_DMA_MINALIGN 0x10
121
14f47234 122struct uniphier_sd_plat {
a111bfbf 123 struct mmc_config cfg;
14f47234
MY		 124 struct mmc mmc;
125};
126
127struct uniphier_sd_priv {
a111bfbf
MY		 128 void __iomem *regbase;
129 unsigned long mclk;
130 unsigned int version;
131 u32 caps;
132#define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
133#define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
134#define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
1c99f68e 135#define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
a111bfbf
MY		 136};
137
3d7b1d1b
MV		 138static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg)
139{
1c99f68e
MV		 140 if (priv->caps & UNIPHIER_SD_CAP_64BIT)
141 return readl(priv->regbase + (reg << 1));
142 else
143 return readl(priv->regbase + reg);
3d7b1d1b
MV		 144}
145
146static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
147 const u32 val, const u32 reg)
148{
1c99f68e
MV		 149 if (priv->caps & UNIPHIER_SD_CAP_64BIT)
150 writel(val, priv->regbase + (reg << 1));
151 else
152 writel(val, priv->regbase + reg);
3d7b1d1b
MV		 153}
154
a111bfbf
MY		 155static dma_addr_t __dma_map_single(void *ptr, size_t size,
156 enum dma_data_direction dir)
157{
158 unsigned long addr = (unsigned long)ptr;
159
160 if (dir == DMA_FROM_DEVICE)
161 invalidate_dcache_range(addr, addr + size);
162 else
163 flush_dcache_range(addr, addr + size);
164
165 return addr;
166}
167
168static void __dma_unmap_single(dma_addr_t addr, size_t size,
169 enum dma_data_direction dir)
170{
171 if (dir != DMA_TO_DEVICE)
172 invalidate_dcache_range(addr, addr + size);
173}
174
3937404f 175static int uniphier_sd_check_error(struct udevice *dev)
a111bfbf 176{
3937404f 177 struct uniphier_sd_priv *priv = dev_get_priv(dev);
3d7b1d1b 178 u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2);
a111bfbf
MY		 179
180 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
181 /*
182 * TIMEOUT must be returned for unsupported command. Do not
183 * display error log since this might be a part of sequence to
184 * distinguish between SD and MMC.
185 */
915ffa52 186 return -ETIMEDOUT;
a111bfbf
MY		 187 }
188
189 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) {
3937404f 190 dev_err(dev, "timeout error\n");
a111bfbf
MY		 191 return -ETIMEDOUT;
192 }
193
194 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC |
195 UNIPHIER_SD_INFO2_ERR_IDX)) {
3937404f 196 dev_err(dev, "communication out of sync\n");
a111bfbf
MY		 197 return -EILSEQ;
198 }
199
200 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR |
201 UNIPHIER_SD_INFO2_ERR_ILW)) {
3937404f 202 dev_err(dev, "illegal access\n");
a111bfbf
MY		 203 return -EIO;
204 }
205
206 return 0;
207}
208
3937404f
MY		 209static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
210 u32 flag)
a111bfbf 211{
3937404f 212 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 213 long wait = 1000000;
214 int ret;
215
3d7b1d1b 216 while (!(uniphier_sd_readl(priv, reg) & flag)) {
a111bfbf 217 if (wait-- < 0) {
3937404f 218 dev_err(dev, "timeout\n");
a111bfbf
MY		 219 return -ETIMEDOUT;
220 }
221
3937404f 222 ret = uniphier_sd_check_error(dev);
a111bfbf
MY		 223 if (ret)
224 return ret;
225
226 udelay(1);
227 }
228
229 return 0;
230}
231
3937404f 232static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
a111bfbf
MY		 233 uint blocksize)
234{
3937404f 235 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 236 int i, ret;
237
238 /* wait until the buffer is filled with data */
3937404f 239 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
a111bfbf
MY		 240 UNIPHIER_SD_INFO2_BRE);
241 if (ret)
242 return ret;
243
244 /*
245 * Clear the status flag _before_ read the buffer out because
246 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
247 */
3d7b1d1b 248 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
a111bfbf
MY		 249
250 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
251 for (i = 0; i < blocksize / 4; i++)
3d7b1d1b 252 *(*pbuf)++ = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
a111bfbf
MY		 253 } else {
254 for (i = 0; i < blocksize / 4; i++)
3d7b1d1b 255 put_unaligned(uniphier_sd_readl(priv, UNIPHIER_SD_BUF),
a111bfbf
MY		 256 (*pbuf)++);
257 }
258
259 return 0;
260}
261
3937404f
MY		 262static int uniphier_sd_pio_write_one_block(struct udevice *dev,
263 const u32 **pbuf, uint blocksize)
a111bfbf 264{
3937404f 265 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 266 int i, ret;
267
268 /* wait until the buffer becomes empty */
3937404f 269 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
a111bfbf
MY		 270 UNIPHIER_SD_INFO2_BWE);
271 if (ret)
272 return ret;
273
3d7b1d1b 274 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
a111bfbf
MY		 275
276 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
277 for (i = 0; i < blocksize / 4; i++)
3d7b1d1b 278 uniphier_sd_writel(priv, *(*pbuf)++, UNIPHIER_SD_BUF);
a111bfbf
MY		 279 } else {
280 for (i = 0; i < blocksize / 4; i++)
3d7b1d1b
MV		 281 uniphier_sd_writel(priv, get_unaligned((*pbuf)++),
282 UNIPHIER_SD_BUF);
a111bfbf
MY		 283 }
284
285 return 0;
286}
287
3937404f 288static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
a111bfbf
MY		 289{
290 u32 *dest = (u32 *)data->dest;
291 const u32 *src = (const u32 *)data->src;
292 int i, ret;
293
294 for (i = 0; i < data->blocks; i++) {
295 if (data->flags & MMC_DATA_READ)
3937404f 296 ret = uniphier_sd_pio_read_one_block(dev, &dest,
a111bfbf
MY		 297 data->blocksize);
298 else
3937404f 299 ret = uniphier_sd_pio_write_one_block(dev, &src,
a111bfbf
MY		 300 data->blocksize);
301 if (ret)
302 return ret;
303 }
304
305 return 0;
306}
307
308static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
309 dma_addr_t dma_addr)
310{
311 u32 tmp;
312
3d7b1d1b
MV		 313 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1);
314 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2);
a111bfbf
MY		 315
316 /* enable DMA */
3d7b1d1b 317 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
a111bfbf 318 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
3d7b1d1b 319 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
a111bfbf 320
3d7b1d1b 321 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L);
a111bfbf
MY		 322
323 /* suppress the warning "right shift count >= width of type" */
324 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
325
3d7b1d1b 326 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H);
a111bfbf 327
3d7b1d1b 328 uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL);
a111bfbf
MY		 329}
330
3937404f 331static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
a111bfbf
MY		 332 unsigned int blocks)
333{
3937404f 334 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 335 long wait = 1000000 + 10 * blocks;
336
3d7b1d1b 337 while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) {
a111bfbf 338 if (wait-- < 0) {
3937404f 339 dev_err(dev, "timeout during DMA\n");
a111bfbf
MY		 340 return -ETIMEDOUT;
341 }
342
343 udelay(10);
344 }
345
3d7b1d1b 346 if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) {
3937404f 347 dev_err(dev, "error during DMA\n");
a111bfbf
MY		 348 return -EIO;
349 }
350
351 return 0;
352}
353
3937404f 354static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
a111bfbf 355{
3937404f 356 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 357 size_t len = data->blocks * data->blocksize;
358 void *buf;
359 enum dma_data_direction dir;
360 dma_addr_t dma_addr;
361 u32 poll_flag, tmp;
362 int ret;
363
3d7b1d1b 364 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
a111bfbf
MY		 365
366 if (data->flags & MMC_DATA_READ) {
367 buf = data->dest;
368 dir = DMA_FROM_DEVICE;
369 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2;
370 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD;
371 } else {
372 buf = (void *)data->src;
373 dir = DMA_TO_DEVICE;
374 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR;
375 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
376 }
377
3d7b1d1b 378 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
a111bfbf
MY		 379
380 dma_addr = __dma_map_single(buf, len, dir);
381
382 uniphier_sd_dma_start(priv, dma_addr);
383
3937404f 384 ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
a111bfbf
MY		 385
386 __dma_unmap_single(dma_addr, len, dir);
387
388 return ret;
389}
390
391/* check if the address is DMA'able */
392static bool uniphier_sd_addr_is_dmaable(unsigned long addr)
393{
394 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN))
395 return false;
396
397#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
398 defined(CONFIG_SPL_BUILD)
399 /*
400 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
401 * of L2, which is unreachable from the DMA engine.
402 */
403 if (addr < CONFIG_SPL_STACK)
404 return false;
405#endif
406
407 return true;
408}
409
3937404f 410static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
a111bfbf
MY		 411 struct mmc_data *data)
412{
3937404f 413 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 414 int ret;
415 u32 tmp;
416
3d7b1d1b 417 if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
3937404f 418 dev_err(dev, "command busy\n");
a111bfbf
MY		 419 return -EBUSY;
420 }
421
422 /* clear all status flags */
3d7b1d1b
MV		 423 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
424 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
a111bfbf
MY		 425
426 /* disable DMA once */
3d7b1d1b 427 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
a111bfbf 428 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
3d7b1d1b 429 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
a111bfbf 430
3d7b1d1b 431 uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG);
a111bfbf
MY		 432
433 tmp = cmd->cmdidx;
434
435 if (data) {
3d7b1d1b
MV		 436 uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE);
437 uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT);
a111bfbf
MY		 438
439 /* Do not send CMD12 automatically */
440 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
441
442 if (data->blocks > 1)
443 tmp |= UNIPHIER_SD_CMD_MULTI;
444
445 if (data->flags & MMC_DATA_READ)
446 tmp |= UNIPHIER_SD_CMD_RD;
447 }
448
449 /*
450 * Do not use the response type auto-detection on this hardware.
451 * CMD8, for example, has different response types on SD and eMMC,
452 * while this controller always assumes the response type for SD.
453 * Set the response type manually.
454 */
455 switch (cmd->resp_type) {
456 case MMC_RSP_NONE:
457 tmp |= UNIPHIER_SD_CMD_RSP_NONE;
458 break;
459 case MMC_RSP_R1:
460 tmp |= UNIPHIER_SD_CMD_RSP_R1;
461 break;
462 case MMC_RSP_R1b:
463 tmp |= UNIPHIER_SD_CMD_RSP_R1B;
464 break;
465 case MMC_RSP_R2:
466 tmp |= UNIPHIER_SD_CMD_RSP_R2;
467 break;
468 case MMC_RSP_R3:
469 tmp |= UNIPHIER_SD_CMD_RSP_R3;
470 break;
471 default:
3937404f 472 dev_err(dev, "unknown response type\n");
a111bfbf
MY		 473 return -EINVAL;
474 }
475
3937404f 476 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
a111bfbf 477 cmd->cmdidx, tmp, cmd->cmdarg);
3d7b1d1b 478 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD);
a111bfbf 479
3937404f 480 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
a111bfbf
MY		 481 UNIPHIER_SD_INFO1_RSP);
482 if (ret)
483 return ret;
484
485 if (cmd->resp_type & MMC_RSP_136) {
3d7b1d1b
MV		 486 u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76);
487 u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54);
488 u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32);
489 u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
a111bfbf 490
ac5efc35
MV		 491 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
492 ((rsp_103_72 & 0xff000000) >> 24);
493 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
494 ((rsp_71_40 & 0xff000000) >> 24);
495 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
496 ((rsp_39_8 & 0xff000000) >> 24);
497 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
a111bfbf
MY		 498 } else {
499 /* bit 39-8 */
3d7b1d1b 500 cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
a111bfbf
MY		 501 }
502
503 if (data) {
504 /* use DMA if the HW supports it and the buffer is aligned */
505 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL &&
506 uniphier_sd_addr_is_dmaable((long)data->src))
3937404f 507 ret = uniphier_sd_dma_xfer(dev, data);
a111bfbf 508 else
3937404f 509 ret = uniphier_sd_pio_xfer(dev, data);
a111bfbf 510
3937404f 511 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
a111bfbf
MY		 512 UNIPHIER_SD_INFO1_CMP);
513 if (ret)
514 return ret;
515 }
516
517 return ret;
518}
519
8be12e28
MY		 520static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
521 struct mmc *mmc)
a111bfbf
MY		 522{
523 u32 val, tmp;
524
525 switch (mmc->bus_width) {
526 case 1:
527 val = UNIPHIER_SD_OPTION_WIDTH_1;
528 break;
529 case 4:
530 val = UNIPHIER_SD_OPTION_WIDTH_4;
531 break;
532 case 8:
533 val = UNIPHIER_SD_OPTION_WIDTH_8;
534 break;
535 default:
8be12e28 536 return -EINVAL;
a111bfbf
MY		 537 }
538
3d7b1d1b 539 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION);
a111bfbf
MY		 540 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
541 tmp |= val;
3d7b1d1b 542 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION);
8be12e28
MY		 543
544 return 0;
a111bfbf
MY		 545}
546
547static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
548 struct mmc *mmc)
549{
550 u32 tmp;
551
3d7b1d1b 552 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE);
a111bfbf
MY		 553 if (mmc->ddr_mode)
554 tmp |= UNIPHIER_SD_IF_MODE_DDR;
555 else
556 tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
3d7b1d1b 557 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE);
a111bfbf
MY		 558}
559
560static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
561 struct mmc *mmc)
562{
563 unsigned int divisor;
564 u32 val, tmp;
565
566 if (!mmc->clock)
567 return;
568
569 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
570
571 if (divisor <= 1)
572 val = UNIPHIER_SD_CLKCTL_DIV1;
573 else if (divisor <= 2)
574 val = UNIPHIER_SD_CLKCTL_DIV2;
575 else if (divisor <= 4)
576 val = UNIPHIER_SD_CLKCTL_DIV4;
577 else if (divisor <= 8)
578 val = UNIPHIER_SD_CLKCTL_DIV8;
579 else if (divisor <= 16)
580 val = UNIPHIER_SD_CLKCTL_DIV16;
581 else if (divisor <= 32)
582 val = UNIPHIER_SD_CLKCTL_DIV32;
583 else if (divisor <= 64)
584 val = UNIPHIER_SD_CLKCTL_DIV64;
585 else if (divisor <= 128)
586 val = UNIPHIER_SD_CLKCTL_DIV128;
587 else if (divisor <= 256)
588 val = UNIPHIER_SD_CLKCTL_DIV256;
589 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024))
590 val = UNIPHIER_SD_CLKCTL_DIV512;
591 else
592 val = UNIPHIER_SD_CLKCTL_DIV1024;
593
3d7b1d1b 594 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
4a89a24e
MY		 595 if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
596 (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
597 return;
a111bfbf
MY		 598
599 /* stop the clock before changing its rate to avoid a glitch signal */
600 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
3d7b1d1b 601 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
a111bfbf
MY		 602
603 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
604 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
3d7b1d1b 605 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
a111bfbf
MY		 606
607 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
3d7b1d1b 608 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
4a89a24e
MY		 609
610 udelay(1000);
a111bfbf
MY		 611}
612
3937404f 613static int uniphier_sd_set_ios(struct udevice *dev)
a111bfbf 614{
3937404f
MY		 615 struct uniphier_sd_priv *priv = dev_get_priv(dev);
616 struct mmc *mmc = mmc_get_mmc_dev(dev);
8be12e28 617 int ret;
a111bfbf 618
3937404f 619 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
a111bfbf
MY		 620 mmc->clock, mmc->ddr_mode, mmc->bus_width);
621
8be12e28
MY		 622 ret = uniphier_sd_set_bus_width(priv, mmc);
623 if (ret)
624 return ret;
a111bfbf
MY		 625 uniphier_sd_set_ddr_mode(priv, mmc);
626 uniphier_sd_set_clk_rate(priv, mmc);
627
3937404f 628 return 0;
a111bfbf
MY		 629}
630
4eb00846
MY		 631static int uniphier_sd_get_cd(struct udevice *dev)
632{
633 struct uniphier_sd_priv *priv = dev_get_priv(dev);
634
635 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
636 return 1;
637
3d7b1d1b 638 return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) &
4eb00846
MY		 639 UNIPHIER_SD_INFO1_CD);
640}
641
642static const struct dm_mmc_ops uniphier_sd_ops = {
643 .send_cmd = uniphier_sd_send_cmd,
644 .set_ios = uniphier_sd_set_ios,
645 .get_cd = uniphier_sd_get_cd,
646};
647
648static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
a111bfbf 649{
a111bfbf
MY		 650 u32 tmp;
651
652 /* soft reset of the host */
3d7b1d1b 653 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST);
a111bfbf 654 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
3d7b1d1b 655 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
a111bfbf 656 tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
3d7b1d1b 657 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
a111bfbf
MY		 658
659 /* FIXME: implement eMMC hw_reset */
660
3d7b1d1b 661 uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP);
a111bfbf
MY		 662
663 /*
664 * Connected to 32bit AXI.
665 * This register dropped backward compatibility at version 0x10.
666 * Write an appropriate value depending on the IP version.
667 */
3d7b1d1b
MV		 668 uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
669 UNIPHIER_SD_HOST_MODE);
a111bfbf
MY		 670
671 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
3d7b1d1b 672 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
a111bfbf 673 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
3d7b1d1b 674 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
a111bfbf 675 }
a111bfbf
MY		 676}
677
14f47234
MY		 678static int uniphier_sd_bind(struct udevice *dev)
679{
680 struct uniphier_sd_plat *plat = dev_get_platdata(dev);
681
682 return mmc_bind(dev, &plat->mmc, &plat->cfg);
683}
684
4a70d262 685static int uniphier_sd_probe(struct udevice *dev)
a111bfbf 686{
14f47234 687 struct uniphier_sd_plat *plat = dev_get_platdata(dev);
a111bfbf
MY		 688 struct uniphier_sd_priv *priv = dev_get_priv(dev);
689 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
690 fdt_addr_t base;
135aa950 691 struct clk clk;
a111bfbf
MY		 692 int ret;
693
a821c4af 694 base = devfdt_get_addr(dev);
4f80501b
MY		 695 if (base == FDT_ADDR_T_NONE)
696 return -EINVAL;
697
4e3d8406 698 priv->regbase = devm_ioremap(dev, base, SZ_2K);
a111bfbf
MY		 699 if (!priv->regbase)
700 return -ENOMEM;
701
135aa950
SW		 702 ret = clk_get_by_index(dev, 0, &clk);
703 if (ret < 0) {
a111bfbf 704 dev_err(dev, "failed to get host clock\n");
135aa950 705 return ret;
a111bfbf
MY		 706 }
707
708 /* set to max rate */
135aa950 709 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
a111bfbf
MY		 710 if (IS_ERR_VALUE(priv->mclk)) {
711 dev_err(dev, "failed to set rate for host clock\n");
135aa950 712 clk_free(&clk);
a111bfbf
MY		 713 return priv->mclk;
714 }
715
135aa950
SW		 716 ret = clk_enable(&clk);
717 clk_free(&clk);
a111bfbf
MY		 718 if (ret) {
719 dev_err(dev, "failed to enable host clock\n");
720 return ret;
721 }
722
14f47234
MY		 723 plat->cfg.name = dev->name;
724 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
a111bfbf 725
e160f7d4
SG		 726 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
727 1)) {
a111bfbf 728 case 8:
14f47234 729 plat->cfg.host_caps |= MMC_MODE_8BIT;
a111bfbf
MY		 730 break;
731 case 4:
14f47234 732 plat->cfg.host_caps |= MMC_MODE_4BIT;
a111bfbf
MY		 733 break;
734 case 1:
735 break;
736 default:
737 dev_err(dev, "Invalid \"bus-width\" value\n");
738 return -EINVAL;
739 }
740
e160f7d4 741 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
a111bfbf
MY		 742 NULL))
743 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
744
3d7b1d1b 745 priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
a111bfbf
MY		 746 UNIPHIER_SD_VERSION_IP;
747 dev_dbg(dev, "version %x\n", priv->version);
748 if (priv->version >= 0x10) {
749 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
750 priv->caps |= UNIPHIER_SD_CAP_DIV1024;
751 }
752
4eb00846 753 uniphier_sd_host_init(priv);
3937404f 754
14f47234
MY		 755 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
756 plat->cfg.f_min = priv->mclk /
a111bfbf 757 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
14f47234
MY		 758 plat->cfg.f_max = priv->mclk;
759 plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
a111bfbf 760
14f47234 761 upriv->mmc = &plat->mmc;
a111bfbf
MY		 762
763 return 0;
764}
765
766static const struct udevice_id uniphier_sd_match[] = {
767 { .compatible = "socionext,uniphier-sdhc" },
768 { /* sentinel */ }
769};
770
771U_BOOT_DRIVER(uniphier_mmc) = {
772 .name = "uniphier-mmc",
773 .id = UCLASS_MMC,
774 .of_match = uniphier_sd_match,
14f47234 775 .bind = uniphier_sd_bind,
a111bfbf 776 .probe = uniphier_sd_probe,
a111bfbf 777 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
14f47234 778 .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat),
3937404f 779 .ops = &uniphier_sd_ops,
a111bfbf 780};
"Das U-Boot" Source Tree