[people/ms/u-boot.git] / drivers / mmc / zynq_sdhci.c

/*
 * (C) Copyright 2013 Inc.
 *
 * Xilinx Zynq SD Host Controller Interface
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/sys_proto.h>

int zynq_sdhci_init(phys_addr_t regbase)
{
	struct sdhci_host *host = NULL;

	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
	if (!host) {
		printf("zynq_sdhci_init: sdhci_host malloc fail\n");
		return 1;
	}

	host->name = "zynq_sdhci";
	host->ioaddr = (void *)regbase;
	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
		       SDHCI_QUIRK_BROKEN_R1B;
	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);

	add_sdhci(host, 52000000, 52000000 >> 9);
	return 0;
}

#ifdef CONFIG_OF_CONTROL
int zynq_sdhci_of_init(const void *blob)
{
	int offset = 0;
	u32 ret = 0;
	phys_addr_t reg;

	debug("ZYNQ SDHCI: Initialization\n");

	do {
		offset = fdt_node_offset_by_compatible(blob, offset,
					"arasan,sdhci-8.9a");
		if (offset != -1) {
			reg = fdtdec_get_addr(blob, offset, "reg");
			if (reg != FDT_ADDR_T_NONE) {
				ret |= zynq_sdhci_init(reg);
			} else {
				debug("ZYNQ SDHCI: Can't get base address\n");
				return -1;
			}
		}
	} while (offset != -1);

	return ret;
}
#endif
Commit	Line	Data
293eb33f MS	1	/*
	2	* (C) Copyright 2013 Inc.
	3	*
	4	* Xilinx Zynq SD Host Controller Interface
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
293eb33f MS	7	*/
	8
	9	#include <common.h>
345d3c0f MS	10	#include <fdtdec.h>
345d3c0f MS	11	#include <libfdt.h>
293eb33f MS	12	#include <malloc.h>
	13	#include <sdhci.h>
	14	#include <asm/arch/sys_proto.h>
	15
38cd2d9c	16	int zynq_sdhci_init(phys_addr_t regbase)
293eb33f MS	17	{
	18	struct sdhci_host *host = NULL;
	19
	20	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
	21	if (!host) {
	22	printf("zynq_sdhci_init: sdhci_host malloc fail\n");
	23	return 1;
	24	}
	25
	26	host->name = "zynq_sdhci";
	27	host->ioaddr = (void *)regbase;
eddabd16	28	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD \|
f9ec45d1	29	SDHCI_QUIRK_BROKEN_R1B;
293eb33f MS	30	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
293eb33f MS	31
293eb33f MS	32	add_sdhci(host, 52000000, 52000000 >> 9);
	33	return 0;
	34	}
345d3c0f MS	35
	36	#ifdef CONFIG_OF_CONTROL
	37	int zynq_sdhci_of_init(const void *blob)
	38	{
	39	int offset = 0;
	40	u32 ret = 0;
38cd2d9c	41	phys_addr_t reg;
345d3c0f MS	42
	43	debug("ZYNQ SDHCI: Initialization\n");
	44
	45	do {
	46	offset = fdt_node_offset_by_compatible(blob, offset,
	47	"arasan,sdhci-8.9a");
	48	if (offset != -1) {
	49	reg = fdtdec_get_addr(blob, offset, "reg");
	50	if (reg != FDT_ADDR_T_NONE) {
	51	ret \|= zynq_sdhci_init(reg);
	52	} else {
	53	debug("ZYNQ SDHCI: Can't get base address\n");
	54	return -1;
	55	}
	56	}
	57	} while (offset != -1);
	58
	59	return ret;
	60	}
	61	#endif