[people/ms/u-boot.git] / drivers / mmc / zynq_sdhci.c

/*
 * (C) Copyright 2013 - 2015 Xilinx, Inc.
 *
 * Xilinx Zynq SD Host Controller Interface
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>

#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
# define CONFIG_ZYNQ_SDHCI_MIN_FREQ	0
#endif

struct arasan_sdhci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};

static int arasan_sdhci_probe(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct sdhci_host *host = dev_get_priv(dev);
	u32 caps;
	int ret;

	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
		       SDHCI_QUIRK_BROKEN_R1B;

#ifdef CONFIG_ZYNQ_HISPD_BROKEN
	host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif

	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	ret = sdhci_setup_cfg(&plat->cfg, dev->name,
			      caps, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
			      CONFIG_ZYNQ_SDHCI_MIN_FREQ, host->version,
			      host->quirks, 0);
	host->mmc = &plat->mmc;
	if (ret)
		return ret;
	host->mmc->priv = host;
	host->mmc->dev = dev;
	upriv->mmc = host->mmc;

	return sdhci_probe(dev);
}

static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
	struct sdhci_host *host = dev_get_priv(dev);

	host->name = dev->name;
	host->ioaddr = (void *)dev_get_addr(dev);

	return 0;
}

static int arasan_sdhci_bind(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
	int ret;

	ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
	if (ret)
		return ret;

	return 0;
}

static const struct udevice_id arasan_sdhci_ids[] = {
	{ .compatible = "arasan,sdhci-8.9a" },
	{ }
};

U_BOOT_DRIVER(arasan_sdhci_drv) = {
	.name		= "arasan_sdhci",
	.id		= UCLASS_MMC,
	.of_match	= arasan_sdhci_ids,
	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
	.ops		= &sdhci_ops,
	.bind		= arasan_sdhci_bind,
	.probe		= arasan_sdhci_probe,
	.priv_auto_alloc_size = sizeof(struct sdhci_host),
	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
};
Commit	Line	Data
293eb33f	1	/*
d9ae52c8	2	* (C) Copyright 2013 - 2015 Xilinx, Inc.
293eb33f MS	3	*
	4	* Xilinx Zynq SD Host Controller Interface
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
293eb33f MS	7	*/
	8
	9	#include <common.h>
d9ae52c8	10	#include <dm.h>
345d3c0f MS	11	#include <fdtdec.h>
345d3c0f MS	12	#include <libfdt.h>
293eb33f MS	13	#include <malloc.h>
293eb33f MS	14	#include <sdhci.h>
293eb33f	15
a57a4a5d SDPP	16	#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
	17	# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
	18	#endif
	19
329a449f SG	20	struct arasan_sdhci_plat {
	21	struct mmc_config cfg;
	22	struct mmc mmc;
	23	};
	24
d9ae52c8	25	static int arasan_sdhci_probe(struct udevice *dev)
293eb33f	26	{
329a449f	27	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
d9ae52c8 MS	28	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
d9ae52c8 MS	29	struct sdhci_host *host = dev_get_priv(dev);
329a449f SG	30	u32 caps;
329a449f SG	31	int ret;
293eb33f	32
eddabd16	33	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD \|
f9ec45d1	34	SDHCI_QUIRK_BROKEN_R1B;
b2156146 SDPP	35
	36	#ifdef CONFIG_ZYNQ_HISPD_BROKEN
	37	host->quirks \|= SDHCI_QUIRK_NO_HISPD_BIT;
	38	#endif
	39
293eb33f MS	40	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
293eb33f MS	41
329a449f	42	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
6a879ec8	43	ret = sdhci_setup_cfg(&plat->cfg, dev->name,
329a449f SG	44	caps, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
	45	CONFIG_ZYNQ_SDHCI_MIN_FREQ, host->version,
	46	host->quirks, 0);
	47	host->mmc = &plat->mmc;
	48	if (ret)
	49	return ret;
	50	host->mmc->priv = host;
cffe5d86	51	host->mmc->dev = dev;
329a449f	52	upriv->mmc = host->mmc;
d9ae52c8	53
329a449f	54	return sdhci_probe(dev);
293eb33f	55	}
d9ae52c8 MS	56
	57	static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
	58	{
	59	struct sdhci_host *host = dev_get_priv(dev);
	60
cacd1d2f	61	host->name = dev->name;
d9ae52c8 MS	62	host->ioaddr = (void *)dev_get_addr(dev);
	63
	64	return 0;
	65	}
	66
329a449f SG	67	static int arasan_sdhci_bind(struct udevice *dev)
	68	{
	69	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
	70	int ret;
	71
	72	ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
	73	if (ret)
	74	return ret;
	75
	76	return 0;
	77	}
	78
d9ae52c8 MS	79	static const struct udevice_id arasan_sdhci_ids[] = {
	80	{ .compatible = "arasan,sdhci-8.9a" },
	81	{ }
	82	};
	83
	84	U_BOOT_DRIVER(arasan_sdhci_drv) = {
	85	.name = "arasan_sdhci",
	86	.id = UCLASS_MMC,
	87	.of_match = arasan_sdhci_ids,
	88	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
329a449f SG	89	.ops = &sdhci_ops,
329a449f SG	90	.bind = arasan_sdhci_bind,
d9ae52c8 MS	91	.probe = arasan_sdhci_probe,
d9ae52c8 MS	92	.priv_auto_alloc_size = sizeof(struct sdhci_host),
329a449f	93	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
d9ae52c8	94	};