[thirdparty/u-boot.git] / drivers / mmc / zynq_sdhci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2013 - 2015 Xilinx, Inc.
 *
 * Xilinx Zynq SD Host Controller Interface
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include "mmc_private.h"
#include <linux/libfdt.h>
#include <malloc.h>
#include <sdhci.h>
#include <zynqmp_tap_delay.h>

DECLARE_GLOBAL_DATA_PTR;

struct arasan_sdhci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
	unsigned int f_max;
};

struct arasan_sdhci_priv {
	struct sdhci_host *host;
	u8 deviceid;
	u8 bank;
	u8 no_1p8;
	bool pwrseq;
};

#if defined(CONFIG_ARCH_ZYNQMP)
#define MMC_HS200_BUS_SPEED	5

static const u8 mode2timing[] = {
	[MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
	[SD_LEGACY] = UHS_SDR12_BUS_SPEED,
	[MMC_HS] = HIGH_SPEED_BUS_SPEED,
	[SD_HS] = HIGH_SPEED_BUS_SPEED,
	[MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
	[MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
	[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
	[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
	[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
	[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
	[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
	[MMC_HS_200] = MMC_HS200_BUS_SPEED,
};

#define SDHCI_HOST_CTRL2	0x3E
#define SDHCI_CTRL2_MODE_MASK	0x7
#define SDHCI_18V_SIGNAL	0x8
#define SDHCI_CTRL_EXEC_TUNING	0x0040
#define SDHCI_CTRL_TUNED_CLK	0x80
#define SDHCI_TUNING_LOOP_COUNT	40

static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
{
	u16 clk;
	unsigned long timeout;

	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	clk &= ~(SDHCI_CLOCK_CARD_EN);
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Issue DLL Reset */
	zynqmp_dll_reset(deviceid);

	/* Wait max 20 ms */
	timeout = 100;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
				& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			dev_err(mmc_dev(host->mmc),
				": Internal clock never stabilised.\n");
			return;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
}

static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
{
	struct mmc_cmd cmd;
	struct mmc_data data;
	u32 ctrl;
	struct sdhci_host *host;
	struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
	u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
	u8 deviceid;

	debug("%s\n", __func__);

	host = priv->host;
	deviceid = priv->deviceid;

	ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
	ctrl |= SDHCI_CTRL_EXEC_TUNING;
	sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);

	mdelay(1);

	arasan_zynqmp_dll_reset(host, deviceid);

	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);

	do {
		cmd.cmdidx = opcode;
		cmd.resp_type = MMC_RSP_R1;
		cmd.cmdarg = 0;

		data.blocksize = 64;
		data.blocks = 1;
		data.flags = MMC_DATA_READ;

		if (tuning_loop_counter-- == 0)
			break;

		if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
		    mmc->bus_width == 8)
			data.blocksize = 128;

		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
						    data.blocksize),
			     SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);

		mmc_send_cmd(mmc, &cmd, NULL);
		ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);

		if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
			udelay(1);

	} while (ctrl & SDHCI_CTRL_EXEC_TUNING);

	if (tuning_loop_counter < 0) {
		ctrl &= ~SDHCI_CTRL_TUNED_CLK;
		sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
	}

	if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
		printf("%s:Tuning failed\n", __func__);
		return -1;
	}

	udelay(1);
	arasan_zynqmp_dll_reset(host, deviceid);

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
		     SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}

static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
{
	struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
	struct mmc *mmc = (struct mmc *)host->mmc;
	u8 uhsmode;

	uhsmode = mode2timing[mmc->selected_mode];

	if (uhsmode >= UHS_SDR25_BUS_SPEED)
		arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
					   priv->bank);
}

static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
{
	struct mmc *mmc = (struct mmc *)host->mmc;
	u32 reg;

	if (!IS_SD(mmc))
		return;

	if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
		reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
		reg |= SDHCI_18V_SIGNAL;
		sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
	}

	if (mmc->selected_mode > SD_HS &&
	    mmc->selected_mode <= UHS_DDR50) {
		reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
		reg &= ~SDHCI_CTRL2_MODE_MASK;
		switch (mmc->selected_mode) {
		case UHS_SDR12:
			reg |= UHS_SDR12_BUS_SPEED;
			break;
		case UHS_SDR25:
			reg |= UHS_SDR25_BUS_SPEED;
			break;
		case UHS_SDR50:
			reg |= UHS_SDR50_BUS_SPEED;
			break;
		case UHS_SDR104:
			reg |= UHS_SDR104_BUS_SPEED;
			break;
		case UHS_DDR50:
			reg |= UHS_DDR50_BUS_SPEED;
			break;
		default:
			break;
		}
		sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
	}
}
#endif

#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
const struct sdhci_ops arasan_ops = {
	.platform_execute_tuning	= &arasan_sdhci_execute_tuning,
	.set_delay = &arasan_sdhci_set_tapdelay,
	.set_control_reg = &arasan_sdhci_set_control_reg,
};
#endif

static int arasan_sdhci_probe(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct arasan_sdhci_priv *priv = dev_get_priv(dev);
	struct sdhci_host *host;
	struct clk clk;
	unsigned long clock;
	int ret;

	host = priv->host;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0) {
		dev_err(dev, "failed to get clock\n");
		return ret;
	}

	clock = clk_get_rate(&clk);
	if (IS_ERR_VALUE(clock)) {
		dev_err(dev, "failed to get rate\n");
		return clock;
	}

	debug("%s: CLK %ld\n", __func__, clock);

	ret = clk_enable(&clk);
	if (ret && ret != -ENOSYS) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
		       SDHCI_QUIRK_BROKEN_R1B;

#ifdef CONFIG_ZYNQ_HISPD_BROKEN
	host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
#endif

	if (priv->no_1p8)
		host->quirks |= SDHCI_QUIRK_NO_1_8_V;

	host->max_clk = clock;

	ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
			      CONFIG_ZYNQ_SDHCI_MIN_FREQ);
	host->mmc = &plat->mmc;
	if (ret)
		return ret;
	host->mmc->priv = host;
	host->mmc->dev = dev;
	upriv->mmc = host->mmc;

	return sdhci_probe(dev);
}

static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
	struct arasan_sdhci_priv *priv = dev_get_priv(dev);

	priv->host = calloc(1, sizeof(struct sdhci_host));
	if (!priv->host)
		return -1;

	priv->host->name = dev->name;

#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
	priv->host->ops = &arasan_ops;
#endif

	priv->host->ioaddr = (void *)dev_read_addr(dev);
	if (IS_ERR(priv->host->ioaddr))
		return PTR_ERR(priv->host->ioaddr);

	priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
	priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
	priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");

	plat->f_max = dev_read_u32_default(dev, "max-frequency",
					   CONFIG_ZYNQ_SDHCI_MAX_FREQ);
	return 0;
}

static int arasan_sdhci_bind(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id arasan_sdhci_ids[] = {
	{ .compatible = "arasan,sdhci-8.9a" },
	{ }
};

U_BOOT_DRIVER(arasan_sdhci_drv) = {
	.name		= "arasan_sdhci",
	.id		= UCLASS_MMC,
	.of_match	= arasan_sdhci_ids,
	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
	.ops		= &sdhci_ops,
	.bind		= arasan_sdhci_bind,
	.probe		= arasan_sdhci_probe,
	.priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
293eb33f	2	/*
d9ae52c8	3	* (C) Copyright 2013 - 2015 Xilinx, Inc.
293eb33f MS	4	*
293eb33f MS	5	* Xilinx Zynq SD Host Controller Interface
293eb33f MS	6	*/
293eb33f MS	7
e0f4de1a	8	#include <clk.h>
293eb33f	9	#include <common.h>
d9ae52c8	10	#include <dm.h>
345d3c0f	11	#include <fdtdec.h>
d1f4e39d	12	#include "mmc_private.h"
b08c8c48	13	#include <linux/libfdt.h>
293eb33f MS	14	#include <malloc.h>
293eb33f MS	15	#include <sdhci.h>
d1f4e39d	16	#include <zynqmp_tap_delay.h>
293eb33f	17
61e745d1 SH	18	DECLARE_GLOBAL_DATA_PTR;
61e745d1 SH	19
329a449f SG	20	struct arasan_sdhci_plat {
	21	struct mmc_config cfg;
	22	struct mmc mmc;
61e745d1	23	unsigned int f_max;
329a449f SG	24	};
329a449f SG	25
d1f4e39d SDPP	26	struct arasan_sdhci_priv {
	27	struct sdhci_host *host;
	28	u8 deviceid;
	29	u8 bank;
	30	u8 no_1p8;
	31	bool pwrseq;
	32	};
	33
	34	#if defined(CONFIG_ARCH_ZYNQMP)
84333708 SDPP	35	#define MMC_HS200_BUS_SPEED 5
84333708 SDPP	36
d1f4e39d	37	static const u8 mode2timing[] = {
84333708 SDPP	38	[MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
	39	[SD_LEGACY] = UHS_SDR12_BUS_SPEED,
	40	[MMC_HS] = HIGH_SPEED_BUS_SPEED,
	41	[SD_HS] = HIGH_SPEED_BUS_SPEED,
	42	[MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
	43	[MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
	44	[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
	45	[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
	46	[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
	47	[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
	48	[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
	49	[MMC_HS_200] = MMC_HS200_BUS_SPEED,
d1f4e39d SDPP	50	};
	51
	52	#define SDHCI_HOST_CTRL2 0x3E
	53	#define SDHCI_CTRL2_MODE_MASK 0x7
	54	#define SDHCI_18V_SIGNAL 0x8
	55	#define SDHCI_CTRL_EXEC_TUNING 0x0040
	56	#define SDHCI_CTRL_TUNED_CLK 0x80
	57	#define SDHCI_TUNING_LOOP_COUNT 40
	58
	59	static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
	60	{
	61	u16 clk;
	62	unsigned long timeout;
	63
	64	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	65	clk &= ~(SDHCI_CLOCK_CARD_EN);
	66	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	67
	68	/* Issue DLL Reset */
	69	zynqmp_dll_reset(deviceid);
	70
	71	/* Wait max 20 ms */
	72	timeout = 100;
	73	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	74	& SDHCI_CLOCK_INT_STABLE)) {
	75	if (timeout == 0) {
	76	dev_err(mmc_dev(host->mmc),
	77	": Internal clock never stabilised.\n");
	78	return;
	79	}
	80	timeout--;
	81	udelay(1000);
	82	}
	83
	84	clk \|= SDHCI_CLOCK_CARD_EN;
	85	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	86	}
	87
	88	static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
	89	{
	90	struct mmc_cmd cmd;
	91	struct mmc_data data;
	92	u32 ctrl;
	93	struct sdhci_host *host;
	94	struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
	95	u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
	96	u8 deviceid;
	97
	98	debug("%s\n", __func__);
	99
	100	host = priv->host;
	101	deviceid = priv->deviceid;
	102
	103	ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
	104	ctrl \|= SDHCI_CTRL_EXEC_TUNING;
	105	sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
	106
	107	mdelay(1);
	108
	109	arasan_zynqmp_dll_reset(host, deviceid);
	110
	111	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
	112	sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
	113
114	do {
115	cmd.cmdidx = opcode;
116	cmd.resp_type = MMC_RSP_R1;
117	cmd.cmdarg = 0;
118
119	data.blocksize = 64;
120	data.blocks = 1;
121	data.flags = MMC_DATA_READ;
122
123	if (tuning_loop_counter-- == 0)
124	break;
125
126	if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
127	mmc->bus_width == 8)
128	data.blocksize = 128;
129
130	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
131	data.blocksize),
132	SDHCI_BLOCK_SIZE);
133	sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
134	sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
135
136	mmc_send_cmd(mmc, &cmd, NULL);
137	ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
138
139	if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
140	udelay(1);
141
142	} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
143
144	if (tuning_loop_counter < 0) {
145	ctrl &= ~SDHCI_CTRL_TUNED_CLK;
146	sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
147	}
148
149	if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
150	printf("%s:Tuning failed\n", __func__);
151	return -1;
152	}
153
154	udelay(1);
155	arasan_zynqmp_dll_reset(host, deviceid);
156
157	/* Enable only interrupts served by the SD controller */
158	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK,
159	SDHCI_INT_ENABLE);
160	/* Mask all sdhci interrupt sources */
161	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
162
163	return 0;
164	}
165
166	static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
167	{
168	struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
169	struct mmc mmc = (struct mmc )host->mmc;
170	u8 uhsmode;
171
d1f4e39d SDPP	172	uhsmode = mode2timing[mmc->selected_mode];
	173
	174	if (uhsmode >= UHS_SDR25_BUS_SPEED)
	175	arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
	176	priv->bank);
	177	}
	178
	179	static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
	180	{
	181	struct mmc mmc = (struct mmc )host->mmc;
	182	u32 reg;
	183
84333708 SDPP	184	if (!IS_SD(mmc))
	185	return;
	186
d1f4e39d SDPP	187	if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
	188	reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
	189	reg \|= SDHCI_18V_SIGNAL;
	190	sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
	191	}
	192
	193	if (mmc->selected_mode > SD_HS &&
	194	mmc->selected_mode <= UHS_DDR50) {
	195	reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
	196	reg &= ~SDHCI_CTRL2_MODE_MASK;
	197	switch (mmc->selected_mode) {
	198	case UHS_SDR12:
	199	reg \|= UHS_SDR12_BUS_SPEED;
	200	break;
	201	case UHS_SDR25:
	202	reg \|= UHS_SDR25_BUS_SPEED;
	203	break;
	204	case UHS_SDR50:
	205	reg \|= UHS_SDR50_BUS_SPEED;
	206	break;
	207	case UHS_SDR104:
	208	reg \|= UHS_SDR104_BUS_SPEED;
	209	break;
	210	case UHS_DDR50:
	211	reg \|= UHS_DDR50_BUS_SPEED;
	212	break;
	213	default:
	214	break;
	215	}
	216	sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
	217	}
	218	}
	219	#endif
	220
	221	#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
	222	const struct sdhci_ops arasan_ops = {
	223	.platform_execute_tuning = &arasan_sdhci_execute_tuning,
	224	.set_delay = &arasan_sdhci_set_tapdelay,
	225	.set_control_reg = &arasan_sdhci_set_control_reg,
	226	};
	227	#endif
	228
d9ae52c8	229	static int arasan_sdhci_probe(struct udevice *dev)
293eb33f	230	{
329a449f	231	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
d9ae52c8	232	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
d1f4e39d SDPP	233	struct arasan_sdhci_priv *priv = dev_get_priv(dev);
d1f4e39d SDPP	234	struct sdhci_host *host;
e0f4de1a SH	235	struct clk clk;
e0f4de1a SH	236	unsigned long clock;
329a449f	237	int ret;
293eb33f	238
d1f4e39d SDPP	239	host = priv->host;
d1f4e39d SDPP	240
e0f4de1a SH	241	ret = clk_get_by_index(dev, 0, &clk);
	242	if (ret < 0) {
	243	dev_err(dev, "failed to get clock\n");
	244	return ret;
	245	}
	246
	247	clock = clk_get_rate(&clk);
	248	if (IS_ERR_VALUE(clock)) {
	249	dev_err(dev, "failed to get rate\n");
	250	return clock;
	251	}
d1f4e39d	252
e0f4de1a SH	253	debug("%s: CLK %ld\n", __func__, clock);
	254
	255	ret = clk_enable(&clk);
	256	if (ret && ret != -ENOSYS) {
	257	dev_err(dev, "failed to enable clock\n");
	258	return ret;
	259	}
	260
eddabd16	261	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD \|
f9ec45d1	262	SDHCI_QUIRK_BROKEN_R1B;
b2156146 SDPP	263
b2156146 SDPP	264	#ifdef CONFIG_ZYNQ_HISPD_BROKEN
47819216	265	host->quirks \|= SDHCI_QUIRK_BROKEN_HISPD_MODE;
b2156146 SDPP	266	#endif
b2156146 SDPP	267
d1f4e39d SDPP	268	if (priv->no_1p8)
	269	host->quirks \|= SDHCI_QUIRK_NO_1_8_V;
	270
e0f4de1a	271	host->max_clk = clock;
6d0e34bf	272
61e745d1	273	ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
14bed52d	274	CONFIG_ZYNQ_SDHCI_MIN_FREQ);
329a449f SG	275	host->mmc = &plat->mmc;
	276	if (ret)
	277	return ret;
	278	host->mmc->priv = host;
cffe5d86	279	host->mmc->dev = dev;
329a449f	280	upriv->mmc = host->mmc;
d9ae52c8	281
329a449f	282	return sdhci_probe(dev);
293eb33f	283	}
d9ae52c8 MS	284
	285	static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
	286	{
61e745d1	287	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
d1f4e39d SDPP	288	struct arasan_sdhci_priv *priv = dev_get_priv(dev);
	289
	290	priv->host = calloc(1, sizeof(struct sdhci_host));
	291	if (!priv->host)
	292	return -1;
d9ae52c8	293
d1f4e39d	294	priv->host->name = dev->name;
d1f4e39d SDPP	295
	296	#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
	297	priv->host->ops = &arasan_ops;
	298	#endif
d9ae52c8	299
458e8d80 MS	300	priv->host->ioaddr = (void *)dev_read_addr(dev);
	301	if (IS_ERR(priv->host->ioaddr))
	302	return PTR_ERR(priv->host->ioaddr);
61e745d1	303
458e8d80 MS	304	priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
	305	priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
	306	priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
	307
	308	plat->f_max = dev_read_u32_default(dev, "max-frequency",
	309	CONFIG_ZYNQ_SDHCI_MAX_FREQ);
d9ae52c8 MS	310	return 0;
	311	}
	312
329a449f SG	313	static int arasan_sdhci_bind(struct udevice *dev)
	314	{
	315	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
329a449f	316
24f5aec3	317	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
329a449f SG	318	}
329a449f SG	319
d9ae52c8 MS	320	static const struct udevice_id arasan_sdhci_ids[] = {
	321	{ .compatible = "arasan,sdhci-8.9a" },
	322	{ }
	323	};
	324
	325	U_BOOT_DRIVER(arasan_sdhci_drv) = {
	326	.name = "arasan_sdhci",
	327	.id = UCLASS_MMC,
	328	.of_match = arasan_sdhci_ids,
	329	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
329a449f SG	330	.ops = &sdhci_ops,
329a449f SG	331	.bind = arasan_sdhci_bind,
d9ae52c8	332	.probe = arasan_sdhci_probe,
d1f4e39d	333	.priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
329a449f	334	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
d9ae52c8	335	};