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5653fc33 | 1 | /* |
bf9e3b38 | 2 | * (C) Copyright 2002-2004 |
5653fc33 WD |
3 | * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
4 | * | |
5 | * Copyright (C) 2003 Arabella Software Ltd. | |
6 | * Yuli Barcohen <yuli@arabellasw.com> | |
5653fc33 | 7 | * |
bf9e3b38 WD |
8 | * Copyright (C) 2004 |
9 | * Ed Okerson | |
260421a2 SR |
10 | * |
11 | * Copyright (C) 2006 | |
12 | * Tolunay Orkun <listmember@orkun.us> | |
bf9e3b38 | 13 | * |
5653fc33 WD |
14 | * See file CREDITS for list of people who contributed to this |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 | * MA 02111-1307 USA | |
31 | * | |
5653fc33 WD |
32 | */ |
33 | ||
34 | /* The DEBUG define must be before common to enable debugging */ | |
2d1a537d WD |
35 | /* #define DEBUG */ |
36 | ||
5653fc33 WD |
37 | #include <common.h> |
38 | #include <asm/processor.h> | |
3a197b2f | 39 | #include <asm/io.h> |
4c0d4c3b | 40 | #include <asm/byteorder.h> |
2a8af187 | 41 | #include <environment.h> |
028ab6b5 | 42 | |
5653fc33 | 43 | /* |
7e5b9b47 HS |
44 | * This file implements a Common Flash Interface (CFI) driver for |
45 | * U-Boot. | |
46 | * | |
47 | * The width of the port and the width of the chips are determined at | |
48 | * initialization. These widths are used to calculate the address for | |
49 | * access CFI data structures. | |
5653fc33 WD |
50 | * |
51 | * References | |
52 | * JEDEC Standard JESD68 - Common Flash Interface (CFI) | |
53 | * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes | |
54 | * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets | |
55 | * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet | |
260421a2 SR |
56 | * AMD CFI Specification, Release 2.0 December 1, 2001 |
57 | * AMD/Spansion Application Note: Migration from Single-byte to Three-byte | |
58 | * Device IDs, Publication Number 25538 Revision A, November 8, 2001 | |
5653fc33 | 59 | * |
6d0f6bcf | 60 | * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between |
d0b6e140 | 61 | * reading and writing ... (yes there is such a Hardware). |
5653fc33 WD |
62 | */ |
63 | ||
6d0f6bcf JCPV |
64 | #ifndef CONFIG_SYS_FLASH_BANKS_LIST |
65 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
bf9e3b38 WD |
66 | #endif |
67 | ||
5653fc33 WD |
68 | #define FLASH_CMD_CFI 0x98 |
69 | #define FLASH_CMD_READ_ID 0x90 | |
70 | #define FLASH_CMD_RESET 0xff | |
71 | #define FLASH_CMD_BLOCK_ERASE 0x20 | |
72 | #define FLASH_CMD_ERASE_CONFIRM 0xD0 | |
73 | #define FLASH_CMD_WRITE 0x40 | |
74 | #define FLASH_CMD_PROTECT 0x60 | |
75 | #define FLASH_CMD_PROTECT_SET 0x01 | |
76 | #define FLASH_CMD_PROTECT_CLEAR 0xD0 | |
77 | #define FLASH_CMD_CLEAR_STATUS 0x50 | |
9c048b52 | 78 | #define FLASH_CMD_READ_STATUS 0x70 |
bf9e3b38 | 79 | #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 |
9c048b52 | 80 | #define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 |
bf9e3b38 | 81 | #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 |
5653fc33 WD |
82 | |
83 | #define FLASH_STATUS_DONE 0x80 | |
84 | #define FLASH_STATUS_ESS 0x40 | |
85 | #define FLASH_STATUS_ECLBS 0x20 | |
86 | #define FLASH_STATUS_PSLBS 0x10 | |
87 | #define FLASH_STATUS_VPENS 0x08 | |
88 | #define FLASH_STATUS_PSS 0x04 | |
89 | #define FLASH_STATUS_DPS 0x02 | |
90 | #define FLASH_STATUS_R 0x01 | |
91 | #define FLASH_STATUS_PROTECT 0x01 | |
92 | ||
93 | #define AMD_CMD_RESET 0xF0 | |
94 | #define AMD_CMD_WRITE 0xA0 | |
95 | #define AMD_CMD_ERASE_START 0x80 | |
96 | #define AMD_CMD_ERASE_SECTOR 0x30 | |
855a496f WD |
97 | #define AMD_CMD_UNLOCK_START 0xAA |
98 | #define AMD_CMD_UNLOCK_ACK 0x55 | |
79b4cda0 SR |
99 | #define AMD_CMD_WRITE_TO_BUFFER 0x25 |
100 | #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 | |
5653fc33 WD |
101 | |
102 | #define AMD_STATUS_TOGGLE 0x40 | |
103 | #define AMD_STATUS_ERROR 0x20 | |
79b4cda0 | 104 | |
bc9019e1 RC |
105 | #define ATM_CMD_UNLOCK_SECT 0x70 |
106 | #define ATM_CMD_SOFTLOCK_START 0x80 | |
107 | #define ATM_CMD_LOCK_SECT 0x40 | |
108 | ||
260421a2 SR |
109 | #define FLASH_OFFSET_MANUFACTURER_ID 0x00 |
110 | #define FLASH_OFFSET_DEVICE_ID 0x01 | |
111 | #define FLASH_OFFSET_DEVICE_ID2 0x0E | |
112 | #define FLASH_OFFSET_DEVICE_ID3 0x0F | |
5653fc33 | 113 | #define FLASH_OFFSET_CFI 0x55 |
92eb729b | 114 | #define FLASH_OFFSET_CFI_ALT 0x555 |
5653fc33 | 115 | #define FLASH_OFFSET_CFI_RESP 0x10 |
bf9e3b38 | 116 | #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 |
7e5b9b47 HS |
117 | /* extended query table primary address */ |
118 | #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 | |
5653fc33 | 119 | #define FLASH_OFFSET_WTOUT 0x1F |
bf9e3b38 | 120 | #define FLASH_OFFSET_WBTOUT 0x20 |
5653fc33 | 121 | #define FLASH_OFFSET_ETOUT 0x21 |
bf9e3b38 | 122 | #define FLASH_OFFSET_CETOUT 0x22 |
5653fc33 | 123 | #define FLASH_OFFSET_WMAX_TOUT 0x23 |
bf9e3b38 | 124 | #define FLASH_OFFSET_WBMAX_TOUT 0x24 |
5653fc33 | 125 | #define FLASH_OFFSET_EMAX_TOUT 0x25 |
bf9e3b38 | 126 | #define FLASH_OFFSET_CEMAX_TOUT 0x26 |
5653fc33 | 127 | #define FLASH_OFFSET_SIZE 0x27 |
bf9e3b38 WD |
128 | #define FLASH_OFFSET_INTERFACE 0x28 |
129 | #define FLASH_OFFSET_BUFFER_SIZE 0x2A | |
5653fc33 WD |
130 | #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C |
131 | #define FLASH_OFFSET_ERASE_REGIONS 0x2D | |
132 | #define FLASH_OFFSET_PROTECT 0x02 | |
bf9e3b38 WD |
133 | #define FLASH_OFFSET_USER_PROTECTION 0x85 |
134 | #define FLASH_OFFSET_INTEL_PROTECTION 0x81 | |
5653fc33 | 135 | |
260421a2 SR |
136 | #define CFI_CMDSET_NONE 0 |
137 | #define CFI_CMDSET_INTEL_EXTENDED 1 | |
138 | #define CFI_CMDSET_AMD_STANDARD 2 | |
139 | #define CFI_CMDSET_INTEL_STANDARD 3 | |
140 | #define CFI_CMDSET_AMD_EXTENDED 4 | |
141 | #define CFI_CMDSET_MITSU_STANDARD 256 | |
142 | #define CFI_CMDSET_MITSU_EXTENDED 257 | |
143 | #define CFI_CMDSET_SST 258 | |
9c048b52 | 144 | #define CFI_CMDSET_INTEL_PROG_REGIONS 512 |
5653fc33 | 145 | |
6d0f6bcf | 146 | #ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ |
f7d1572b | 147 | # undef FLASH_CMD_RESET |
260421a2 | 148 | # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ |
f7d1572b WD |
149 | #endif |
150 | ||
5653fc33 WD |
151 | typedef union { |
152 | unsigned char c; | |
153 | unsigned short w; | |
154 | unsigned long l; | |
155 | unsigned long long ll; | |
156 | } cfiword_t; | |
157 | ||
260421a2 | 158 | #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ |
5653fc33 | 159 | |
7e5b9b47 | 160 | static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; |
6ea808ef | 161 | static uint flash_verbose = 1; |
92eb729b | 162 | |
6d0f6bcf JCPV |
163 | /* use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined */ |
164 | #ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT | |
165 | # define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT | |
e6f2e902 | 166 | #else |
6d0f6bcf | 167 | # define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS |
e6f2e902 | 168 | #endif |
5653fc33 | 169 | |
2a112b23 WD |
170 | flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ |
171 | ||
79b4cda0 SR |
172 | /* |
173 | * Check if chip width is defined. If not, start detecting with 8bit. | |
174 | */ | |
6d0f6bcf JCPV |
175 | #ifndef CONFIG_SYS_FLASH_CFI_WIDTH |
176 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
79b4cda0 SR |
177 | #endif |
178 | ||
e23741f4 HS |
179 | /* CFI standard query structure */ |
180 | struct cfi_qry { | |
181 | u8 qry[3]; | |
182 | u16 p_id; | |
183 | u16 p_adr; | |
184 | u16 a_id; | |
185 | u16 a_adr; | |
186 | u8 vcc_min; | |
187 | u8 vcc_max; | |
188 | u8 vpp_min; | |
189 | u8 vpp_max; | |
190 | u8 word_write_timeout_typ; | |
191 | u8 buf_write_timeout_typ; | |
192 | u8 block_erase_timeout_typ; | |
193 | u8 chip_erase_timeout_typ; | |
194 | u8 word_write_timeout_max; | |
195 | u8 buf_write_timeout_max; | |
196 | u8 block_erase_timeout_max; | |
197 | u8 chip_erase_timeout_max; | |
198 | u8 dev_size; | |
199 | u16 interface_desc; | |
200 | u16 max_buf_write_size; | |
201 | u8 num_erase_regions; | |
202 | u32 erase_region_info[NUM_ERASE_REGIONS]; | |
203 | } __attribute__((packed)); | |
204 | ||
205 | struct cfi_pri_hdr { | |
206 | u8 pri[3]; | |
207 | u8 major_version; | |
208 | u8 minor_version; | |
209 | } __attribute__((packed)); | |
210 | ||
45aa5a7f | 211 | static void __flash_write8(u8 value, void *addr) |
cdbaefb5 HS |
212 | { |
213 | __raw_writeb(value, addr); | |
214 | } | |
215 | ||
45aa5a7f | 216 | static void __flash_write16(u16 value, void *addr) |
cdbaefb5 HS |
217 | { |
218 | __raw_writew(value, addr); | |
219 | } | |
220 | ||
45aa5a7f | 221 | static void __flash_write32(u32 value, void *addr) |
cdbaefb5 HS |
222 | { |
223 | __raw_writel(value, addr); | |
224 | } | |
225 | ||
45aa5a7f | 226 | static void __flash_write64(u64 value, void *addr) |
cdbaefb5 HS |
227 | { |
228 | /* No architectures currently implement __raw_writeq() */ | |
229 | *(volatile u64 *)addr = value; | |
230 | } | |
231 | ||
45aa5a7f | 232 | static u8 __flash_read8(void *addr) |
cdbaefb5 HS |
233 | { |
234 | return __raw_readb(addr); | |
235 | } | |
236 | ||
45aa5a7f | 237 | static u16 __flash_read16(void *addr) |
cdbaefb5 HS |
238 | { |
239 | return __raw_readw(addr); | |
240 | } | |
241 | ||
45aa5a7f | 242 | static u32 __flash_read32(void *addr) |
cdbaefb5 HS |
243 | { |
244 | return __raw_readl(addr); | |
245 | } | |
246 | ||
97bf85d7 | 247 | static u64 __flash_read64(void *addr) |
cdbaefb5 HS |
248 | { |
249 | /* No architectures currently implement __raw_readq() */ | |
250 | return *(volatile u64 *)addr; | |
251 | } | |
252 | ||
45aa5a7f SR |
253 | #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
254 | void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8"))); | |
255 | void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16"))); | |
256 | void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32"))); | |
257 | void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64"))); | |
258 | u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8"))); | |
259 | u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16"))); | |
260 | u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32"))); | |
97bf85d7 | 261 | u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); |
45aa5a7f SR |
262 | #else |
263 | #define flash_write8 __flash_write8 | |
264 | #define flash_write16 __flash_write16 | |
265 | #define flash_write32 __flash_write32 | |
266 | #define flash_write64 __flash_write64 | |
267 | #define flash_read8 __flash_read8 | |
268 | #define flash_read16 __flash_read16 | |
269 | #define flash_read32 __flash_read32 | |
270 | #define flash_read64 __flash_read64 | |
271 | #endif | |
97bf85d7 | 272 | |
5653fc33 | 273 | /*----------------------------------------------------------------------- |
5653fc33 | 274 | */ |
6d0f6bcf | 275 | #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) |
4f975678 | 276 | flash_info_t *flash_get_info(ulong base) |
be60a902 HS |
277 | { |
278 | int i; | |
279 | flash_info_t * info = 0; | |
5653fc33 | 280 | |
6d0f6bcf | 281 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { |
be60a902 HS |
282 | info = & flash_info[i]; |
283 | if (info->size && info->start[0] <= base && | |
284 | base <= info->start[0] + info->size - 1) | |
285 | break; | |
286 | } | |
5653fc33 | 287 | |
6d0f6bcf | 288 | return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; |
be60a902 | 289 | } |
5653fc33 WD |
290 | #endif |
291 | ||
12d30aa7 HS |
292 | unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) |
293 | { | |
294 | if (sect != (info->sector_count - 1)) | |
295 | return info->start[sect + 1] - info->start[sect]; | |
296 | else | |
297 | return info->start[0] + info->size - info->start[sect]; | |
298 | } | |
299 | ||
bf9e3b38 WD |
300 | /*----------------------------------------------------------------------- |
301 | * create an address based on the offset and the port width | |
302 | */ | |
12d30aa7 HS |
303 | static inline void * |
304 | flash_map (flash_info_t * info, flash_sect_t sect, uint offset) | |
bf9e3b38 | 305 | { |
12d30aa7 HS |
306 | unsigned int byte_offset = offset * info->portwidth; |
307 | ||
09ce9921 | 308 | return (void *)(info->start[sect] + byte_offset); |
12d30aa7 HS |
309 | } |
310 | ||
311 | static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, | |
312 | unsigned int offset, void *addr) | |
313 | { | |
bf9e3b38 WD |
314 | } |
315 | ||
be60a902 HS |
316 | /*----------------------------------------------------------------------- |
317 | * make a proper sized command based on the port and chip widths | |
318 | */ | |
7288f972 | 319 | static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) |
be60a902 HS |
320 | { |
321 | int i; | |
93c56f21 VL |
322 | int cword_offset; |
323 | int cp_offset; | |
6d0f6bcf | 324 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
340ccb26 SS |
325 | u32 cmd_le = cpu_to_le32(cmd); |
326 | #endif | |
93c56f21 | 327 | uchar val; |
be60a902 HS |
328 | uchar *cp = (uchar *) cmdbuf; |
329 | ||
93c56f21 VL |
330 | for (i = info->portwidth; i > 0; i--){ |
331 | cword_offset = (info->portwidth-i)%info->chipwidth; | |
6d0f6bcf | 332 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
93c56f21 | 333 | cp_offset = info->portwidth - i; |
340ccb26 | 334 | val = *((uchar*)&cmd_le + cword_offset); |
be60a902 | 335 | #else |
93c56f21 | 336 | cp_offset = i - 1; |
7288f972 | 337 | val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1); |
be60a902 | 338 | #endif |
7288f972 | 339 | cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; |
93c56f21 | 340 | } |
be60a902 HS |
341 | } |
342 | ||
5653fc33 | 343 | #ifdef DEBUG |
bf9e3b38 WD |
344 | /*----------------------------------------------------------------------- |
345 | * Debug support | |
346 | */ | |
3055793b | 347 | static void print_longlong (char *str, unsigned long long data) |
5653fc33 WD |
348 | { |
349 | int i; | |
350 | char *cp; | |
bf9e3b38 | 351 | |
657f2062 | 352 | cp = (char *) &data; |
bf9e3b38 WD |
353 | for (i = 0; i < 8; i++) |
354 | sprintf (&str[i * 2], "%2.2x", *cp++); | |
355 | } | |
be60a902 | 356 | |
e23741f4 | 357 | static void flash_printqry (struct cfi_qry *qry) |
bf9e3b38 | 358 | { |
e23741f4 | 359 | u8 *p = (u8 *)qry; |
bf9e3b38 WD |
360 | int x, y; |
361 | ||
e23741f4 HS |
362 | for (x = 0; x < sizeof(struct cfi_qry); x += 16) { |
363 | debug("%02x : ", x); | |
364 | for (y = 0; y < 16; y++) | |
365 | debug("%2.2x ", p[x + y]); | |
366 | debug(" "); | |
bf9e3b38 | 367 | for (y = 0; y < 16; y++) { |
e23741f4 HS |
368 | unsigned char c = p[x + y]; |
369 | if (c >= 0x20 && c <= 0x7e) | |
370 | debug("%c", c); | |
371 | else | |
372 | debug("."); | |
bf9e3b38 | 373 | } |
e23741f4 | 374 | debug("\n"); |
bf9e3b38 | 375 | } |
5653fc33 WD |
376 | } |
377 | #endif | |
378 | ||
379 | ||
5653fc33 WD |
380 | /*----------------------------------------------------------------------- |
381 | * read a character at a port width address | |
382 | */ | |
3055793b | 383 | static inline uchar flash_read_uchar (flash_info_t * info, uint offset) |
5653fc33 WD |
384 | { |
385 | uchar *cp; | |
12d30aa7 | 386 | uchar retval; |
bf9e3b38 | 387 | |
12d30aa7 | 388 | cp = flash_map (info, 0, offset); |
6d0f6bcf | 389 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
12d30aa7 | 390 | retval = flash_read8(cp); |
bf9e3b38 | 391 | #else |
12d30aa7 | 392 | retval = flash_read8(cp + info->portwidth - 1); |
bf9e3b38 | 393 | #endif |
12d30aa7 HS |
394 | flash_unmap (info, 0, offset, cp); |
395 | return retval; | |
5653fc33 WD |
396 | } |
397 | ||
90447ecb TK |
398 | /*----------------------------------------------------------------------- |
399 | * read a word at a port width address, assume 16bit bus | |
400 | */ | |
401 | static inline ushort flash_read_word (flash_info_t * info, uint offset) | |
402 | { | |
403 | ushort *addr, retval; | |
404 | ||
405 | addr = flash_map (info, 0, offset); | |
406 | retval = flash_read16 (addr); | |
407 | flash_unmap (info, 0, offset, addr); | |
408 | return retval; | |
409 | } | |
410 | ||
411 | ||
5653fc33 | 412 | /*----------------------------------------------------------------------- |
260421a2 | 413 | * read a long word by picking the least significant byte of each maximum |
5653fc33 WD |
414 | * port size word. Swap for ppc format. |
415 | */ | |
3055793b HS |
416 | static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, |
417 | uint offset) | |
5653fc33 | 418 | { |
bf9e3b38 WD |
419 | uchar *addr; |
420 | ulong retval; | |
421 | ||
422 | #ifdef DEBUG | |
423 | int x; | |
424 | #endif | |
12d30aa7 | 425 | addr = flash_map (info, sect, offset); |
5653fc33 | 426 | |
bf9e3b38 WD |
427 | #ifdef DEBUG |
428 | debug ("long addr is at %p info->portwidth = %d\n", addr, | |
429 | info->portwidth); | |
430 | for (x = 0; x < 4 * info->portwidth; x++) { | |
12d30aa7 | 431 | debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); |
bf9e3b38 WD |
432 | } |
433 | #endif | |
6d0f6bcf | 434 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
12d30aa7 HS |
435 | retval = ((flash_read8(addr) << 16) | |
436 | (flash_read8(addr + info->portwidth) << 24) | | |
437 | (flash_read8(addr + 2 * info->portwidth)) | | |
438 | (flash_read8(addr + 3 * info->portwidth) << 8)); | |
bf9e3b38 | 439 | #else |
12d30aa7 HS |
440 | retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | |
441 | (flash_read8(addr + info->portwidth - 1) << 16) | | |
442 | (flash_read8(addr + 4 * info->portwidth - 1) << 8) | | |
443 | (flash_read8(addr + 3 * info->portwidth - 1))); | |
bf9e3b38 | 444 | #endif |
12d30aa7 HS |
445 | flash_unmap(info, sect, offset, addr); |
446 | ||
bf9e3b38 | 447 | return retval; |
5653fc33 WD |
448 | } |
449 | ||
be60a902 HS |
450 | /* |
451 | * Write a proper sized command to the correct address | |
81b20ccc | 452 | */ |
be60a902 | 453 | static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, |
7288f972 | 454 | uint offset, u32 cmd) |
81b20ccc | 455 | { |
7e5b9b47 | 456 | |
cdbaefb5 | 457 | void *addr; |
be60a902 | 458 | cfiword_t cword; |
81b20ccc | 459 | |
12d30aa7 | 460 | addr = flash_map (info, sect, offset); |
be60a902 HS |
461 | flash_make_cmd (info, cmd, &cword); |
462 | switch (info->portwidth) { | |
463 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 464 | debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, |
be60a902 | 465 | cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
cdbaefb5 | 466 | flash_write8(cword.c, addr); |
be60a902 HS |
467 | break; |
468 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 469 | debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, |
be60a902 HS |
470 | cmd, cword.w, |
471 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
cdbaefb5 | 472 | flash_write16(cword.w, addr); |
be60a902 HS |
473 | break; |
474 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 475 | debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, |
be60a902 HS |
476 | cmd, cword.l, |
477 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
cdbaefb5 | 478 | flash_write32(cword.l, addr); |
be60a902 HS |
479 | break; |
480 | case FLASH_CFI_64BIT: | |
481 | #ifdef DEBUG | |
482 | { | |
483 | char str[20]; | |
7e5b9b47 | 484 | |
be60a902 HS |
485 | print_longlong (str, cword.ll); |
486 | ||
487 | debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", | |
cdbaefb5 | 488 | addr, cmd, str, |
be60a902 | 489 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
81b20ccc | 490 | } |
be60a902 | 491 | #endif |
cdbaefb5 | 492 | flash_write64(cword.ll, addr); |
be60a902 | 493 | break; |
81b20ccc | 494 | } |
be60a902 HS |
495 | |
496 | /* Ensure all the instructions are fully finished */ | |
497 | sync(); | |
12d30aa7 HS |
498 | |
499 | flash_unmap(info, sect, offset, addr); | |
81b20ccc | 500 | } |
be60a902 HS |
501 | |
502 | static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) | |
81b20ccc | 503 | { |
be60a902 HS |
504 | flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); |
505 | flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); | |
81b20ccc | 506 | } |
81b20ccc | 507 | |
5653fc33 WD |
508 | /*----------------------------------------------------------------------- |
509 | */ | |
be60a902 HS |
510 | static int flash_isequal (flash_info_t * info, flash_sect_t sect, |
511 | uint offset, uchar cmd) | |
5653fc33 | 512 | { |
cdbaefb5 | 513 | void *addr; |
be60a902 HS |
514 | cfiword_t cword; |
515 | int retval; | |
5653fc33 | 516 | |
12d30aa7 | 517 | addr = flash_map (info, sect, offset); |
be60a902 | 518 | flash_make_cmd (info, cmd, &cword); |
2662b40c | 519 | |
cdbaefb5 | 520 | debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); |
be60a902 HS |
521 | switch (info->portwidth) { |
522 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
523 | debug ("is= %x %x\n", flash_read8(addr), cword.c); |
524 | retval = (flash_read8(addr) == cword.c); | |
be60a902 HS |
525 | break; |
526 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
527 | debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); |
528 | retval = (flash_read16(addr) == cword.w); | |
be60a902 HS |
529 | break; |
530 | case FLASH_CFI_32BIT: | |
52514699 | 531 | debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l); |
cdbaefb5 | 532 | retval = (flash_read32(addr) == cword.l); |
be60a902 HS |
533 | break; |
534 | case FLASH_CFI_64BIT: | |
535 | #ifdef DEBUG | |
536 | { | |
537 | char str1[20]; | |
538 | char str2[20]; | |
81b20ccc | 539 | |
cdbaefb5 | 540 | print_longlong (str1, flash_read64(addr)); |
be60a902 HS |
541 | print_longlong (str2, cword.ll); |
542 | debug ("is= %s %s\n", str1, str2); | |
5653fc33 | 543 | } |
be60a902 | 544 | #endif |
cdbaefb5 | 545 | retval = (flash_read64(addr) == cword.ll); |
be60a902 HS |
546 | break; |
547 | default: | |
548 | retval = 0; | |
549 | break; | |
550 | } | |
12d30aa7 HS |
551 | flash_unmap(info, sect, offset, addr); |
552 | ||
be60a902 HS |
553 | return retval; |
554 | } | |
79b4cda0 | 555 | |
be60a902 HS |
556 | /*----------------------------------------------------------------------- |
557 | */ | |
558 | static int flash_isset (flash_info_t * info, flash_sect_t sect, | |
559 | uint offset, uchar cmd) | |
560 | { | |
cdbaefb5 | 561 | void *addr; |
be60a902 HS |
562 | cfiword_t cword; |
563 | int retval; | |
2662b40c | 564 | |
12d30aa7 | 565 | addr = flash_map (info, sect, offset); |
be60a902 HS |
566 | flash_make_cmd (info, cmd, &cword); |
567 | switch (info->portwidth) { | |
568 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 569 | retval = ((flash_read8(addr) & cword.c) == cword.c); |
be60a902 HS |
570 | break; |
571 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 572 | retval = ((flash_read16(addr) & cword.w) == cword.w); |
be60a902 HS |
573 | break; |
574 | case FLASH_CFI_32BIT: | |
47cc23cb | 575 | retval = ((flash_read32(addr) & cword.l) == cword.l); |
be60a902 HS |
576 | break; |
577 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 578 | retval = ((flash_read64(addr) & cword.ll) == cword.ll); |
be60a902 HS |
579 | break; |
580 | default: | |
581 | retval = 0; | |
582 | break; | |
583 | } | |
12d30aa7 HS |
584 | flash_unmap(info, sect, offset, addr); |
585 | ||
be60a902 HS |
586 | return retval; |
587 | } | |
2662b40c | 588 | |
be60a902 HS |
589 | /*----------------------------------------------------------------------- |
590 | */ | |
591 | static int flash_toggle (flash_info_t * info, flash_sect_t sect, | |
592 | uint offset, uchar cmd) | |
593 | { | |
cdbaefb5 | 594 | void *addr; |
be60a902 HS |
595 | cfiword_t cword; |
596 | int retval; | |
656658dd | 597 | |
12d30aa7 | 598 | addr = flash_map (info, sect, offset); |
be60a902 HS |
599 | flash_make_cmd (info, cmd, &cword); |
600 | switch (info->portwidth) { | |
601 | case FLASH_CFI_8BIT: | |
fb8c061e | 602 | retval = flash_read8(addr) != flash_read8(addr); |
be60a902 HS |
603 | break; |
604 | case FLASH_CFI_16BIT: | |
fb8c061e | 605 | retval = flash_read16(addr) != flash_read16(addr); |
be60a902 HS |
606 | break; |
607 | case FLASH_CFI_32BIT: | |
fb8c061e | 608 | retval = flash_read32(addr) != flash_read32(addr); |
be60a902 HS |
609 | break; |
610 | case FLASH_CFI_64BIT: | |
9abda6ba WD |
611 | retval = ( (flash_read32( addr ) != flash_read32( addr )) || |
612 | (flash_read32(addr+4) != flash_read32(addr+4)) ); | |
be60a902 HS |
613 | break; |
614 | default: | |
615 | retval = 0; | |
616 | break; | |
617 | } | |
12d30aa7 HS |
618 | flash_unmap(info, sect, offset, addr); |
619 | ||
be60a902 | 620 | return retval; |
5653fc33 WD |
621 | } |
622 | ||
be60a902 HS |
623 | /* |
624 | * flash_is_busy - check to see if the flash is busy | |
625 | * | |
626 | * This routine checks the status of the chip and returns true if the | |
627 | * chip is busy. | |
7680c140 | 628 | */ |
be60a902 | 629 | static int flash_is_busy (flash_info_t * info, flash_sect_t sect) |
7680c140 | 630 | { |
be60a902 | 631 | int retval; |
7680c140 | 632 | |
be60a902 | 633 | switch (info->vendor) { |
9c048b52 | 634 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
635 | case CFI_CMDSET_INTEL_STANDARD: |
636 | case CFI_CMDSET_INTEL_EXTENDED: | |
637 | retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); | |
638 | break; | |
639 | case CFI_CMDSET_AMD_STANDARD: | |
640 | case CFI_CMDSET_AMD_EXTENDED: | |
641 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
642 | case CFI_CMDSET_AMD_LEGACY: | |
643 | #endif | |
644 | retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); | |
645 | break; | |
646 | default: | |
647 | retval = 0; | |
7680c140 | 648 | } |
be60a902 HS |
649 | debug ("flash_is_busy: %d\n", retval); |
650 | return retval; | |
7680c140 WD |
651 | } |
652 | ||
5653fc33 | 653 | /*----------------------------------------------------------------------- |
be60a902 HS |
654 | * wait for XSR.7 to be set. Time out with an error if it does not. |
655 | * This routine does not set the flash to read-array mode. | |
5653fc33 | 656 | */ |
be60a902 HS |
657 | static int flash_status_check (flash_info_t * info, flash_sect_t sector, |
658 | ulong tout, char *prompt) | |
5653fc33 | 659 | { |
be60a902 | 660 | ulong start; |
5653fc33 | 661 | |
6d0f6bcf JCPV |
662 | #if CONFIG_SYS_HZ != 1000 |
663 | tout *= CONFIG_SYS_HZ/1000; | |
be60a902 | 664 | #endif |
5653fc33 | 665 | |
be60a902 HS |
666 | /* Wait for command completion */ |
667 | start = get_timer (0); | |
668 | while (flash_is_busy (info, sector)) { | |
669 | if (get_timer (start) > tout) { | |
670 | printf ("Flash %s timeout at address %lx data %lx\n", | |
671 | prompt, info->start[sector], | |
672 | flash_read_long (info, sector, 0)); | |
673 | flash_write_cmd (info, sector, 0, info->cmd_reset); | |
674 | return ERR_TIMOUT; | |
5653fc33 | 675 | } |
be60a902 | 676 | udelay (1); /* also triggers watchdog */ |
5653fc33 | 677 | } |
be60a902 HS |
678 | return ERR_OK; |
679 | } | |
5653fc33 | 680 | |
be60a902 HS |
681 | /*----------------------------------------------------------------------- |
682 | * Wait for XSR.7 to be set, if it times out print an error, otherwise | |
683 | * do a full status check. | |
684 | * | |
685 | * This routine sets the flash to read-array mode. | |
686 | */ | |
687 | static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, | |
688 | ulong tout, char *prompt) | |
689 | { | |
690 | int retcode; | |
5653fc33 | 691 | |
be60a902 HS |
692 | retcode = flash_status_check (info, sector, tout, prompt); |
693 | switch (info->vendor) { | |
9c048b52 | 694 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
695 | case CFI_CMDSET_INTEL_EXTENDED: |
696 | case CFI_CMDSET_INTEL_STANDARD: | |
0d01f66d | 697 | if ((retcode != ERR_OK) |
be60a902 HS |
698 | && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { |
699 | retcode = ERR_INVAL; | |
700 | printf ("Flash %s error at address %lx\n", prompt, | |
701 | info->start[sector]); | |
702 | if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | | |
703 | FLASH_STATUS_PSLBS)) { | |
704 | puts ("Command Sequence Error.\n"); | |
705 | } else if (flash_isset (info, sector, 0, | |
706 | FLASH_STATUS_ECLBS)) { | |
707 | puts ("Block Erase Error.\n"); | |
708 | retcode = ERR_NOT_ERASED; | |
709 | } else if (flash_isset (info, sector, 0, | |
710 | FLASH_STATUS_PSLBS)) { | |
711 | puts ("Locking Error\n"); | |
5653fc33 | 712 | } |
be60a902 HS |
713 | if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { |
714 | puts ("Block locked.\n"); | |
715 | retcode = ERR_PROTECTED; | |
716 | } | |
717 | if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) | |
718 | puts ("Vpp Low Error.\n"); | |
5653fc33 | 719 | } |
be60a902 HS |
720 | flash_write_cmd (info, sector, 0, info->cmd_reset); |
721 | break; | |
722 | default: | |
723 | break; | |
5653fc33 | 724 | } |
be60a902 | 725 | return retcode; |
5653fc33 WD |
726 | } |
727 | ||
728 | /*----------------------------------------------------------------------- | |
729 | */ | |
be60a902 | 730 | static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) |
5653fc33 | 731 | { |
6d0f6bcf | 732 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
733 | unsigned short w; |
734 | unsigned int l; | |
735 | unsigned long long ll; | |
736 | #endif | |
5653fc33 | 737 | |
be60a902 HS |
738 | switch (info->portwidth) { |
739 | case FLASH_CFI_8BIT: | |
740 | cword->c = c; | |
741 | break; | |
742 | case FLASH_CFI_16BIT: | |
6d0f6bcf | 743 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
744 | w = c; |
745 | w <<= 8; | |
746 | cword->w = (cword->w >> 8) | w; | |
747 | #else | |
748 | cword->w = (cword->w << 8) | c; | |
81b20ccc | 749 | #endif |
be60a902 HS |
750 | break; |
751 | case FLASH_CFI_32BIT: | |
6d0f6bcf | 752 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
753 | l = c; |
754 | l <<= 24; | |
755 | cword->l = (cword->l >> 8) | l; | |
756 | #else | |
757 | cword->l = (cword->l << 8) | c; | |
758 | #endif | |
759 | break; | |
760 | case FLASH_CFI_64BIT: | |
6d0f6bcf | 761 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
762 | ll = c; |
763 | ll <<= 56; | |
764 | cword->ll = (cword->ll >> 8) | ll; | |
765 | #else | |
766 | cword->ll = (cword->ll << 8) | c; | |
767 | #endif | |
768 | break; | |
260421a2 | 769 | } |
be60a902 | 770 | } |
5653fc33 | 771 | |
0f8e851e JG |
772 | /* |
773 | * Loop through the sector table starting from the previously found sector. | |
774 | * Searches forwards or backwards, dependent on the passed address. | |
be60a902 HS |
775 | */ |
776 | static flash_sect_t find_sector (flash_info_t * info, ulong addr) | |
777 | { | |
0f8e851e JG |
778 | static flash_sect_t saved_sector = 0; /* previously found sector */ |
779 | flash_sect_t sector = saved_sector; | |
780 | ||
781 | while ((info->start[sector] < addr) | |
782 | && (sector < info->sector_count - 1)) | |
783 | sector++; | |
784 | while ((info->start[sector] > addr) && (sector > 0)) | |
785 | /* | |
786 | * also decrements the sector in case of an overshot | |
787 | * in the first loop | |
788 | */ | |
789 | sector--; | |
790 | ||
791 | saved_sector = sector; | |
be60a902 | 792 | return sector; |
5653fc33 WD |
793 | } |
794 | ||
795 | /*----------------------------------------------------------------------- | |
5653fc33 | 796 | */ |
be60a902 HS |
797 | static int flash_write_cfiword (flash_info_t * info, ulong dest, |
798 | cfiword_t cword) | |
5653fc33 | 799 | { |
09ce9921 | 800 | void *dstaddr = (void *)dest; |
be60a902 | 801 | int flag; |
a7292871 JG |
802 | flash_sect_t sect = 0; |
803 | char sect_found = 0; | |
5653fc33 | 804 | |
be60a902 HS |
805 | /* Check if Flash is (sufficiently) erased */ |
806 | switch (info->portwidth) { | |
807 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 808 | flag = ((flash_read8(dstaddr) & cword.c) == cword.c); |
be60a902 HS |
809 | break; |
810 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 811 | flag = ((flash_read16(dstaddr) & cword.w) == cword.w); |
be60a902 HS |
812 | break; |
813 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 814 | flag = ((flash_read32(dstaddr) & cword.l) == cword.l); |
be60a902 HS |
815 | break; |
816 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 817 | flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); |
be60a902 HS |
818 | break; |
819 | default: | |
12d30aa7 HS |
820 | flag = 0; |
821 | break; | |
5653fc33 | 822 | } |
09ce9921 | 823 | if (!flag) |
0dc80e27 | 824 | return ERR_NOT_ERASED; |
5653fc33 | 825 | |
be60a902 HS |
826 | /* Disable interrupts which might cause a timeout here */ |
827 | flag = disable_interrupts (); | |
79b4cda0 | 828 | |
be60a902 | 829 | switch (info->vendor) { |
9c048b52 | 830 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
831 | case CFI_CMDSET_INTEL_EXTENDED: |
832 | case CFI_CMDSET_INTEL_STANDARD: | |
833 | flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); | |
834 | flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); | |
835 | break; | |
836 | case CFI_CMDSET_AMD_EXTENDED: | |
837 | case CFI_CMDSET_AMD_STANDARD: | |
838 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
839 | case CFI_CMDSET_AMD_LEGACY: | |
840 | #endif | |
0d01f66d ES |
841 | sect = find_sector(info, dest); |
842 | flash_unlock_seq (info, sect); | |
843 | flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE); | |
a7292871 | 844 | sect_found = 1; |
be60a902 | 845 | break; |
5653fc33 WD |
846 | } |
847 | ||
be60a902 HS |
848 | switch (info->portwidth) { |
849 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 850 | flash_write8(cword.c, dstaddr); |
be60a902 HS |
851 | break; |
852 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 853 | flash_write16(cword.w, dstaddr); |
be60a902 HS |
854 | break; |
855 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 856 | flash_write32(cword.l, dstaddr); |
be60a902 HS |
857 | break; |
858 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 859 | flash_write64(cword.ll, dstaddr); |
be60a902 | 860 | break; |
5653fc33 WD |
861 | } |
862 | ||
be60a902 HS |
863 | /* re-enable interrupts if necessary */ |
864 | if (flag) | |
865 | enable_interrupts (); | |
5653fc33 | 866 | |
a7292871 JG |
867 | if (!sect_found) |
868 | sect = find_sector (info, dest); | |
869 | ||
870 | return flash_full_status_check (info, sect, info->write_tout, "write"); | |
5653fc33 WD |
871 | } |
872 | ||
6d0f6bcf | 873 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
5653fc33 | 874 | |
be60a902 HS |
875 | static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, |
876 | int len) | |
5653fc33 | 877 | { |
be60a902 HS |
878 | flash_sect_t sector; |
879 | int cnt; | |
880 | int retcode; | |
cdbaefb5 | 881 | void *src = cp; |
ec21d5cf | 882 | void *dst = (void *)dest; |
0dc80e27 SR |
883 | void *dst2 = dst; |
884 | int flag = 0; | |
96ef831f GL |
885 | uint offset = 0; |
886 | unsigned int shift; | |
9c048b52 | 887 | uchar write_cmd; |
cdbaefb5 | 888 | |
0dc80e27 SR |
889 | switch (info->portwidth) { |
890 | case FLASH_CFI_8BIT: | |
96ef831f | 891 | shift = 0; |
0dc80e27 SR |
892 | break; |
893 | case FLASH_CFI_16BIT: | |
96ef831f | 894 | shift = 1; |
0dc80e27 SR |
895 | break; |
896 | case FLASH_CFI_32BIT: | |
96ef831f | 897 | shift = 2; |
0dc80e27 SR |
898 | break; |
899 | case FLASH_CFI_64BIT: | |
96ef831f | 900 | shift = 3; |
0dc80e27 SR |
901 | break; |
902 | default: | |
903 | retcode = ERR_INVAL; | |
904 | goto out_unmap; | |
905 | } | |
906 | ||
96ef831f GL |
907 | cnt = len >> shift; |
908 | ||
0dc80e27 SR |
909 | while ((cnt-- > 0) && (flag == 0)) { |
910 | switch (info->portwidth) { | |
911 | case FLASH_CFI_8BIT: | |
912 | flag = ((flash_read8(dst2) & flash_read8(src)) == | |
913 | flash_read8(src)); | |
914 | src += 1, dst2 += 1; | |
915 | break; | |
916 | case FLASH_CFI_16BIT: | |
917 | flag = ((flash_read16(dst2) & flash_read16(src)) == | |
918 | flash_read16(src)); | |
919 | src += 2, dst2 += 2; | |
920 | break; | |
921 | case FLASH_CFI_32BIT: | |
922 | flag = ((flash_read32(dst2) & flash_read32(src)) == | |
923 | flash_read32(src)); | |
924 | src += 4, dst2 += 4; | |
925 | break; | |
926 | case FLASH_CFI_64BIT: | |
927 | flag = ((flash_read64(dst2) & flash_read64(src)) == | |
928 | flash_read64(src)); | |
929 | src += 8, dst2 += 8; | |
930 | break; | |
931 | } | |
932 | } | |
933 | if (!flag) { | |
934 | retcode = ERR_NOT_ERASED; | |
935 | goto out_unmap; | |
936 | } | |
937 | ||
938 | src = cp; | |
cdbaefb5 | 939 | sector = find_sector (info, dest); |
bf9e3b38 WD |
940 | |
941 | switch (info->vendor) { | |
9c048b52 | 942 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
5653fc33 WD |
943 | case CFI_CMDSET_INTEL_STANDARD: |
944 | case CFI_CMDSET_INTEL_EXTENDED: | |
9c048b52 VL |
945 | write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? |
946 | FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; | |
be60a902 | 947 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
9c048b52 VL |
948 | flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS); |
949 | flash_write_cmd (info, sector, 0, write_cmd); | |
be60a902 HS |
950 | retcode = flash_status_check (info, sector, |
951 | info->buffer_write_tout, | |
952 | "write to buffer"); | |
953 | if (retcode == ERR_OK) { | |
954 | /* reduce the number of loops by the width of | |
955 | * the port */ | |
96ef831f | 956 | cnt = len >> shift; |
93c56f21 | 957 | flash_write_cmd (info, sector, 0, cnt - 1); |
be60a902 HS |
958 | while (cnt-- > 0) { |
959 | switch (info->portwidth) { | |
960 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
961 | flash_write8(flash_read8(src), dst); |
962 | src += 1, dst += 1; | |
be60a902 HS |
963 | break; |
964 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
965 | flash_write16(flash_read16(src), dst); |
966 | src += 2, dst += 2; | |
be60a902 HS |
967 | break; |
968 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
969 | flash_write32(flash_read32(src), dst); |
970 | src += 4, dst += 4; | |
be60a902 HS |
971 | break; |
972 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
973 | flash_write64(flash_read64(src), dst); |
974 | src += 8, dst += 8; | |
be60a902 HS |
975 | break; |
976 | default: | |
12d30aa7 HS |
977 | retcode = ERR_INVAL; |
978 | goto out_unmap; | |
be60a902 HS |
979 | } |
980 | } | |
981 | flash_write_cmd (info, sector, 0, | |
982 | FLASH_CMD_WRITE_BUFFER_CONFIRM); | |
983 | retcode = flash_full_status_check ( | |
984 | info, sector, info->buffer_write_tout, | |
985 | "buffer write"); | |
986 | } | |
12d30aa7 HS |
987 | |
988 | break; | |
be60a902 | 989 | |
5653fc33 WD |
990 | case CFI_CMDSET_AMD_STANDARD: |
991 | case CFI_CMDSET_AMD_EXTENDED: | |
be60a902 | 992 | flash_unlock_seq(info,0); |
96ef831f GL |
993 | |
994 | #ifdef CONFIG_FLASH_SPANSION_S29WS_N | |
995 | offset = ((unsigned long)dst - info->start[sector]) >> shift; | |
996 | #endif | |
997 | flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); | |
998 | cnt = len >> shift; | |
999 | flash_write_cmd(info, sector, offset, (uchar)cnt - 1); | |
be60a902 HS |
1000 | |
1001 | switch (info->portwidth) { | |
1002 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
1003 | while (cnt-- > 0) { |
1004 | flash_write8(flash_read8(src), dst); | |
1005 | src += 1, dst += 1; | |
1006 | } | |
be60a902 HS |
1007 | break; |
1008 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
1009 | while (cnt-- > 0) { |
1010 | flash_write16(flash_read16(src), dst); | |
1011 | src += 2, dst += 2; | |
1012 | } | |
be60a902 HS |
1013 | break; |
1014 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
1015 | while (cnt-- > 0) { |
1016 | flash_write32(flash_read32(src), dst); | |
1017 | src += 4, dst += 4; | |
1018 | } | |
be60a902 HS |
1019 | break; |
1020 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
1021 | while (cnt-- > 0) { |
1022 | flash_write64(flash_read64(src), dst); | |
1023 | src += 8, dst += 8; | |
1024 | } | |
be60a902 HS |
1025 | break; |
1026 | default: | |
12d30aa7 HS |
1027 | retcode = ERR_INVAL; |
1028 | goto out_unmap; | |
be60a902 HS |
1029 | } |
1030 | ||
1031 | flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); | |
1032 | retcode = flash_full_status_check (info, sector, | |
1033 | info->buffer_write_tout, | |
1034 | "buffer write"); | |
12d30aa7 | 1035 | break; |
be60a902 | 1036 | |
5653fc33 | 1037 | default: |
be60a902 | 1038 | debug ("Unknown Command Set\n"); |
12d30aa7 HS |
1039 | retcode = ERR_INVAL; |
1040 | break; | |
5653fc33 | 1041 | } |
12d30aa7 HS |
1042 | |
1043 | out_unmap: | |
12d30aa7 | 1044 | return retcode; |
5653fc33 | 1045 | } |
6d0f6bcf | 1046 | #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
be60a902 | 1047 | |
bf9e3b38 | 1048 | |
5653fc33 | 1049 | /*----------------------------------------------------------------------- |
5653fc33 | 1050 | */ |
be60a902 | 1051 | int flash_erase (flash_info_t * info, int s_first, int s_last) |
5653fc33 | 1052 | { |
be60a902 HS |
1053 | int rcode = 0; |
1054 | int prot; | |
1055 | flash_sect_t sect; | |
5653fc33 | 1056 | |
be60a902 HS |
1057 | if (info->flash_id != FLASH_MAN_CFI) { |
1058 | puts ("Can't erase unknown flash type - aborted\n"); | |
1059 | return 1; | |
1060 | } | |
1061 | if ((s_first < 0) || (s_first > s_last)) { | |
1062 | puts ("- no sectors to erase\n"); | |
1063 | return 1; | |
1064 | } | |
2662b40c | 1065 | |
be60a902 HS |
1066 | prot = 0; |
1067 | for (sect = s_first; sect <= s_last; ++sect) { | |
1068 | if (info->protect[sect]) { | |
1069 | prot++; | |
5653fc33 WD |
1070 | } |
1071 | } | |
be60a902 HS |
1072 | if (prot) { |
1073 | printf ("- Warning: %d protected sectors will not be erased!\n", | |
1074 | prot); | |
6ea808ef | 1075 | } else if (flash_verbose) { |
be60a902 HS |
1076 | putc ('\n'); |
1077 | } | |
bf9e3b38 | 1078 | |
bf9e3b38 | 1079 | |
be60a902 HS |
1080 | for (sect = s_first; sect <= s_last; sect++) { |
1081 | if (info->protect[sect] == 0) { /* not protected */ | |
1082 | switch (info->vendor) { | |
9c048b52 | 1083 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
1084 | case CFI_CMDSET_INTEL_STANDARD: |
1085 | case CFI_CMDSET_INTEL_EXTENDED: | |
1086 | flash_write_cmd (info, sect, 0, | |
1087 | FLASH_CMD_CLEAR_STATUS); | |
1088 | flash_write_cmd (info, sect, 0, | |
1089 | FLASH_CMD_BLOCK_ERASE); | |
1090 | flash_write_cmd (info, sect, 0, | |
1091 | FLASH_CMD_ERASE_CONFIRM); | |
1092 | break; | |
1093 | case CFI_CMDSET_AMD_STANDARD: | |
1094 | case CFI_CMDSET_AMD_EXTENDED: | |
1095 | flash_unlock_seq (info, sect); | |
1096 | flash_write_cmd (info, sect, | |
1097 | info->addr_unlock1, | |
1098 | AMD_CMD_ERASE_START); | |
1099 | flash_unlock_seq (info, sect); | |
1100 | flash_write_cmd (info, sect, 0, | |
1101 | AMD_CMD_ERASE_SECTOR); | |
1102 | break; | |
1103 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1104 | case CFI_CMDSET_AMD_LEGACY: | |
1105 | flash_unlock_seq (info, 0); | |
1106 | flash_write_cmd (info, 0, info->addr_unlock1, | |
1107 | AMD_CMD_ERASE_START); | |
1108 | flash_unlock_seq (info, 0); | |
1109 | flash_write_cmd (info, sect, 0, | |
1110 | AMD_CMD_ERASE_SECTOR); | |
1111 | break; | |
1112 | #endif | |
1113 | default: | |
1114 | debug ("Unkown flash vendor %d\n", | |
1115 | info->vendor); | |
1116 | break; | |
bf9e3b38 | 1117 | } |
be60a902 HS |
1118 | |
1119 | if (flash_full_status_check | |
1120 | (info, sect, info->erase_blk_tout, "erase")) { | |
1121 | rcode = 1; | |
6ea808ef | 1122 | } else if (flash_verbose) |
be60a902 | 1123 | putc ('.'); |
5653fc33 | 1124 | } |
5653fc33 | 1125 | } |
6ea808ef PZ |
1126 | |
1127 | if (flash_verbose) | |
1128 | puts (" done\n"); | |
1129 | ||
be60a902 | 1130 | return rcode; |
5653fc33 | 1131 | } |
bf9e3b38 | 1132 | |
5653fc33 WD |
1133 | /*----------------------------------------------------------------------- |
1134 | */ | |
be60a902 | 1135 | void flash_print_info (flash_info_t * info) |
5653fc33 | 1136 | { |
be60a902 | 1137 | int i; |
4d13cbad | 1138 | |
be60a902 HS |
1139 | if (info->flash_id != FLASH_MAN_CFI) { |
1140 | puts ("missing or unknown FLASH type\n"); | |
1141 | return; | |
1142 | } | |
1143 | ||
1144 | printf ("%s FLASH (%d x %d)", | |
1145 | info->name, | |
1146 | (info->portwidth << 3), (info->chipwidth << 3)); | |
1147 | if (info->size < 1024*1024) | |
1148 | printf (" Size: %ld kB in %d Sectors\n", | |
1149 | info->size >> 10, info->sector_count); | |
1150 | else | |
1151 | printf (" Size: %ld MB in %d Sectors\n", | |
1152 | info->size >> 20, info->sector_count); | |
1153 | printf (" "); | |
1154 | switch (info->vendor) { | |
9c048b52 VL |
1155 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
1156 | printf ("Intel Prog Regions"); | |
1157 | break; | |
be60a902 HS |
1158 | case CFI_CMDSET_INTEL_STANDARD: |
1159 | printf ("Intel Standard"); | |
1160 | break; | |
1161 | case CFI_CMDSET_INTEL_EXTENDED: | |
1162 | printf ("Intel Extended"); | |
1163 | break; | |
1164 | case CFI_CMDSET_AMD_STANDARD: | |
1165 | printf ("AMD Standard"); | |
1166 | break; | |
1167 | case CFI_CMDSET_AMD_EXTENDED: | |
1168 | printf ("AMD Extended"); | |
1169 | break; | |
1170 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1171 | case CFI_CMDSET_AMD_LEGACY: | |
1172 | printf ("AMD Legacy"); | |
1173 | break; | |
4d13cbad | 1174 | #endif |
be60a902 HS |
1175 | default: |
1176 | printf ("Unknown (%d)", info->vendor); | |
1177 | break; | |
1178 | } | |
1179 | printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X", | |
1180 | info->manufacturer_id, info->device_id); | |
1181 | if (info->device_id == 0x7E) { | |
1182 | printf("%04X", info->device_id2); | |
1183 | } | |
1184 | printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", | |
1185 | info->erase_blk_tout, | |
1186 | info->write_tout); | |
1187 | if (info->buffer_size > 1) { | |
1188 | printf (" Buffer write timeout: %ld ms, " | |
1189 | "buffer size: %d bytes\n", | |
1190 | info->buffer_write_tout, | |
1191 | info->buffer_size); | |
5653fc33 | 1192 | } |
5653fc33 | 1193 | |
be60a902 HS |
1194 | puts ("\n Sector Start Addresses:"); |
1195 | for (i = 0; i < info->sector_count; ++i) { | |
1196 | if ((i % 5) == 0) | |
1197 | printf ("\n"); | |
6d0f6bcf | 1198 | #ifdef CONFIG_SYS_FLASH_EMPTY_INFO |
be60a902 HS |
1199 | int k; |
1200 | int size; | |
1201 | int erased; | |
1202 | volatile unsigned long *flash; | |
5653fc33 | 1203 | |
be60a902 HS |
1204 | /* |
1205 | * Check if whole sector is erased | |
1206 | */ | |
12d30aa7 | 1207 | size = flash_sector_size(info, i); |
be60a902 HS |
1208 | erased = 1; |
1209 | flash = (volatile unsigned long *) info->start[i]; | |
1210 | size = size >> 2; /* divide by 4 for longword access */ | |
1211 | for (k = 0; k < size; k++) { | |
1212 | if (*flash++ != 0xffffffff) { | |
1213 | erased = 0; | |
1214 | break; | |
1215 | } | |
1216 | } | |
bf9e3b38 | 1217 | |
be60a902 HS |
1218 | /* print empty and read-only info */ |
1219 | printf (" %08lX %c %s ", | |
1220 | info->start[i], | |
1221 | erased ? 'E' : ' ', | |
1222 | info->protect[i] ? "RO" : " "); | |
6d0f6bcf | 1223 | #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ |
be60a902 HS |
1224 | printf (" %08lX %s ", |
1225 | info->start[i], | |
1226 | info->protect[i] ? "RO" : " "); | |
bf9e3b38 | 1227 | #endif |
be60a902 HS |
1228 | } |
1229 | putc ('\n'); | |
1230 | return; | |
5653fc33 WD |
1231 | } |
1232 | ||
9a042e9c JVB |
1233 | /*----------------------------------------------------------------------- |
1234 | * This is used in a few places in write_buf() to show programming | |
1235 | * progress. Making it a function is nasty because it needs to do side | |
1236 | * effect updates to digit and dots. Repeated code is nasty too, so | |
1237 | * we define it once here. | |
1238 | */ | |
f0105727 SR |
1239 | #ifdef CONFIG_FLASH_SHOW_PROGRESS |
1240 | #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ | |
6ea808ef PZ |
1241 | if (flash_verbose) { \ |
1242 | dots -= dots_sub; \ | |
1243 | if ((scale > 0) && (dots <= 0)) { \ | |
1244 | if ((digit % 5) == 0) \ | |
1245 | printf ("%d", digit / 5); \ | |
1246 | else \ | |
1247 | putc ('.'); \ | |
1248 | digit--; \ | |
1249 | dots += scale; \ | |
1250 | } \ | |
9a042e9c | 1251 | } |
f0105727 SR |
1252 | #else |
1253 | #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) | |
1254 | #endif | |
9a042e9c | 1255 | |
be60a902 HS |
1256 | /*----------------------------------------------------------------------- |
1257 | * Copy memory to flash, returns: | |
1258 | * 0 - OK | |
1259 | * 1 - write timeout | |
1260 | * 2 - Flash not erased | |
5653fc33 | 1261 | */ |
be60a902 | 1262 | int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
5653fc33 | 1263 | { |
be60a902 | 1264 | ulong wp; |
12d30aa7 | 1265 | uchar *p; |
be60a902 | 1266 | int aln; |
5653fc33 | 1267 | cfiword_t cword; |
be60a902 | 1268 | int i, rc; |
6d0f6bcf | 1269 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be60a902 | 1270 | int buffered_size; |
5653fc33 | 1271 | #endif |
9a042e9c JVB |
1272 | #ifdef CONFIG_FLASH_SHOW_PROGRESS |
1273 | int digit = CONFIG_FLASH_SHOW_PROGRESS; | |
1274 | int scale = 0; | |
1275 | int dots = 0; | |
1276 | ||
1277 | /* | |
1278 | * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. | |
1279 | */ | |
1280 | if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { | |
1281 | scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / | |
1282 | CONFIG_FLASH_SHOW_PROGRESS); | |
1283 | } | |
1284 | #endif | |
1285 | ||
be60a902 HS |
1286 | /* get lower aligned address */ |
1287 | wp = (addr & ~(info->portwidth - 1)); | |
3a197b2f | 1288 | |
be60a902 HS |
1289 | /* handle unaligned start */ |
1290 | if ((aln = addr - wp) != 0) { | |
1291 | cword.l = 0; | |
09ce9921 | 1292 | p = (uchar *)wp; |
12d30aa7 HS |
1293 | for (i = 0; i < aln; ++i) |
1294 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
5653fc33 | 1295 | |
be60a902 HS |
1296 | for (; (i < info->portwidth) && (cnt > 0); i++) { |
1297 | flash_add_byte (info, &cword, *src++); | |
1298 | cnt--; | |
be60a902 | 1299 | } |
12d30aa7 HS |
1300 | for (; (cnt == 0) && (i < info->portwidth); ++i) |
1301 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
1302 | ||
1303 | rc = flash_write_cfiword (info, wp, cword); | |
12d30aa7 | 1304 | if (rc != 0) |
be60a902 | 1305 | return rc; |
12d30aa7 HS |
1306 | |
1307 | wp += i; | |
f0105727 | 1308 | FLASH_SHOW_PROGRESS(scale, dots, digit, i); |
be60a902 HS |
1309 | } |
1310 | ||
1311 | /* handle the aligned part */ | |
6d0f6bcf | 1312 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be60a902 HS |
1313 | buffered_size = (info->portwidth / info->chipwidth); |
1314 | buffered_size *= info->buffer_size; | |
1315 | while (cnt >= info->portwidth) { | |
1316 | /* prohibit buffer write when buffer_size is 1 */ | |
1317 | if (info->buffer_size == 1) { | |
1318 | cword.l = 0; | |
1319 | for (i = 0; i < info->portwidth; i++) | |
1320 | flash_add_byte (info, &cword, *src++); | |
1321 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
1322 | return rc; | |
1323 | wp += info->portwidth; | |
1324 | cnt -= info->portwidth; | |
1325 | continue; | |
1326 | } | |
1327 | ||
1328 | /* write buffer until next buffered_size aligned boundary */ | |
1329 | i = buffered_size - (wp % buffered_size); | |
1330 | if (i > cnt) | |
1331 | i = cnt; | |
1332 | if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) | |
1333 | return rc; | |
1334 | i -= i & (info->portwidth - 1); | |
1335 | wp += i; | |
1336 | src += i; | |
1337 | cnt -= i; | |
f0105727 | 1338 | FLASH_SHOW_PROGRESS(scale, dots, digit, i); |
be60a902 HS |
1339 | } |
1340 | #else | |
1341 | while (cnt >= info->portwidth) { | |
1342 | cword.l = 0; | |
1343 | for (i = 0; i < info->portwidth; i++) { | |
1344 | flash_add_byte (info, &cword, *src++); | |
1345 | } | |
1346 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
1347 | return rc; | |
1348 | wp += info->portwidth; | |
1349 | cnt -= info->portwidth; | |
f0105727 | 1350 | FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); |
be60a902 | 1351 | } |
6d0f6bcf | 1352 | #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
9a042e9c | 1353 | |
be60a902 HS |
1354 | if (cnt == 0) { |
1355 | return (0); | |
1356 | } | |
1357 | ||
1358 | /* | |
1359 | * handle unaligned tail bytes | |
1360 | */ | |
1361 | cword.l = 0; | |
09ce9921 | 1362 | p = (uchar *)wp; |
12d30aa7 | 1363 | for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { |
be60a902 HS |
1364 | flash_add_byte (info, &cword, *src++); |
1365 | --cnt; | |
1366 | } | |
12d30aa7 HS |
1367 | for (; i < info->portwidth; ++i) |
1368 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
be60a902 HS |
1369 | |
1370 | return flash_write_cfiword (info, wp, cword); | |
5653fc33 | 1371 | } |
bf9e3b38 | 1372 | |
5653fc33 WD |
1373 | /*----------------------------------------------------------------------- |
1374 | */ | |
6d0f6bcf | 1375 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
be60a902 HS |
1376 | |
1377 | int flash_real_protect (flash_info_t * info, long sector, int prot) | |
5653fc33 | 1378 | { |
be60a902 | 1379 | int retcode = 0; |
5653fc33 | 1380 | |
bc9019e1 RC |
1381 | switch (info->vendor) { |
1382 | case CFI_CMDSET_INTEL_PROG_REGIONS: | |
1383 | case CFI_CMDSET_INTEL_STANDARD: | |
9e8e63cc | 1384 | case CFI_CMDSET_INTEL_EXTENDED: |
bc9019e1 RC |
1385 | flash_write_cmd (info, sector, 0, |
1386 | FLASH_CMD_CLEAR_STATUS); | |
1387 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); | |
1388 | if (prot) | |
1389 | flash_write_cmd (info, sector, 0, | |
1390 | FLASH_CMD_PROTECT_SET); | |
1391 | else | |
1392 | flash_write_cmd (info, sector, 0, | |
1393 | FLASH_CMD_PROTECT_CLEAR); | |
1394 | break; | |
1395 | case CFI_CMDSET_AMD_EXTENDED: | |
1396 | case CFI_CMDSET_AMD_STANDARD: | |
bc9019e1 RC |
1397 | /* U-Boot only checks the first byte */ |
1398 | if (info->manufacturer_id == (uchar)ATM_MANUFACT) { | |
1399 | if (prot) { | |
1400 | flash_unlock_seq (info, 0); | |
1401 | flash_write_cmd (info, 0, | |
1402 | info->addr_unlock1, | |
1403 | ATM_CMD_SOFTLOCK_START); | |
1404 | flash_unlock_seq (info, 0); | |
1405 | flash_write_cmd (info, sector, 0, | |
1406 | ATM_CMD_LOCK_SECT); | |
1407 | } else { | |
1408 | flash_write_cmd (info, 0, | |
1409 | info->addr_unlock1, | |
1410 | AMD_CMD_UNLOCK_START); | |
1411 | if (info->device_id == ATM_ID_BV6416) | |
1412 | flash_write_cmd (info, sector, | |
1413 | 0, ATM_CMD_UNLOCK_SECT); | |
1414 | } | |
1415 | } | |
1416 | break; | |
4e00acde TL |
1417 | #ifdef CONFIG_FLASH_CFI_LEGACY |
1418 | case CFI_CMDSET_AMD_LEGACY: | |
1419 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); | |
1420 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); | |
1421 | if (prot) | |
1422 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); | |
1423 | else | |
1424 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); | |
1425 | #endif | |
bc9019e1 | 1426 | }; |
bf9e3b38 | 1427 | |
be60a902 HS |
1428 | if ((retcode = |
1429 | flash_full_status_check (info, sector, info->erase_blk_tout, | |
1430 | prot ? "protect" : "unprotect")) == 0) { | |
bf9e3b38 | 1431 | |
be60a902 HS |
1432 | info->protect[sector] = prot; |
1433 | ||
1434 | /* | |
1435 | * On some of Intel's flash chips (marked via legacy_unlock) | |
1436 | * unprotect unprotects all locking. | |
1437 | */ | |
1438 | if ((prot == 0) && (info->legacy_unlock)) { | |
1439 | flash_sect_t i; | |
1440 | ||
1441 | for (i = 0; i < info->sector_count; i++) { | |
1442 | if (info->protect[i]) | |
1443 | flash_real_protect (info, i, 1); | |
1444 | } | |
5653fc33 | 1445 | } |
5653fc33 | 1446 | } |
be60a902 | 1447 | return retcode; |
5653fc33 | 1448 | } |
bf9e3b38 | 1449 | |
5653fc33 | 1450 | /*----------------------------------------------------------------------- |
be60a902 | 1451 | * flash_read_user_serial - read the OneTimeProgramming cells |
5653fc33 | 1452 | */ |
be60a902 HS |
1453 | void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, |
1454 | int len) | |
5653fc33 | 1455 | { |
be60a902 HS |
1456 | uchar *src; |
1457 | uchar *dst; | |
bf9e3b38 | 1458 | |
be60a902 | 1459 | dst = buffer; |
12d30aa7 | 1460 | src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION); |
be60a902 HS |
1461 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); |
1462 | memcpy (dst, src + offset, len); | |
1463 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
12d30aa7 | 1464 | flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); |
5653fc33 WD |
1465 | } |
1466 | ||
be60a902 HS |
1467 | /* |
1468 | * flash_read_factory_serial - read the device Id from the protection area | |
5653fc33 | 1469 | */ |
be60a902 HS |
1470 | void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, |
1471 | int len) | |
5653fc33 | 1472 | { |
be60a902 | 1473 | uchar *src; |
bf9e3b38 | 1474 | |
12d30aa7 | 1475 | src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION); |
be60a902 HS |
1476 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); |
1477 | memcpy (buffer, src + offset, len); | |
1478 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
12d30aa7 | 1479 | flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); |
5653fc33 WD |
1480 | } |
1481 | ||
6d0f6bcf | 1482 | #endif /* CONFIG_SYS_FLASH_PROTECTION */ |
be60a902 | 1483 | |
0ddf06dd HS |
1484 | /*----------------------------------------------------------------------- |
1485 | * Reverse the order of the erase regions in the CFI QRY structure. | |
1486 | * This is needed for chips that are either a) correctly detected as | |
1487 | * top-boot, or b) buggy. | |
1488 | */ | |
1489 | static void cfi_reverse_geometry(struct cfi_qry *qry) | |
1490 | { | |
1491 | unsigned int i, j; | |
1492 | u32 tmp; | |
1493 | ||
1494 | for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { | |
1495 | tmp = qry->erase_region_info[i]; | |
1496 | qry->erase_region_info[i] = qry->erase_region_info[j]; | |
1497 | qry->erase_region_info[j] = tmp; | |
1498 | } | |
1499 | } | |
be60a902 | 1500 | |
260421a2 SR |
1501 | /*----------------------------------------------------------------------- |
1502 | * read jedec ids from device and set corresponding fields in info struct | |
1503 | * | |
1504 | * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct | |
1505 | * | |
0ddf06dd HS |
1506 | */ |
1507 | static void cmdset_intel_read_jedec_ids(flash_info_t *info) | |
1508 | { | |
1509 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1510 | flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); | |
1511 | udelay(1000); /* some flash are slow to respond */ | |
1512 | info->manufacturer_id = flash_read_uchar (info, | |
1513 | FLASH_OFFSET_MANUFACTURER_ID); | |
1514 | info->device_id = flash_read_uchar (info, | |
1515 | FLASH_OFFSET_DEVICE_ID); | |
1516 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1517 | } | |
1518 | ||
1519 | static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) | |
1520 | { | |
1521 | info->cmd_reset = FLASH_CMD_RESET; | |
1522 | ||
1523 | cmdset_intel_read_jedec_ids(info); | |
1524 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1525 | ||
6d0f6bcf | 1526 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
0ddf06dd HS |
1527 | /* read legacy lock/unlock bit from intel flash */ |
1528 | if (info->ext_addr) { | |
1529 | info->legacy_unlock = flash_read_uchar (info, | |
1530 | info->ext_addr + 5) & 0x08; | |
1531 | } | |
1532 | #endif | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | static void cmdset_amd_read_jedec_ids(flash_info_t *info) | |
1538 | { | |
1539 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
1540 | flash_unlock_seq(info, 0); | |
1541 | flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); | |
1542 | udelay(1000); /* some flash are slow to respond */ | |
90447ecb | 1543 | |
0ddf06dd HS |
1544 | info->manufacturer_id = flash_read_uchar (info, |
1545 | FLASH_OFFSET_MANUFACTURER_ID); | |
90447ecb TK |
1546 | |
1547 | switch (info->chipwidth){ | |
1548 | case FLASH_CFI_8BIT: | |
1549 | info->device_id = flash_read_uchar (info, | |
1550 | FLASH_OFFSET_DEVICE_ID); | |
1551 | if (info->device_id == 0x7E) { | |
1552 | /* AMD 3-byte (expanded) device ids */ | |
1553 | info->device_id2 = flash_read_uchar (info, | |
1554 | FLASH_OFFSET_DEVICE_ID2); | |
1555 | info->device_id2 <<= 8; | |
1556 | info->device_id2 |= flash_read_uchar (info, | |
1557 | FLASH_OFFSET_DEVICE_ID3); | |
1558 | } | |
1559 | break; | |
1560 | case FLASH_CFI_16BIT: | |
1561 | info->device_id = flash_read_word (info, | |
1562 | FLASH_OFFSET_DEVICE_ID); | |
1563 | break; | |
1564 | default: | |
1565 | break; | |
0ddf06dd HS |
1566 | } |
1567 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
1568 | } | |
1569 | ||
1570 | static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) | |
1571 | { | |
1572 | info->cmd_reset = AMD_CMD_RESET; | |
1573 | ||
1574 | cmdset_amd_read_jedec_ids(info); | |
1575 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1576 | ||
0ddf06dd HS |
1577 | return 0; |
1578 | } | |
1579 | ||
1580 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
260421a2 SR |
1581 | static void flash_read_jedec_ids (flash_info_t * info) |
1582 | { | |
1583 | info->manufacturer_id = 0; | |
1584 | info->device_id = 0; | |
1585 | info->device_id2 = 0; | |
1586 | ||
1587 | switch (info->vendor) { | |
9c048b52 | 1588 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
260421a2 SR |
1589 | case CFI_CMDSET_INTEL_STANDARD: |
1590 | case CFI_CMDSET_INTEL_EXTENDED: | |
8225d1e3 | 1591 | cmdset_intel_read_jedec_ids(info); |
260421a2 SR |
1592 | break; |
1593 | case CFI_CMDSET_AMD_STANDARD: | |
1594 | case CFI_CMDSET_AMD_EXTENDED: | |
8225d1e3 | 1595 | cmdset_amd_read_jedec_ids(info); |
260421a2 SR |
1596 | break; |
1597 | default: | |
1598 | break; | |
1599 | } | |
1600 | } | |
1601 | ||
5653fc33 | 1602 | /*----------------------------------------------------------------------- |
be60a902 HS |
1603 | * Call board code to request info about non-CFI flash. |
1604 | * board_flash_get_legacy needs to fill in at least: | |
1605 | * info->portwidth, info->chipwidth and info->interface for Jedec probing. | |
7e5b9b47 | 1606 | */ |
09ce9921 | 1607 | static int flash_detect_legacy(phys_addr_t base, int banknum) |
5653fc33 | 1608 | { |
be60a902 | 1609 | flash_info_t *info = &flash_info[banknum]; |
7e5b9b47 | 1610 | |
be60a902 HS |
1611 | if (board_flash_get_legacy(base, banknum, info)) { |
1612 | /* board code may have filled info completely. If not, we | |
1613 | use JEDEC ID probing. */ | |
1614 | if (!info->vendor) { | |
1615 | int modes[] = { | |
1616 | CFI_CMDSET_AMD_STANDARD, | |
1617 | CFI_CMDSET_INTEL_STANDARD | |
1618 | }; | |
1619 | int i; | |
7e5b9b47 | 1620 | |
be60a902 HS |
1621 | for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) { |
1622 | info->vendor = modes[i]; | |
09ce9921 BB |
1623 | info->start[0] = |
1624 | (ulong)map_physmem(base, | |
e1fb6d0d | 1625 | info->portwidth, |
09ce9921 | 1626 | MAP_NOCACHE); |
be60a902 HS |
1627 | if (info->portwidth == FLASH_CFI_8BIT |
1628 | && info->interface == FLASH_CFI_X8X16) { | |
1629 | info->addr_unlock1 = 0x2AAA; | |
1630 | info->addr_unlock2 = 0x5555; | |
1631 | } else { | |
1632 | info->addr_unlock1 = 0x5555; | |
1633 | info->addr_unlock2 = 0x2AAA; | |
1634 | } | |
1635 | flash_read_jedec_ids(info); | |
1636 | debug("JEDEC PROBE: ID %x %x %x\n", | |
1637 | info->manufacturer_id, | |
1638 | info->device_id, | |
1639 | info->device_id2); | |
09ce9921 | 1640 | if (jedec_flash_match(info, info->start[0])) |
be60a902 | 1641 | break; |
09ce9921 | 1642 | else |
e1fb6d0d | 1643 | unmap_physmem((void *)info->start[0], |
09ce9921 | 1644 | MAP_NOCACHE); |
be60a902 HS |
1645 | } |
1646 | } | |
1647 | ||
1648 | switch(info->vendor) { | |
9c048b52 | 1649 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
1650 | case CFI_CMDSET_INTEL_STANDARD: |
1651 | case CFI_CMDSET_INTEL_EXTENDED: | |
1652 | info->cmd_reset = FLASH_CMD_RESET; | |
1653 | break; | |
1654 | case CFI_CMDSET_AMD_STANDARD: | |
1655 | case CFI_CMDSET_AMD_EXTENDED: | |
1656 | case CFI_CMDSET_AMD_LEGACY: | |
1657 | info->cmd_reset = AMD_CMD_RESET; | |
1658 | break; | |
1659 | } | |
1660 | info->flash_id = FLASH_MAN_CFI; | |
1661 | return 1; | |
1662 | } | |
1663 | return 0; /* use CFI */ | |
1664 | } | |
1665 | #else | |
09ce9921 | 1666 | static inline int flash_detect_legacy(phys_addr_t base, int banknum) |
be60a902 HS |
1667 | { |
1668 | return 0; /* use CFI */ | |
1669 | } | |
1670 | #endif | |
1671 | ||
1672 | /*----------------------------------------------------------------------- | |
1673 | * detect if flash is compatible with the Common Flash Interface (CFI) | |
1674 | * http://www.jedec.org/download/search/jesd68.pdf | |
1675 | */ | |
e23741f4 HS |
1676 | static void flash_read_cfi (flash_info_t *info, void *buf, |
1677 | unsigned int start, size_t len) | |
1678 | { | |
1679 | u8 *p = buf; | |
1680 | unsigned int i; | |
1681 | ||
1682 | for (i = 0; i < len; i++) | |
1683 | p[i] = flash_read_uchar(info, start + i); | |
1684 | } | |
1685 | ||
1686 | static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) | |
be60a902 HS |
1687 | { |
1688 | int cfi_offset; | |
1689 | ||
1ba639da MS |
1690 | /* We do not yet know what kind of commandset to use, so we issue |
1691 | the reset command in both Intel and AMD variants, in the hope | |
1692 | that AMD flash roms ignore the Intel command. */ | |
1693 | flash_write_cmd (info, 0, 0, AMD_CMD_RESET); | |
1694 | flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); | |
1695 | ||
be60a902 HS |
1696 | for (cfi_offset=0; |
1697 | cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); | |
1698 | cfi_offset++) { | |
1699 | flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], | |
1700 | FLASH_CMD_CFI); | |
1701 | if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') | |
1702 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') | |
1703 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { | |
e23741f4 HS |
1704 | flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, |
1705 | sizeof(struct cfi_qry)); | |
1706 | info->interface = le16_to_cpu(qry->interface_desc); | |
1707 | ||
be60a902 HS |
1708 | info->cfi_offset = flash_offset_cfi[cfi_offset]; |
1709 | debug ("device interface is %d\n", | |
1710 | info->interface); | |
1711 | debug ("found port %d chip %d ", | |
1712 | info->portwidth, info->chipwidth); | |
1713 | debug ("port %d bits chip %d bits\n", | |
1714 | info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1715 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1716 | ||
1717 | /* calculate command offsets as in the Linux driver */ | |
1718 | info->addr_unlock1 = 0x555; | |
7e5b9b47 HS |
1719 | info->addr_unlock2 = 0x2aa; |
1720 | ||
1721 | /* | |
1722 | * modify the unlock address if we are | |
1723 | * in compatibility mode | |
1724 | */ | |
1725 | if ( /* x8/x16 in x8 mode */ | |
1726 | ((info->chipwidth == FLASH_CFI_BY8) && | |
1727 | (info->interface == FLASH_CFI_X8X16)) || | |
1728 | /* x16/x32 in x16 mode */ | |
1729 | ((info->chipwidth == FLASH_CFI_BY16) && | |
1730 | (info->interface == FLASH_CFI_X16X32))) | |
1731 | { | |
1732 | info->addr_unlock1 = 0xaaa; | |
1733 | info->addr_unlock2 = 0x555; | |
1734 | } | |
1735 | ||
1736 | info->name = "CFI conformant"; | |
1737 | return 1; | |
1738 | } | |
1739 | } | |
1740 | ||
1741 | return 0; | |
1742 | } | |
1743 | ||
e23741f4 | 1744 | static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) |
7e5b9b47 | 1745 | { |
bf9e3b38 WD |
1746 | debug ("flash detect cfi\n"); |
1747 | ||
6d0f6bcf | 1748 | for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; |
bf9e3b38 WD |
1749 | info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { |
1750 | for (info->chipwidth = FLASH_CFI_BY8; | |
1751 | info->chipwidth <= info->portwidth; | |
7e5b9b47 | 1752 | info->chipwidth <<= 1) |
e23741f4 | 1753 | if (__flash_detect_cfi(info, qry)) |
7e5b9b47 | 1754 | return 1; |
5653fc33 | 1755 | } |
bf9e3b38 | 1756 | debug ("not found\n"); |
5653fc33 WD |
1757 | return 0; |
1758 | } | |
bf9e3b38 | 1759 | |
467bcee1 HS |
1760 | /* |
1761 | * Manufacturer-specific quirks. Add workarounds for geometry | |
1762 | * reversal, etc. here. | |
1763 | */ | |
1764 | static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) | |
1765 | { | |
1766 | /* check if flash geometry needs reversal */ | |
1767 | if (qry->num_erase_regions > 1) { | |
1768 | /* reverse geometry if top boot part */ | |
1769 | if (info->cfi_version < 0x3131) { | |
1770 | /* CFI < 1.1, try to guess from device id */ | |
1771 | if ((info->device_id & 0x80) != 0) | |
1772 | cfi_reverse_geometry(qry); | |
1773 | } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { | |
1774 | /* CFI >= 1.1, deduct from top/bottom flag */ | |
1775 | /* note: ext_addr is valid since cfi_version > 0 */ | |
1776 | cfi_reverse_geometry(qry); | |
1777 | } | |
1778 | } | |
1779 | } | |
1780 | ||
1781 | static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) | |
1782 | { | |
1783 | int reverse_geometry = 0; | |
1784 | ||
1785 | /* Check the "top boot" bit in the PRI */ | |
1786 | if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) | |
1787 | reverse_geometry = 1; | |
1788 | ||
1789 | /* AT49BV6416(T) list the erase regions in the wrong order. | |
1790 | * However, the device ID is identical with the non-broken | |
1791 | * AT49BV642D since u-boot only reads the low byte (they | |
1792 | * differ in the high byte.) So leave out this fixup for now. | |
1793 | */ | |
1794 | #if 0 | |
1795 | if (info->device_id == 0xd6 || info->device_id == 0xd2) | |
1796 | reverse_geometry = !reverse_geometry; | |
1797 | #endif | |
1798 | ||
1799 | if (reverse_geometry) | |
1800 | cfi_reverse_geometry(qry); | |
1801 | } | |
1802 | ||
e8eac437 RR |
1803 | static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) |
1804 | { | |
1805 | /* check if flash geometry needs reversal */ | |
1806 | if (qry->num_erase_regions > 1) { | |
1807 | /* reverse geometry if top boot part */ | |
1808 | if (info->cfi_version < 0x3131) { | |
1809 | /* CFI < 1.1, guess by device id (only M29W320ET now) */ | |
1810 | if (info->device_id == 0x2256) { | |
1811 | cfi_reverse_geometry(qry); | |
1812 | } | |
1813 | } | |
1814 | } | |
1815 | } | |
1816 | ||
5653fc33 WD |
1817 | /* |
1818 | * The following code cannot be run from FLASH! | |
1819 | * | |
1820 | */ | |
09ce9921 | 1821 | ulong flash_get_size (phys_addr_t base, int banknum) |
5653fc33 | 1822 | { |
bf9e3b38 | 1823 | flash_info_t *info = &flash_info[banknum]; |
5653fc33 WD |
1824 | int i, j; |
1825 | flash_sect_t sect_cnt; | |
09ce9921 | 1826 | phys_addr_t sector; |
5653fc33 WD |
1827 | unsigned long tmp; |
1828 | int size_ratio; | |
1829 | uchar num_erase_regions; | |
bf9e3b38 WD |
1830 | int erase_region_size; |
1831 | int erase_region_count; | |
e23741f4 | 1832 | struct cfi_qry qry; |
260421a2 | 1833 | |
f979690e KG |
1834 | memset(&qry, 0, sizeof(qry)); |
1835 | ||
260421a2 SR |
1836 | info->ext_addr = 0; |
1837 | info->cfi_version = 0; | |
6d0f6bcf | 1838 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
2662b40c SR |
1839 | info->legacy_unlock = 0; |
1840 | #endif | |
5653fc33 | 1841 | |
09ce9921 | 1842 | info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); |
5653fc33 | 1843 | |
e23741f4 HS |
1844 | if (flash_detect_cfi (info, &qry)) { |
1845 | info->vendor = le16_to_cpu(qry.p_id); | |
1846 | info->ext_addr = le16_to_cpu(qry.p_adr); | |
1847 | num_erase_regions = qry.num_erase_regions; | |
1848 | ||
260421a2 SR |
1849 | if (info->ext_addr) { |
1850 | info->cfi_version = (ushort) flash_read_uchar (info, | |
1851 | info->ext_addr + 3) << 8; | |
1852 | info->cfi_version |= (ushort) flash_read_uchar (info, | |
1853 | info->ext_addr + 4); | |
1854 | } | |
0ddf06dd | 1855 | |
bf9e3b38 | 1856 | #ifdef DEBUG |
e23741f4 | 1857 | flash_printqry (&qry); |
bf9e3b38 | 1858 | #endif |
0ddf06dd | 1859 | |
bf9e3b38 | 1860 | switch (info->vendor) { |
9c048b52 | 1861 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
5653fc33 WD |
1862 | case CFI_CMDSET_INTEL_STANDARD: |
1863 | case CFI_CMDSET_INTEL_EXTENDED: | |
0ddf06dd | 1864 | cmdset_intel_init(info, &qry); |
5653fc33 WD |
1865 | break; |
1866 | case CFI_CMDSET_AMD_STANDARD: | |
1867 | case CFI_CMDSET_AMD_EXTENDED: | |
0ddf06dd | 1868 | cmdset_amd_init(info, &qry); |
5653fc33 | 1869 | break; |
0ddf06dd HS |
1870 | default: |
1871 | printf("CFI: Unknown command set 0x%x\n", | |
1872 | info->vendor); | |
1873 | /* | |
1874 | * Unfortunately, this means we don't know how | |
1875 | * to get the chip back to Read mode. Might | |
1876 | * as well try an Intel-style reset... | |
1877 | */ | |
1878 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1879 | return 0; | |
5653fc33 | 1880 | } |
cd37d9e6 | 1881 | |
467bcee1 HS |
1882 | /* Do manufacturer-specific fixups */ |
1883 | switch (info->manufacturer_id) { | |
1884 | case 0x0001: | |
1885 | flash_fixup_amd(info, &qry); | |
1886 | break; | |
1887 | case 0x001f: | |
1888 | flash_fixup_atmel(info, &qry); | |
1889 | break; | |
e8eac437 RR |
1890 | case 0x0020: |
1891 | flash_fixup_stm(info, &qry); | |
1892 | break; | |
467bcee1 HS |
1893 | } |
1894 | ||
bf9e3b38 | 1895 | debug ("manufacturer is %d\n", info->vendor); |
260421a2 SR |
1896 | debug ("manufacturer id is 0x%x\n", info->manufacturer_id); |
1897 | debug ("device id is 0x%x\n", info->device_id); | |
1898 | debug ("device id2 is 0x%x\n", info->device_id2); | |
1899 | debug ("cfi version is 0x%04x\n", info->cfi_version); | |
1900 | ||
5653fc33 | 1901 | size_ratio = info->portwidth / info->chipwidth; |
bf9e3b38 WD |
1902 | /* if the chip is x8/x16 reduce the ratio by half */ |
1903 | if ((info->interface == FLASH_CFI_X8X16) | |
1904 | && (info->chipwidth == FLASH_CFI_BY8)) { | |
1905 | size_ratio >>= 1; | |
1906 | } | |
bf9e3b38 WD |
1907 | debug ("size_ratio %d port %d bits chip %d bits\n", |
1908 | size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1909 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1910 | debug ("found %d erase regions\n", num_erase_regions); | |
5653fc33 WD |
1911 | sect_cnt = 0; |
1912 | sector = base; | |
bf9e3b38 WD |
1913 | for (i = 0; i < num_erase_regions; i++) { |
1914 | if (i > NUM_ERASE_REGIONS) { | |
028ab6b5 WD |
1915 | printf ("%d erase regions found, only %d used\n", |
1916 | num_erase_regions, NUM_ERASE_REGIONS); | |
5653fc33 WD |
1917 | break; |
1918 | } | |
e23741f4 | 1919 | |
0ddf06dd HS |
1920 | tmp = le32_to_cpu(qry.erase_region_info[i]); |
1921 | debug("erase region %u: 0x%08lx\n", i, tmp); | |
e23741f4 HS |
1922 | |
1923 | erase_region_count = (tmp & 0xffff) + 1; | |
1924 | tmp >>= 16; | |
bf9e3b38 WD |
1925 | erase_region_size = |
1926 | (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; | |
4c0d4c3b | 1927 | debug ("erase_region_count = %d erase_region_size = %d\n", |
028ab6b5 | 1928 | erase_region_count, erase_region_size); |
bf9e3b38 | 1929 | for (j = 0; j < erase_region_count; j++) { |
6d0f6bcf | 1930 | if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { |
81b20ccc MS |
1931 | printf("ERROR: too many flash sectors\n"); |
1932 | break; | |
1933 | } | |
09ce9921 BB |
1934 | info->start[sect_cnt] = |
1935 | (ulong)map_physmem(sector, | |
1936 | info->portwidth, | |
1937 | MAP_NOCACHE); | |
5653fc33 | 1938 | sector += (erase_region_size * size_ratio); |
a1191902 WD |
1939 | |
1940 | /* | |
7e5b9b47 HS |
1941 | * Only read protection status from |
1942 | * supported devices (intel...) | |
a1191902 WD |
1943 | */ |
1944 | switch (info->vendor) { | |
9c048b52 | 1945 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
a1191902 WD |
1946 | case CFI_CMDSET_INTEL_EXTENDED: |
1947 | case CFI_CMDSET_INTEL_STANDARD: | |
1948 | info->protect[sect_cnt] = | |
1949 | flash_isset (info, sect_cnt, | |
1950 | FLASH_OFFSET_PROTECT, | |
1951 | FLASH_STATUS_PROTECT); | |
1952 | break; | |
1953 | default: | |
7e5b9b47 HS |
1954 | /* default: not protected */ |
1955 | info->protect[sect_cnt] = 0; | |
a1191902 WD |
1956 | } |
1957 | ||
5653fc33 WD |
1958 | sect_cnt++; |
1959 | } | |
1960 | } | |
1961 | ||
1962 | info->sector_count = sect_cnt; | |
e23741f4 | 1963 | info->size = 1 << qry.dev_size; |
5653fc33 | 1964 | /* multiply the size by the number of chips */ |
7e5b9b47 | 1965 | info->size *= size_ratio; |
e23741f4 HS |
1966 | info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); |
1967 | tmp = 1 << qry.block_erase_timeout_typ; | |
7e5b9b47 | 1968 | info->erase_blk_tout = tmp * |
e23741f4 HS |
1969 | (1 << qry.block_erase_timeout_max); |
1970 | tmp = (1 << qry.buf_write_timeout_typ) * | |
1971 | (1 << qry.buf_write_timeout_max); | |
1972 | ||
7e5b9b47 | 1973 | /* round up when converting to ms */ |
e23741f4 HS |
1974 | info->buffer_write_tout = (tmp + 999) / 1000; |
1975 | tmp = (1 << qry.word_write_timeout_typ) * | |
1976 | (1 << qry.word_write_timeout_max); | |
7e5b9b47 | 1977 | /* round up when converting to ms */ |
e23741f4 | 1978 | info->write_tout = (tmp + 999) / 1000; |
5653fc33 | 1979 | info->flash_id = FLASH_MAN_CFI; |
7e5b9b47 HS |
1980 | if ((info->interface == FLASH_CFI_X8X16) && |
1981 | (info->chipwidth == FLASH_CFI_BY8)) { | |
1982 | /* XXX - Need to test on x8/x16 in parallel. */ | |
1983 | info->portwidth >>= 1; | |
855a496f | 1984 | } |
2215987e MF |
1985 | |
1986 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
5653fc33 WD |
1987 | } |
1988 | ||
bf9e3b38 | 1989 | return (info->size); |
5653fc33 WD |
1990 | } |
1991 | ||
6ea808ef PZ |
1992 | void flash_set_verbose(uint v) |
1993 | { | |
1994 | flash_verbose = v; | |
1995 | } | |
1996 | ||
5653fc33 WD |
1997 | /*----------------------------------------------------------------------- |
1998 | */ | |
be60a902 | 1999 | unsigned long flash_init (void) |
5653fc33 | 2000 | { |
be60a902 HS |
2001 | unsigned long size = 0; |
2002 | int i; | |
6d0f6bcf | 2003 | #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) |
c63ad632 MF |
2004 | struct apl_s { |
2005 | ulong start; | |
2006 | ulong size; | |
6d0f6bcf | 2007 | } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; |
c63ad632 | 2008 | #endif |
5653fc33 | 2009 | |
6d0f6bcf | 2010 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
be60a902 | 2011 | char *s = getenv("unlock"); |
81b20ccc | 2012 | #endif |
5653fc33 | 2013 | |
09ce9921 | 2014 | #define BANK_BASE(i) (((phys_addr_t [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i]) |
2a112b23 | 2015 | |
be60a902 | 2016 | /* Init: no FLASHes known */ |
6d0f6bcf | 2017 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
be60a902 | 2018 | flash_info[i].flash_id = FLASH_UNKNOWN; |
5653fc33 | 2019 | |
2a112b23 WD |
2020 | if (!flash_detect_legacy (BANK_BASE(i), i)) |
2021 | flash_get_size (BANK_BASE(i), i); | |
be60a902 HS |
2022 | size += flash_info[i].size; |
2023 | if (flash_info[i].flash_id == FLASH_UNKNOWN) { | |
6d0f6bcf | 2024 | #ifndef CONFIG_SYS_FLASH_QUIET_TEST |
be60a902 HS |
2025 | printf ("## Unknown FLASH on Bank %d " |
2026 | "- Size = 0x%08lx = %ld MB\n", | |
2027 | i+1, flash_info[i].size, | |
2028 | flash_info[i].size << 20); | |
6d0f6bcf | 2029 | #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ |
be60a902 | 2030 | } |
6d0f6bcf | 2031 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
be60a902 HS |
2032 | else if ((s != NULL) && (strcmp(s, "yes") == 0)) { |
2033 | /* | |
2034 | * Only the U-Boot image and it's environment | |
2035 | * is protected, all other sectors are | |
2036 | * unprotected (unlocked) if flash hardware | |
6d0f6bcf | 2037 | * protection is used (CONFIG_SYS_FLASH_PROTECTION) |
be60a902 HS |
2038 | * and the environment variable "unlock" is |
2039 | * set to "yes". | |
2040 | */ | |
2041 | if (flash_info[i].legacy_unlock) { | |
2042 | int k; | |
5653fc33 | 2043 | |
be60a902 HS |
2044 | /* |
2045 | * Disable legacy_unlock temporarily, | |
2046 | * since flash_real_protect would | |
2047 | * relock all other sectors again | |
2048 | * otherwise. | |
2049 | */ | |
2050 | flash_info[i].legacy_unlock = 0; | |
5653fc33 | 2051 | |
be60a902 HS |
2052 | /* |
2053 | * Legacy unlocking (e.g. Intel J3) -> | |
2054 | * unlock only one sector. This will | |
2055 | * unlock all sectors. | |
2056 | */ | |
2057 | flash_real_protect (&flash_info[i], 0, 0); | |
5653fc33 | 2058 | |
be60a902 | 2059 | flash_info[i].legacy_unlock = 1; |
5653fc33 | 2060 | |
be60a902 HS |
2061 | /* |
2062 | * Manually mark other sectors as | |
2063 | * unlocked (unprotected) | |
2064 | */ | |
2065 | for (k = 1; k < flash_info[i].sector_count; k++) | |
2066 | flash_info[i].protect[k] = 0; | |
2067 | } else { | |
2068 | /* | |
2069 | * No legancy unlocking -> unlock all sectors | |
2070 | */ | |
2071 | flash_protect (FLAG_PROTECT_CLEAR, | |
2072 | flash_info[i].start[0], | |
2073 | flash_info[i].start[0] | |
2074 | + flash_info[i].size - 1, | |
2075 | &flash_info[i]); | |
79b4cda0 | 2076 | } |
79b4cda0 | 2077 | } |
6d0f6bcf | 2078 | #endif /* CONFIG_SYS_FLASH_PROTECTION */ |
be60a902 | 2079 | } |
79b4cda0 | 2080 | |
be60a902 | 2081 | /* Monitor protection ON by default */ |
6d0f6bcf | 2082 | #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) |
be60a902 | 2083 | flash_protect (FLAG_PROTECT_SET, |
6d0f6bcf JCPV |
2084 | CONFIG_SYS_MONITOR_BASE, |
2085 | CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, | |
2086 | flash_get_info(CONFIG_SYS_MONITOR_BASE)); | |
be60a902 | 2087 | #endif |
79b4cda0 | 2088 | |
be60a902 | 2089 | /* Environment protection ON by default */ |
5a1aceb0 | 2090 | #ifdef CONFIG_ENV_IS_IN_FLASH |
be60a902 | 2091 | flash_protect (FLAG_PROTECT_SET, |
0e8d1586 JCPV |
2092 | CONFIG_ENV_ADDR, |
2093 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, | |
2094 | flash_get_info(CONFIG_ENV_ADDR)); | |
be60a902 | 2095 | #endif |
79b4cda0 | 2096 | |
be60a902 | 2097 | /* Redundant environment protection ON by default */ |
0e8d1586 | 2098 | #ifdef CONFIG_ENV_ADDR_REDUND |
be60a902 | 2099 | flash_protect (FLAG_PROTECT_SET, |
0e8d1586 JCPV |
2100 | CONFIG_ENV_ADDR_REDUND, |
2101 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, | |
2102 | flash_get_info(CONFIG_ENV_ADDR_REDUND)); | |
be60a902 | 2103 | #endif |
c63ad632 | 2104 | |
6d0f6bcf | 2105 | #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) |
c63ad632 MF |
2106 | for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) { |
2107 | debug("autoprotecting from %08x to %08x\n", | |
2108 | apl[i].start, apl[i].start + apl[i].size - 1); | |
2109 | flash_protect (FLAG_PROTECT_SET, | |
2110 | apl[i].start, | |
2111 | apl[i].start + apl[i].size - 1, | |
2112 | flash_get_info(apl[i].start)); | |
2113 | } | |
2114 | #endif | |
91809ed5 PZ |
2115 | |
2116 | #ifdef CONFIG_FLASH_CFI_MTD | |
2117 | cfi_mtd_init(); | |
2118 | #endif | |
2119 | ||
be60a902 | 2120 | return (size); |
5653fc33 | 2121 | } |