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5653fc33 | 1 | /* |
bf9e3b38 | 2 | * (C) Copyright 2002-2004 |
5653fc33 WD |
3 | * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
4 | * | |
5 | * Copyright (C) 2003 Arabella Software Ltd. | |
6 | * Yuli Barcohen <yuli@arabellasw.com> | |
5653fc33 | 7 | * |
bf9e3b38 WD |
8 | * Copyright (C) 2004 |
9 | * Ed Okerson | |
260421a2 SR |
10 | * |
11 | * Copyright (C) 2006 | |
12 | * Tolunay Orkun <listmember@orkun.us> | |
bf9e3b38 | 13 | * |
5653fc33 WD |
14 | * See file CREDITS for list of people who contributed to this |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 | * MA 02111-1307 USA | |
31 | * | |
5653fc33 WD |
32 | */ |
33 | ||
34 | /* The DEBUG define must be before common to enable debugging */ | |
2d1a537d WD |
35 | /* #define DEBUG */ |
36 | ||
5653fc33 WD |
37 | #include <common.h> |
38 | #include <asm/processor.h> | |
3a197b2f | 39 | #include <asm/io.h> |
4c0d4c3b | 40 | #include <asm/byteorder.h> |
2a8af187 | 41 | #include <environment.h> |
bf9e3b38 | 42 | #ifdef CFG_FLASH_CFI_DRIVER |
028ab6b5 | 43 | |
5653fc33 | 44 | /* |
7e5b9b47 HS |
45 | * This file implements a Common Flash Interface (CFI) driver for |
46 | * U-Boot. | |
47 | * | |
48 | * The width of the port and the width of the chips are determined at | |
49 | * initialization. These widths are used to calculate the address for | |
50 | * access CFI data structures. | |
5653fc33 WD |
51 | * |
52 | * References | |
53 | * JEDEC Standard JESD68 - Common Flash Interface (CFI) | |
54 | * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes | |
55 | * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets | |
56 | * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet | |
260421a2 SR |
57 | * AMD CFI Specification, Release 2.0 December 1, 2001 |
58 | * AMD/Spansion Application Note: Migration from Single-byte to Three-byte | |
59 | * Device IDs, Publication Number 25538 Revision A, November 8, 2001 | |
5653fc33 | 60 | * |
7e5b9b47 | 61 | * Define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between |
d0b6e140 | 62 | * reading and writing ... (yes there is such a Hardware). |
5653fc33 WD |
63 | */ |
64 | ||
bf9e3b38 WD |
65 | #ifndef CFG_FLASH_BANKS_LIST |
66 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
67 | #endif | |
68 | ||
5653fc33 WD |
69 | #define FLASH_CMD_CFI 0x98 |
70 | #define FLASH_CMD_READ_ID 0x90 | |
71 | #define FLASH_CMD_RESET 0xff | |
72 | #define FLASH_CMD_BLOCK_ERASE 0x20 | |
73 | #define FLASH_CMD_ERASE_CONFIRM 0xD0 | |
74 | #define FLASH_CMD_WRITE 0x40 | |
75 | #define FLASH_CMD_PROTECT 0x60 | |
76 | #define FLASH_CMD_PROTECT_SET 0x01 | |
77 | #define FLASH_CMD_PROTECT_CLEAR 0xD0 | |
78 | #define FLASH_CMD_CLEAR_STATUS 0x50 | |
bf9e3b38 WD |
79 | #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 |
80 | #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 | |
5653fc33 WD |
81 | |
82 | #define FLASH_STATUS_DONE 0x80 | |
83 | #define FLASH_STATUS_ESS 0x40 | |
84 | #define FLASH_STATUS_ECLBS 0x20 | |
85 | #define FLASH_STATUS_PSLBS 0x10 | |
86 | #define FLASH_STATUS_VPENS 0x08 | |
87 | #define FLASH_STATUS_PSS 0x04 | |
88 | #define FLASH_STATUS_DPS 0x02 | |
89 | #define FLASH_STATUS_R 0x01 | |
90 | #define FLASH_STATUS_PROTECT 0x01 | |
91 | ||
92 | #define AMD_CMD_RESET 0xF0 | |
93 | #define AMD_CMD_WRITE 0xA0 | |
94 | #define AMD_CMD_ERASE_START 0x80 | |
95 | #define AMD_CMD_ERASE_SECTOR 0x30 | |
855a496f WD |
96 | #define AMD_CMD_UNLOCK_START 0xAA |
97 | #define AMD_CMD_UNLOCK_ACK 0x55 | |
79b4cda0 SR |
98 | #define AMD_CMD_WRITE_TO_BUFFER 0x25 |
99 | #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 | |
5653fc33 WD |
100 | |
101 | #define AMD_STATUS_TOGGLE 0x40 | |
102 | #define AMD_STATUS_ERROR 0x20 | |
79b4cda0 | 103 | |
260421a2 SR |
104 | #define FLASH_OFFSET_MANUFACTURER_ID 0x00 |
105 | #define FLASH_OFFSET_DEVICE_ID 0x01 | |
106 | #define FLASH_OFFSET_DEVICE_ID2 0x0E | |
107 | #define FLASH_OFFSET_DEVICE_ID3 0x0F | |
5653fc33 | 108 | #define FLASH_OFFSET_CFI 0x55 |
92eb729b | 109 | #define FLASH_OFFSET_CFI_ALT 0x555 |
5653fc33 | 110 | #define FLASH_OFFSET_CFI_RESP 0x10 |
bf9e3b38 | 111 | #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 |
7e5b9b47 HS |
112 | /* extended query table primary address */ |
113 | #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 | |
5653fc33 | 114 | #define FLASH_OFFSET_WTOUT 0x1F |
bf9e3b38 | 115 | #define FLASH_OFFSET_WBTOUT 0x20 |
5653fc33 | 116 | #define FLASH_OFFSET_ETOUT 0x21 |
bf9e3b38 | 117 | #define FLASH_OFFSET_CETOUT 0x22 |
5653fc33 | 118 | #define FLASH_OFFSET_WMAX_TOUT 0x23 |
bf9e3b38 | 119 | #define FLASH_OFFSET_WBMAX_TOUT 0x24 |
5653fc33 | 120 | #define FLASH_OFFSET_EMAX_TOUT 0x25 |
bf9e3b38 | 121 | #define FLASH_OFFSET_CEMAX_TOUT 0x26 |
5653fc33 | 122 | #define FLASH_OFFSET_SIZE 0x27 |
bf9e3b38 WD |
123 | #define FLASH_OFFSET_INTERFACE 0x28 |
124 | #define FLASH_OFFSET_BUFFER_SIZE 0x2A | |
5653fc33 WD |
125 | #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C |
126 | #define FLASH_OFFSET_ERASE_REGIONS 0x2D | |
127 | #define FLASH_OFFSET_PROTECT 0x02 | |
bf9e3b38 WD |
128 | #define FLASH_OFFSET_USER_PROTECTION 0x85 |
129 | #define FLASH_OFFSET_INTEL_PROTECTION 0x81 | |
5653fc33 | 130 | |
260421a2 SR |
131 | #define CFI_CMDSET_NONE 0 |
132 | #define CFI_CMDSET_INTEL_EXTENDED 1 | |
133 | #define CFI_CMDSET_AMD_STANDARD 2 | |
134 | #define CFI_CMDSET_INTEL_STANDARD 3 | |
135 | #define CFI_CMDSET_AMD_EXTENDED 4 | |
136 | #define CFI_CMDSET_MITSU_STANDARD 256 | |
137 | #define CFI_CMDSET_MITSU_EXTENDED 257 | |
138 | #define CFI_CMDSET_SST 258 | |
5653fc33 | 139 | |
f7d1572b WD |
140 | #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ |
141 | # undef FLASH_CMD_RESET | |
260421a2 | 142 | # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ |
f7d1572b WD |
143 | #endif |
144 | ||
5653fc33 WD |
145 | typedef union { |
146 | unsigned char c; | |
147 | unsigned short w; | |
148 | unsigned long l; | |
149 | unsigned long long ll; | |
150 | } cfiword_t; | |
151 | ||
260421a2 | 152 | #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ |
5653fc33 | 153 | |
7e5b9b47 | 154 | static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; |
92eb729b | 155 | |
e6f2e902 MB |
156 | /* use CFG_MAX_FLASH_BANKS_DETECT if defined */ |
157 | #ifdef CFG_MAX_FLASH_BANKS_DETECT | |
158 | static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST; | |
159 | flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */ | |
160 | #else | |
5653fc33 | 161 | static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; |
e6f2e902 MB |
162 | flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */ |
163 | #endif | |
5653fc33 | 164 | |
79b4cda0 SR |
165 | /* |
166 | * Check if chip width is defined. If not, start detecting with 8bit. | |
167 | */ | |
168 | #ifndef CFG_FLASH_CFI_WIDTH | |
169 | #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
170 | #endif | |
171 | ||
be60a902 | 172 | typedef unsigned long flash_sect_t; |
5653fc33 | 173 | |
e23741f4 HS |
174 | /* CFI standard query structure */ |
175 | struct cfi_qry { | |
176 | u8 qry[3]; | |
177 | u16 p_id; | |
178 | u16 p_adr; | |
179 | u16 a_id; | |
180 | u16 a_adr; | |
181 | u8 vcc_min; | |
182 | u8 vcc_max; | |
183 | u8 vpp_min; | |
184 | u8 vpp_max; | |
185 | u8 word_write_timeout_typ; | |
186 | u8 buf_write_timeout_typ; | |
187 | u8 block_erase_timeout_typ; | |
188 | u8 chip_erase_timeout_typ; | |
189 | u8 word_write_timeout_max; | |
190 | u8 buf_write_timeout_max; | |
191 | u8 block_erase_timeout_max; | |
192 | u8 chip_erase_timeout_max; | |
193 | u8 dev_size; | |
194 | u16 interface_desc; | |
195 | u16 max_buf_write_size; | |
196 | u8 num_erase_regions; | |
197 | u32 erase_region_info[NUM_ERASE_REGIONS]; | |
198 | } __attribute__((packed)); | |
199 | ||
200 | struct cfi_pri_hdr { | |
201 | u8 pri[3]; | |
202 | u8 major_version; | |
203 | u8 minor_version; | |
204 | } __attribute__((packed)); | |
205 | ||
cdbaefb5 HS |
206 | static void flash_write8(u8 value, void *addr) |
207 | { | |
208 | __raw_writeb(value, addr); | |
209 | } | |
210 | ||
211 | static void flash_write16(u16 value, void *addr) | |
212 | { | |
213 | __raw_writew(value, addr); | |
214 | } | |
215 | ||
216 | static void flash_write32(u32 value, void *addr) | |
217 | { | |
218 | __raw_writel(value, addr); | |
219 | } | |
220 | ||
221 | static void flash_write64(u64 value, void *addr) | |
222 | { | |
223 | /* No architectures currently implement __raw_writeq() */ | |
224 | *(volatile u64 *)addr = value; | |
225 | } | |
226 | ||
227 | static u8 flash_read8(void *addr) | |
228 | { | |
229 | return __raw_readb(addr); | |
230 | } | |
231 | ||
232 | static u16 flash_read16(void *addr) | |
233 | { | |
234 | return __raw_readw(addr); | |
235 | } | |
236 | ||
237 | static u32 flash_read32(void *addr) | |
238 | { | |
239 | return __raw_readl(addr); | |
240 | } | |
241 | ||
242 | static u64 flash_read64(void *addr) | |
243 | { | |
244 | /* No architectures currently implement __raw_readq() */ | |
245 | return *(volatile u64 *)addr; | |
246 | } | |
247 | ||
5653fc33 | 248 | /*----------------------------------------------------------------------- |
5653fc33 | 249 | */ |
be60a902 HS |
250 | #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) |
251 | static flash_info_t *flash_get_info(ulong base) | |
252 | { | |
253 | int i; | |
254 | flash_info_t * info = 0; | |
5653fc33 | 255 | |
be60a902 HS |
256 | for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
257 | info = & flash_info[i]; | |
258 | if (info->size && info->start[0] <= base && | |
259 | base <= info->start[0] + info->size - 1) | |
260 | break; | |
261 | } | |
5653fc33 | 262 | |
be60a902 HS |
263 | return i == CFG_MAX_FLASH_BANKS ? 0 : info; |
264 | } | |
5653fc33 WD |
265 | #endif |
266 | ||
12d30aa7 HS |
267 | unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) |
268 | { | |
269 | if (sect != (info->sector_count - 1)) | |
270 | return info->start[sect + 1] - info->start[sect]; | |
271 | else | |
272 | return info->start[0] + info->size - info->start[sect]; | |
273 | } | |
274 | ||
bf9e3b38 WD |
275 | /*----------------------------------------------------------------------- |
276 | * create an address based on the offset and the port width | |
277 | */ | |
12d30aa7 HS |
278 | static inline void * |
279 | flash_map (flash_info_t * info, flash_sect_t sect, uint offset) | |
bf9e3b38 | 280 | { |
12d30aa7 HS |
281 | unsigned int byte_offset = offset * info->portwidth; |
282 | ||
283 | return map_physmem(info->start[sect] + byte_offset, | |
284 | flash_sector_size(info, sect) - byte_offset, | |
285 | MAP_NOCACHE); | |
286 | } | |
287 | ||
288 | static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, | |
289 | unsigned int offset, void *addr) | |
290 | { | |
291 | unsigned int byte_offset = offset * info->portwidth; | |
292 | ||
293 | unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset); | |
bf9e3b38 WD |
294 | } |
295 | ||
be60a902 HS |
296 | /*----------------------------------------------------------------------- |
297 | * make a proper sized command based on the port and chip widths | |
298 | */ | |
299 | static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) | |
300 | { | |
301 | int i; | |
302 | uchar *cp = (uchar *) cmdbuf; | |
303 | ||
304 | #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) | |
305 | for (i = info->portwidth; i > 0; i--) | |
306 | #else | |
307 | for (i = 1; i <= info->portwidth; i++) | |
308 | #endif | |
309 | *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd; | |
310 | } | |
311 | ||
5653fc33 | 312 | #ifdef DEBUG |
bf9e3b38 WD |
313 | /*----------------------------------------------------------------------- |
314 | * Debug support | |
315 | */ | |
3055793b | 316 | static void print_longlong (char *str, unsigned long long data) |
5653fc33 WD |
317 | { |
318 | int i; | |
319 | char *cp; | |
bf9e3b38 WD |
320 | |
321 | cp = (unsigned char *) &data; | |
322 | for (i = 0; i < 8; i++) | |
323 | sprintf (&str[i * 2], "%2.2x", *cp++); | |
324 | } | |
be60a902 | 325 | |
e23741f4 | 326 | static void flash_printqry (struct cfi_qry *qry) |
bf9e3b38 | 327 | { |
e23741f4 | 328 | u8 *p = (u8 *)qry; |
bf9e3b38 WD |
329 | int x, y; |
330 | ||
e23741f4 HS |
331 | for (x = 0; x < sizeof(struct cfi_qry); x += 16) { |
332 | debug("%02x : ", x); | |
333 | for (y = 0; y < 16; y++) | |
334 | debug("%2.2x ", p[x + y]); | |
335 | debug(" "); | |
bf9e3b38 | 336 | for (y = 0; y < 16; y++) { |
e23741f4 HS |
337 | unsigned char c = p[x + y]; |
338 | if (c >= 0x20 && c <= 0x7e) | |
339 | debug("%c", c); | |
340 | else | |
341 | debug("."); | |
bf9e3b38 | 342 | } |
e23741f4 | 343 | debug("\n"); |
bf9e3b38 | 344 | } |
5653fc33 WD |
345 | } |
346 | #endif | |
347 | ||
348 | ||
5653fc33 WD |
349 | /*----------------------------------------------------------------------- |
350 | * read a character at a port width address | |
351 | */ | |
3055793b | 352 | static inline uchar flash_read_uchar (flash_info_t * info, uint offset) |
5653fc33 WD |
353 | { |
354 | uchar *cp; | |
12d30aa7 | 355 | uchar retval; |
bf9e3b38 | 356 | |
12d30aa7 | 357 | cp = flash_map (info, 0, offset); |
d0b6e140 | 358 | #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) |
12d30aa7 | 359 | retval = flash_read8(cp); |
bf9e3b38 | 360 | #else |
12d30aa7 | 361 | retval = flash_read8(cp + info->portwidth - 1); |
bf9e3b38 | 362 | #endif |
12d30aa7 HS |
363 | flash_unmap (info, 0, offset, cp); |
364 | return retval; | |
5653fc33 WD |
365 | } |
366 | ||
5653fc33 | 367 | /*----------------------------------------------------------------------- |
260421a2 | 368 | * read a long word by picking the least significant byte of each maximum |
5653fc33 WD |
369 | * port size word. Swap for ppc format. |
370 | */ | |
3055793b HS |
371 | static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, |
372 | uint offset) | |
5653fc33 | 373 | { |
bf9e3b38 WD |
374 | uchar *addr; |
375 | ulong retval; | |
376 | ||
377 | #ifdef DEBUG | |
378 | int x; | |
379 | #endif | |
12d30aa7 | 380 | addr = flash_map (info, sect, offset); |
5653fc33 | 381 | |
bf9e3b38 WD |
382 | #ifdef DEBUG |
383 | debug ("long addr is at %p info->portwidth = %d\n", addr, | |
384 | info->portwidth); | |
385 | for (x = 0; x < 4 * info->portwidth; x++) { | |
12d30aa7 | 386 | debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); |
bf9e3b38 WD |
387 | } |
388 | #endif | |
d0b6e140 | 389 | #if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) |
12d30aa7 HS |
390 | retval = ((flash_read8(addr) << 16) | |
391 | (flash_read8(addr + info->portwidth) << 24) | | |
392 | (flash_read8(addr + 2 * info->portwidth)) | | |
393 | (flash_read8(addr + 3 * info->portwidth) << 8)); | |
bf9e3b38 | 394 | #else |
12d30aa7 HS |
395 | retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | |
396 | (flash_read8(addr + info->portwidth - 1) << 16) | | |
397 | (flash_read8(addr + 4 * info->portwidth - 1) << 8) | | |
398 | (flash_read8(addr + 3 * info->portwidth - 1))); | |
bf9e3b38 | 399 | #endif |
12d30aa7 HS |
400 | flash_unmap(info, sect, offset, addr); |
401 | ||
bf9e3b38 | 402 | return retval; |
5653fc33 WD |
403 | } |
404 | ||
be60a902 HS |
405 | /* |
406 | * Write a proper sized command to the correct address | |
81b20ccc | 407 | */ |
be60a902 HS |
408 | static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, |
409 | uint offset, uchar cmd) | |
81b20ccc | 410 | { |
7e5b9b47 | 411 | |
cdbaefb5 | 412 | void *addr; |
be60a902 | 413 | cfiword_t cword; |
81b20ccc | 414 | |
12d30aa7 | 415 | addr = flash_map (info, sect, offset); |
be60a902 HS |
416 | flash_make_cmd (info, cmd, &cword); |
417 | switch (info->portwidth) { | |
418 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 419 | debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, |
be60a902 | 420 | cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
cdbaefb5 | 421 | flash_write8(cword.c, addr); |
be60a902 HS |
422 | break; |
423 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 424 | debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, |
be60a902 HS |
425 | cmd, cword.w, |
426 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
cdbaefb5 | 427 | flash_write16(cword.w, addr); |
be60a902 HS |
428 | break; |
429 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 430 | debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, |
be60a902 HS |
431 | cmd, cword.l, |
432 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
cdbaefb5 | 433 | flash_write32(cword.l, addr); |
be60a902 HS |
434 | break; |
435 | case FLASH_CFI_64BIT: | |
436 | #ifdef DEBUG | |
437 | { | |
438 | char str[20]; | |
7e5b9b47 | 439 | |
be60a902 HS |
440 | print_longlong (str, cword.ll); |
441 | ||
442 | debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", | |
cdbaefb5 | 443 | addr, cmd, str, |
be60a902 | 444 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
81b20ccc | 445 | } |
be60a902 | 446 | #endif |
cdbaefb5 | 447 | flash_write64(cword.ll, addr); |
be60a902 | 448 | break; |
81b20ccc | 449 | } |
be60a902 HS |
450 | |
451 | /* Ensure all the instructions are fully finished */ | |
452 | sync(); | |
12d30aa7 HS |
453 | |
454 | flash_unmap(info, sect, offset, addr); | |
81b20ccc | 455 | } |
be60a902 HS |
456 | |
457 | static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) | |
81b20ccc | 458 | { |
be60a902 HS |
459 | flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); |
460 | flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); | |
81b20ccc | 461 | } |
81b20ccc | 462 | |
5653fc33 WD |
463 | /*----------------------------------------------------------------------- |
464 | */ | |
be60a902 HS |
465 | static int flash_isequal (flash_info_t * info, flash_sect_t sect, |
466 | uint offset, uchar cmd) | |
5653fc33 | 467 | { |
cdbaefb5 | 468 | void *addr; |
be60a902 HS |
469 | cfiword_t cword; |
470 | int retval; | |
5653fc33 | 471 | |
12d30aa7 | 472 | addr = flash_map (info, sect, offset); |
be60a902 | 473 | flash_make_cmd (info, cmd, &cword); |
2662b40c | 474 | |
cdbaefb5 | 475 | debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); |
be60a902 HS |
476 | switch (info->portwidth) { |
477 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
478 | debug ("is= %x %x\n", flash_read8(addr), cword.c); |
479 | retval = (flash_read8(addr) == cword.c); | |
be60a902 HS |
480 | break; |
481 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
482 | debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); |
483 | retval = (flash_read16(addr) == cword.w); | |
be60a902 HS |
484 | break; |
485 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
486 | debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l); |
487 | retval = (flash_read32(addr) == cword.l); | |
be60a902 HS |
488 | break; |
489 | case FLASH_CFI_64BIT: | |
490 | #ifdef DEBUG | |
491 | { | |
492 | char str1[20]; | |
493 | char str2[20]; | |
81b20ccc | 494 | |
cdbaefb5 | 495 | print_longlong (str1, flash_read64(addr)); |
be60a902 HS |
496 | print_longlong (str2, cword.ll); |
497 | debug ("is= %s %s\n", str1, str2); | |
5653fc33 | 498 | } |
be60a902 | 499 | #endif |
cdbaefb5 | 500 | retval = (flash_read64(addr) == cword.ll); |
be60a902 HS |
501 | break; |
502 | default: | |
503 | retval = 0; | |
504 | break; | |
505 | } | |
12d30aa7 HS |
506 | flash_unmap(info, sect, offset, addr); |
507 | ||
be60a902 HS |
508 | return retval; |
509 | } | |
79b4cda0 | 510 | |
be60a902 HS |
511 | /*----------------------------------------------------------------------- |
512 | */ | |
513 | static int flash_isset (flash_info_t * info, flash_sect_t sect, | |
514 | uint offset, uchar cmd) | |
515 | { | |
cdbaefb5 | 516 | void *addr; |
be60a902 HS |
517 | cfiword_t cword; |
518 | int retval; | |
2662b40c | 519 | |
12d30aa7 | 520 | addr = flash_map (info, sect, offset); |
be60a902 HS |
521 | flash_make_cmd (info, cmd, &cword); |
522 | switch (info->portwidth) { | |
523 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 524 | retval = ((flash_read8(addr) & cword.c) == cword.c); |
be60a902 HS |
525 | break; |
526 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 527 | retval = ((flash_read16(addr) & cword.w) == cword.w); |
be60a902 HS |
528 | break; |
529 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 530 | retval = ((flash_read16(addr) & cword.l) == cword.l); |
be60a902 HS |
531 | break; |
532 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 533 | retval = ((flash_read64(addr) & cword.ll) == cword.ll); |
be60a902 HS |
534 | break; |
535 | default: | |
536 | retval = 0; | |
537 | break; | |
538 | } | |
12d30aa7 HS |
539 | flash_unmap(info, sect, offset, addr); |
540 | ||
be60a902 HS |
541 | return retval; |
542 | } | |
2662b40c | 543 | |
be60a902 HS |
544 | /*----------------------------------------------------------------------- |
545 | */ | |
546 | static int flash_toggle (flash_info_t * info, flash_sect_t sect, | |
547 | uint offset, uchar cmd) | |
548 | { | |
cdbaefb5 | 549 | void *addr; |
be60a902 HS |
550 | cfiword_t cword; |
551 | int retval; | |
656658dd | 552 | |
12d30aa7 | 553 | addr = flash_map (info, sect, offset); |
be60a902 HS |
554 | flash_make_cmd (info, cmd, &cword); |
555 | switch (info->portwidth) { | |
556 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
557 | retval = ((flash_read8(addr) & cword.c) != |
558 | (flash_read8(addr) & cword.c)); | |
be60a902 HS |
559 | break; |
560 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
561 | retval = ((flash_read16(addr) & cword.w) != |
562 | (flash_read16(addr) & cword.w)); | |
be60a902 HS |
563 | break; |
564 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
565 | retval = ((flash_read32(addr) & cword.l) != |
566 | (flash_read32(addr) & cword.l)); | |
be60a902 HS |
567 | break; |
568 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
569 | retval = ((flash_read64(addr) & cword.ll) != |
570 | (flash_read64(addr) & cword.ll)); | |
be60a902 HS |
571 | break; |
572 | default: | |
573 | retval = 0; | |
574 | break; | |
575 | } | |
12d30aa7 HS |
576 | flash_unmap(info, sect, offset, addr); |
577 | ||
be60a902 | 578 | return retval; |
5653fc33 WD |
579 | } |
580 | ||
be60a902 HS |
581 | /* |
582 | * flash_is_busy - check to see if the flash is busy | |
583 | * | |
584 | * This routine checks the status of the chip and returns true if the | |
585 | * chip is busy. | |
7680c140 | 586 | */ |
be60a902 | 587 | static int flash_is_busy (flash_info_t * info, flash_sect_t sect) |
7680c140 | 588 | { |
be60a902 | 589 | int retval; |
7680c140 | 590 | |
be60a902 HS |
591 | switch (info->vendor) { |
592 | case CFI_CMDSET_INTEL_STANDARD: | |
593 | case CFI_CMDSET_INTEL_EXTENDED: | |
594 | retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); | |
595 | break; | |
596 | case CFI_CMDSET_AMD_STANDARD: | |
597 | case CFI_CMDSET_AMD_EXTENDED: | |
598 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
599 | case CFI_CMDSET_AMD_LEGACY: | |
600 | #endif | |
601 | retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); | |
602 | break; | |
603 | default: | |
604 | retval = 0; | |
7680c140 | 605 | } |
be60a902 HS |
606 | debug ("flash_is_busy: %d\n", retval); |
607 | return retval; | |
7680c140 WD |
608 | } |
609 | ||
5653fc33 | 610 | /*----------------------------------------------------------------------- |
be60a902 HS |
611 | * wait for XSR.7 to be set. Time out with an error if it does not. |
612 | * This routine does not set the flash to read-array mode. | |
5653fc33 | 613 | */ |
be60a902 HS |
614 | static int flash_status_check (flash_info_t * info, flash_sect_t sector, |
615 | ulong tout, char *prompt) | |
5653fc33 | 616 | { |
be60a902 | 617 | ulong start; |
5653fc33 | 618 | |
be60a902 HS |
619 | #if CFG_HZ != 1000 |
620 | tout *= CFG_HZ/1000; | |
621 | #endif | |
5653fc33 | 622 | |
be60a902 HS |
623 | /* Wait for command completion */ |
624 | start = get_timer (0); | |
625 | while (flash_is_busy (info, sector)) { | |
626 | if (get_timer (start) > tout) { | |
627 | printf ("Flash %s timeout at address %lx data %lx\n", | |
628 | prompt, info->start[sector], | |
629 | flash_read_long (info, sector, 0)); | |
630 | flash_write_cmd (info, sector, 0, info->cmd_reset); | |
631 | return ERR_TIMOUT; | |
5653fc33 | 632 | } |
be60a902 | 633 | udelay (1); /* also triggers watchdog */ |
5653fc33 | 634 | } |
be60a902 HS |
635 | return ERR_OK; |
636 | } | |
5653fc33 | 637 | |
be60a902 HS |
638 | /*----------------------------------------------------------------------- |
639 | * Wait for XSR.7 to be set, if it times out print an error, otherwise | |
640 | * do a full status check. | |
641 | * | |
642 | * This routine sets the flash to read-array mode. | |
643 | */ | |
644 | static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, | |
645 | ulong tout, char *prompt) | |
646 | { | |
647 | int retcode; | |
5653fc33 | 648 | |
be60a902 HS |
649 | retcode = flash_status_check (info, sector, tout, prompt); |
650 | switch (info->vendor) { | |
651 | case CFI_CMDSET_INTEL_EXTENDED: | |
652 | case CFI_CMDSET_INTEL_STANDARD: | |
653 | if ((retcode == ERR_OK) | |
654 | && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { | |
655 | retcode = ERR_INVAL; | |
656 | printf ("Flash %s error at address %lx\n", prompt, | |
657 | info->start[sector]); | |
658 | if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | | |
659 | FLASH_STATUS_PSLBS)) { | |
660 | puts ("Command Sequence Error.\n"); | |
661 | } else if (flash_isset (info, sector, 0, | |
662 | FLASH_STATUS_ECLBS)) { | |
663 | puts ("Block Erase Error.\n"); | |
664 | retcode = ERR_NOT_ERASED; | |
665 | } else if (flash_isset (info, sector, 0, | |
666 | FLASH_STATUS_PSLBS)) { | |
667 | puts ("Locking Error\n"); | |
5653fc33 | 668 | } |
be60a902 HS |
669 | if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { |
670 | puts ("Block locked.\n"); | |
671 | retcode = ERR_PROTECTED; | |
672 | } | |
673 | if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) | |
674 | puts ("Vpp Low Error.\n"); | |
5653fc33 | 675 | } |
be60a902 HS |
676 | flash_write_cmd (info, sector, 0, info->cmd_reset); |
677 | break; | |
678 | default: | |
679 | break; | |
5653fc33 | 680 | } |
be60a902 | 681 | return retcode; |
5653fc33 WD |
682 | } |
683 | ||
684 | /*----------------------------------------------------------------------- | |
685 | */ | |
be60a902 | 686 | static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) |
5653fc33 | 687 | { |
be60a902 HS |
688 | #if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) |
689 | unsigned short w; | |
690 | unsigned int l; | |
691 | unsigned long long ll; | |
692 | #endif | |
5653fc33 | 693 | |
be60a902 HS |
694 | switch (info->portwidth) { |
695 | case FLASH_CFI_8BIT: | |
696 | cword->c = c; | |
697 | break; | |
698 | case FLASH_CFI_16BIT: | |
699 | #if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) | |
700 | w = c; | |
701 | w <<= 8; | |
702 | cword->w = (cword->w >> 8) | w; | |
703 | #else | |
704 | cword->w = (cword->w << 8) | c; | |
81b20ccc | 705 | #endif |
be60a902 HS |
706 | break; |
707 | case FLASH_CFI_32BIT: | |
708 | #if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) | |
709 | l = c; | |
710 | l <<= 24; | |
711 | cword->l = (cword->l >> 8) | l; | |
712 | #else | |
713 | cword->l = (cword->l << 8) | c; | |
714 | #endif | |
715 | break; | |
716 | case FLASH_CFI_64BIT: | |
717 | #if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) | |
718 | ll = c; | |
719 | ll <<= 56; | |
720 | cword->ll = (cword->ll >> 8) | ll; | |
721 | #else | |
722 | cword->ll = (cword->ll << 8) | c; | |
723 | #endif | |
724 | break; | |
260421a2 | 725 | } |
be60a902 | 726 | } |
5653fc33 | 727 | |
be60a902 HS |
728 | /* loop through the sectors from the highest address when the passed |
729 | * address is greater or equal to the sector address we have a match | |
730 | */ | |
731 | static flash_sect_t find_sector (flash_info_t * info, ulong addr) | |
732 | { | |
733 | flash_sect_t sector; | |
5653fc33 | 734 | |
be60a902 HS |
735 | for (sector = info->sector_count - 1; sector >= 0; sector--) { |
736 | if (addr >= info->start[sector]) | |
737 | break; | |
5653fc33 | 738 | } |
be60a902 | 739 | return sector; |
5653fc33 WD |
740 | } |
741 | ||
742 | /*----------------------------------------------------------------------- | |
5653fc33 | 743 | */ |
be60a902 HS |
744 | static int flash_write_cfiword (flash_info_t * info, ulong dest, |
745 | cfiword_t cword) | |
5653fc33 | 746 | { |
cdbaefb5 | 747 | void *dstaddr; |
be60a902 | 748 | int flag; |
5653fc33 | 749 | |
12d30aa7 | 750 | dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE); |
5653fc33 | 751 | |
be60a902 HS |
752 | /* Check if Flash is (sufficiently) erased */ |
753 | switch (info->portwidth) { | |
754 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 755 | flag = ((flash_read8(dstaddr) & cword.c) == cword.c); |
be60a902 HS |
756 | break; |
757 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 758 | flag = ((flash_read16(dstaddr) & cword.w) == cword.w); |
be60a902 HS |
759 | break; |
760 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 761 | flag = ((flash_read32(dstaddr) & cword.l) == cword.l); |
be60a902 HS |
762 | break; |
763 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 764 | flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); |
be60a902 HS |
765 | break; |
766 | default: | |
12d30aa7 HS |
767 | flag = 0; |
768 | break; | |
5653fc33 | 769 | } |
12d30aa7 HS |
770 | if (!flag) { |
771 | unmap_physmem(dstaddr, info->portwidth); | |
be60a902 | 772 | return 2; |
12d30aa7 | 773 | } |
5653fc33 | 774 | |
be60a902 HS |
775 | /* Disable interrupts which might cause a timeout here */ |
776 | flag = disable_interrupts (); | |
79b4cda0 | 777 | |
be60a902 HS |
778 | switch (info->vendor) { |
779 | case CFI_CMDSET_INTEL_EXTENDED: | |
780 | case CFI_CMDSET_INTEL_STANDARD: | |
781 | flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); | |
782 | flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); | |
783 | break; | |
784 | case CFI_CMDSET_AMD_EXTENDED: | |
785 | case CFI_CMDSET_AMD_STANDARD: | |
786 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
787 | case CFI_CMDSET_AMD_LEGACY: | |
788 | #endif | |
789 | flash_unlock_seq (info, 0); | |
790 | flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); | |
791 | break; | |
5653fc33 WD |
792 | } |
793 | ||
be60a902 HS |
794 | switch (info->portwidth) { |
795 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 796 | flash_write8(cword.c, dstaddr); |
be60a902 HS |
797 | break; |
798 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 799 | flash_write16(cword.w, dstaddr); |
be60a902 HS |
800 | break; |
801 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 802 | flash_write32(cword.l, dstaddr); |
be60a902 HS |
803 | break; |
804 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 805 | flash_write64(cword.ll, dstaddr); |
be60a902 | 806 | break; |
5653fc33 WD |
807 | } |
808 | ||
be60a902 HS |
809 | /* re-enable interrupts if necessary */ |
810 | if (flag) | |
811 | enable_interrupts (); | |
5653fc33 | 812 | |
12d30aa7 HS |
813 | unmap_physmem(dstaddr, info->portwidth); |
814 | ||
be60a902 HS |
815 | return flash_full_status_check (info, find_sector (info, dest), |
816 | info->write_tout, "write"); | |
5653fc33 WD |
817 | } |
818 | ||
be60a902 | 819 | #ifdef CFG_FLASH_USE_BUFFER_WRITE |
5653fc33 | 820 | |
be60a902 HS |
821 | static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, |
822 | int len) | |
5653fc33 | 823 | { |
be60a902 HS |
824 | flash_sect_t sector; |
825 | int cnt; | |
826 | int retcode; | |
cdbaefb5 | 827 | void *src = cp; |
12d30aa7 | 828 | void *dst = map_physmem(dest, len, MAP_NOCACHE); |
cdbaefb5 HS |
829 | |
830 | sector = find_sector (info, dest); | |
bf9e3b38 WD |
831 | |
832 | switch (info->vendor) { | |
5653fc33 WD |
833 | case CFI_CMDSET_INTEL_STANDARD: |
834 | case CFI_CMDSET_INTEL_EXTENDED: | |
be60a902 HS |
835 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
836 | flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); | |
837 | retcode = flash_status_check (info, sector, | |
838 | info->buffer_write_tout, | |
839 | "write to buffer"); | |
840 | if (retcode == ERR_OK) { | |
841 | /* reduce the number of loops by the width of | |
842 | * the port */ | |
843 | switch (info->portwidth) { | |
844 | case FLASH_CFI_8BIT: | |
845 | cnt = len; | |
846 | break; | |
847 | case FLASH_CFI_16BIT: | |
848 | cnt = len >> 1; | |
849 | break; | |
850 | case FLASH_CFI_32BIT: | |
851 | cnt = len >> 2; | |
852 | break; | |
853 | case FLASH_CFI_64BIT: | |
854 | cnt = len >> 3; | |
855 | break; | |
856 | default: | |
12d30aa7 HS |
857 | retcode = ERR_INVAL; |
858 | goto out_unmap; | |
be60a902 HS |
859 | } |
860 | flash_write_cmd (info, sector, 0, (uchar) cnt - 1); | |
861 | while (cnt-- > 0) { | |
862 | switch (info->portwidth) { | |
863 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
864 | flash_write8(flash_read8(src), dst); |
865 | src += 1, dst += 1; | |
be60a902 HS |
866 | break; |
867 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
868 | flash_write16(flash_read16(src), dst); |
869 | src += 2, dst += 2; | |
be60a902 HS |
870 | break; |
871 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
872 | flash_write32(flash_read32(src), dst); |
873 | src += 4, dst += 4; | |
be60a902 HS |
874 | break; |
875 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
876 | flash_write64(flash_read64(src), dst); |
877 | src += 8, dst += 8; | |
be60a902 HS |
878 | break; |
879 | default: | |
12d30aa7 HS |
880 | retcode = ERR_INVAL; |
881 | goto out_unmap; | |
be60a902 HS |
882 | } |
883 | } | |
884 | flash_write_cmd (info, sector, 0, | |
885 | FLASH_CMD_WRITE_BUFFER_CONFIRM); | |
886 | retcode = flash_full_status_check ( | |
887 | info, sector, info->buffer_write_tout, | |
888 | "buffer write"); | |
889 | } | |
12d30aa7 HS |
890 | |
891 | break; | |
be60a902 | 892 | |
5653fc33 WD |
893 | case CFI_CMDSET_AMD_STANDARD: |
894 | case CFI_CMDSET_AMD_EXTENDED: | |
be60a902 HS |
895 | flash_unlock_seq(info,0); |
896 | flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER); | |
897 | ||
898 | switch (info->portwidth) { | |
899 | case FLASH_CFI_8BIT: | |
900 | cnt = len; | |
901 | flash_write_cmd (info, sector, 0, (uchar) cnt - 1); | |
cdbaefb5 HS |
902 | while (cnt-- > 0) { |
903 | flash_write8(flash_read8(src), dst); | |
904 | src += 1, dst += 1; | |
905 | } | |
be60a902 HS |
906 | break; |
907 | case FLASH_CFI_16BIT: | |
908 | cnt = len >> 1; | |
909 | flash_write_cmd (info, sector, 0, (uchar) cnt - 1); | |
cdbaefb5 HS |
910 | while (cnt-- > 0) { |
911 | flash_write16(flash_read16(src), dst); | |
912 | src += 2, dst += 2; | |
913 | } | |
be60a902 HS |
914 | break; |
915 | case FLASH_CFI_32BIT: | |
916 | cnt = len >> 2; | |
917 | flash_write_cmd (info, sector, 0, (uchar) cnt - 1); | |
cdbaefb5 HS |
918 | while (cnt-- > 0) { |
919 | flash_write32(flash_read32(src), dst); | |
920 | src += 4, dst += 4; | |
921 | } | |
be60a902 HS |
922 | break; |
923 | case FLASH_CFI_64BIT: | |
924 | cnt = len >> 3; | |
925 | flash_write_cmd (info, sector, 0, (uchar) cnt - 1); | |
cdbaefb5 HS |
926 | while (cnt-- > 0) { |
927 | flash_write64(flash_read64(src), dst); | |
928 | src += 8, dst += 8; | |
929 | } | |
be60a902 HS |
930 | break; |
931 | default: | |
12d30aa7 HS |
932 | retcode = ERR_INVAL; |
933 | goto out_unmap; | |
be60a902 HS |
934 | } |
935 | ||
936 | flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); | |
937 | retcode = flash_full_status_check (info, sector, | |
938 | info->buffer_write_tout, | |
939 | "buffer write"); | |
12d30aa7 | 940 | break; |
be60a902 | 941 | |
5653fc33 | 942 | default: |
be60a902 | 943 | debug ("Unknown Command Set\n"); |
12d30aa7 HS |
944 | retcode = ERR_INVAL; |
945 | break; | |
5653fc33 | 946 | } |
12d30aa7 HS |
947 | |
948 | out_unmap: | |
949 | unmap_physmem(dst, len); | |
950 | return retcode; | |
5653fc33 | 951 | } |
be60a902 HS |
952 | #endif /* CFG_FLASH_USE_BUFFER_WRITE */ |
953 | ||
bf9e3b38 | 954 | |
5653fc33 | 955 | /*----------------------------------------------------------------------- |
5653fc33 | 956 | */ |
be60a902 | 957 | int flash_erase (flash_info_t * info, int s_first, int s_last) |
5653fc33 | 958 | { |
be60a902 HS |
959 | int rcode = 0; |
960 | int prot; | |
961 | flash_sect_t sect; | |
5653fc33 | 962 | |
be60a902 HS |
963 | if (info->flash_id != FLASH_MAN_CFI) { |
964 | puts ("Can't erase unknown flash type - aborted\n"); | |
965 | return 1; | |
966 | } | |
967 | if ((s_first < 0) || (s_first > s_last)) { | |
968 | puts ("- no sectors to erase\n"); | |
969 | return 1; | |
970 | } | |
2662b40c | 971 | |
be60a902 HS |
972 | prot = 0; |
973 | for (sect = s_first; sect <= s_last; ++sect) { | |
974 | if (info->protect[sect]) { | |
975 | prot++; | |
5653fc33 WD |
976 | } |
977 | } | |
be60a902 HS |
978 | if (prot) { |
979 | printf ("- Warning: %d protected sectors will not be erased!\n", | |
980 | prot); | |
981 | } else { | |
982 | putc ('\n'); | |
983 | } | |
bf9e3b38 | 984 | |
bf9e3b38 | 985 | |
be60a902 HS |
986 | for (sect = s_first; sect <= s_last; sect++) { |
987 | if (info->protect[sect] == 0) { /* not protected */ | |
988 | switch (info->vendor) { | |
989 | case CFI_CMDSET_INTEL_STANDARD: | |
990 | case CFI_CMDSET_INTEL_EXTENDED: | |
991 | flash_write_cmd (info, sect, 0, | |
992 | FLASH_CMD_CLEAR_STATUS); | |
993 | flash_write_cmd (info, sect, 0, | |
994 | FLASH_CMD_BLOCK_ERASE); | |
995 | flash_write_cmd (info, sect, 0, | |
996 | FLASH_CMD_ERASE_CONFIRM); | |
997 | break; | |
998 | case CFI_CMDSET_AMD_STANDARD: | |
999 | case CFI_CMDSET_AMD_EXTENDED: | |
1000 | flash_unlock_seq (info, sect); | |
1001 | flash_write_cmd (info, sect, | |
1002 | info->addr_unlock1, | |
1003 | AMD_CMD_ERASE_START); | |
1004 | flash_unlock_seq (info, sect); | |
1005 | flash_write_cmd (info, sect, 0, | |
1006 | AMD_CMD_ERASE_SECTOR); | |
1007 | break; | |
1008 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1009 | case CFI_CMDSET_AMD_LEGACY: | |
1010 | flash_unlock_seq (info, 0); | |
1011 | flash_write_cmd (info, 0, info->addr_unlock1, | |
1012 | AMD_CMD_ERASE_START); | |
1013 | flash_unlock_seq (info, 0); | |
1014 | flash_write_cmd (info, sect, 0, | |
1015 | AMD_CMD_ERASE_SECTOR); | |
1016 | break; | |
1017 | #endif | |
1018 | default: | |
1019 | debug ("Unkown flash vendor %d\n", | |
1020 | info->vendor); | |
1021 | break; | |
bf9e3b38 | 1022 | } |
be60a902 HS |
1023 | |
1024 | if (flash_full_status_check | |
1025 | (info, sect, info->erase_blk_tout, "erase")) { | |
1026 | rcode = 1; | |
1027 | } else | |
1028 | putc ('.'); | |
5653fc33 | 1029 | } |
5653fc33 | 1030 | } |
be60a902 HS |
1031 | puts (" done\n"); |
1032 | return rcode; | |
5653fc33 | 1033 | } |
bf9e3b38 | 1034 | |
5653fc33 WD |
1035 | /*----------------------------------------------------------------------- |
1036 | */ | |
be60a902 | 1037 | void flash_print_info (flash_info_t * info) |
5653fc33 | 1038 | { |
be60a902 | 1039 | int i; |
4d13cbad | 1040 | |
be60a902 HS |
1041 | if (info->flash_id != FLASH_MAN_CFI) { |
1042 | puts ("missing or unknown FLASH type\n"); | |
1043 | return; | |
1044 | } | |
1045 | ||
1046 | printf ("%s FLASH (%d x %d)", | |
1047 | info->name, | |
1048 | (info->portwidth << 3), (info->chipwidth << 3)); | |
1049 | if (info->size < 1024*1024) | |
1050 | printf (" Size: %ld kB in %d Sectors\n", | |
1051 | info->size >> 10, info->sector_count); | |
1052 | else | |
1053 | printf (" Size: %ld MB in %d Sectors\n", | |
1054 | info->size >> 20, info->sector_count); | |
1055 | printf (" "); | |
1056 | switch (info->vendor) { | |
1057 | case CFI_CMDSET_INTEL_STANDARD: | |
1058 | printf ("Intel Standard"); | |
1059 | break; | |
1060 | case CFI_CMDSET_INTEL_EXTENDED: | |
1061 | printf ("Intel Extended"); | |
1062 | break; | |
1063 | case CFI_CMDSET_AMD_STANDARD: | |
1064 | printf ("AMD Standard"); | |
1065 | break; | |
1066 | case CFI_CMDSET_AMD_EXTENDED: | |
1067 | printf ("AMD Extended"); | |
1068 | break; | |
1069 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1070 | case CFI_CMDSET_AMD_LEGACY: | |
1071 | printf ("AMD Legacy"); | |
1072 | break; | |
4d13cbad | 1073 | #endif |
be60a902 HS |
1074 | default: |
1075 | printf ("Unknown (%d)", info->vendor); | |
1076 | break; | |
1077 | } | |
1078 | printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X", | |
1079 | info->manufacturer_id, info->device_id); | |
1080 | if (info->device_id == 0x7E) { | |
1081 | printf("%04X", info->device_id2); | |
1082 | } | |
1083 | printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", | |
1084 | info->erase_blk_tout, | |
1085 | info->write_tout); | |
1086 | if (info->buffer_size > 1) { | |
1087 | printf (" Buffer write timeout: %ld ms, " | |
1088 | "buffer size: %d bytes\n", | |
1089 | info->buffer_write_tout, | |
1090 | info->buffer_size); | |
5653fc33 | 1091 | } |
5653fc33 | 1092 | |
be60a902 HS |
1093 | puts ("\n Sector Start Addresses:"); |
1094 | for (i = 0; i < info->sector_count; ++i) { | |
1095 | if ((i % 5) == 0) | |
1096 | printf ("\n"); | |
1097 | #ifdef CFG_FLASH_EMPTY_INFO | |
1098 | int k; | |
1099 | int size; | |
1100 | int erased; | |
1101 | volatile unsigned long *flash; | |
5653fc33 | 1102 | |
be60a902 HS |
1103 | /* |
1104 | * Check if whole sector is erased | |
1105 | */ | |
12d30aa7 | 1106 | size = flash_sector_size(info, i); |
be60a902 HS |
1107 | erased = 1; |
1108 | flash = (volatile unsigned long *) info->start[i]; | |
1109 | size = size >> 2; /* divide by 4 for longword access */ | |
1110 | for (k = 0; k < size; k++) { | |
1111 | if (*flash++ != 0xffffffff) { | |
1112 | erased = 0; | |
1113 | break; | |
1114 | } | |
1115 | } | |
bf9e3b38 | 1116 | |
be60a902 HS |
1117 | /* print empty and read-only info */ |
1118 | printf (" %08lX %c %s ", | |
1119 | info->start[i], | |
1120 | erased ? 'E' : ' ', | |
1121 | info->protect[i] ? "RO" : " "); | |
1122 | #else /* ! CFG_FLASH_EMPTY_INFO */ | |
1123 | printf (" %08lX %s ", | |
1124 | info->start[i], | |
1125 | info->protect[i] ? "RO" : " "); | |
bf9e3b38 | 1126 | #endif |
be60a902 HS |
1127 | } |
1128 | putc ('\n'); | |
1129 | return; | |
5653fc33 WD |
1130 | } |
1131 | ||
be60a902 HS |
1132 | /*----------------------------------------------------------------------- |
1133 | * Copy memory to flash, returns: | |
1134 | * 0 - OK | |
1135 | * 1 - write timeout | |
1136 | * 2 - Flash not erased | |
5653fc33 | 1137 | */ |
be60a902 | 1138 | int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
5653fc33 | 1139 | { |
be60a902 | 1140 | ulong wp; |
12d30aa7 | 1141 | uchar *p; |
be60a902 | 1142 | int aln; |
5653fc33 | 1143 | cfiword_t cword; |
be60a902 | 1144 | int i, rc; |
bf9e3b38 | 1145 | |
be60a902 HS |
1146 | #ifdef CFG_FLASH_USE_BUFFER_WRITE |
1147 | int buffered_size; | |
5653fc33 | 1148 | #endif |
be60a902 HS |
1149 | /* get lower aligned address */ |
1150 | wp = (addr & ~(info->portwidth - 1)); | |
3a197b2f | 1151 | |
be60a902 HS |
1152 | /* handle unaligned start */ |
1153 | if ((aln = addr - wp) != 0) { | |
1154 | cword.l = 0; | |
12d30aa7 HS |
1155 | p = map_physmem(wp, info->portwidth, MAP_NOCACHE); |
1156 | for (i = 0; i < aln; ++i) | |
1157 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
5653fc33 | 1158 | |
be60a902 HS |
1159 | for (; (i < info->portwidth) && (cnt > 0); i++) { |
1160 | flash_add_byte (info, &cword, *src++); | |
1161 | cnt--; | |
be60a902 | 1162 | } |
12d30aa7 HS |
1163 | for (; (cnt == 0) && (i < info->portwidth); ++i) |
1164 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
1165 | ||
1166 | rc = flash_write_cfiword (info, wp, cword); | |
1167 | unmap_physmem(p, info->portwidth); | |
1168 | if (rc != 0) | |
be60a902 | 1169 | return rc; |
12d30aa7 HS |
1170 | |
1171 | wp += i; | |
be60a902 HS |
1172 | } |
1173 | ||
1174 | /* handle the aligned part */ | |
1175 | #ifdef CFG_FLASH_USE_BUFFER_WRITE | |
1176 | buffered_size = (info->portwidth / info->chipwidth); | |
1177 | buffered_size *= info->buffer_size; | |
1178 | while (cnt >= info->portwidth) { | |
1179 | /* prohibit buffer write when buffer_size is 1 */ | |
1180 | if (info->buffer_size == 1) { | |
1181 | cword.l = 0; | |
1182 | for (i = 0; i < info->portwidth; i++) | |
1183 | flash_add_byte (info, &cword, *src++); | |
1184 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
1185 | return rc; | |
1186 | wp += info->portwidth; | |
1187 | cnt -= info->portwidth; | |
1188 | continue; | |
1189 | } | |
1190 | ||
1191 | /* write buffer until next buffered_size aligned boundary */ | |
1192 | i = buffered_size - (wp % buffered_size); | |
1193 | if (i > cnt) | |
1194 | i = cnt; | |
1195 | if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) | |
1196 | return rc; | |
1197 | i -= i & (info->portwidth - 1); | |
1198 | wp += i; | |
1199 | src += i; | |
1200 | cnt -= i; | |
1201 | } | |
1202 | #else | |
1203 | while (cnt >= info->portwidth) { | |
1204 | cword.l = 0; | |
1205 | for (i = 0; i < info->portwidth; i++) { | |
1206 | flash_add_byte (info, &cword, *src++); | |
1207 | } | |
1208 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
1209 | return rc; | |
1210 | wp += info->portwidth; | |
1211 | cnt -= info->portwidth; | |
1212 | } | |
1213 | #endif /* CFG_FLASH_USE_BUFFER_WRITE */ | |
1214 | if (cnt == 0) { | |
1215 | return (0); | |
1216 | } | |
1217 | ||
1218 | /* | |
1219 | * handle unaligned tail bytes | |
1220 | */ | |
1221 | cword.l = 0; | |
12d30aa7 HS |
1222 | p = map_physmem(wp, info->portwidth, MAP_NOCACHE); |
1223 | for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { | |
be60a902 HS |
1224 | flash_add_byte (info, &cword, *src++); |
1225 | --cnt; | |
1226 | } | |
12d30aa7 HS |
1227 | for (; i < info->portwidth; ++i) |
1228 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
1229 | unmap_physmem(p, info->portwidth); | |
be60a902 HS |
1230 | |
1231 | return flash_write_cfiword (info, wp, cword); | |
5653fc33 | 1232 | } |
bf9e3b38 | 1233 | |
5653fc33 WD |
1234 | /*----------------------------------------------------------------------- |
1235 | */ | |
be60a902 HS |
1236 | #ifdef CFG_FLASH_PROTECTION |
1237 | ||
1238 | int flash_real_protect (flash_info_t * info, long sector, int prot) | |
5653fc33 | 1239 | { |
be60a902 | 1240 | int retcode = 0; |
5653fc33 | 1241 | |
be60a902 HS |
1242 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
1243 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); | |
1244 | if (prot) | |
1245 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); | |
1246 | else | |
1247 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); | |
bf9e3b38 | 1248 | |
be60a902 HS |
1249 | if ((retcode = |
1250 | flash_full_status_check (info, sector, info->erase_blk_tout, | |
1251 | prot ? "protect" : "unprotect")) == 0) { | |
bf9e3b38 | 1252 | |
be60a902 HS |
1253 | info->protect[sector] = prot; |
1254 | ||
1255 | /* | |
1256 | * On some of Intel's flash chips (marked via legacy_unlock) | |
1257 | * unprotect unprotects all locking. | |
1258 | */ | |
1259 | if ((prot == 0) && (info->legacy_unlock)) { | |
1260 | flash_sect_t i; | |
1261 | ||
1262 | for (i = 0; i < info->sector_count; i++) { | |
1263 | if (info->protect[i]) | |
1264 | flash_real_protect (info, i, 1); | |
1265 | } | |
5653fc33 | 1266 | } |
5653fc33 | 1267 | } |
be60a902 | 1268 | return retcode; |
5653fc33 | 1269 | } |
bf9e3b38 | 1270 | |
5653fc33 | 1271 | /*----------------------------------------------------------------------- |
be60a902 | 1272 | * flash_read_user_serial - read the OneTimeProgramming cells |
5653fc33 | 1273 | */ |
be60a902 HS |
1274 | void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, |
1275 | int len) | |
5653fc33 | 1276 | { |
be60a902 HS |
1277 | uchar *src; |
1278 | uchar *dst; | |
bf9e3b38 | 1279 | |
be60a902 | 1280 | dst = buffer; |
12d30aa7 | 1281 | src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION); |
be60a902 HS |
1282 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); |
1283 | memcpy (dst, src + offset, len); | |
1284 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
12d30aa7 | 1285 | flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); |
5653fc33 WD |
1286 | } |
1287 | ||
be60a902 HS |
1288 | /* |
1289 | * flash_read_factory_serial - read the device Id from the protection area | |
5653fc33 | 1290 | */ |
be60a902 HS |
1291 | void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, |
1292 | int len) | |
5653fc33 | 1293 | { |
be60a902 | 1294 | uchar *src; |
bf9e3b38 | 1295 | |
12d30aa7 | 1296 | src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION); |
be60a902 HS |
1297 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); |
1298 | memcpy (buffer, src + offset, len); | |
1299 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
12d30aa7 | 1300 | flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); |
5653fc33 WD |
1301 | } |
1302 | ||
be60a902 HS |
1303 | #endif /* CFG_FLASH_PROTECTION */ |
1304 | ||
0ddf06dd HS |
1305 | /*----------------------------------------------------------------------- |
1306 | * Reverse the order of the erase regions in the CFI QRY structure. | |
1307 | * This is needed for chips that are either a) correctly detected as | |
1308 | * top-boot, or b) buggy. | |
1309 | */ | |
1310 | static void cfi_reverse_geometry(struct cfi_qry *qry) | |
1311 | { | |
1312 | unsigned int i, j; | |
1313 | u32 tmp; | |
1314 | ||
1315 | for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { | |
1316 | tmp = qry->erase_region_info[i]; | |
1317 | qry->erase_region_info[i] = qry->erase_region_info[j]; | |
1318 | qry->erase_region_info[j] = tmp; | |
1319 | } | |
1320 | } | |
be60a902 | 1321 | |
260421a2 SR |
1322 | /*----------------------------------------------------------------------- |
1323 | * read jedec ids from device and set corresponding fields in info struct | |
1324 | * | |
1325 | * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct | |
1326 | * | |
0ddf06dd HS |
1327 | */ |
1328 | static void cmdset_intel_read_jedec_ids(flash_info_t *info) | |
1329 | { | |
1330 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1331 | flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); | |
1332 | udelay(1000); /* some flash are slow to respond */ | |
1333 | info->manufacturer_id = flash_read_uchar (info, | |
1334 | FLASH_OFFSET_MANUFACTURER_ID); | |
1335 | info->device_id = flash_read_uchar (info, | |
1336 | FLASH_OFFSET_DEVICE_ID); | |
1337 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1338 | } | |
1339 | ||
1340 | static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) | |
1341 | { | |
1342 | info->cmd_reset = FLASH_CMD_RESET; | |
1343 | ||
1344 | cmdset_intel_read_jedec_ids(info); | |
1345 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1346 | ||
1347 | #ifdef CFG_FLASH_PROTECTION | |
1348 | /* read legacy lock/unlock bit from intel flash */ | |
1349 | if (info->ext_addr) { | |
1350 | info->legacy_unlock = flash_read_uchar (info, | |
1351 | info->ext_addr + 5) & 0x08; | |
1352 | } | |
1353 | #endif | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static void cmdset_amd_read_jedec_ids(flash_info_t *info) | |
1359 | { | |
1360 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
1361 | flash_unlock_seq(info, 0); | |
1362 | flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); | |
1363 | udelay(1000); /* some flash are slow to respond */ | |
1364 | info->manufacturer_id = flash_read_uchar (info, | |
1365 | FLASH_OFFSET_MANUFACTURER_ID); | |
1366 | info->device_id = flash_read_uchar (info, | |
1367 | FLASH_OFFSET_DEVICE_ID); | |
1368 | if (info->device_id == 0x7E) { | |
1369 | /* AMD 3-byte (expanded) device ids */ | |
1370 | info->device_id2 = flash_read_uchar (info, | |
1371 | FLASH_OFFSET_DEVICE_ID2); | |
1372 | info->device_id2 <<= 8; | |
1373 | info->device_id2 |= flash_read_uchar (info, | |
1374 | FLASH_OFFSET_DEVICE_ID3); | |
1375 | } | |
1376 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
1377 | } | |
1378 | ||
1379 | static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) | |
1380 | { | |
1381 | info->cmd_reset = AMD_CMD_RESET; | |
1382 | ||
1383 | cmdset_amd_read_jedec_ids(info); | |
1384 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1385 | ||
0ddf06dd HS |
1386 | return 0; |
1387 | } | |
1388 | ||
1389 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
260421a2 SR |
1390 | static void flash_read_jedec_ids (flash_info_t * info) |
1391 | { | |
1392 | info->manufacturer_id = 0; | |
1393 | info->device_id = 0; | |
1394 | info->device_id2 = 0; | |
1395 | ||
1396 | switch (info->vendor) { | |
1397 | case CFI_CMDSET_INTEL_STANDARD: | |
1398 | case CFI_CMDSET_INTEL_EXTENDED: | |
0ddf06dd | 1399 | flash_read_jedec_ids_intel(info); |
260421a2 SR |
1400 | break; |
1401 | case CFI_CMDSET_AMD_STANDARD: | |
1402 | case CFI_CMDSET_AMD_EXTENDED: | |
0ddf06dd | 1403 | flash_read_jedec_ids_amd(info); |
260421a2 SR |
1404 | break; |
1405 | default: | |
1406 | break; | |
1407 | } | |
1408 | } | |
1409 | ||
5653fc33 | 1410 | /*----------------------------------------------------------------------- |
be60a902 HS |
1411 | * Call board code to request info about non-CFI flash. |
1412 | * board_flash_get_legacy needs to fill in at least: | |
1413 | * info->portwidth, info->chipwidth and info->interface for Jedec probing. | |
7e5b9b47 | 1414 | */ |
be60a902 | 1415 | static int flash_detect_legacy(ulong base, int banknum) |
5653fc33 | 1416 | { |
be60a902 | 1417 | flash_info_t *info = &flash_info[banknum]; |
7e5b9b47 | 1418 | |
be60a902 HS |
1419 | if (board_flash_get_legacy(base, banknum, info)) { |
1420 | /* board code may have filled info completely. If not, we | |
1421 | use JEDEC ID probing. */ | |
1422 | if (!info->vendor) { | |
1423 | int modes[] = { | |
1424 | CFI_CMDSET_AMD_STANDARD, | |
1425 | CFI_CMDSET_INTEL_STANDARD | |
1426 | }; | |
1427 | int i; | |
7e5b9b47 | 1428 | |
be60a902 HS |
1429 | for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) { |
1430 | info->vendor = modes[i]; | |
1431 | info->start[0] = base; | |
1432 | if (info->portwidth == FLASH_CFI_8BIT | |
1433 | && info->interface == FLASH_CFI_X8X16) { | |
1434 | info->addr_unlock1 = 0x2AAA; | |
1435 | info->addr_unlock2 = 0x5555; | |
1436 | } else { | |
1437 | info->addr_unlock1 = 0x5555; | |
1438 | info->addr_unlock2 = 0x2AAA; | |
1439 | } | |
1440 | flash_read_jedec_ids(info); | |
1441 | debug("JEDEC PROBE: ID %x %x %x\n", | |
1442 | info->manufacturer_id, | |
1443 | info->device_id, | |
1444 | info->device_id2); | |
1445 | if (jedec_flash_match(info, base)) | |
1446 | break; | |
1447 | } | |
1448 | } | |
1449 | ||
1450 | switch(info->vendor) { | |
1451 | case CFI_CMDSET_INTEL_STANDARD: | |
1452 | case CFI_CMDSET_INTEL_EXTENDED: | |
1453 | info->cmd_reset = FLASH_CMD_RESET; | |
1454 | break; | |
1455 | case CFI_CMDSET_AMD_STANDARD: | |
1456 | case CFI_CMDSET_AMD_EXTENDED: | |
1457 | case CFI_CMDSET_AMD_LEGACY: | |
1458 | info->cmd_reset = AMD_CMD_RESET; | |
1459 | break; | |
1460 | } | |
1461 | info->flash_id = FLASH_MAN_CFI; | |
1462 | return 1; | |
1463 | } | |
1464 | return 0; /* use CFI */ | |
1465 | } | |
1466 | #else | |
1467 | static inline int flash_detect_legacy(ulong base, int banknum) | |
1468 | { | |
1469 | return 0; /* use CFI */ | |
1470 | } | |
1471 | #endif | |
1472 | ||
1473 | /*----------------------------------------------------------------------- | |
1474 | * detect if flash is compatible with the Common Flash Interface (CFI) | |
1475 | * http://www.jedec.org/download/search/jesd68.pdf | |
1476 | */ | |
e23741f4 HS |
1477 | static void flash_read_cfi (flash_info_t *info, void *buf, |
1478 | unsigned int start, size_t len) | |
1479 | { | |
1480 | u8 *p = buf; | |
1481 | unsigned int i; | |
1482 | ||
1483 | for (i = 0; i < len; i++) | |
1484 | p[i] = flash_read_uchar(info, start + i); | |
1485 | } | |
1486 | ||
1487 | static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) | |
be60a902 HS |
1488 | { |
1489 | int cfi_offset; | |
1490 | ||
1491 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
1492 | for (cfi_offset=0; | |
1493 | cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); | |
1494 | cfi_offset++) { | |
1495 | flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], | |
1496 | FLASH_CMD_CFI); | |
1497 | if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') | |
1498 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') | |
1499 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { | |
e23741f4 HS |
1500 | flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, |
1501 | sizeof(struct cfi_qry)); | |
1502 | info->interface = le16_to_cpu(qry->interface_desc); | |
1503 | ||
be60a902 HS |
1504 | info->cfi_offset = flash_offset_cfi[cfi_offset]; |
1505 | debug ("device interface is %d\n", | |
1506 | info->interface); | |
1507 | debug ("found port %d chip %d ", | |
1508 | info->portwidth, info->chipwidth); | |
1509 | debug ("port %d bits chip %d bits\n", | |
1510 | info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1511 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1512 | ||
1513 | /* calculate command offsets as in the Linux driver */ | |
1514 | info->addr_unlock1 = 0x555; | |
7e5b9b47 HS |
1515 | info->addr_unlock2 = 0x2aa; |
1516 | ||
1517 | /* | |
1518 | * modify the unlock address if we are | |
1519 | * in compatibility mode | |
1520 | */ | |
1521 | if ( /* x8/x16 in x8 mode */ | |
1522 | ((info->chipwidth == FLASH_CFI_BY8) && | |
1523 | (info->interface == FLASH_CFI_X8X16)) || | |
1524 | /* x16/x32 in x16 mode */ | |
1525 | ((info->chipwidth == FLASH_CFI_BY16) && | |
1526 | (info->interface == FLASH_CFI_X16X32))) | |
1527 | { | |
1528 | info->addr_unlock1 = 0xaaa; | |
1529 | info->addr_unlock2 = 0x555; | |
1530 | } | |
1531 | ||
1532 | info->name = "CFI conformant"; | |
1533 | return 1; | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | return 0; | |
1538 | } | |
1539 | ||
e23741f4 | 1540 | static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) |
7e5b9b47 | 1541 | { |
bf9e3b38 WD |
1542 | debug ("flash detect cfi\n"); |
1543 | ||
79b4cda0 | 1544 | for (info->portwidth = CFG_FLASH_CFI_WIDTH; |
bf9e3b38 WD |
1545 | info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { |
1546 | for (info->chipwidth = FLASH_CFI_BY8; | |
1547 | info->chipwidth <= info->portwidth; | |
7e5b9b47 | 1548 | info->chipwidth <<= 1) |
e23741f4 | 1549 | if (__flash_detect_cfi(info, qry)) |
7e5b9b47 | 1550 | return 1; |
5653fc33 | 1551 | } |
bf9e3b38 | 1552 | debug ("not found\n"); |
5653fc33 WD |
1553 | return 0; |
1554 | } | |
bf9e3b38 | 1555 | |
467bcee1 HS |
1556 | /* |
1557 | * Manufacturer-specific quirks. Add workarounds for geometry | |
1558 | * reversal, etc. here. | |
1559 | */ | |
1560 | static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) | |
1561 | { | |
1562 | /* check if flash geometry needs reversal */ | |
1563 | if (qry->num_erase_regions > 1) { | |
1564 | /* reverse geometry if top boot part */ | |
1565 | if (info->cfi_version < 0x3131) { | |
1566 | /* CFI < 1.1, try to guess from device id */ | |
1567 | if ((info->device_id & 0x80) != 0) | |
1568 | cfi_reverse_geometry(qry); | |
1569 | } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { | |
1570 | /* CFI >= 1.1, deduct from top/bottom flag */ | |
1571 | /* note: ext_addr is valid since cfi_version > 0 */ | |
1572 | cfi_reverse_geometry(qry); | |
1573 | } | |
1574 | } | |
1575 | } | |
1576 | ||
1577 | static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) | |
1578 | { | |
1579 | int reverse_geometry = 0; | |
1580 | ||
1581 | /* Check the "top boot" bit in the PRI */ | |
1582 | if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) | |
1583 | reverse_geometry = 1; | |
1584 | ||
1585 | /* AT49BV6416(T) list the erase regions in the wrong order. | |
1586 | * However, the device ID is identical with the non-broken | |
1587 | * AT49BV642D since u-boot only reads the low byte (they | |
1588 | * differ in the high byte.) So leave out this fixup for now. | |
1589 | */ | |
1590 | #if 0 | |
1591 | if (info->device_id == 0xd6 || info->device_id == 0xd2) | |
1592 | reverse_geometry = !reverse_geometry; | |
1593 | #endif | |
1594 | ||
1595 | if (reverse_geometry) | |
1596 | cfi_reverse_geometry(qry); | |
1597 | } | |
1598 | ||
5653fc33 WD |
1599 | /* |
1600 | * The following code cannot be run from FLASH! | |
1601 | * | |
1602 | */ | |
e6f2e902 | 1603 | ulong flash_get_size (ulong base, int banknum) |
5653fc33 | 1604 | { |
bf9e3b38 | 1605 | flash_info_t *info = &flash_info[banknum]; |
5653fc33 WD |
1606 | int i, j; |
1607 | flash_sect_t sect_cnt; | |
1608 | unsigned long sector; | |
1609 | unsigned long tmp; | |
1610 | int size_ratio; | |
1611 | uchar num_erase_regions; | |
bf9e3b38 WD |
1612 | int erase_region_size; |
1613 | int erase_region_count; | |
e23741f4 | 1614 | struct cfi_qry qry; |
260421a2 SR |
1615 | |
1616 | info->ext_addr = 0; | |
1617 | info->cfi_version = 0; | |
2662b40c | 1618 | #ifdef CFG_FLASH_PROTECTION |
2662b40c SR |
1619 | info->legacy_unlock = 0; |
1620 | #endif | |
5653fc33 WD |
1621 | |
1622 | info->start[0] = base; | |
1623 | ||
e23741f4 HS |
1624 | if (flash_detect_cfi (info, &qry)) { |
1625 | info->vendor = le16_to_cpu(qry.p_id); | |
1626 | info->ext_addr = le16_to_cpu(qry.p_adr); | |
1627 | num_erase_regions = qry.num_erase_regions; | |
1628 | ||
260421a2 SR |
1629 | if (info->ext_addr) { |
1630 | info->cfi_version = (ushort) flash_read_uchar (info, | |
1631 | info->ext_addr + 3) << 8; | |
1632 | info->cfi_version |= (ushort) flash_read_uchar (info, | |
1633 | info->ext_addr + 4); | |
1634 | } | |
0ddf06dd | 1635 | |
bf9e3b38 | 1636 | #ifdef DEBUG |
e23741f4 | 1637 | flash_printqry (&qry); |
bf9e3b38 | 1638 | #endif |
0ddf06dd | 1639 | |
bf9e3b38 | 1640 | switch (info->vendor) { |
5653fc33 WD |
1641 | case CFI_CMDSET_INTEL_STANDARD: |
1642 | case CFI_CMDSET_INTEL_EXTENDED: | |
0ddf06dd | 1643 | cmdset_intel_init(info, &qry); |
5653fc33 WD |
1644 | break; |
1645 | case CFI_CMDSET_AMD_STANDARD: | |
1646 | case CFI_CMDSET_AMD_EXTENDED: | |
0ddf06dd | 1647 | cmdset_amd_init(info, &qry); |
5653fc33 | 1648 | break; |
0ddf06dd HS |
1649 | default: |
1650 | printf("CFI: Unknown command set 0x%x\n", | |
1651 | info->vendor); | |
1652 | /* | |
1653 | * Unfortunately, this means we don't know how | |
1654 | * to get the chip back to Read mode. Might | |
1655 | * as well try an Intel-style reset... | |
1656 | */ | |
1657 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1658 | return 0; | |
5653fc33 | 1659 | } |
cd37d9e6 | 1660 | |
467bcee1 HS |
1661 | /* Do manufacturer-specific fixups */ |
1662 | switch (info->manufacturer_id) { | |
1663 | case 0x0001: | |
1664 | flash_fixup_amd(info, &qry); | |
1665 | break; | |
1666 | case 0x001f: | |
1667 | flash_fixup_atmel(info, &qry); | |
1668 | break; | |
1669 | } | |
1670 | ||
bf9e3b38 | 1671 | debug ("manufacturer is %d\n", info->vendor); |
260421a2 SR |
1672 | debug ("manufacturer id is 0x%x\n", info->manufacturer_id); |
1673 | debug ("device id is 0x%x\n", info->device_id); | |
1674 | debug ("device id2 is 0x%x\n", info->device_id2); | |
1675 | debug ("cfi version is 0x%04x\n", info->cfi_version); | |
1676 | ||
5653fc33 | 1677 | size_ratio = info->portwidth / info->chipwidth; |
bf9e3b38 WD |
1678 | /* if the chip is x8/x16 reduce the ratio by half */ |
1679 | if ((info->interface == FLASH_CFI_X8X16) | |
1680 | && (info->chipwidth == FLASH_CFI_BY8)) { | |
1681 | size_ratio >>= 1; | |
1682 | } | |
bf9e3b38 WD |
1683 | debug ("size_ratio %d port %d bits chip %d bits\n", |
1684 | size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1685 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1686 | debug ("found %d erase regions\n", num_erase_regions); | |
5653fc33 WD |
1687 | sect_cnt = 0; |
1688 | sector = base; | |
bf9e3b38 WD |
1689 | for (i = 0; i < num_erase_regions; i++) { |
1690 | if (i > NUM_ERASE_REGIONS) { | |
028ab6b5 WD |
1691 | printf ("%d erase regions found, only %d used\n", |
1692 | num_erase_regions, NUM_ERASE_REGIONS); | |
5653fc33 WD |
1693 | break; |
1694 | } | |
e23741f4 | 1695 | |
0ddf06dd HS |
1696 | tmp = le32_to_cpu(qry.erase_region_info[i]); |
1697 | debug("erase region %u: 0x%08lx\n", i, tmp); | |
e23741f4 HS |
1698 | |
1699 | erase_region_count = (tmp & 0xffff) + 1; | |
1700 | tmp >>= 16; | |
bf9e3b38 WD |
1701 | erase_region_size = |
1702 | (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; | |
4c0d4c3b | 1703 | debug ("erase_region_count = %d erase_region_size = %d\n", |
028ab6b5 | 1704 | erase_region_count, erase_region_size); |
bf9e3b38 | 1705 | for (j = 0; j < erase_region_count; j++) { |
81b20ccc MS |
1706 | if (sect_cnt >= CFG_MAX_FLASH_SECT) { |
1707 | printf("ERROR: too many flash sectors\n"); | |
1708 | break; | |
1709 | } | |
5653fc33 WD |
1710 | info->start[sect_cnt] = sector; |
1711 | sector += (erase_region_size * size_ratio); | |
a1191902 WD |
1712 | |
1713 | /* | |
7e5b9b47 HS |
1714 | * Only read protection status from |
1715 | * supported devices (intel...) | |
a1191902 WD |
1716 | */ |
1717 | switch (info->vendor) { | |
1718 | case CFI_CMDSET_INTEL_EXTENDED: | |
1719 | case CFI_CMDSET_INTEL_STANDARD: | |
1720 | info->protect[sect_cnt] = | |
1721 | flash_isset (info, sect_cnt, | |
1722 | FLASH_OFFSET_PROTECT, | |
1723 | FLASH_STATUS_PROTECT); | |
1724 | break; | |
1725 | default: | |
7e5b9b47 HS |
1726 | /* default: not protected */ |
1727 | info->protect[sect_cnt] = 0; | |
a1191902 WD |
1728 | } |
1729 | ||
5653fc33 WD |
1730 | sect_cnt++; |
1731 | } | |
1732 | } | |
1733 | ||
1734 | info->sector_count = sect_cnt; | |
e23741f4 | 1735 | info->size = 1 << qry.dev_size; |
5653fc33 | 1736 | /* multiply the size by the number of chips */ |
7e5b9b47 | 1737 | info->size *= size_ratio; |
e23741f4 HS |
1738 | info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); |
1739 | tmp = 1 << qry.block_erase_timeout_typ; | |
7e5b9b47 | 1740 | info->erase_blk_tout = tmp * |
e23741f4 HS |
1741 | (1 << qry.block_erase_timeout_max); |
1742 | tmp = (1 << qry.buf_write_timeout_typ) * | |
1743 | (1 << qry.buf_write_timeout_max); | |
1744 | ||
7e5b9b47 | 1745 | /* round up when converting to ms */ |
e23741f4 HS |
1746 | info->buffer_write_tout = (tmp + 999) / 1000; |
1747 | tmp = (1 << qry.word_write_timeout_typ) * | |
1748 | (1 << qry.word_write_timeout_max); | |
7e5b9b47 | 1749 | /* round up when converting to ms */ |
e23741f4 | 1750 | info->write_tout = (tmp + 999) / 1000; |
5653fc33 | 1751 | info->flash_id = FLASH_MAN_CFI; |
7e5b9b47 HS |
1752 | if ((info->interface == FLASH_CFI_X8X16) && |
1753 | (info->chipwidth == FLASH_CFI_BY8)) { | |
1754 | /* XXX - Need to test on x8/x16 in parallel. */ | |
1755 | info->portwidth >>= 1; | |
855a496f | 1756 | } |
5653fc33 WD |
1757 | } |
1758 | ||
db421e64 | 1759 | flash_write_cmd (info, 0, 0, info->cmd_reset); |
bf9e3b38 | 1760 | return (info->size); |
5653fc33 WD |
1761 | } |
1762 | ||
5653fc33 WD |
1763 | /*----------------------------------------------------------------------- |
1764 | */ | |
be60a902 | 1765 | unsigned long flash_init (void) |
5653fc33 | 1766 | { |
be60a902 HS |
1767 | unsigned long size = 0; |
1768 | int i; | |
5653fc33 | 1769 | |
be60a902 HS |
1770 | #ifdef CFG_FLASH_PROTECTION |
1771 | char *s = getenv("unlock"); | |
81b20ccc | 1772 | #endif |
5653fc33 | 1773 | |
be60a902 HS |
1774 | /* Init: no FLASHes known */ |
1775 | for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { | |
1776 | flash_info[i].flash_id = FLASH_UNKNOWN; | |
5653fc33 | 1777 | |
be60a902 HS |
1778 | if (!flash_detect_legacy (bank_base[i], i)) |
1779 | flash_get_size (bank_base[i], i); | |
1780 | size += flash_info[i].size; | |
1781 | if (flash_info[i].flash_id == FLASH_UNKNOWN) { | |
1782 | #ifndef CFG_FLASH_QUIET_TEST | |
1783 | printf ("## Unknown FLASH on Bank %d " | |
1784 | "- Size = 0x%08lx = %ld MB\n", | |
1785 | i+1, flash_info[i].size, | |
1786 | flash_info[i].size << 20); | |
1787 | #endif /* CFG_FLASH_QUIET_TEST */ | |
1788 | } | |
1789 | #ifdef CFG_FLASH_PROTECTION | |
1790 | else if ((s != NULL) && (strcmp(s, "yes") == 0)) { | |
1791 | /* | |
1792 | * Only the U-Boot image and it's environment | |
1793 | * is protected, all other sectors are | |
1794 | * unprotected (unlocked) if flash hardware | |
1795 | * protection is used (CFG_FLASH_PROTECTION) | |
1796 | * and the environment variable "unlock" is | |
1797 | * set to "yes". | |
1798 | */ | |
1799 | if (flash_info[i].legacy_unlock) { | |
1800 | int k; | |
5653fc33 | 1801 | |
be60a902 HS |
1802 | /* |
1803 | * Disable legacy_unlock temporarily, | |
1804 | * since flash_real_protect would | |
1805 | * relock all other sectors again | |
1806 | * otherwise. | |
1807 | */ | |
1808 | flash_info[i].legacy_unlock = 0; | |
5653fc33 | 1809 | |
be60a902 HS |
1810 | /* |
1811 | * Legacy unlocking (e.g. Intel J3) -> | |
1812 | * unlock only one sector. This will | |
1813 | * unlock all sectors. | |
1814 | */ | |
1815 | flash_real_protect (&flash_info[i], 0, 0); | |
5653fc33 | 1816 | |
be60a902 | 1817 | flash_info[i].legacy_unlock = 1; |
5653fc33 | 1818 | |
be60a902 HS |
1819 | /* |
1820 | * Manually mark other sectors as | |
1821 | * unlocked (unprotected) | |
1822 | */ | |
1823 | for (k = 1; k < flash_info[i].sector_count; k++) | |
1824 | flash_info[i].protect[k] = 0; | |
1825 | } else { | |
1826 | /* | |
1827 | * No legancy unlocking -> unlock all sectors | |
1828 | */ | |
1829 | flash_protect (FLAG_PROTECT_CLEAR, | |
1830 | flash_info[i].start[0], | |
1831 | flash_info[i].start[0] | |
1832 | + flash_info[i].size - 1, | |
1833 | &flash_info[i]); | |
79b4cda0 | 1834 | } |
79b4cda0 | 1835 | } |
be60a902 HS |
1836 | #endif /* CFG_FLASH_PROTECTION */ |
1837 | } | |
79b4cda0 | 1838 | |
be60a902 HS |
1839 | /* Monitor protection ON by default */ |
1840 | #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) | |
1841 | flash_protect (FLAG_PROTECT_SET, | |
1842 | CFG_MONITOR_BASE, | |
1843 | CFG_MONITOR_BASE + monitor_flash_len - 1, | |
1844 | flash_get_info(CFG_MONITOR_BASE)); | |
1845 | #endif | |
79b4cda0 | 1846 | |
be60a902 HS |
1847 | /* Environment protection ON by default */ |
1848 | #ifdef CFG_ENV_IS_IN_FLASH | |
1849 | flash_protect (FLAG_PROTECT_SET, | |
1850 | CFG_ENV_ADDR, | |
1851 | CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, | |
1852 | flash_get_info(CFG_ENV_ADDR)); | |
1853 | #endif | |
79b4cda0 | 1854 | |
be60a902 HS |
1855 | /* Redundant environment protection ON by default */ |
1856 | #ifdef CFG_ENV_ADDR_REDUND | |
1857 | flash_protect (FLAG_PROTECT_SET, | |
1858 | CFG_ENV_ADDR_REDUND, | |
1859 | CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, | |
1860 | flash_get_info(CFG_ENV_ADDR_REDUND)); | |
1861 | #endif | |
1862 | return (size); | |
5653fc33 | 1863 | } |
ca43ba18 | 1864 | |
5653fc33 | 1865 | #endif /* CFG_FLASH_CFI */ |