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5653fc33 | 1 | /* |
bf9e3b38 | 2 | * (C) Copyright 2002-2004 |
5653fc33 WD |
3 | * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
4 | * | |
5 | * Copyright (C) 2003 Arabella Software Ltd. | |
6 | * Yuli Barcohen <yuli@arabellasw.com> | |
5653fc33 | 7 | * |
bf9e3b38 WD |
8 | * Copyright (C) 2004 |
9 | * Ed Okerson | |
260421a2 SR |
10 | * |
11 | * Copyright (C) 2006 | |
12 | * Tolunay Orkun <listmember@orkun.us> | |
bf9e3b38 | 13 | * |
5653fc33 WD |
14 | * See file CREDITS for list of people who contributed to this |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 | * MA 02111-1307 USA | |
31 | * | |
5653fc33 WD |
32 | */ |
33 | ||
34 | /* The DEBUG define must be before common to enable debugging */ | |
2d1a537d WD |
35 | /* #define DEBUG */ |
36 | ||
5653fc33 WD |
37 | #include <common.h> |
38 | #include <asm/processor.h> | |
3a197b2f | 39 | #include <asm/io.h> |
4c0d4c3b | 40 | #include <asm/byteorder.h> |
2a8af187 | 41 | #include <environment.h> |
fa36ae79 | 42 | #include <mtd/cfi_flash.h> |
a9f5faba | 43 | #include <watchdog.h> |
028ab6b5 | 44 | |
5653fc33 | 45 | /* |
7e5b9b47 HS |
46 | * This file implements a Common Flash Interface (CFI) driver for |
47 | * U-Boot. | |
48 | * | |
49 | * The width of the port and the width of the chips are determined at | |
50 | * initialization. These widths are used to calculate the address for | |
51 | * access CFI data structures. | |
5653fc33 WD |
52 | * |
53 | * References | |
54 | * JEDEC Standard JESD68 - Common Flash Interface (CFI) | |
55 | * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes | |
56 | * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets | |
57 | * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet | |
260421a2 SR |
58 | * AMD CFI Specification, Release 2.0 December 1, 2001 |
59 | * AMD/Spansion Application Note: Migration from Single-byte to Three-byte | |
60 | * Device IDs, Publication Number 25538 Revision A, November 8, 2001 | |
5653fc33 | 61 | * |
6d0f6bcf | 62 | * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between |
d0b6e140 | 63 | * reading and writing ... (yes there is such a Hardware). |
5653fc33 WD |
64 | */ |
65 | ||
7e5b9b47 | 66 | static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; |
4ffeab2c | 67 | #ifdef CONFIG_FLASH_CFI_MTD |
6ea808ef | 68 | static uint flash_verbose = 1; |
4ffeab2c MF |
69 | #else |
70 | #define flash_verbose 1 | |
71 | #endif | |
92eb729b | 72 | |
2a112b23 WD |
73 | flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ |
74 | ||
79b4cda0 SR |
75 | /* |
76 | * Check if chip width is defined. If not, start detecting with 8bit. | |
77 | */ | |
6d0f6bcf JCPV |
78 | #ifndef CONFIG_SYS_FLASH_CFI_WIDTH |
79 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
79b4cda0 SR |
80 | #endif |
81 | ||
6f726f95 SR |
82 | /* |
83 | * 0xffff is an undefined value for the configuration register. When | |
84 | * this value is returned, the configuration register shall not be | |
85 | * written at all (default mode). | |
86 | */ | |
87 | static u16 cfi_flash_config_reg(int i) | |
88 | { | |
89 | #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS | |
90 | return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; | |
91 | #else | |
92 | return 0xffff; | |
93 | #endif | |
94 | } | |
95 | ||
ca5def3f SR |
96 | #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) |
97 | int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; | |
98 | #endif | |
99 | ||
b00e19cc SR |
100 | static phys_addr_t __cfi_flash_bank_addr(int i) |
101 | { | |
102 | return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; | |
103 | } | |
104 | phys_addr_t cfi_flash_bank_addr(int i) | |
105 | __attribute__((weak, alias("__cfi_flash_bank_addr"))); | |
106 | ||
ec50a8e3 IY |
107 | static unsigned long __cfi_flash_bank_size(int i) |
108 | { | |
109 | #ifdef CONFIG_SYS_FLASH_BANKS_SIZES | |
110 | return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; | |
111 | #else | |
112 | return 0; | |
113 | #endif | |
114 | } | |
115 | unsigned long cfi_flash_bank_size(int i) | |
116 | __attribute__((weak, alias("__cfi_flash_bank_size"))); | |
117 | ||
45aa5a7f | 118 | static void __flash_write8(u8 value, void *addr) |
cdbaefb5 HS |
119 | { |
120 | __raw_writeb(value, addr); | |
121 | } | |
122 | ||
45aa5a7f | 123 | static void __flash_write16(u16 value, void *addr) |
cdbaefb5 HS |
124 | { |
125 | __raw_writew(value, addr); | |
126 | } | |
127 | ||
45aa5a7f | 128 | static void __flash_write32(u32 value, void *addr) |
cdbaefb5 HS |
129 | { |
130 | __raw_writel(value, addr); | |
131 | } | |
132 | ||
45aa5a7f | 133 | static void __flash_write64(u64 value, void *addr) |
cdbaefb5 HS |
134 | { |
135 | /* No architectures currently implement __raw_writeq() */ | |
136 | *(volatile u64 *)addr = value; | |
137 | } | |
138 | ||
45aa5a7f | 139 | static u8 __flash_read8(void *addr) |
cdbaefb5 HS |
140 | { |
141 | return __raw_readb(addr); | |
142 | } | |
143 | ||
45aa5a7f | 144 | static u16 __flash_read16(void *addr) |
cdbaefb5 HS |
145 | { |
146 | return __raw_readw(addr); | |
147 | } | |
148 | ||
45aa5a7f | 149 | static u32 __flash_read32(void *addr) |
cdbaefb5 HS |
150 | { |
151 | return __raw_readl(addr); | |
152 | } | |
153 | ||
97bf85d7 | 154 | static u64 __flash_read64(void *addr) |
cdbaefb5 HS |
155 | { |
156 | /* No architectures currently implement __raw_readq() */ | |
157 | return *(volatile u64 *)addr; | |
158 | } | |
159 | ||
45aa5a7f SR |
160 | #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
161 | void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8"))); | |
162 | void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16"))); | |
163 | void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32"))); | |
164 | void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64"))); | |
165 | u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8"))); | |
166 | u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16"))); | |
167 | u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32"))); | |
97bf85d7 | 168 | u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); |
45aa5a7f SR |
169 | #else |
170 | #define flash_write8 __flash_write8 | |
171 | #define flash_write16 __flash_write16 | |
172 | #define flash_write32 __flash_write32 | |
173 | #define flash_write64 __flash_write64 | |
174 | #define flash_read8 __flash_read8 | |
175 | #define flash_read16 __flash_read16 | |
176 | #define flash_read32 __flash_read32 | |
177 | #define flash_read64 __flash_read64 | |
178 | #endif | |
97bf85d7 | 179 | |
5653fc33 | 180 | /*----------------------------------------------------------------------- |
5653fc33 | 181 | */ |
6d0f6bcf | 182 | #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) |
4f975678 | 183 | flash_info_t *flash_get_info(ulong base) |
be60a902 HS |
184 | { |
185 | int i; | |
cba34aaf | 186 | flash_info_t *info = NULL; |
5653fc33 | 187 | |
6d0f6bcf | 188 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { |
be60a902 HS |
189 | info = & flash_info[i]; |
190 | if (info->size && info->start[0] <= base && | |
191 | base <= info->start[0] + info->size - 1) | |
192 | break; | |
193 | } | |
5653fc33 | 194 | |
cba34aaf | 195 | return info; |
be60a902 | 196 | } |
5653fc33 WD |
197 | #endif |
198 | ||
12d30aa7 HS |
199 | unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) |
200 | { | |
201 | if (sect != (info->sector_count - 1)) | |
202 | return info->start[sect + 1] - info->start[sect]; | |
203 | else | |
204 | return info->start[0] + info->size - info->start[sect]; | |
205 | } | |
206 | ||
bf9e3b38 WD |
207 | /*----------------------------------------------------------------------- |
208 | * create an address based on the offset and the port width | |
209 | */ | |
12d30aa7 HS |
210 | static inline void * |
211 | flash_map (flash_info_t * info, flash_sect_t sect, uint offset) | |
bf9e3b38 | 212 | { |
239cb9d9 | 213 | unsigned int byte_offset = offset * info->portwidth / info->chipwidth; |
214 | unsigned int addr = (info->start[sect] + byte_offset); | |
215 | unsigned int mask = 0xffffffff << (info->portwidth - 1); | |
12d30aa7 | 216 | |
81a4f709 | 217 | return (void *)(uintptr_t)(addr & mask); |
12d30aa7 HS |
218 | } |
219 | ||
220 | static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, | |
221 | unsigned int offset, void *addr) | |
222 | { | |
bf9e3b38 WD |
223 | } |
224 | ||
be60a902 HS |
225 | /*----------------------------------------------------------------------- |
226 | * make a proper sized command based on the port and chip widths | |
227 | */ | |
7288f972 | 228 | static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) |
be60a902 HS |
229 | { |
230 | int i; | |
93c56f21 VL |
231 | int cword_offset; |
232 | int cp_offset; | |
6d0f6bcf | 233 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
340ccb26 SS |
234 | u32 cmd_le = cpu_to_le32(cmd); |
235 | #endif | |
93c56f21 | 236 | uchar val; |
be60a902 HS |
237 | uchar *cp = (uchar *) cmdbuf; |
238 | ||
93c56f21 VL |
239 | for (i = info->portwidth; i > 0; i--){ |
240 | cword_offset = (info->portwidth-i)%info->chipwidth; | |
6d0f6bcf | 241 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
93c56f21 | 242 | cp_offset = info->portwidth - i; |
340ccb26 | 243 | val = *((uchar*)&cmd_le + cword_offset); |
be60a902 | 244 | #else |
93c56f21 | 245 | cp_offset = i - 1; |
7288f972 | 246 | val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1); |
be60a902 | 247 | #endif |
7288f972 | 248 | cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; |
93c56f21 | 249 | } |
be60a902 HS |
250 | } |
251 | ||
5653fc33 | 252 | #ifdef DEBUG |
bf9e3b38 WD |
253 | /*----------------------------------------------------------------------- |
254 | * Debug support | |
255 | */ | |
3055793b | 256 | static void print_longlong (char *str, unsigned long long data) |
5653fc33 WD |
257 | { |
258 | int i; | |
259 | char *cp; | |
bf9e3b38 | 260 | |
657f2062 | 261 | cp = (char *) &data; |
bf9e3b38 WD |
262 | for (i = 0; i < 8; i++) |
263 | sprintf (&str[i * 2], "%2.2x", *cp++); | |
264 | } | |
be60a902 | 265 | |
e23741f4 | 266 | static void flash_printqry (struct cfi_qry *qry) |
bf9e3b38 | 267 | { |
e23741f4 | 268 | u8 *p = (u8 *)qry; |
bf9e3b38 WD |
269 | int x, y; |
270 | ||
e23741f4 HS |
271 | for (x = 0; x < sizeof(struct cfi_qry); x += 16) { |
272 | debug("%02x : ", x); | |
273 | for (y = 0; y < 16; y++) | |
274 | debug("%2.2x ", p[x + y]); | |
275 | debug(" "); | |
bf9e3b38 | 276 | for (y = 0; y < 16; y++) { |
e23741f4 HS |
277 | unsigned char c = p[x + y]; |
278 | if (c >= 0x20 && c <= 0x7e) | |
279 | debug("%c", c); | |
280 | else | |
281 | debug("."); | |
bf9e3b38 | 282 | } |
e23741f4 | 283 | debug("\n"); |
bf9e3b38 | 284 | } |
5653fc33 WD |
285 | } |
286 | #endif | |
287 | ||
288 | ||
5653fc33 WD |
289 | /*----------------------------------------------------------------------- |
290 | * read a character at a port width address | |
291 | */ | |
3055793b | 292 | static inline uchar flash_read_uchar (flash_info_t * info, uint offset) |
5653fc33 WD |
293 | { |
294 | uchar *cp; | |
12d30aa7 | 295 | uchar retval; |
bf9e3b38 | 296 | |
12d30aa7 | 297 | cp = flash_map (info, 0, offset); |
6d0f6bcf | 298 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
12d30aa7 | 299 | retval = flash_read8(cp); |
bf9e3b38 | 300 | #else |
12d30aa7 | 301 | retval = flash_read8(cp + info->portwidth - 1); |
bf9e3b38 | 302 | #endif |
12d30aa7 HS |
303 | flash_unmap (info, 0, offset, cp); |
304 | return retval; | |
5653fc33 WD |
305 | } |
306 | ||
90447ecb TK |
307 | /*----------------------------------------------------------------------- |
308 | * read a word at a port width address, assume 16bit bus | |
309 | */ | |
310 | static inline ushort flash_read_word (flash_info_t * info, uint offset) | |
311 | { | |
312 | ushort *addr, retval; | |
313 | ||
314 | addr = flash_map (info, 0, offset); | |
315 | retval = flash_read16 (addr); | |
316 | flash_unmap (info, 0, offset, addr); | |
317 | return retval; | |
318 | } | |
319 | ||
320 | ||
5653fc33 | 321 | /*----------------------------------------------------------------------- |
260421a2 | 322 | * read a long word by picking the least significant byte of each maximum |
5653fc33 WD |
323 | * port size word. Swap for ppc format. |
324 | */ | |
3055793b HS |
325 | static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, |
326 | uint offset) | |
5653fc33 | 327 | { |
bf9e3b38 WD |
328 | uchar *addr; |
329 | ulong retval; | |
330 | ||
331 | #ifdef DEBUG | |
332 | int x; | |
333 | #endif | |
12d30aa7 | 334 | addr = flash_map (info, sect, offset); |
5653fc33 | 335 | |
bf9e3b38 WD |
336 | #ifdef DEBUG |
337 | debug ("long addr is at %p info->portwidth = %d\n", addr, | |
338 | info->portwidth); | |
339 | for (x = 0; x < 4 * info->portwidth; x++) { | |
12d30aa7 | 340 | debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); |
bf9e3b38 WD |
341 | } |
342 | #endif | |
6d0f6bcf | 343 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
12d30aa7 HS |
344 | retval = ((flash_read8(addr) << 16) | |
345 | (flash_read8(addr + info->portwidth) << 24) | | |
346 | (flash_read8(addr + 2 * info->portwidth)) | | |
347 | (flash_read8(addr + 3 * info->portwidth) << 8)); | |
bf9e3b38 | 348 | #else |
12d30aa7 HS |
349 | retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | |
350 | (flash_read8(addr + info->portwidth - 1) << 16) | | |
351 | (flash_read8(addr + 4 * info->portwidth - 1) << 8) | | |
352 | (flash_read8(addr + 3 * info->portwidth - 1))); | |
bf9e3b38 | 353 | #endif |
12d30aa7 HS |
354 | flash_unmap(info, sect, offset, addr); |
355 | ||
bf9e3b38 | 356 | return retval; |
5653fc33 WD |
357 | } |
358 | ||
be60a902 HS |
359 | /* |
360 | * Write a proper sized command to the correct address | |
81b20ccc | 361 | */ |
fa36ae79 SR |
362 | void flash_write_cmd (flash_info_t * info, flash_sect_t sect, |
363 | uint offset, u32 cmd) | |
81b20ccc | 364 | { |
7e5b9b47 | 365 | |
cdbaefb5 | 366 | void *addr; |
be60a902 | 367 | cfiword_t cword; |
81b20ccc | 368 | |
12d30aa7 | 369 | addr = flash_map (info, sect, offset); |
be60a902 HS |
370 | flash_make_cmd (info, cmd, &cword); |
371 | switch (info->portwidth) { | |
372 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 373 | debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, |
be60a902 | 374 | cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
cdbaefb5 | 375 | flash_write8(cword.c, addr); |
be60a902 HS |
376 | break; |
377 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 378 | debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, |
be60a902 HS |
379 | cmd, cword.w, |
380 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
cdbaefb5 | 381 | flash_write16(cword.w, addr); |
be60a902 HS |
382 | break; |
383 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 384 | debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, |
be60a902 HS |
385 | cmd, cword.l, |
386 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
cdbaefb5 | 387 | flash_write32(cword.l, addr); |
be60a902 HS |
388 | break; |
389 | case FLASH_CFI_64BIT: | |
390 | #ifdef DEBUG | |
391 | { | |
392 | char str[20]; | |
7e5b9b47 | 393 | |
be60a902 HS |
394 | print_longlong (str, cword.ll); |
395 | ||
396 | debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", | |
cdbaefb5 | 397 | addr, cmd, str, |
be60a902 | 398 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
81b20ccc | 399 | } |
be60a902 | 400 | #endif |
cdbaefb5 | 401 | flash_write64(cword.ll, addr); |
be60a902 | 402 | break; |
239cb9d9 | 403 | default: |
404 | printf("fwc: Unknown port width %d\n", info->portwidth); | |
81b20ccc | 405 | } |
be60a902 HS |
406 | |
407 | /* Ensure all the instructions are fully finished */ | |
408 | sync(); | |
12d30aa7 HS |
409 | |
410 | flash_unmap(info, sect, offset, addr); | |
81b20ccc | 411 | } |
be60a902 HS |
412 | |
413 | static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) | |
81b20ccc | 414 | { |
be60a902 HS |
415 | flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); |
416 | flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); | |
81b20ccc | 417 | } |
81b20ccc | 418 | |
5653fc33 WD |
419 | /*----------------------------------------------------------------------- |
420 | */ | |
be60a902 HS |
421 | static int flash_isequal (flash_info_t * info, flash_sect_t sect, |
422 | uint offset, uchar cmd) | |
5653fc33 | 423 | { |
cdbaefb5 | 424 | void *addr; |
be60a902 HS |
425 | cfiword_t cword; |
426 | int retval; | |
5653fc33 | 427 | |
12d30aa7 | 428 | addr = flash_map (info, sect, offset); |
be60a902 | 429 | flash_make_cmd (info, cmd, &cword); |
2662b40c | 430 | |
cdbaefb5 | 431 | debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); |
be60a902 HS |
432 | switch (info->portwidth) { |
433 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
434 | debug ("is= %x %x\n", flash_read8(addr), cword.c); |
435 | retval = (flash_read8(addr) == cword.c); | |
be60a902 HS |
436 | break; |
437 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
438 | debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); |
439 | retval = (flash_read16(addr) == cword.w); | |
be60a902 HS |
440 | break; |
441 | case FLASH_CFI_32BIT: | |
52514699 | 442 | debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l); |
cdbaefb5 | 443 | retval = (flash_read32(addr) == cword.l); |
be60a902 HS |
444 | break; |
445 | case FLASH_CFI_64BIT: | |
446 | #ifdef DEBUG | |
447 | { | |
448 | char str1[20]; | |
449 | char str2[20]; | |
81b20ccc | 450 | |
cdbaefb5 | 451 | print_longlong (str1, flash_read64(addr)); |
be60a902 HS |
452 | print_longlong (str2, cword.ll); |
453 | debug ("is= %s %s\n", str1, str2); | |
5653fc33 | 454 | } |
be60a902 | 455 | #endif |
cdbaefb5 | 456 | retval = (flash_read64(addr) == cword.ll); |
be60a902 HS |
457 | break; |
458 | default: | |
459 | retval = 0; | |
460 | break; | |
461 | } | |
12d30aa7 HS |
462 | flash_unmap(info, sect, offset, addr); |
463 | ||
be60a902 HS |
464 | return retval; |
465 | } | |
79b4cda0 | 466 | |
be60a902 HS |
467 | /*----------------------------------------------------------------------- |
468 | */ | |
469 | static int flash_isset (flash_info_t * info, flash_sect_t sect, | |
470 | uint offset, uchar cmd) | |
471 | { | |
cdbaefb5 | 472 | void *addr; |
be60a902 HS |
473 | cfiword_t cword; |
474 | int retval; | |
2662b40c | 475 | |
12d30aa7 | 476 | addr = flash_map (info, sect, offset); |
be60a902 HS |
477 | flash_make_cmd (info, cmd, &cword); |
478 | switch (info->portwidth) { | |
479 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 480 | retval = ((flash_read8(addr) & cword.c) == cword.c); |
be60a902 HS |
481 | break; |
482 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 483 | retval = ((flash_read16(addr) & cword.w) == cword.w); |
be60a902 HS |
484 | break; |
485 | case FLASH_CFI_32BIT: | |
47cc23cb | 486 | retval = ((flash_read32(addr) & cword.l) == cword.l); |
be60a902 HS |
487 | break; |
488 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 489 | retval = ((flash_read64(addr) & cword.ll) == cword.ll); |
be60a902 HS |
490 | break; |
491 | default: | |
492 | retval = 0; | |
493 | break; | |
494 | } | |
12d30aa7 HS |
495 | flash_unmap(info, sect, offset, addr); |
496 | ||
be60a902 HS |
497 | return retval; |
498 | } | |
2662b40c | 499 | |
be60a902 HS |
500 | /*----------------------------------------------------------------------- |
501 | */ | |
502 | static int flash_toggle (flash_info_t * info, flash_sect_t sect, | |
503 | uint offset, uchar cmd) | |
504 | { | |
cdbaefb5 | 505 | void *addr; |
be60a902 HS |
506 | cfiword_t cword; |
507 | int retval; | |
656658dd | 508 | |
12d30aa7 | 509 | addr = flash_map (info, sect, offset); |
be60a902 HS |
510 | flash_make_cmd (info, cmd, &cword); |
511 | switch (info->portwidth) { | |
512 | case FLASH_CFI_8BIT: | |
fb8c061e | 513 | retval = flash_read8(addr) != flash_read8(addr); |
be60a902 HS |
514 | break; |
515 | case FLASH_CFI_16BIT: | |
fb8c061e | 516 | retval = flash_read16(addr) != flash_read16(addr); |
be60a902 HS |
517 | break; |
518 | case FLASH_CFI_32BIT: | |
fb8c061e | 519 | retval = flash_read32(addr) != flash_read32(addr); |
be60a902 HS |
520 | break; |
521 | case FLASH_CFI_64BIT: | |
9abda6ba WD |
522 | retval = ( (flash_read32( addr ) != flash_read32( addr )) || |
523 | (flash_read32(addr+4) != flash_read32(addr+4)) ); | |
be60a902 HS |
524 | break; |
525 | default: | |
526 | retval = 0; | |
527 | break; | |
528 | } | |
12d30aa7 HS |
529 | flash_unmap(info, sect, offset, addr); |
530 | ||
be60a902 | 531 | return retval; |
5653fc33 WD |
532 | } |
533 | ||
be60a902 HS |
534 | /* |
535 | * flash_is_busy - check to see if the flash is busy | |
536 | * | |
537 | * This routine checks the status of the chip and returns true if the | |
538 | * chip is busy. | |
7680c140 | 539 | */ |
be60a902 | 540 | static int flash_is_busy (flash_info_t * info, flash_sect_t sect) |
7680c140 | 541 | { |
be60a902 | 542 | int retval; |
7680c140 | 543 | |
be60a902 | 544 | switch (info->vendor) { |
9c048b52 | 545 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
546 | case CFI_CMDSET_INTEL_STANDARD: |
547 | case CFI_CMDSET_INTEL_EXTENDED: | |
548 | retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); | |
549 | break; | |
550 | case CFI_CMDSET_AMD_STANDARD: | |
551 | case CFI_CMDSET_AMD_EXTENDED: | |
552 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
553 | case CFI_CMDSET_AMD_LEGACY: | |
554 | #endif | |
555 | retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); | |
556 | break; | |
557 | default: | |
558 | retval = 0; | |
7680c140 | 559 | } |
be60a902 HS |
560 | debug ("flash_is_busy: %d\n", retval); |
561 | return retval; | |
7680c140 WD |
562 | } |
563 | ||
5653fc33 | 564 | /*----------------------------------------------------------------------- |
be60a902 HS |
565 | * wait for XSR.7 to be set. Time out with an error if it does not. |
566 | * This routine does not set the flash to read-array mode. | |
5653fc33 | 567 | */ |
be60a902 HS |
568 | static int flash_status_check (flash_info_t * info, flash_sect_t sector, |
569 | ulong tout, char *prompt) | |
5653fc33 | 570 | { |
be60a902 | 571 | ulong start; |
5653fc33 | 572 | |
6d0f6bcf | 573 | #if CONFIG_SYS_HZ != 1000 |
c40c94a3 RA |
574 | if ((ulong)CONFIG_SYS_HZ > 100000) |
575 | tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ | |
576 | else | |
577 | tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); | |
be60a902 | 578 | #endif |
5653fc33 | 579 | |
be60a902 | 580 | /* Wait for command completion */ |
e110c4fe | 581 | #ifdef CONFIG_SYS_LOW_RES_TIMER |
22d6c8fa | 582 | reset_timer(); |
e110c4fe | 583 | #endif |
be60a902 | 584 | start = get_timer (0); |
a9f5faba | 585 | WATCHDOG_RESET(); |
be60a902 HS |
586 | while (flash_is_busy (info, sector)) { |
587 | if (get_timer (start) > tout) { | |
588 | printf ("Flash %s timeout at address %lx data %lx\n", | |
589 | prompt, info->start[sector], | |
590 | flash_read_long (info, sector, 0)); | |
591 | flash_write_cmd (info, sector, 0, info->cmd_reset); | |
592 | return ERR_TIMOUT; | |
5653fc33 | 593 | } |
be60a902 | 594 | udelay (1); /* also triggers watchdog */ |
5653fc33 | 595 | } |
be60a902 HS |
596 | return ERR_OK; |
597 | } | |
5653fc33 | 598 | |
be60a902 HS |
599 | /*----------------------------------------------------------------------- |
600 | * Wait for XSR.7 to be set, if it times out print an error, otherwise | |
601 | * do a full status check. | |
602 | * | |
603 | * This routine sets the flash to read-array mode. | |
604 | */ | |
605 | static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, | |
606 | ulong tout, char *prompt) | |
607 | { | |
608 | int retcode; | |
5653fc33 | 609 | |
be60a902 HS |
610 | retcode = flash_status_check (info, sector, tout, prompt); |
611 | switch (info->vendor) { | |
9c048b52 | 612 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
613 | case CFI_CMDSET_INTEL_EXTENDED: |
614 | case CFI_CMDSET_INTEL_STANDARD: | |
0d01f66d | 615 | if ((retcode != ERR_OK) |
be60a902 HS |
616 | && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { |
617 | retcode = ERR_INVAL; | |
618 | printf ("Flash %s error at address %lx\n", prompt, | |
619 | info->start[sector]); | |
620 | if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | | |
621 | FLASH_STATUS_PSLBS)) { | |
622 | puts ("Command Sequence Error.\n"); | |
623 | } else if (flash_isset (info, sector, 0, | |
624 | FLASH_STATUS_ECLBS)) { | |
625 | puts ("Block Erase Error.\n"); | |
626 | retcode = ERR_NOT_ERASED; | |
627 | } else if (flash_isset (info, sector, 0, | |
628 | FLASH_STATUS_PSLBS)) { | |
629 | puts ("Locking Error\n"); | |
5653fc33 | 630 | } |
be60a902 HS |
631 | if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { |
632 | puts ("Block locked.\n"); | |
633 | retcode = ERR_PROTECTED; | |
634 | } | |
635 | if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) | |
636 | puts ("Vpp Low Error.\n"); | |
5653fc33 | 637 | } |
be60a902 | 638 | flash_write_cmd (info, sector, 0, info->cmd_reset); |
a90b9575 | 639 | udelay(1); |
be60a902 HS |
640 | break; |
641 | default: | |
642 | break; | |
5653fc33 | 643 | } |
be60a902 | 644 | return retcode; |
5653fc33 WD |
645 | } |
646 | ||
e5720823 TC |
647 | static int use_flash_status_poll(flash_info_t *info) |
648 | { | |
649 | #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
650 | if (info->vendor == CFI_CMDSET_AMD_EXTENDED || | |
651 | info->vendor == CFI_CMDSET_AMD_STANDARD) | |
652 | return 1; | |
653 | #endif | |
654 | return 0; | |
655 | } | |
656 | ||
657 | static int flash_status_poll(flash_info_t *info, void *src, void *dst, | |
658 | ulong tout, char *prompt) | |
659 | { | |
660 | #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
661 | ulong start; | |
662 | int ready; | |
663 | ||
664 | #if CONFIG_SYS_HZ != 1000 | |
665 | if ((ulong)CONFIG_SYS_HZ > 100000) | |
666 | tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ | |
667 | else | |
668 | tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); | |
669 | #endif | |
670 | ||
671 | /* Wait for command completion */ | |
e110c4fe | 672 | #ifdef CONFIG_SYS_LOW_RES_TIMER |
22d6c8fa | 673 | reset_timer(); |
e110c4fe | 674 | #endif |
e5720823 | 675 | start = get_timer(0); |
a9f5faba | 676 | WATCHDOG_RESET(); |
e5720823 TC |
677 | while (1) { |
678 | switch (info->portwidth) { | |
679 | case FLASH_CFI_8BIT: | |
680 | ready = flash_read8(dst) == flash_read8(src); | |
681 | break; | |
682 | case FLASH_CFI_16BIT: | |
683 | ready = flash_read16(dst) == flash_read16(src); | |
684 | break; | |
685 | case FLASH_CFI_32BIT: | |
686 | ready = flash_read32(dst) == flash_read32(src); | |
687 | break; | |
688 | case FLASH_CFI_64BIT: | |
689 | ready = flash_read64(dst) == flash_read64(src); | |
690 | break; | |
691 | default: | |
692 | ready = 0; | |
693 | break; | |
694 | } | |
695 | if (ready) | |
696 | break; | |
697 | if (get_timer(start) > tout) { | |
698 | printf("Flash %s timeout at address %lx data %lx\n", | |
699 | prompt, (ulong)dst, (ulong)flash_read8(dst)); | |
700 | return ERR_TIMOUT; | |
701 | } | |
702 | udelay(1); /* also triggers watchdog */ | |
703 | } | |
704 | #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ | |
705 | return ERR_OK; | |
706 | } | |
707 | ||
5653fc33 WD |
708 | /*----------------------------------------------------------------------- |
709 | */ | |
be60a902 | 710 | static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) |
5653fc33 | 711 | { |
6d0f6bcf | 712 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
713 | unsigned short w; |
714 | unsigned int l; | |
715 | unsigned long long ll; | |
716 | #endif | |
5653fc33 | 717 | |
be60a902 HS |
718 | switch (info->portwidth) { |
719 | case FLASH_CFI_8BIT: | |
720 | cword->c = c; | |
721 | break; | |
722 | case FLASH_CFI_16BIT: | |
6d0f6bcf | 723 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
724 | w = c; |
725 | w <<= 8; | |
726 | cword->w = (cword->w >> 8) | w; | |
727 | #else | |
728 | cword->w = (cword->w << 8) | c; | |
81b20ccc | 729 | #endif |
be60a902 HS |
730 | break; |
731 | case FLASH_CFI_32BIT: | |
6d0f6bcf | 732 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
733 | l = c; |
734 | l <<= 24; | |
735 | cword->l = (cword->l >> 8) | l; | |
736 | #else | |
737 | cword->l = (cword->l << 8) | c; | |
738 | #endif | |
739 | break; | |
740 | case FLASH_CFI_64BIT: | |
6d0f6bcf | 741 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
742 | ll = c; |
743 | ll <<= 56; | |
744 | cword->ll = (cword->ll >> 8) | ll; | |
745 | #else | |
746 | cword->ll = (cword->ll << 8) | c; | |
747 | #endif | |
748 | break; | |
260421a2 | 749 | } |
be60a902 | 750 | } |
5653fc33 | 751 | |
0f8e851e JG |
752 | /* |
753 | * Loop through the sector table starting from the previously found sector. | |
754 | * Searches forwards or backwards, dependent on the passed address. | |
be60a902 HS |
755 | */ |
756 | static flash_sect_t find_sector (flash_info_t * info, ulong addr) | |
757 | { | |
11dc4010 | 758 | static flash_sect_t saved_sector; /* previously found sector */ |
0f8e851e JG |
759 | flash_sect_t sector = saved_sector; |
760 | ||
761 | while ((info->start[sector] < addr) | |
762 | && (sector < info->sector_count - 1)) | |
763 | sector++; | |
764 | while ((info->start[sector] > addr) && (sector > 0)) | |
765 | /* | |
766 | * also decrements the sector in case of an overshot | |
767 | * in the first loop | |
768 | */ | |
769 | sector--; | |
770 | ||
771 | saved_sector = sector; | |
be60a902 | 772 | return sector; |
5653fc33 WD |
773 | } |
774 | ||
775 | /*----------------------------------------------------------------------- | |
5653fc33 | 776 | */ |
be60a902 HS |
777 | static int flash_write_cfiword (flash_info_t * info, ulong dest, |
778 | cfiword_t cword) | |
5653fc33 | 779 | { |
09ce9921 | 780 | void *dstaddr = (void *)dest; |
be60a902 | 781 | int flag; |
a7292871 JG |
782 | flash_sect_t sect = 0; |
783 | char sect_found = 0; | |
5653fc33 | 784 | |
be60a902 HS |
785 | /* Check if Flash is (sufficiently) erased */ |
786 | switch (info->portwidth) { | |
787 | case FLASH_CFI_8BIT: | |
239cb9d9 | 788 | debug("%s: 8-bit 0x%02x\n", __func__, cword.c); |
cdbaefb5 | 789 | flag = ((flash_read8(dstaddr) & cword.c) == cword.c); |
be60a902 HS |
790 | break; |
791 | case FLASH_CFI_16BIT: | |
239cb9d9 | 792 | debug("%s: 16-bit 0x%04x\n", __func__, cword.w); |
cdbaefb5 | 793 | flag = ((flash_read16(dstaddr) & cword.w) == cword.w); |
be60a902 HS |
794 | break; |
795 | case FLASH_CFI_32BIT: | |
239cb9d9 | 796 | debug("%s: 32-bit 0x%08lx\n", __func__, cword.l); |
cdbaefb5 | 797 | flag = ((flash_read32(dstaddr) & cword.l) == cword.l); |
be60a902 HS |
798 | break; |
799 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 800 | flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); |
be60a902 HS |
801 | break; |
802 | default: | |
12d30aa7 HS |
803 | flag = 0; |
804 | break; | |
5653fc33 | 805 | } |
09ce9921 | 806 | if (!flag) |
0dc80e27 | 807 | return ERR_NOT_ERASED; |
5653fc33 | 808 | |
be60a902 HS |
809 | /* Disable interrupts which might cause a timeout here */ |
810 | flag = disable_interrupts (); | |
79b4cda0 | 811 | |
be60a902 | 812 | switch (info->vendor) { |
9c048b52 | 813 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
814 | case CFI_CMDSET_INTEL_EXTENDED: |
815 | case CFI_CMDSET_INTEL_STANDARD: | |
816 | flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); | |
817 | flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); | |
818 | break; | |
819 | case CFI_CMDSET_AMD_EXTENDED: | |
820 | case CFI_CMDSET_AMD_STANDARD: | |
0d01f66d ES |
821 | sect = find_sector(info, dest); |
822 | flash_unlock_seq (info, sect); | |
823 | flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE); | |
a7292871 | 824 | sect_found = 1; |
be60a902 | 825 | break; |
b4db4a76 PYC |
826 | #ifdef CONFIG_FLASH_CFI_LEGACY |
827 | case CFI_CMDSET_AMD_LEGACY: | |
828 | sect = find_sector(info, dest); | |
829 | flash_unlock_seq (info, 0); | |
830 | flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); | |
831 | sect_found = 1; | |
832 | break; | |
833 | #endif | |
5653fc33 WD |
834 | } |
835 | ||
be60a902 HS |
836 | switch (info->portwidth) { |
837 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 838 | flash_write8(cword.c, dstaddr); |
be60a902 HS |
839 | break; |
840 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 841 | flash_write16(cword.w, dstaddr); |
be60a902 HS |
842 | break; |
843 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 844 | flash_write32(cword.l, dstaddr); |
be60a902 HS |
845 | break; |
846 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 847 | flash_write64(cword.ll, dstaddr); |
be60a902 | 848 | break; |
5653fc33 WD |
849 | } |
850 | ||
be60a902 HS |
851 | /* re-enable interrupts if necessary */ |
852 | if (flag) | |
853 | enable_interrupts (); | |
5653fc33 | 854 | |
a7292871 JG |
855 | if (!sect_found) |
856 | sect = find_sector (info, dest); | |
857 | ||
e5720823 TC |
858 | if (use_flash_status_poll(info)) |
859 | return flash_status_poll(info, &cword, dstaddr, | |
860 | info->write_tout, "write"); | |
861 | else | |
862 | return flash_full_status_check(info, sect, | |
863 | info->write_tout, "write"); | |
5653fc33 WD |
864 | } |
865 | ||
6d0f6bcf | 866 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
5653fc33 | 867 | |
be60a902 HS |
868 | static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, |
869 | int len) | |
5653fc33 | 870 | { |
be60a902 HS |
871 | flash_sect_t sector; |
872 | int cnt; | |
873 | int retcode; | |
cdbaefb5 | 874 | void *src = cp; |
ec21d5cf | 875 | void *dst = (void *)dest; |
0dc80e27 | 876 | void *dst2 = dst; |
85c344e5 | 877 | int flag = 1; |
96ef831f GL |
878 | uint offset = 0; |
879 | unsigned int shift; | |
9c048b52 | 880 | uchar write_cmd; |
cdbaefb5 | 881 | |
0dc80e27 SR |
882 | switch (info->portwidth) { |
883 | case FLASH_CFI_8BIT: | |
96ef831f | 884 | shift = 0; |
0dc80e27 SR |
885 | break; |
886 | case FLASH_CFI_16BIT: | |
96ef831f | 887 | shift = 1; |
0dc80e27 SR |
888 | break; |
889 | case FLASH_CFI_32BIT: | |
96ef831f | 890 | shift = 2; |
0dc80e27 SR |
891 | break; |
892 | case FLASH_CFI_64BIT: | |
96ef831f | 893 | shift = 3; |
0dc80e27 SR |
894 | break; |
895 | default: | |
896 | retcode = ERR_INVAL; | |
897 | goto out_unmap; | |
898 | } | |
899 | ||
96ef831f GL |
900 | cnt = len >> shift; |
901 | ||
85c344e5 | 902 | while ((cnt-- > 0) && (flag == 1)) { |
0dc80e27 SR |
903 | switch (info->portwidth) { |
904 | case FLASH_CFI_8BIT: | |
905 | flag = ((flash_read8(dst2) & flash_read8(src)) == | |
906 | flash_read8(src)); | |
907 | src += 1, dst2 += 1; | |
908 | break; | |
909 | case FLASH_CFI_16BIT: | |
910 | flag = ((flash_read16(dst2) & flash_read16(src)) == | |
911 | flash_read16(src)); | |
912 | src += 2, dst2 += 2; | |
913 | break; | |
914 | case FLASH_CFI_32BIT: | |
915 | flag = ((flash_read32(dst2) & flash_read32(src)) == | |
916 | flash_read32(src)); | |
917 | src += 4, dst2 += 4; | |
918 | break; | |
919 | case FLASH_CFI_64BIT: | |
920 | flag = ((flash_read64(dst2) & flash_read64(src)) == | |
921 | flash_read64(src)); | |
922 | src += 8, dst2 += 8; | |
923 | break; | |
924 | } | |
925 | } | |
926 | if (!flag) { | |
927 | retcode = ERR_NOT_ERASED; | |
928 | goto out_unmap; | |
929 | } | |
930 | ||
931 | src = cp; | |
cdbaefb5 | 932 | sector = find_sector (info, dest); |
bf9e3b38 WD |
933 | |
934 | switch (info->vendor) { | |
9c048b52 | 935 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
5653fc33 WD |
936 | case CFI_CMDSET_INTEL_STANDARD: |
937 | case CFI_CMDSET_INTEL_EXTENDED: | |
9c048b52 VL |
938 | write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? |
939 | FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; | |
be60a902 | 940 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
9c048b52 VL |
941 | flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS); |
942 | flash_write_cmd (info, sector, 0, write_cmd); | |
be60a902 HS |
943 | retcode = flash_status_check (info, sector, |
944 | info->buffer_write_tout, | |
945 | "write to buffer"); | |
946 | if (retcode == ERR_OK) { | |
947 | /* reduce the number of loops by the width of | |
948 | * the port */ | |
96ef831f | 949 | cnt = len >> shift; |
93c56f21 | 950 | flash_write_cmd (info, sector, 0, cnt - 1); |
be60a902 HS |
951 | while (cnt-- > 0) { |
952 | switch (info->portwidth) { | |
953 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
954 | flash_write8(flash_read8(src), dst); |
955 | src += 1, dst += 1; | |
be60a902 HS |
956 | break; |
957 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
958 | flash_write16(flash_read16(src), dst); |
959 | src += 2, dst += 2; | |
be60a902 HS |
960 | break; |
961 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
962 | flash_write32(flash_read32(src), dst); |
963 | src += 4, dst += 4; | |
be60a902 HS |
964 | break; |
965 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
966 | flash_write64(flash_read64(src), dst); |
967 | src += 8, dst += 8; | |
be60a902 HS |
968 | break; |
969 | default: | |
12d30aa7 HS |
970 | retcode = ERR_INVAL; |
971 | goto out_unmap; | |
be60a902 HS |
972 | } |
973 | } | |
974 | flash_write_cmd (info, sector, 0, | |
975 | FLASH_CMD_WRITE_BUFFER_CONFIRM); | |
976 | retcode = flash_full_status_check ( | |
977 | info, sector, info->buffer_write_tout, | |
978 | "buffer write"); | |
979 | } | |
12d30aa7 HS |
980 | |
981 | break; | |
be60a902 | 982 | |
5653fc33 WD |
983 | case CFI_CMDSET_AMD_STANDARD: |
984 | case CFI_CMDSET_AMD_EXTENDED: | |
be60a902 | 985 | flash_unlock_seq(info,0); |
96ef831f GL |
986 | |
987 | #ifdef CONFIG_FLASH_SPANSION_S29WS_N | |
988 | offset = ((unsigned long)dst - info->start[sector]) >> shift; | |
989 | #endif | |
990 | flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); | |
991 | cnt = len >> shift; | |
7dedefdf | 992 | flash_write_cmd(info, sector, offset, cnt - 1); |
be60a902 HS |
993 | |
994 | switch (info->portwidth) { | |
995 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
996 | while (cnt-- > 0) { |
997 | flash_write8(flash_read8(src), dst); | |
998 | src += 1, dst += 1; | |
999 | } | |
be60a902 HS |
1000 | break; |
1001 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
1002 | while (cnt-- > 0) { |
1003 | flash_write16(flash_read16(src), dst); | |
1004 | src += 2, dst += 2; | |
1005 | } | |
be60a902 HS |
1006 | break; |
1007 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
1008 | while (cnt-- > 0) { |
1009 | flash_write32(flash_read32(src), dst); | |
1010 | src += 4, dst += 4; | |
1011 | } | |
be60a902 HS |
1012 | break; |
1013 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
1014 | while (cnt-- > 0) { |
1015 | flash_write64(flash_read64(src), dst); | |
1016 | src += 8, dst += 8; | |
1017 | } | |
be60a902 HS |
1018 | break; |
1019 | default: | |
12d30aa7 HS |
1020 | retcode = ERR_INVAL; |
1021 | goto out_unmap; | |
be60a902 HS |
1022 | } |
1023 | ||
1024 | flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); | |
e5720823 TC |
1025 | if (use_flash_status_poll(info)) |
1026 | retcode = flash_status_poll(info, src - (1 << shift), | |
1027 | dst - (1 << shift), | |
1028 | info->buffer_write_tout, | |
1029 | "buffer write"); | |
1030 | else | |
1031 | retcode = flash_full_status_check(info, sector, | |
1032 | info->buffer_write_tout, | |
1033 | "buffer write"); | |
12d30aa7 | 1034 | break; |
be60a902 | 1035 | |
5653fc33 | 1036 | default: |
be60a902 | 1037 | debug ("Unknown Command Set\n"); |
12d30aa7 HS |
1038 | retcode = ERR_INVAL; |
1039 | break; | |
5653fc33 | 1040 | } |
12d30aa7 HS |
1041 | |
1042 | out_unmap: | |
12d30aa7 | 1043 | return retcode; |
5653fc33 | 1044 | } |
6d0f6bcf | 1045 | #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
be60a902 | 1046 | |
bf9e3b38 | 1047 | |
5653fc33 | 1048 | /*----------------------------------------------------------------------- |
5653fc33 | 1049 | */ |
be60a902 | 1050 | int flash_erase (flash_info_t * info, int s_first, int s_last) |
5653fc33 | 1051 | { |
be60a902 HS |
1052 | int rcode = 0; |
1053 | int prot; | |
1054 | flash_sect_t sect; | |
e5720823 | 1055 | int st; |
5653fc33 | 1056 | |
239cb9d9 | 1057 | debug("%s: erasing sectors %d to %d\n", __func__, s_first, s_last); |
1058 | ||
be60a902 HS |
1059 | if (info->flash_id != FLASH_MAN_CFI) { |
1060 | puts ("Can't erase unknown flash type - aborted\n"); | |
1061 | return 1; | |
1062 | } | |
1063 | if ((s_first < 0) || (s_first > s_last)) { | |
1064 | puts ("- no sectors to erase\n"); | |
1065 | return 1; | |
1066 | } | |
2662b40c | 1067 | |
be60a902 HS |
1068 | prot = 0; |
1069 | for (sect = s_first; sect <= s_last; ++sect) { | |
1070 | if (info->protect[sect]) { | |
1071 | prot++; | |
5653fc33 WD |
1072 | } |
1073 | } | |
be60a902 HS |
1074 | if (prot) { |
1075 | printf ("- Warning: %d protected sectors will not be erased!\n", | |
1076 | prot); | |
6ea808ef | 1077 | } else if (flash_verbose) { |
be60a902 HS |
1078 | putc ('\n'); |
1079 | } | |
bf9e3b38 | 1080 | |
bf9e3b38 | 1081 | |
be60a902 | 1082 | for (sect = s_first; sect <= s_last; sect++) { |
de15a06a JH |
1083 | if (ctrlc()) { |
1084 | printf("\n"); | |
1085 | return 1; | |
1086 | } | |
1087 | ||
be60a902 | 1088 | if (info->protect[sect] == 0) { /* not protected */ |
6822a647 JH |
1089 | #ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE |
1090 | int k; | |
1091 | int size; | |
1092 | int erased; | |
1093 | u32 *flash; | |
1094 | ||
1095 | /* | |
1096 | * Check if whole sector is erased | |
1097 | */ | |
1098 | size = flash_sector_size(info, sect); | |
1099 | erased = 1; | |
1100 | flash = (u32 *)info->start[sect]; | |
1101 | /* divide by 4 for longword access */ | |
1102 | size = size >> 2; | |
1103 | for (k = 0; k < size; k++) { | |
1104 | if (flash_read32(flash++) != 0xffffffff) { | |
1105 | erased = 0; | |
1106 | break; | |
1107 | } | |
1108 | } | |
1109 | if (erased) { | |
1110 | if (flash_verbose) | |
1111 | putc(','); | |
1112 | continue; | |
1113 | } | |
1114 | #endif | |
be60a902 | 1115 | switch (info->vendor) { |
9c048b52 | 1116 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
1117 | case CFI_CMDSET_INTEL_STANDARD: |
1118 | case CFI_CMDSET_INTEL_EXTENDED: | |
1119 | flash_write_cmd (info, sect, 0, | |
1120 | FLASH_CMD_CLEAR_STATUS); | |
1121 | flash_write_cmd (info, sect, 0, | |
1122 | FLASH_CMD_BLOCK_ERASE); | |
1123 | flash_write_cmd (info, sect, 0, | |
1124 | FLASH_CMD_ERASE_CONFIRM); | |
1125 | break; | |
1126 | case CFI_CMDSET_AMD_STANDARD: | |
1127 | case CFI_CMDSET_AMD_EXTENDED: | |
1128 | flash_unlock_seq (info, sect); | |
1129 | flash_write_cmd (info, sect, | |
1130 | info->addr_unlock1, | |
1131 | AMD_CMD_ERASE_START); | |
1132 | flash_unlock_seq (info, sect); | |
1133 | flash_write_cmd (info, sect, 0, | |
07b2c5c0 | 1134 | info->cmd_erase_sector); |
be60a902 HS |
1135 | break; |
1136 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1137 | case CFI_CMDSET_AMD_LEGACY: | |
1138 | flash_unlock_seq (info, 0); | |
1139 | flash_write_cmd (info, 0, info->addr_unlock1, | |
1140 | AMD_CMD_ERASE_START); | |
1141 | flash_unlock_seq (info, 0); | |
1142 | flash_write_cmd (info, sect, 0, | |
1143 | AMD_CMD_ERASE_SECTOR); | |
1144 | break; | |
1145 | #endif | |
1146 | default: | |
1147 | debug ("Unkown flash vendor %d\n", | |
1148 | info->vendor); | |
1149 | break; | |
bf9e3b38 | 1150 | } |
be60a902 | 1151 | |
e5720823 | 1152 | if (use_flash_status_poll(info)) { |
11dc4010 | 1153 | cfiword_t cword; |
e5720823 | 1154 | void *dest; |
11dc4010 | 1155 | cword.ll = 0xffffffffffffffffULL; |
e5720823 TC |
1156 | dest = flash_map(info, sect, 0); |
1157 | st = flash_status_poll(info, &cword, dest, | |
1158 | info->erase_blk_tout, "erase"); | |
1159 | flash_unmap(info, sect, 0, dest); | |
1160 | } else | |
1161 | st = flash_full_status_check(info, sect, | |
1162 | info->erase_blk_tout, | |
1163 | "erase"); | |
1164 | if (st) | |
be60a902 | 1165 | rcode = 1; |
e5720823 | 1166 | else if (flash_verbose) |
be60a902 | 1167 | putc ('.'); |
239cb9d9 | 1168 | } else { |
1169 | debug("\nSector %d is protected.\n", | |
1170 | info->protect[sect]); | |
5653fc33 | 1171 | } |
5653fc33 | 1172 | } |
6ea808ef PZ |
1173 | |
1174 | if (flash_verbose) | |
1175 | puts (" done\n"); | |
1176 | ||
be60a902 | 1177 | return rcode; |
5653fc33 | 1178 | } |
bf9e3b38 | 1179 | |
70084df7 SR |
1180 | #ifdef CONFIG_SYS_FLASH_EMPTY_INFO |
1181 | static int sector_erased(flash_info_t *info, int i) | |
1182 | { | |
1183 | int k; | |
1184 | int size; | |
4d2ca9d6 | 1185 | u32 *flash; |
70084df7 SR |
1186 | |
1187 | /* | |
1188 | * Check if whole sector is erased | |
1189 | */ | |
1190 | size = flash_sector_size(info, i); | |
4d2ca9d6 | 1191 | flash = (u32 *)info->start[i]; |
70084df7 SR |
1192 | /* divide by 4 for longword access */ |
1193 | size = size >> 2; | |
1194 | ||
1195 | for (k = 0; k < size; k++) { | |
4d2ca9d6 | 1196 | if (flash_read32(flash++) != 0xffffffff) |
70084df7 SR |
1197 | return 0; /* not erased */ |
1198 | } | |
1199 | ||
1200 | return 1; /* erased */ | |
1201 | } | |
1202 | #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */ | |
1203 | ||
be60a902 | 1204 | void flash_print_info (flash_info_t * info) |
5653fc33 | 1205 | { |
be60a902 | 1206 | int i; |
4d13cbad | 1207 | |
be60a902 HS |
1208 | if (info->flash_id != FLASH_MAN_CFI) { |
1209 | puts ("missing or unknown FLASH type\n"); | |
1210 | return; | |
1211 | } | |
1212 | ||
eddf52b5 | 1213 | printf ("%s flash (%d x %d)", |
be60a902 HS |
1214 | info->name, |
1215 | (info->portwidth << 3), (info->chipwidth << 3)); | |
1216 | if (info->size < 1024*1024) | |
1217 | printf (" Size: %ld kB in %d Sectors\n", | |
1218 | info->size >> 10, info->sector_count); | |
1219 | else | |
1220 | printf (" Size: %ld MB in %d Sectors\n", | |
1221 | info->size >> 20, info->sector_count); | |
1222 | printf (" "); | |
1223 | switch (info->vendor) { | |
9c048b52 VL |
1224 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
1225 | printf ("Intel Prog Regions"); | |
1226 | break; | |
be60a902 HS |
1227 | case CFI_CMDSET_INTEL_STANDARD: |
1228 | printf ("Intel Standard"); | |
1229 | break; | |
1230 | case CFI_CMDSET_INTEL_EXTENDED: | |
1231 | printf ("Intel Extended"); | |
1232 | break; | |
1233 | case CFI_CMDSET_AMD_STANDARD: | |
1234 | printf ("AMD Standard"); | |
1235 | break; | |
1236 | case CFI_CMDSET_AMD_EXTENDED: | |
1237 | printf ("AMD Extended"); | |
1238 | break; | |
1239 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1240 | case CFI_CMDSET_AMD_LEGACY: | |
1241 | printf ("AMD Legacy"); | |
1242 | break; | |
4d13cbad | 1243 | #endif |
be60a902 HS |
1244 | default: |
1245 | printf ("Unknown (%d)", info->vendor); | |
1246 | break; | |
1247 | } | |
d77c7ac4 PDM |
1248 | printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x", |
1249 | info->manufacturer_id); | |
1250 | printf (info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", | |
1251 | info->device_id); | |
5b448adb HS |
1252 | if ((info->device_id & 0xff) == 0x7E) { |
1253 | printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", | |
1254 | info->device_id2); | |
be60a902 | 1255 | } |
d2af028d SR |
1256 | if ((info->vendor == CFI_CMDSET_AMD_STANDARD) && (info->legacy_unlock)) |
1257 | printf("\n Advanced Sector Protection (PPB) enabled"); | |
be60a902 HS |
1258 | printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", |
1259 | info->erase_blk_tout, | |
1260 | info->write_tout); | |
1261 | if (info->buffer_size > 1) { | |
1262 | printf (" Buffer write timeout: %ld ms, " | |
1263 | "buffer size: %d bytes\n", | |
1264 | info->buffer_write_tout, | |
1265 | info->buffer_size); | |
5653fc33 | 1266 | } |
5653fc33 | 1267 | |
be60a902 HS |
1268 | puts ("\n Sector Start Addresses:"); |
1269 | for (i = 0; i < info->sector_count; ++i) { | |
2e97394a | 1270 | if (ctrlc()) |
70084df7 | 1271 | break; |
be60a902 | 1272 | if ((i % 5) == 0) |
70084df7 | 1273 | putc('\n'); |
6d0f6bcf | 1274 | #ifdef CONFIG_SYS_FLASH_EMPTY_INFO |
be60a902 HS |
1275 | /* print empty and read-only info */ |
1276 | printf (" %08lX %c %s ", | |
1277 | info->start[i], | |
70084df7 | 1278 | sector_erased(info, i) ? 'E' : ' ', |
be60a902 | 1279 | info->protect[i] ? "RO" : " "); |
6d0f6bcf | 1280 | #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ |
be60a902 HS |
1281 | printf (" %08lX %s ", |
1282 | info->start[i], | |
1283 | info->protect[i] ? "RO" : " "); | |
bf9e3b38 | 1284 | #endif |
be60a902 HS |
1285 | } |
1286 | putc ('\n'); | |
1287 | return; | |
5653fc33 WD |
1288 | } |
1289 | ||
9a042e9c JVB |
1290 | /*----------------------------------------------------------------------- |
1291 | * This is used in a few places in write_buf() to show programming | |
1292 | * progress. Making it a function is nasty because it needs to do side | |
1293 | * effect updates to digit and dots. Repeated code is nasty too, so | |
1294 | * we define it once here. | |
1295 | */ | |
f0105727 SR |
1296 | #ifdef CONFIG_FLASH_SHOW_PROGRESS |
1297 | #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ | |
6ea808ef PZ |
1298 | if (flash_verbose) { \ |
1299 | dots -= dots_sub; \ | |
1300 | if ((scale > 0) && (dots <= 0)) { \ | |
1301 | if ((digit % 5) == 0) \ | |
1302 | printf ("%d", digit / 5); \ | |
1303 | else \ | |
1304 | putc ('.'); \ | |
1305 | digit--; \ | |
1306 | dots += scale; \ | |
1307 | } \ | |
9a042e9c | 1308 | } |
f0105727 SR |
1309 | #else |
1310 | #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) | |
1311 | #endif | |
9a042e9c | 1312 | |
be60a902 HS |
1313 | /*----------------------------------------------------------------------- |
1314 | * Copy memory to flash, returns: | |
1315 | * 0 - OK | |
1316 | * 1 - write timeout | |
1317 | * 2 - Flash not erased | |
5653fc33 | 1318 | */ |
be60a902 | 1319 | int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
5653fc33 | 1320 | { |
be60a902 | 1321 | ulong wp; |
12d30aa7 | 1322 | uchar *p; |
be60a902 | 1323 | int aln; |
5653fc33 | 1324 | cfiword_t cword; |
be60a902 | 1325 | int i, rc; |
6d0f6bcf | 1326 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be60a902 | 1327 | int buffered_size; |
5653fc33 | 1328 | #endif |
9a042e9c JVB |
1329 | #ifdef CONFIG_FLASH_SHOW_PROGRESS |
1330 | int digit = CONFIG_FLASH_SHOW_PROGRESS; | |
1331 | int scale = 0; | |
1332 | int dots = 0; | |
1333 | ||
1334 | /* | |
1335 | * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. | |
1336 | */ | |
1337 | if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { | |
1338 | scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / | |
1339 | CONFIG_FLASH_SHOW_PROGRESS); | |
1340 | } | |
1341 | #endif | |
1342 | ||
be60a902 HS |
1343 | /* get lower aligned address */ |
1344 | wp = (addr & ~(info->portwidth - 1)); | |
3a197b2f | 1345 | |
be60a902 HS |
1346 | /* handle unaligned start */ |
1347 | if ((aln = addr - wp) != 0) { | |
1348 | cword.l = 0; | |
09ce9921 | 1349 | p = (uchar *)wp; |
12d30aa7 HS |
1350 | for (i = 0; i < aln; ++i) |
1351 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
5653fc33 | 1352 | |
be60a902 HS |
1353 | for (; (i < info->portwidth) && (cnt > 0); i++) { |
1354 | flash_add_byte (info, &cword, *src++); | |
1355 | cnt--; | |
be60a902 | 1356 | } |
12d30aa7 HS |
1357 | for (; (cnt == 0) && (i < info->portwidth); ++i) |
1358 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
1359 | ||
1360 | rc = flash_write_cfiword (info, wp, cword); | |
12d30aa7 | 1361 | if (rc != 0) |
be60a902 | 1362 | return rc; |
12d30aa7 HS |
1363 | |
1364 | wp += i; | |
f0105727 | 1365 | FLASH_SHOW_PROGRESS(scale, dots, digit, i); |
be60a902 HS |
1366 | } |
1367 | ||
1368 | /* handle the aligned part */ | |
6d0f6bcf | 1369 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be60a902 HS |
1370 | buffered_size = (info->portwidth / info->chipwidth); |
1371 | buffered_size *= info->buffer_size; | |
1372 | while (cnt >= info->portwidth) { | |
1373 | /* prohibit buffer write when buffer_size is 1 */ | |
1374 | if (info->buffer_size == 1) { | |
1375 | cword.l = 0; | |
1376 | for (i = 0; i < info->portwidth; i++) | |
1377 | flash_add_byte (info, &cword, *src++); | |
1378 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
1379 | return rc; | |
1380 | wp += info->portwidth; | |
1381 | cnt -= info->portwidth; | |
1382 | continue; | |
1383 | } | |
1384 | ||
1385 | /* write buffer until next buffered_size aligned boundary */ | |
1386 | i = buffered_size - (wp % buffered_size); | |
1387 | if (i > cnt) | |
1388 | i = cnt; | |
1389 | if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) | |
1390 | return rc; | |
1391 | i -= i & (info->portwidth - 1); | |
1392 | wp += i; | |
1393 | src += i; | |
1394 | cnt -= i; | |
f0105727 | 1395 | FLASH_SHOW_PROGRESS(scale, dots, digit, i); |
de15a06a JH |
1396 | /* Only check every once in a while */ |
1397 | if ((cnt & 0xFFFF) < buffered_size && ctrlc()) | |
1398 | return ERR_ABORTED; | |
be60a902 HS |
1399 | } |
1400 | #else | |
1401 | while (cnt >= info->portwidth) { | |
1402 | cword.l = 0; | |
1403 | for (i = 0; i < info->portwidth; i++) { | |
1404 | flash_add_byte (info, &cword, *src++); | |
1405 | } | |
1406 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
1407 | return rc; | |
1408 | wp += info->portwidth; | |
1409 | cnt -= info->portwidth; | |
f0105727 | 1410 | FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); |
de15a06a JH |
1411 | /* Only check every once in a while */ |
1412 | if ((cnt & 0xFFFF) < info->portwidth && ctrlc()) | |
1413 | return ERR_ABORTED; | |
be60a902 | 1414 | } |
6d0f6bcf | 1415 | #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
9a042e9c | 1416 | |
be60a902 HS |
1417 | if (cnt == 0) { |
1418 | return (0); | |
1419 | } | |
1420 | ||
1421 | /* | |
1422 | * handle unaligned tail bytes | |
1423 | */ | |
1424 | cword.l = 0; | |
09ce9921 | 1425 | p = (uchar *)wp; |
12d30aa7 | 1426 | for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { |
be60a902 HS |
1427 | flash_add_byte (info, &cword, *src++); |
1428 | --cnt; | |
1429 | } | |
12d30aa7 HS |
1430 | for (; i < info->portwidth; ++i) |
1431 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
be60a902 HS |
1432 | |
1433 | return flash_write_cfiword (info, wp, cword); | |
5653fc33 | 1434 | } |
bf9e3b38 | 1435 | |
20043a4c SR |
1436 | static inline int manufact_match(flash_info_t *info, u32 manu) |
1437 | { | |
1438 | return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16); | |
1439 | } | |
1440 | ||
5653fc33 WD |
1441 | /*----------------------------------------------------------------------- |
1442 | */ | |
6d0f6bcf | 1443 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
be60a902 | 1444 | |
81316a90 HB |
1445 | static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot) |
1446 | { | |
20043a4c | 1447 | if (manufact_match(info, INTEL_MANUFACT) |
11dc4010 | 1448 | && info->device_id == NUMONYX_256MBIT) { |
81316a90 HB |
1449 | /* |
1450 | * see errata called | |
1451 | * "Numonyx Axcell P33/P30 Specification Update" :) | |
1452 | */ | |
1453 | flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID); | |
1454 | if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT, | |
1455 | prot)) { | |
1456 | /* | |
1457 | * cmd must come before FLASH_CMD_PROTECT + 20us | |
1458 | * Disable interrupts which might cause a timeout here. | |
1459 | */ | |
1460 | int flag = disable_interrupts(); | |
1461 | unsigned short cmd; | |
1462 | ||
1463 | if (prot) | |
1464 | cmd = FLASH_CMD_PROTECT_SET; | |
1465 | else | |
1466 | cmd = FLASH_CMD_PROTECT_CLEAR; | |
1467 | flash_write_cmd(info, sector, 0, | |
1468 | FLASH_CMD_PROTECT); | |
1469 | flash_write_cmd(info, sector, 0, cmd); | |
1470 | /* re-enable interrupts if necessary */ | |
1471 | if (flag) | |
1472 | enable_interrupts(); | |
1473 | } | |
1474 | return 1; | |
1475 | } | |
1476 | return 0; | |
1477 | } | |
1478 | ||
be60a902 | 1479 | int flash_real_protect (flash_info_t * info, long sector, int prot) |
5653fc33 | 1480 | { |
be60a902 | 1481 | int retcode = 0; |
5653fc33 | 1482 | |
bc9019e1 RC |
1483 | switch (info->vendor) { |
1484 | case CFI_CMDSET_INTEL_PROG_REGIONS: | |
1485 | case CFI_CMDSET_INTEL_STANDARD: | |
9e8e63cc | 1486 | case CFI_CMDSET_INTEL_EXTENDED: |
81316a90 HB |
1487 | if (!cfi_protect_bugfix(info, sector, prot)) { |
1488 | flash_write_cmd(info, sector, 0, | |
1489 | FLASH_CMD_CLEAR_STATUS); | |
1490 | flash_write_cmd(info, sector, 0, | |
1491 | FLASH_CMD_PROTECT); | |
54652991 | 1492 | if (prot) |
81316a90 HB |
1493 | flash_write_cmd(info, sector, 0, |
1494 | FLASH_CMD_PROTECT_SET); | |
54652991 | 1495 | else |
81316a90 HB |
1496 | flash_write_cmd(info, sector, 0, |
1497 | FLASH_CMD_PROTECT_CLEAR); | |
1498 | ||
54652991 | 1499 | } |
bc9019e1 RC |
1500 | break; |
1501 | case CFI_CMDSET_AMD_EXTENDED: | |
1502 | case CFI_CMDSET_AMD_STANDARD: | |
bc9019e1 | 1503 | /* U-Boot only checks the first byte */ |
20043a4c | 1504 | if (manufact_match(info, ATM_MANUFACT)) { |
bc9019e1 RC |
1505 | if (prot) { |
1506 | flash_unlock_seq (info, 0); | |
1507 | flash_write_cmd (info, 0, | |
1508 | info->addr_unlock1, | |
1509 | ATM_CMD_SOFTLOCK_START); | |
1510 | flash_unlock_seq (info, 0); | |
1511 | flash_write_cmd (info, sector, 0, | |
1512 | ATM_CMD_LOCK_SECT); | |
1513 | } else { | |
1514 | flash_write_cmd (info, 0, | |
1515 | info->addr_unlock1, | |
1516 | AMD_CMD_UNLOCK_START); | |
1517 | if (info->device_id == ATM_ID_BV6416) | |
1518 | flash_write_cmd (info, sector, | |
1519 | 0, ATM_CMD_UNLOCK_SECT); | |
1520 | } | |
1521 | } | |
ac6b9115 | 1522 | if (info->legacy_unlock) { |
66863b05 AG |
1523 | int flag = disable_interrupts(); |
1524 | int lock_flag; | |
1525 | ||
1526 | flash_unlock_seq(info, 0); | |
1527 | flash_write_cmd(info, 0, info->addr_unlock1, | |
1528 | AMD_CMD_SET_PPB_ENTRY); | |
1529 | lock_flag = flash_isset(info, sector, 0, 0x01); | |
1530 | if (prot) { | |
1531 | if (lock_flag) { | |
1532 | flash_write_cmd(info, sector, 0, | |
1533 | AMD_CMD_PPB_LOCK_BC1); | |
1534 | flash_write_cmd(info, sector, 0, | |
1535 | AMD_CMD_PPB_LOCK_BC2); | |
1536 | } | |
1537 | debug("sector %ld %slocked\n", sector, | |
1538 | lock_flag ? "" : "already "); | |
1539 | } else { | |
1540 | if (!lock_flag) { | |
1541 | debug("unlock %ld\n", sector); | |
1542 | flash_write_cmd(info, 0, 0, | |
1543 | AMD_CMD_PPB_UNLOCK_BC1); | |
1544 | flash_write_cmd(info, 0, 0, | |
1545 | AMD_CMD_PPB_UNLOCK_BC2); | |
1546 | } | |
1547 | debug("sector %ld %sunlocked\n", sector, | |
1548 | !lock_flag ? "" : "already "); | |
1549 | } | |
1550 | if (flag) | |
1551 | enable_interrupts(); | |
1552 | ||
1553 | if (flash_status_check(info, sector, | |
1554 | info->erase_blk_tout, | |
1555 | prot ? "protect" : "unprotect")) | |
1556 | printf("status check error\n"); | |
1557 | ||
1558 | flash_write_cmd(info, 0, 0, | |
1559 | AMD_CMD_SET_PPB_EXIT_BC1); | |
1560 | flash_write_cmd(info, 0, 0, | |
1561 | AMD_CMD_SET_PPB_EXIT_BC2); | |
1562 | } | |
bc9019e1 | 1563 | break; |
4e00acde TL |
1564 | #ifdef CONFIG_FLASH_CFI_LEGACY |
1565 | case CFI_CMDSET_AMD_LEGACY: | |
1566 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); | |
1567 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); | |
1568 | if (prot) | |
1569 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); | |
1570 | else | |
1571 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); | |
1572 | #endif | |
bc9019e1 | 1573 | }; |
bf9e3b38 | 1574 | |
df4e813b SR |
1575 | /* |
1576 | * Flash needs to be in status register read mode for | |
1577 | * flash_full_status_check() to work correctly | |
1578 | */ | |
1579 | flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); | |
be60a902 HS |
1580 | if ((retcode = |
1581 | flash_full_status_check (info, sector, info->erase_blk_tout, | |
1582 | prot ? "protect" : "unprotect")) == 0) { | |
bf9e3b38 | 1583 | |
be60a902 HS |
1584 | info->protect[sector] = prot; |
1585 | ||
1586 | /* | |
1587 | * On some of Intel's flash chips (marked via legacy_unlock) | |
1588 | * unprotect unprotects all locking. | |
1589 | */ | |
1590 | if ((prot == 0) && (info->legacy_unlock)) { | |
1591 | flash_sect_t i; | |
1592 | ||
1593 | for (i = 0; i < info->sector_count; i++) { | |
1594 | if (info->protect[i]) | |
1595 | flash_real_protect (info, i, 1); | |
1596 | } | |
5653fc33 | 1597 | } |
5653fc33 | 1598 | } |
be60a902 | 1599 | return retcode; |
5653fc33 | 1600 | } |
bf9e3b38 | 1601 | |
5653fc33 | 1602 | /*----------------------------------------------------------------------- |
be60a902 | 1603 | * flash_read_user_serial - read the OneTimeProgramming cells |
5653fc33 | 1604 | */ |
be60a902 HS |
1605 | void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, |
1606 | int len) | |
5653fc33 | 1607 | { |
be60a902 HS |
1608 | uchar *src; |
1609 | uchar *dst; | |
bf9e3b38 | 1610 | |
be60a902 | 1611 | dst = buffer; |
12d30aa7 | 1612 | src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION); |
be60a902 HS |
1613 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); |
1614 | memcpy (dst, src + offset, len); | |
1615 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
a90b9575 | 1616 | udelay(1); |
12d30aa7 | 1617 | flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); |
5653fc33 WD |
1618 | } |
1619 | ||
be60a902 HS |
1620 | /* |
1621 | * flash_read_factory_serial - read the device Id from the protection area | |
5653fc33 | 1622 | */ |
be60a902 HS |
1623 | void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, |
1624 | int len) | |
5653fc33 | 1625 | { |
be60a902 | 1626 | uchar *src; |
bf9e3b38 | 1627 | |
12d30aa7 | 1628 | src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION); |
be60a902 HS |
1629 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); |
1630 | memcpy (buffer, src + offset, len); | |
1631 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
a90b9575 | 1632 | udelay(1); |
12d30aa7 | 1633 | flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); |
5653fc33 WD |
1634 | } |
1635 | ||
6d0f6bcf | 1636 | #endif /* CONFIG_SYS_FLASH_PROTECTION */ |
be60a902 | 1637 | |
0ddf06dd HS |
1638 | /*----------------------------------------------------------------------- |
1639 | * Reverse the order of the erase regions in the CFI QRY structure. | |
1640 | * This is needed for chips that are either a) correctly detected as | |
1641 | * top-boot, or b) buggy. | |
1642 | */ | |
1643 | static void cfi_reverse_geometry(struct cfi_qry *qry) | |
1644 | { | |
1645 | unsigned int i, j; | |
1646 | u32 tmp; | |
1647 | ||
1648 | for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { | |
1649 | tmp = qry->erase_region_info[i]; | |
1650 | qry->erase_region_info[i] = qry->erase_region_info[j]; | |
1651 | qry->erase_region_info[j] = tmp; | |
1652 | } | |
1653 | } | |
be60a902 | 1654 | |
260421a2 SR |
1655 | /*----------------------------------------------------------------------- |
1656 | * read jedec ids from device and set corresponding fields in info struct | |
1657 | * | |
1658 | * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct | |
1659 | * | |
0ddf06dd HS |
1660 | */ |
1661 | static void cmdset_intel_read_jedec_ids(flash_info_t *info) | |
1662 | { | |
1663 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
a90b9575 | 1664 | udelay(1); |
0ddf06dd HS |
1665 | flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); |
1666 | udelay(1000); /* some flash are slow to respond */ | |
1667 | info->manufacturer_id = flash_read_uchar (info, | |
1668 | FLASH_OFFSET_MANUFACTURER_ID); | |
d77c7ac4 PDM |
1669 | info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ? |
1670 | flash_read_word (info, FLASH_OFFSET_DEVICE_ID) : | |
1671 | flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID); | |
0ddf06dd HS |
1672 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
1673 | } | |
1674 | ||
1675 | static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) | |
1676 | { | |
1677 | info->cmd_reset = FLASH_CMD_RESET; | |
1678 | ||
1679 | cmdset_intel_read_jedec_ids(info); | |
1680 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1681 | ||
6d0f6bcf | 1682 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
0ddf06dd HS |
1683 | /* read legacy lock/unlock bit from intel flash */ |
1684 | if (info->ext_addr) { | |
1685 | info->legacy_unlock = flash_read_uchar (info, | |
1686 | info->ext_addr + 5) & 0x08; | |
1687 | } | |
1688 | #endif | |
1689 | ||
1690 | return 0; | |
1691 | } | |
1692 | ||
1693 | static void cmdset_amd_read_jedec_ids(flash_info_t *info) | |
1694 | { | |
3a7b2c21 NG |
1695 | ushort bankId = 0; |
1696 | uchar manuId; | |
1697 | ||
0ddf06dd HS |
1698 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); |
1699 | flash_unlock_seq(info, 0); | |
1700 | flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); | |
1701 | udelay(1000); /* some flash are slow to respond */ | |
90447ecb | 1702 | |
3a7b2c21 NG |
1703 | manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); |
1704 | /* JEDEC JEP106Z specifies ID codes up to bank 7 */ | |
1705 | while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { | |
1706 | bankId += 0x100; | |
1707 | manuId = flash_read_uchar (info, | |
1708 | bankId | FLASH_OFFSET_MANUFACTURER_ID); | |
1709 | } | |
1710 | info->manufacturer_id = manuId; | |
90447ecb TK |
1711 | |
1712 | switch (info->chipwidth){ | |
1713 | case FLASH_CFI_8BIT: | |
1714 | info->device_id = flash_read_uchar (info, | |
1715 | FLASH_OFFSET_DEVICE_ID); | |
1716 | if (info->device_id == 0x7E) { | |
1717 | /* AMD 3-byte (expanded) device ids */ | |
1718 | info->device_id2 = flash_read_uchar (info, | |
1719 | FLASH_OFFSET_DEVICE_ID2); | |
1720 | info->device_id2 <<= 8; | |
1721 | info->device_id2 |= flash_read_uchar (info, | |
1722 | FLASH_OFFSET_DEVICE_ID3); | |
1723 | } | |
1724 | break; | |
1725 | case FLASH_CFI_16BIT: | |
1726 | info->device_id = flash_read_word (info, | |
1727 | FLASH_OFFSET_DEVICE_ID); | |
5b448adb HS |
1728 | if ((info->device_id & 0xff) == 0x7E) { |
1729 | /* AMD 3-byte (expanded) device ids */ | |
1730 | info->device_id2 = flash_read_uchar (info, | |
1731 | FLASH_OFFSET_DEVICE_ID2); | |
1732 | info->device_id2 <<= 8; | |
1733 | info->device_id2 |= flash_read_uchar (info, | |
1734 | FLASH_OFFSET_DEVICE_ID3); | |
1735 | } | |
90447ecb TK |
1736 | break; |
1737 | default: | |
1738 | break; | |
0ddf06dd HS |
1739 | } |
1740 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
a90b9575 | 1741 | udelay(1); |
0ddf06dd HS |
1742 | } |
1743 | ||
1744 | static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) | |
1745 | { | |
1746 | info->cmd_reset = AMD_CMD_RESET; | |
07b2c5c0 | 1747 | info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR; |
0ddf06dd HS |
1748 | |
1749 | cmdset_amd_read_jedec_ids(info); | |
1750 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1751 | ||
66863b05 | 1752 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
ac6b9115 SR |
1753 | if (info->ext_addr) { |
1754 | /* read sector protect/unprotect scheme (at 0x49) */ | |
1755 | if (flash_read_uchar(info, info->ext_addr + 9) == 0x8) | |
66863b05 AG |
1756 | info->legacy_unlock = 1; |
1757 | } | |
1758 | #endif | |
1759 | ||
0ddf06dd HS |
1760 | return 0; |
1761 | } | |
1762 | ||
1763 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
260421a2 SR |
1764 | static void flash_read_jedec_ids (flash_info_t * info) |
1765 | { | |
1766 | info->manufacturer_id = 0; | |
1767 | info->device_id = 0; | |
1768 | info->device_id2 = 0; | |
1769 | ||
1770 | switch (info->vendor) { | |
9c048b52 | 1771 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
260421a2 SR |
1772 | case CFI_CMDSET_INTEL_STANDARD: |
1773 | case CFI_CMDSET_INTEL_EXTENDED: | |
8225d1e3 | 1774 | cmdset_intel_read_jedec_ids(info); |
260421a2 SR |
1775 | break; |
1776 | case CFI_CMDSET_AMD_STANDARD: | |
1777 | case CFI_CMDSET_AMD_EXTENDED: | |
8225d1e3 | 1778 | cmdset_amd_read_jedec_ids(info); |
260421a2 SR |
1779 | break; |
1780 | default: | |
1781 | break; | |
1782 | } | |
1783 | } | |
1784 | ||
5653fc33 | 1785 | /*----------------------------------------------------------------------- |
be60a902 HS |
1786 | * Call board code to request info about non-CFI flash. |
1787 | * board_flash_get_legacy needs to fill in at least: | |
1788 | * info->portwidth, info->chipwidth and info->interface for Jedec probing. | |
7e5b9b47 | 1789 | */ |
09ce9921 | 1790 | static int flash_detect_legacy(phys_addr_t base, int banknum) |
5653fc33 | 1791 | { |
be60a902 | 1792 | flash_info_t *info = &flash_info[banknum]; |
7e5b9b47 | 1793 | |
be60a902 HS |
1794 | if (board_flash_get_legacy(base, banknum, info)) { |
1795 | /* board code may have filled info completely. If not, we | |
1796 | use JEDEC ID probing. */ | |
1797 | if (!info->vendor) { | |
1798 | int modes[] = { | |
1799 | CFI_CMDSET_AMD_STANDARD, | |
1800 | CFI_CMDSET_INTEL_STANDARD | |
1801 | }; | |
1802 | int i; | |
7e5b9b47 | 1803 | |
be60a902 HS |
1804 | for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) { |
1805 | info->vendor = modes[i]; | |
09ce9921 BB |
1806 | info->start[0] = |
1807 | (ulong)map_physmem(base, | |
e1fb6d0d | 1808 | info->portwidth, |
09ce9921 | 1809 | MAP_NOCACHE); |
be60a902 HS |
1810 | if (info->portwidth == FLASH_CFI_8BIT |
1811 | && info->interface == FLASH_CFI_X8X16) { | |
1812 | info->addr_unlock1 = 0x2AAA; | |
1813 | info->addr_unlock2 = 0x5555; | |
1814 | } else { | |
1815 | info->addr_unlock1 = 0x5555; | |
1816 | info->addr_unlock2 = 0x2AAA; | |
1817 | } | |
1818 | flash_read_jedec_ids(info); | |
1819 | debug("JEDEC PROBE: ID %x %x %x\n", | |
1820 | info->manufacturer_id, | |
1821 | info->device_id, | |
1822 | info->device_id2); | |
09ce9921 | 1823 | if (jedec_flash_match(info, info->start[0])) |
be60a902 | 1824 | break; |
09ce9921 | 1825 | else |
e1fb6d0d | 1826 | unmap_physmem((void *)info->start[0], |
09ce9921 | 1827 | MAP_NOCACHE); |
be60a902 HS |
1828 | } |
1829 | } | |
1830 | ||
1831 | switch(info->vendor) { | |
9c048b52 | 1832 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
1833 | case CFI_CMDSET_INTEL_STANDARD: |
1834 | case CFI_CMDSET_INTEL_EXTENDED: | |
1835 | info->cmd_reset = FLASH_CMD_RESET; | |
1836 | break; | |
1837 | case CFI_CMDSET_AMD_STANDARD: | |
1838 | case CFI_CMDSET_AMD_EXTENDED: | |
1839 | case CFI_CMDSET_AMD_LEGACY: | |
1840 | info->cmd_reset = AMD_CMD_RESET; | |
1841 | break; | |
1842 | } | |
1843 | info->flash_id = FLASH_MAN_CFI; | |
1844 | return 1; | |
1845 | } | |
1846 | return 0; /* use CFI */ | |
1847 | } | |
1848 | #else | |
09ce9921 | 1849 | static inline int flash_detect_legacy(phys_addr_t base, int banknum) |
be60a902 HS |
1850 | { |
1851 | return 0; /* use CFI */ | |
1852 | } | |
1853 | #endif | |
1854 | ||
1855 | /*----------------------------------------------------------------------- | |
1856 | * detect if flash is compatible with the Common Flash Interface (CFI) | |
1857 | * http://www.jedec.org/download/search/jesd68.pdf | |
1858 | */ | |
e23741f4 HS |
1859 | static void flash_read_cfi (flash_info_t *info, void *buf, |
1860 | unsigned int start, size_t len) | |
1861 | { | |
1862 | u8 *p = buf; | |
1863 | unsigned int i; | |
1864 | ||
1865 | for (i = 0; i < len; i++) | |
239cb9d9 | 1866 | p[i] = flash_read_uchar(info, start + (i * 2)); |
e23741f4 HS |
1867 | } |
1868 | ||
11dc4010 | 1869 | static void __flash_cmd_reset(flash_info_t *info) |
fa36ae79 SR |
1870 | { |
1871 | /* | |
1872 | * We do not yet know what kind of commandset to use, so we issue | |
1873 | * the reset command in both Intel and AMD variants, in the hope | |
1874 | * that AMD flash roms ignore the Intel command. | |
1875 | */ | |
1876 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
a90b9575 | 1877 | udelay(1); |
fa36ae79 SR |
1878 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
1879 | } | |
1880 | void flash_cmd_reset(flash_info_t *info) | |
1881 | __attribute__((weak,alias("__flash_cmd_reset"))); | |
1882 | ||
e23741f4 | 1883 | static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) |
be60a902 HS |
1884 | { |
1885 | int cfi_offset; | |
1886 | ||
be60a902 HS |
1887 | for (cfi_offset=0; |
1888 | cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); | |
1889 | cfi_offset++) { | |
239cb9d9 | 1890 | /* Issue FLASH reset command */ |
1891 | flash_cmd_reset(info); | |
be60a902 HS |
1892 | flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], |
1893 | FLASH_CMD_CFI); | |
239cb9d9 | 1894 | if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && |
1895 | flash_isequal(info, 0, | |
1896 | FLASH_OFFSET_CFI_RESP + 2, 'R') && | |
1897 | flash_isequal(info, 0, | |
1898 | FLASH_OFFSET_CFI_RESP + 4, 'Y')) { | |
e23741f4 HS |
1899 | flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, |
1900 | sizeof(struct cfi_qry)); | |
239cb9d9 | 1901 | #ifdef CONFIG_SYS_FLASH_INTERFACE_WIDTH |
1902 | info->interface = CONFIG_SYS_FLASH_INTERFACE_WIDTH; | |
1903 | #else | |
e23741f4 | 1904 | info->interface = le16_to_cpu(qry->interface_desc); |
239cb9d9 | 1905 | /* Some flash chips can support multiple bus widths. |
1906 | * In this case, override the interface width and | |
1907 | * limit it to the port width. | |
1908 | */ | |
1909 | if ((info->interface == FLASH_CFI_X8X16) && | |
1910 | (info->portwidth == FLASH_CFI_8BIT)) { | |
1911 | debug("Overriding 16-bit interface" | |
1912 | " width to 8-bit port width.\n"); | |
1913 | info->interface = FLASH_CFI_X8; | |
1914 | } else if ((info->interface == FLASH_CFI_X16X32) && | |
1915 | (info->portwidth == FLASH_CFI_16BIT)) { | |
1916 | debug("Overriding 16-bit interface" | |
1917 | " width to 16-bit port width.\n"); | |
1918 | info->interface = FLASH_CFI_X16; | |
1919 | } | |
1920 | #endif | |
be60a902 HS |
1921 | info->cfi_offset = flash_offset_cfi[cfi_offset]; |
1922 | debug ("device interface is %d\n", | |
1923 | info->interface); | |
1924 | debug ("found port %d chip %d ", | |
1925 | info->portwidth, info->chipwidth); | |
1926 | debug ("port %d bits chip %d bits\n", | |
1927 | info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1928 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1929 | ||
1930 | /* calculate command offsets as in the Linux driver */ | |
239cb9d9 | 1931 | info->addr_unlock1 = 0xaaa; |
1932 | info->addr_unlock2 = 0x555; | |
7e5b9b47 HS |
1933 | |
1934 | /* | |
1935 | * modify the unlock address if we are | |
1936 | * in compatibility mode | |
1937 | */ | |
1938 | if ( /* x8/x16 in x8 mode */ | |
1939 | ((info->chipwidth == FLASH_CFI_BY8) && | |
1940 | (info->interface == FLASH_CFI_X8X16)) || | |
1941 | /* x16/x32 in x16 mode */ | |
1942 | ((info->chipwidth == FLASH_CFI_BY16) && | |
1943 | (info->interface == FLASH_CFI_X16X32))) | |
1944 | { | |
1945 | info->addr_unlock1 = 0xaaa; | |
1946 | info->addr_unlock2 = 0x555; | |
1947 | } | |
1948 | ||
1949 | info->name = "CFI conformant"; | |
1950 | return 1; | |
1951 | } | |
1952 | } | |
1953 | ||
1954 | return 0; | |
1955 | } | |
1956 | ||
e23741f4 | 1957 | static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) |
7e5b9b47 | 1958 | { |
bf9e3b38 WD |
1959 | debug ("flash detect cfi\n"); |
1960 | ||
6d0f6bcf | 1961 | for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; |
bf9e3b38 WD |
1962 | info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { |
1963 | for (info->chipwidth = FLASH_CFI_BY8; | |
1964 | info->chipwidth <= info->portwidth; | |
7e5b9b47 | 1965 | info->chipwidth <<= 1) |
239cb9d9 | 1966 | if (__flash_detect_cfi(info, qry)) { |
1967 | debug("Found CFI flash, portwidth %d," | |
1968 | " chipwidth %d\n", | |
1969 | info->portwidth, info->chipwidth); | |
7e5b9b47 | 1970 | return 1; |
239cb9d9 | 1971 | } |
5653fc33 | 1972 | } |
bf9e3b38 | 1973 | debug ("not found\n"); |
5653fc33 WD |
1974 | return 0; |
1975 | } | |
bf9e3b38 | 1976 | |
467bcee1 HS |
1977 | /* |
1978 | * Manufacturer-specific quirks. Add workarounds for geometry | |
1979 | * reversal, etc. here. | |
1980 | */ | |
1981 | static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) | |
1982 | { | |
1983 | /* check if flash geometry needs reversal */ | |
1984 | if (qry->num_erase_regions > 1) { | |
1985 | /* reverse geometry if top boot part */ | |
1986 | if (info->cfi_version < 0x3131) { | |
1987 | /* CFI < 1.1, try to guess from device id */ | |
1988 | if ((info->device_id & 0x80) != 0) | |
1989 | cfi_reverse_geometry(qry); | |
239cb9d9 | 1990 | } else if (flash_read_uchar(info, info->ext_addr + 0x1e) == 3) { |
467bcee1 HS |
1991 | /* CFI >= 1.1, deduct from top/bottom flag */ |
1992 | /* note: ext_addr is valid since cfi_version > 0 */ | |
1993 | cfi_reverse_geometry(qry); | |
1994 | } | |
1995 | } | |
1996 | } | |
1997 | ||
1998 | static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) | |
1999 | { | |
2000 | int reverse_geometry = 0; | |
2001 | ||
2002 | /* Check the "top boot" bit in the PRI */ | |
2003 | if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) | |
2004 | reverse_geometry = 1; | |
2005 | ||
2006 | /* AT49BV6416(T) list the erase regions in the wrong order. | |
2007 | * However, the device ID is identical with the non-broken | |
cb82a532 | 2008 | * AT49BV642D they differ in the high byte. |
467bcee1 | 2009 | */ |
467bcee1 HS |
2010 | if (info->device_id == 0xd6 || info->device_id == 0xd2) |
2011 | reverse_geometry = !reverse_geometry; | |
467bcee1 HS |
2012 | |
2013 | if (reverse_geometry) | |
2014 | cfi_reverse_geometry(qry); | |
2015 | } | |
2016 | ||
e8eac437 RR |
2017 | static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) |
2018 | { | |
2019 | /* check if flash geometry needs reversal */ | |
2020 | if (qry->num_erase_regions > 1) { | |
2021 | /* reverse geometry if top boot part */ | |
2022 | if (info->cfi_version < 0x3131) { | |
6a011ce8 MF |
2023 | /* CFI < 1.1, guess by device id */ |
2024 | if (info->device_id == 0x22CA || /* M29W320DT */ | |
2025 | info->device_id == 0x2256 || /* M29W320ET */ | |
2026 | info->device_id == 0x22D7) { /* M29W800DT */ | |
e8eac437 RR |
2027 | cfi_reverse_geometry(qry); |
2028 | } | |
4c2105cb MF |
2029 | } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { |
2030 | /* CFI >= 1.1, deduct from top/bottom flag */ | |
2031 | /* note: ext_addr is valid since cfi_version > 0 */ | |
2032 | cfi_reverse_geometry(qry); | |
e8eac437 RR |
2033 | } |
2034 | } | |
2035 | } | |
2036 | ||
07b2c5c0 AD |
2037 | static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) |
2038 | { | |
2039 | /* | |
2040 | * SST, for many recent nor parallel flashes, says they are | |
2041 | * CFI-conformant. This is not true, since qry struct. | |
2042 | * reports a std. AMD command set (0x0002), while SST allows to | |
2043 | * erase two different sector sizes for the same memory. | |
2044 | * 64KB sector (SST call it block) needs 0x30 to be erased. | |
2045 | * 4KB sector (SST call it sector) needs 0x50 to be erased. | |
2046 | * Since CFI query detect the 4KB number of sectors, users expects | |
2047 | * a sector granularity of 4KB, and it is here set. | |
2048 | */ | |
2049 | if (info->device_id == 0x5D23 || /* SST39VF3201B */ | |
2050 | info->device_id == 0x5C23) { /* SST39VF3202B */ | |
2051 | /* set sector granularity to 4KB */ | |
2052 | info->cmd_erase_sector=0x50; | |
2053 | } | |
2054 | } | |
2055 | ||
c502321c JT |
2056 | static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) |
2057 | { | |
2058 | /* | |
2059 | * The M29EW devices seem to report the CFI information wrong | |
2060 | * when it's in 8 bit mode. | |
2061 | * There's an app note from Numonyx on this issue. | |
2062 | * So adjust the buffer size for M29EW while operating in 8-bit mode | |
2063 | */ | |
2064 | if (((qry->max_buf_write_size) > 0x8) && | |
2065 | (info->device_id == 0x7E) && | |
2066 | (info->device_id2 == 0x2201 || | |
2067 | info->device_id2 == 0x2301 || | |
2068 | info->device_id2 == 0x2801 || | |
2069 | info->device_id2 == 0x4801)) { | |
2070 | debug("Adjusted buffer size on Numonyx flash" | |
2071 | " M29EW family in 8 bit mode\n"); | |
2072 | qry->max_buf_write_size = 0x8; | |
2073 | } | |
2074 | } | |
2075 | ||
5653fc33 WD |
2076 | /* |
2077 | * The following code cannot be run from FLASH! | |
2078 | * | |
2079 | */ | |
34bbb8fb | 2080 | ulong flash_get_size (phys_addr_t base, int banknum) |
5653fc33 | 2081 | { |
bf9e3b38 | 2082 | flash_info_t *info = &flash_info[banknum]; |
5653fc33 WD |
2083 | int i, j; |
2084 | flash_sect_t sect_cnt; | |
09ce9921 | 2085 | phys_addr_t sector; |
5653fc33 WD |
2086 | unsigned long tmp; |
2087 | int size_ratio; | |
2088 | uchar num_erase_regions; | |
bf9e3b38 WD |
2089 | int erase_region_size; |
2090 | int erase_region_count; | |
e23741f4 | 2091 | struct cfi_qry qry; |
34bbb8fb | 2092 | unsigned long max_size; |
260421a2 | 2093 | |
f979690e KG |
2094 | memset(&qry, 0, sizeof(qry)); |
2095 | ||
260421a2 SR |
2096 | info->ext_addr = 0; |
2097 | info->cfi_version = 0; | |
6d0f6bcf | 2098 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
2662b40c SR |
2099 | info->legacy_unlock = 0; |
2100 | #endif | |
5653fc33 | 2101 | |
09ce9921 | 2102 | info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); |
5653fc33 | 2103 | |
e23741f4 HS |
2104 | if (flash_detect_cfi (info, &qry)) { |
2105 | info->vendor = le16_to_cpu(qry.p_id); | |
239cb9d9 | 2106 | info->ext_addr = le16_to_cpu(qry.p_adr) * 2; |
2107 | debug("extended address is 0x%x\n", info->ext_addr); | |
e23741f4 HS |
2108 | num_erase_regions = qry.num_erase_regions; |
2109 | ||
260421a2 SR |
2110 | if (info->ext_addr) { |
2111 | info->cfi_version = (ushort) flash_read_uchar (info, | |
239cb9d9 | 2112 | info->ext_addr + 6) << 8; |
260421a2 | 2113 | info->cfi_version |= (ushort) flash_read_uchar (info, |
239cb9d9 | 2114 | info->ext_addr + 8); |
260421a2 | 2115 | } |
0ddf06dd | 2116 | |
bf9e3b38 | 2117 | #ifdef DEBUG |
e23741f4 | 2118 | flash_printqry (&qry); |
bf9e3b38 | 2119 | #endif |
0ddf06dd | 2120 | |
bf9e3b38 | 2121 | switch (info->vendor) { |
9c048b52 | 2122 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
5653fc33 WD |
2123 | case CFI_CMDSET_INTEL_STANDARD: |
2124 | case CFI_CMDSET_INTEL_EXTENDED: | |
0ddf06dd | 2125 | cmdset_intel_init(info, &qry); |
5653fc33 WD |
2126 | break; |
2127 | case CFI_CMDSET_AMD_STANDARD: | |
2128 | case CFI_CMDSET_AMD_EXTENDED: | |
0ddf06dd | 2129 | cmdset_amd_init(info, &qry); |
5653fc33 | 2130 | break; |
0ddf06dd HS |
2131 | default: |
2132 | printf("CFI: Unknown command set 0x%x\n", | |
2133 | info->vendor); | |
2134 | /* | |
2135 | * Unfortunately, this means we don't know how | |
2136 | * to get the chip back to Read mode. Might | |
2137 | * as well try an Intel-style reset... | |
2138 | */ | |
2139 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
2140 | return 0; | |
5653fc33 | 2141 | } |
cd37d9e6 | 2142 | |
467bcee1 HS |
2143 | /* Do manufacturer-specific fixups */ |
2144 | switch (info->manufacturer_id) { | |
2c9f48af MS |
2145 | case 0x0001: /* AMD */ |
2146 | case 0x0037: /* AMIC */ | |
467bcee1 HS |
2147 | flash_fixup_amd(info, &qry); |
2148 | break; | |
2149 | case 0x001f: | |
2150 | flash_fixup_atmel(info, &qry); | |
2151 | break; | |
e8eac437 RR |
2152 | case 0x0020: |
2153 | flash_fixup_stm(info, &qry); | |
2154 | break; | |
07b2c5c0 AD |
2155 | case 0x00bf: /* SST */ |
2156 | flash_fixup_sst(info, &qry); | |
2157 | break; | |
c502321c JT |
2158 | case 0x0089: /* Numonyx */ |
2159 | flash_fixup_num(info, &qry); | |
2160 | break; | |
467bcee1 HS |
2161 | } |
2162 | ||
bf9e3b38 | 2163 | debug ("manufacturer is %d\n", info->vendor); |
260421a2 SR |
2164 | debug ("manufacturer id is 0x%x\n", info->manufacturer_id); |
2165 | debug ("device id is 0x%x\n", info->device_id); | |
2166 | debug ("device id2 is 0x%x\n", info->device_id2); | |
2167 | debug ("cfi version is 0x%04x\n", info->cfi_version); | |
239cb9d9 | 2168 | debug("port width: %d, chipwidth: %d, interface: %d\n", |
2169 | info->portwidth, info->chipwidth, info->interface); | |
260421a2 | 2170 | |
5653fc33 | 2171 | size_ratio = info->portwidth / info->chipwidth; |
bf9e3b38 WD |
2172 | /* if the chip is x8/x16 reduce the ratio by half */ |
2173 | if ((info->interface == FLASH_CFI_X8X16) | |
2174 | && (info->chipwidth == FLASH_CFI_BY8)) { | |
2175 | size_ratio >>= 1; | |
2176 | } | |
bf9e3b38 WD |
2177 | debug ("size_ratio %d port %d bits chip %d bits\n", |
2178 | size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
2179 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
ec50a8e3 IY |
2180 | info->size = 1 << qry.dev_size; |
2181 | /* multiply the size by the number of chips */ | |
2182 | info->size *= size_ratio; | |
34bbb8fb | 2183 | max_size = cfi_flash_bank_size(banknum); |
ec50a8e3 IY |
2184 | if (max_size && (info->size > max_size)) { |
2185 | debug("[truncated from %ldMiB]", info->size >> 20); | |
2186 | info->size = max_size; | |
2187 | } | |
bf9e3b38 | 2188 | debug ("found %d erase regions\n", num_erase_regions); |
5653fc33 WD |
2189 | sect_cnt = 0; |
2190 | sector = base; | |
bf9e3b38 WD |
2191 | for (i = 0; i < num_erase_regions; i++) { |
2192 | if (i > NUM_ERASE_REGIONS) { | |
028ab6b5 WD |
2193 | printf ("%d erase regions found, only %d used\n", |
2194 | num_erase_regions, NUM_ERASE_REGIONS); | |
5653fc33 WD |
2195 | break; |
2196 | } | |
e23741f4 | 2197 | |
0ddf06dd HS |
2198 | tmp = le32_to_cpu(qry.erase_region_info[i]); |
2199 | debug("erase region %u: 0x%08lx\n", i, tmp); | |
e23741f4 HS |
2200 | |
2201 | erase_region_count = (tmp & 0xffff) + 1; | |
2202 | tmp >>= 16; | |
bf9e3b38 WD |
2203 | erase_region_size = |
2204 | (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; | |
4c0d4c3b | 2205 | debug ("erase_region_count = %d erase_region_size = %d\n", |
028ab6b5 | 2206 | erase_region_count, erase_region_size); |
bf9e3b38 | 2207 | for (j = 0; j < erase_region_count; j++) { |
ec50a8e3 IY |
2208 | if (sector - base >= info->size) |
2209 | break; | |
6d0f6bcf | 2210 | if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { |
81b20ccc MS |
2211 | printf("ERROR: too many flash sectors\n"); |
2212 | break; | |
2213 | } | |
09ce9921 BB |
2214 | info->start[sect_cnt] = |
2215 | (ulong)map_physmem(sector, | |
2216 | info->portwidth, | |
2217 | MAP_NOCACHE); | |
5653fc33 | 2218 | sector += (erase_region_size * size_ratio); |
a1191902 WD |
2219 | |
2220 | /* | |
7e5b9b47 HS |
2221 | * Only read protection status from |
2222 | * supported devices (intel...) | |
a1191902 WD |
2223 | */ |
2224 | switch (info->vendor) { | |
9c048b52 | 2225 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
a1191902 WD |
2226 | case CFI_CMDSET_INTEL_EXTENDED: |
2227 | case CFI_CMDSET_INTEL_STANDARD: | |
df4e813b SR |
2228 | /* |
2229 | * Set flash to read-id mode. Otherwise | |
2230 | * reading protected status is not | |
2231 | * guaranteed. | |
2232 | */ | |
2233 | flash_write_cmd(info, sect_cnt, 0, | |
2234 | FLASH_CMD_READ_ID); | |
a1191902 WD |
2235 | info->protect[sect_cnt] = |
2236 | flash_isset (info, sect_cnt, | |
2237 | FLASH_OFFSET_PROTECT, | |
2238 | FLASH_STATUS_PROTECT); | |
2239 | break; | |
03deff43 SR |
2240 | case CFI_CMDSET_AMD_EXTENDED: |
2241 | case CFI_CMDSET_AMD_STANDARD: | |
ac6b9115 | 2242 | if (!info->legacy_unlock) { |
03deff43 SR |
2243 | /* default: not protected */ |
2244 | info->protect[sect_cnt] = 0; | |
2245 | break; | |
2246 | } | |
2247 | ||
2248 | /* Read protection (PPB) from sector */ | |
2249 | flash_write_cmd(info, 0, 0, | |
2250 | info->cmd_reset); | |
2251 | flash_unlock_seq(info, 0); | |
2252 | flash_write_cmd(info, 0, | |
2253 | info->addr_unlock1, | |
2254 | FLASH_CMD_READ_ID); | |
2255 | info->protect[sect_cnt] = | |
2256 | flash_isset( | |
2257 | info, sect_cnt, | |
2258 | FLASH_OFFSET_PROTECT, | |
2259 | FLASH_STATUS_PROTECT); | |
2260 | break; | |
a1191902 | 2261 | default: |
7e5b9b47 HS |
2262 | /* default: not protected */ |
2263 | info->protect[sect_cnt] = 0; | |
a1191902 WD |
2264 | } |
2265 | ||
5653fc33 WD |
2266 | sect_cnt++; |
2267 | } | |
2268 | } | |
2269 | ||
2270 | info->sector_count = sect_cnt; | |
e23741f4 HS |
2271 | info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); |
2272 | tmp = 1 << qry.block_erase_timeout_typ; | |
7e5b9b47 | 2273 | info->erase_blk_tout = tmp * |
e23741f4 HS |
2274 | (1 << qry.block_erase_timeout_max); |
2275 | tmp = (1 << qry.buf_write_timeout_typ) * | |
2276 | (1 << qry.buf_write_timeout_max); | |
2277 | ||
7e5b9b47 | 2278 | /* round up when converting to ms */ |
e23741f4 HS |
2279 | info->buffer_write_tout = (tmp + 999) / 1000; |
2280 | tmp = (1 << qry.word_write_timeout_typ) * | |
2281 | (1 << qry.word_write_timeout_max); | |
7e5b9b47 | 2282 | /* round up when converting to ms */ |
e23741f4 | 2283 | info->write_tout = (tmp + 999) / 1000; |
5653fc33 | 2284 | info->flash_id = FLASH_MAN_CFI; |
7e5b9b47 HS |
2285 | if ((info->interface == FLASH_CFI_X8X16) && |
2286 | (info->chipwidth == FLASH_CFI_BY8)) { | |
2287 | /* XXX - Need to test on x8/x16 in parallel. */ | |
2288 | info->portwidth >>= 1; | |
855a496f | 2289 | } |
2215987e MF |
2290 | |
2291 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
5653fc33 WD |
2292 | } |
2293 | ||
bf9e3b38 | 2294 | return (info->size); |
5653fc33 WD |
2295 | } |
2296 | ||
4ffeab2c | 2297 | #ifdef CONFIG_FLASH_CFI_MTD |
6ea808ef PZ |
2298 | void flash_set_verbose(uint v) |
2299 | { | |
2300 | flash_verbose = v; | |
2301 | } | |
4ffeab2c | 2302 | #endif |
6ea808ef | 2303 | |
6f726f95 SR |
2304 | static void cfi_flash_set_config_reg(u32 base, u16 val) |
2305 | { | |
2306 | #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS | |
2307 | /* | |
2308 | * Only set this config register if really defined | |
2309 | * to a valid value (0xffff is invalid) | |
2310 | */ | |
2311 | if (val == 0xffff) | |
2312 | return; | |
2313 | ||
2314 | /* | |
2315 | * Set configuration register. Data is "encrypted" in the 16 lower | |
2316 | * address bits. | |
2317 | */ | |
2318 | flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); | |
2319 | flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); | |
2320 | ||
2321 | /* | |
2322 | * Finally issue reset-command to bring device back to | |
2323 | * read-array mode | |
2324 | */ | |
2325 | flash_write16(FLASH_CMD_RESET, (void *)base); | |
2326 | #endif | |
2327 | } | |
2328 | ||
5653fc33 WD |
2329 | /*----------------------------------------------------------------------- |
2330 | */ | |
6ee1416e HS |
2331 | |
2332 | void flash_protect_default(void) | |
2333 | { | |
2c51983b PT |
2334 | #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) |
2335 | int i; | |
2336 | struct apl_s { | |
2337 | ulong start; | |
2338 | ulong size; | |
2339 | } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; | |
2340 | #endif | |
2341 | ||
6ee1416e HS |
2342 | /* Monitor protection ON by default */ |
2343 | #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ | |
2344 | (!defined(CONFIG_MONITOR_IS_IN_RAM)) | |
2345 | flash_protect(FLAG_PROTECT_SET, | |
2346 | CONFIG_SYS_MONITOR_BASE, | |
2347 | CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, | |
2348 | flash_get_info(CONFIG_SYS_MONITOR_BASE)); | |
2349 | #endif | |
2350 | ||
2351 | /* Environment protection ON by default */ | |
2352 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
2353 | flash_protect(FLAG_PROTECT_SET, | |
2354 | CONFIG_ENV_ADDR, | |
2355 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, | |
2356 | flash_get_info(CONFIG_ENV_ADDR)); | |
2357 | #endif | |
2358 | ||
2359 | /* Redundant environment protection ON by default */ | |
2360 | #ifdef CONFIG_ENV_ADDR_REDUND | |
2361 | flash_protect(FLAG_PROTECT_SET, | |
2362 | CONFIG_ENV_ADDR_REDUND, | |
2363 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, | |
2364 | flash_get_info(CONFIG_ENV_ADDR_REDUND)); | |
2365 | #endif | |
2366 | ||
2367 | #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) | |
2368 | for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) { | |
31d34143 | 2369 | debug("autoprotecting from %08lx to %08lx\n", |
6ee1416e HS |
2370 | apl[i].start, apl[i].start + apl[i].size - 1); |
2371 | flash_protect(FLAG_PROTECT_SET, | |
2372 | apl[i].start, | |
2373 | apl[i].start + apl[i].size - 1, | |
2374 | flash_get_info(apl[i].start)); | |
2375 | } | |
2376 | #endif | |
2377 | } | |
2378 | ||
be60a902 | 2379 | unsigned long flash_init (void) |
5653fc33 | 2380 | { |
be60a902 HS |
2381 | unsigned long size = 0; |
2382 | int i; | |
5653fc33 | 2383 | |
6d0f6bcf | 2384 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
3a3baf3e ES |
2385 | /* read environment from EEPROM */ |
2386 | char s[64]; | |
cdb74977 | 2387 | getenv_f("unlock", s, sizeof(s)); |
81b20ccc | 2388 | #endif |
5653fc33 | 2389 | |
be60a902 | 2390 | /* Init: no FLASHes known */ |
6d0f6bcf | 2391 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
be60a902 | 2392 | flash_info[i].flash_id = FLASH_UNKNOWN; |
5653fc33 | 2393 | |
6f726f95 SR |
2394 | /* Optionally write flash configuration register */ |
2395 | cfi_flash_set_config_reg(cfi_flash_bank_addr(i), | |
2396 | cfi_flash_config_reg(i)); | |
2397 | ||
b00e19cc | 2398 | if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) |
34bbb8fb | 2399 | flash_get_size(cfi_flash_bank_addr(i), i); |
be60a902 HS |
2400 | size += flash_info[i].size; |
2401 | if (flash_info[i].flash_id == FLASH_UNKNOWN) { | |
6d0f6bcf | 2402 | #ifndef CONFIG_SYS_FLASH_QUIET_TEST |
eddf52b5 | 2403 | printf ("## Unknown flash on Bank %d " |
be60a902 HS |
2404 | "- Size = 0x%08lx = %ld MB\n", |
2405 | i+1, flash_info[i].size, | |
0e3fa01a | 2406 | flash_info[i].size >> 20); |
6d0f6bcf | 2407 | #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ |
be60a902 | 2408 | } |
6d0f6bcf | 2409 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
be60a902 HS |
2410 | else if ((s != NULL) && (strcmp(s, "yes") == 0)) { |
2411 | /* | |
2412 | * Only the U-Boot image and it's environment | |
2413 | * is protected, all other sectors are | |
2414 | * unprotected (unlocked) if flash hardware | |
6d0f6bcf | 2415 | * protection is used (CONFIG_SYS_FLASH_PROTECTION) |
be60a902 HS |
2416 | * and the environment variable "unlock" is |
2417 | * set to "yes". | |
2418 | */ | |
2419 | if (flash_info[i].legacy_unlock) { | |
2420 | int k; | |
5653fc33 | 2421 | |
be60a902 HS |
2422 | /* |
2423 | * Disable legacy_unlock temporarily, | |
2424 | * since flash_real_protect would | |
2425 | * relock all other sectors again | |
2426 | * otherwise. | |
2427 | */ | |
2428 | flash_info[i].legacy_unlock = 0; | |
5653fc33 | 2429 | |
be60a902 HS |
2430 | /* |
2431 | * Legacy unlocking (e.g. Intel J3) -> | |
2432 | * unlock only one sector. This will | |
2433 | * unlock all sectors. | |
2434 | */ | |
2435 | flash_real_protect (&flash_info[i], 0, 0); | |
5653fc33 | 2436 | |
be60a902 | 2437 | flash_info[i].legacy_unlock = 1; |
5653fc33 | 2438 | |
be60a902 HS |
2439 | /* |
2440 | * Manually mark other sectors as | |
2441 | * unlocked (unprotected) | |
2442 | */ | |
2443 | for (k = 1; k < flash_info[i].sector_count; k++) | |
2444 | flash_info[i].protect[k] = 0; | |
2445 | } else { | |
2446 | /* | |
2447 | * No legancy unlocking -> unlock all sectors | |
2448 | */ | |
2449 | flash_protect (FLAG_PROTECT_CLEAR, | |
2450 | flash_info[i].start[0], | |
2451 | flash_info[i].start[0] | |
2452 | + flash_info[i].size - 1, | |
2453 | &flash_info[i]); | |
79b4cda0 | 2454 | } |
79b4cda0 | 2455 | } |
6d0f6bcf | 2456 | #endif /* CONFIG_SYS_FLASH_PROTECTION */ |
be60a902 | 2457 | } |
79b4cda0 | 2458 | |
6ee1416e | 2459 | flash_protect_default(); |
91809ed5 PZ |
2460 | #ifdef CONFIG_FLASH_CFI_MTD |
2461 | cfi_mtd_init(); | |
2462 | #endif | |
2463 | ||
be60a902 | 2464 | return (size); |
5653fc33 | 2465 | } |