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5653fc33 | 1 | /* |
bf9e3b38 | 2 | * (C) Copyright 2002-2004 |
5653fc33 WD |
3 | * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
4 | * | |
5 | * Copyright (C) 2003 Arabella Software Ltd. | |
6 | * Yuli Barcohen <yuli@arabellasw.com> | |
5653fc33 | 7 | * |
bf9e3b38 WD |
8 | * Copyright (C) 2004 |
9 | * Ed Okerson | |
260421a2 SR |
10 | * |
11 | * Copyright (C) 2006 | |
12 | * Tolunay Orkun <listmember@orkun.us> | |
bf9e3b38 | 13 | * |
5653fc33 WD |
14 | * See file CREDITS for list of people who contributed to this |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 | * MA 02111-1307 USA | |
31 | * | |
5653fc33 WD |
32 | */ |
33 | ||
34 | /* The DEBUG define must be before common to enable debugging */ | |
2d1a537d WD |
35 | /* #define DEBUG */ |
36 | ||
5653fc33 WD |
37 | #include <common.h> |
38 | #include <asm/processor.h> | |
3a197b2f | 39 | #include <asm/io.h> |
4c0d4c3b | 40 | #include <asm/byteorder.h> |
2a8af187 | 41 | #include <environment.h> |
fa36ae79 | 42 | #include <mtd/cfi_flash.h> |
028ab6b5 | 43 | |
5653fc33 | 44 | /* |
7e5b9b47 HS |
45 | * This file implements a Common Flash Interface (CFI) driver for |
46 | * U-Boot. | |
47 | * | |
48 | * The width of the port and the width of the chips are determined at | |
49 | * initialization. These widths are used to calculate the address for | |
50 | * access CFI data structures. | |
5653fc33 WD |
51 | * |
52 | * References | |
53 | * JEDEC Standard JESD68 - Common Flash Interface (CFI) | |
54 | * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes | |
55 | * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets | |
56 | * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet | |
260421a2 SR |
57 | * AMD CFI Specification, Release 2.0 December 1, 2001 |
58 | * AMD/Spansion Application Note: Migration from Single-byte to Three-byte | |
59 | * Device IDs, Publication Number 25538 Revision A, November 8, 2001 | |
5653fc33 | 60 | * |
6d0f6bcf | 61 | * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between |
d0b6e140 | 62 | * reading and writing ... (yes there is such a Hardware). |
5653fc33 WD |
63 | */ |
64 | ||
7e5b9b47 | 65 | static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; |
6ea808ef | 66 | static uint flash_verbose = 1; |
92eb729b | 67 | |
2a112b23 WD |
68 | flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ |
69 | ||
79b4cda0 SR |
70 | /* |
71 | * Check if chip width is defined. If not, start detecting with 8bit. | |
72 | */ | |
6d0f6bcf JCPV |
73 | #ifndef CONFIG_SYS_FLASH_CFI_WIDTH |
74 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
79b4cda0 SR |
75 | #endif |
76 | ||
6f726f95 SR |
77 | /* |
78 | * 0xffff is an undefined value for the configuration register. When | |
79 | * this value is returned, the configuration register shall not be | |
80 | * written at all (default mode). | |
81 | */ | |
82 | static u16 cfi_flash_config_reg(int i) | |
83 | { | |
84 | #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS | |
85 | return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; | |
86 | #else | |
87 | return 0xffff; | |
88 | #endif | |
89 | } | |
90 | ||
ca5def3f SR |
91 | #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) |
92 | int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; | |
93 | #endif | |
94 | ||
b00e19cc SR |
95 | static phys_addr_t __cfi_flash_bank_addr(int i) |
96 | { | |
97 | return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; | |
98 | } | |
99 | phys_addr_t cfi_flash_bank_addr(int i) | |
100 | __attribute__((weak, alias("__cfi_flash_bank_addr"))); | |
101 | ||
ec50a8e3 IY |
102 | static unsigned long __cfi_flash_bank_size(int i) |
103 | { | |
104 | #ifdef CONFIG_SYS_FLASH_BANKS_SIZES | |
105 | return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; | |
106 | #else | |
107 | return 0; | |
108 | #endif | |
109 | } | |
110 | unsigned long cfi_flash_bank_size(int i) | |
111 | __attribute__((weak, alias("__cfi_flash_bank_size"))); | |
112 | ||
45aa5a7f | 113 | static void __flash_write8(u8 value, void *addr) |
cdbaefb5 HS |
114 | { |
115 | __raw_writeb(value, addr); | |
116 | } | |
117 | ||
45aa5a7f | 118 | static void __flash_write16(u16 value, void *addr) |
cdbaefb5 HS |
119 | { |
120 | __raw_writew(value, addr); | |
121 | } | |
122 | ||
45aa5a7f | 123 | static void __flash_write32(u32 value, void *addr) |
cdbaefb5 HS |
124 | { |
125 | __raw_writel(value, addr); | |
126 | } | |
127 | ||
45aa5a7f | 128 | static void __flash_write64(u64 value, void *addr) |
cdbaefb5 HS |
129 | { |
130 | /* No architectures currently implement __raw_writeq() */ | |
131 | *(volatile u64 *)addr = value; | |
132 | } | |
133 | ||
45aa5a7f | 134 | static u8 __flash_read8(void *addr) |
cdbaefb5 HS |
135 | { |
136 | return __raw_readb(addr); | |
137 | } | |
138 | ||
45aa5a7f | 139 | static u16 __flash_read16(void *addr) |
cdbaefb5 HS |
140 | { |
141 | return __raw_readw(addr); | |
142 | } | |
143 | ||
45aa5a7f | 144 | static u32 __flash_read32(void *addr) |
cdbaefb5 HS |
145 | { |
146 | return __raw_readl(addr); | |
147 | } | |
148 | ||
97bf85d7 | 149 | static u64 __flash_read64(void *addr) |
cdbaefb5 HS |
150 | { |
151 | /* No architectures currently implement __raw_readq() */ | |
152 | return *(volatile u64 *)addr; | |
153 | } | |
154 | ||
45aa5a7f SR |
155 | #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
156 | void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8"))); | |
157 | void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16"))); | |
158 | void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32"))); | |
159 | void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64"))); | |
160 | u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8"))); | |
161 | u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16"))); | |
162 | u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32"))); | |
97bf85d7 | 163 | u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); |
45aa5a7f SR |
164 | #else |
165 | #define flash_write8 __flash_write8 | |
166 | #define flash_write16 __flash_write16 | |
167 | #define flash_write32 __flash_write32 | |
168 | #define flash_write64 __flash_write64 | |
169 | #define flash_read8 __flash_read8 | |
170 | #define flash_read16 __flash_read16 | |
171 | #define flash_read32 __flash_read32 | |
172 | #define flash_read64 __flash_read64 | |
173 | #endif | |
97bf85d7 | 174 | |
5653fc33 | 175 | /*----------------------------------------------------------------------- |
5653fc33 | 176 | */ |
6d0f6bcf | 177 | #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) |
4f975678 | 178 | flash_info_t *flash_get_info(ulong base) |
be60a902 HS |
179 | { |
180 | int i; | |
cba34aaf | 181 | flash_info_t *info = NULL; |
5653fc33 | 182 | |
6d0f6bcf | 183 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { |
be60a902 HS |
184 | info = & flash_info[i]; |
185 | if (info->size && info->start[0] <= base && | |
186 | base <= info->start[0] + info->size - 1) | |
187 | break; | |
188 | } | |
5653fc33 | 189 | |
cba34aaf | 190 | return info; |
be60a902 | 191 | } |
5653fc33 WD |
192 | #endif |
193 | ||
12d30aa7 HS |
194 | unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) |
195 | { | |
196 | if (sect != (info->sector_count - 1)) | |
197 | return info->start[sect + 1] - info->start[sect]; | |
198 | else | |
199 | return info->start[0] + info->size - info->start[sect]; | |
200 | } | |
201 | ||
bf9e3b38 WD |
202 | /*----------------------------------------------------------------------- |
203 | * create an address based on the offset and the port width | |
204 | */ | |
12d30aa7 HS |
205 | static inline void * |
206 | flash_map (flash_info_t * info, flash_sect_t sect, uint offset) | |
bf9e3b38 | 207 | { |
12d30aa7 HS |
208 | unsigned int byte_offset = offset * info->portwidth; |
209 | ||
09ce9921 | 210 | return (void *)(info->start[sect] + byte_offset); |
12d30aa7 HS |
211 | } |
212 | ||
213 | static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, | |
214 | unsigned int offset, void *addr) | |
215 | { | |
bf9e3b38 WD |
216 | } |
217 | ||
be60a902 HS |
218 | /*----------------------------------------------------------------------- |
219 | * make a proper sized command based on the port and chip widths | |
220 | */ | |
7288f972 | 221 | static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) |
be60a902 HS |
222 | { |
223 | int i; | |
93c56f21 VL |
224 | int cword_offset; |
225 | int cp_offset; | |
6d0f6bcf | 226 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
340ccb26 SS |
227 | u32 cmd_le = cpu_to_le32(cmd); |
228 | #endif | |
93c56f21 | 229 | uchar val; |
be60a902 HS |
230 | uchar *cp = (uchar *) cmdbuf; |
231 | ||
93c56f21 VL |
232 | for (i = info->portwidth; i > 0; i--){ |
233 | cword_offset = (info->portwidth-i)%info->chipwidth; | |
6d0f6bcf | 234 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
93c56f21 | 235 | cp_offset = info->portwidth - i; |
340ccb26 | 236 | val = *((uchar*)&cmd_le + cword_offset); |
be60a902 | 237 | #else |
93c56f21 | 238 | cp_offset = i - 1; |
7288f972 | 239 | val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1); |
be60a902 | 240 | #endif |
7288f972 | 241 | cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; |
93c56f21 | 242 | } |
be60a902 HS |
243 | } |
244 | ||
5653fc33 | 245 | #ifdef DEBUG |
bf9e3b38 WD |
246 | /*----------------------------------------------------------------------- |
247 | * Debug support | |
248 | */ | |
3055793b | 249 | static void print_longlong (char *str, unsigned long long data) |
5653fc33 WD |
250 | { |
251 | int i; | |
252 | char *cp; | |
bf9e3b38 | 253 | |
657f2062 | 254 | cp = (char *) &data; |
bf9e3b38 WD |
255 | for (i = 0; i < 8; i++) |
256 | sprintf (&str[i * 2], "%2.2x", *cp++); | |
257 | } | |
be60a902 | 258 | |
e23741f4 | 259 | static void flash_printqry (struct cfi_qry *qry) |
bf9e3b38 | 260 | { |
e23741f4 | 261 | u8 *p = (u8 *)qry; |
bf9e3b38 WD |
262 | int x, y; |
263 | ||
e23741f4 HS |
264 | for (x = 0; x < sizeof(struct cfi_qry); x += 16) { |
265 | debug("%02x : ", x); | |
266 | for (y = 0; y < 16; y++) | |
267 | debug("%2.2x ", p[x + y]); | |
268 | debug(" "); | |
bf9e3b38 | 269 | for (y = 0; y < 16; y++) { |
e23741f4 HS |
270 | unsigned char c = p[x + y]; |
271 | if (c >= 0x20 && c <= 0x7e) | |
272 | debug("%c", c); | |
273 | else | |
274 | debug("."); | |
bf9e3b38 | 275 | } |
e23741f4 | 276 | debug("\n"); |
bf9e3b38 | 277 | } |
5653fc33 WD |
278 | } |
279 | #endif | |
280 | ||
281 | ||
5653fc33 WD |
282 | /*----------------------------------------------------------------------- |
283 | * read a character at a port width address | |
284 | */ | |
3055793b | 285 | static inline uchar flash_read_uchar (flash_info_t * info, uint offset) |
5653fc33 WD |
286 | { |
287 | uchar *cp; | |
12d30aa7 | 288 | uchar retval; |
bf9e3b38 | 289 | |
12d30aa7 | 290 | cp = flash_map (info, 0, offset); |
6d0f6bcf | 291 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
12d30aa7 | 292 | retval = flash_read8(cp); |
bf9e3b38 | 293 | #else |
12d30aa7 | 294 | retval = flash_read8(cp + info->portwidth - 1); |
bf9e3b38 | 295 | #endif |
12d30aa7 HS |
296 | flash_unmap (info, 0, offset, cp); |
297 | return retval; | |
5653fc33 WD |
298 | } |
299 | ||
90447ecb TK |
300 | /*----------------------------------------------------------------------- |
301 | * read a word at a port width address, assume 16bit bus | |
302 | */ | |
303 | static inline ushort flash_read_word (flash_info_t * info, uint offset) | |
304 | { | |
305 | ushort *addr, retval; | |
306 | ||
307 | addr = flash_map (info, 0, offset); | |
308 | retval = flash_read16 (addr); | |
309 | flash_unmap (info, 0, offset, addr); | |
310 | return retval; | |
311 | } | |
312 | ||
313 | ||
5653fc33 | 314 | /*----------------------------------------------------------------------- |
260421a2 | 315 | * read a long word by picking the least significant byte of each maximum |
5653fc33 WD |
316 | * port size word. Swap for ppc format. |
317 | */ | |
3055793b HS |
318 | static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, |
319 | uint offset) | |
5653fc33 | 320 | { |
bf9e3b38 WD |
321 | uchar *addr; |
322 | ulong retval; | |
323 | ||
324 | #ifdef DEBUG | |
325 | int x; | |
326 | #endif | |
12d30aa7 | 327 | addr = flash_map (info, sect, offset); |
5653fc33 | 328 | |
bf9e3b38 WD |
329 | #ifdef DEBUG |
330 | debug ("long addr is at %p info->portwidth = %d\n", addr, | |
331 | info->portwidth); | |
332 | for (x = 0; x < 4 * info->portwidth; x++) { | |
12d30aa7 | 333 | debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); |
bf9e3b38 WD |
334 | } |
335 | #endif | |
6d0f6bcf | 336 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
12d30aa7 HS |
337 | retval = ((flash_read8(addr) << 16) | |
338 | (flash_read8(addr + info->portwidth) << 24) | | |
339 | (flash_read8(addr + 2 * info->portwidth)) | | |
340 | (flash_read8(addr + 3 * info->portwidth) << 8)); | |
bf9e3b38 | 341 | #else |
12d30aa7 HS |
342 | retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | |
343 | (flash_read8(addr + info->portwidth - 1) << 16) | | |
344 | (flash_read8(addr + 4 * info->portwidth - 1) << 8) | | |
345 | (flash_read8(addr + 3 * info->portwidth - 1))); | |
bf9e3b38 | 346 | #endif |
12d30aa7 HS |
347 | flash_unmap(info, sect, offset, addr); |
348 | ||
bf9e3b38 | 349 | return retval; |
5653fc33 WD |
350 | } |
351 | ||
be60a902 HS |
352 | /* |
353 | * Write a proper sized command to the correct address | |
81b20ccc | 354 | */ |
fa36ae79 SR |
355 | void flash_write_cmd (flash_info_t * info, flash_sect_t sect, |
356 | uint offset, u32 cmd) | |
81b20ccc | 357 | { |
7e5b9b47 | 358 | |
cdbaefb5 | 359 | void *addr; |
be60a902 | 360 | cfiword_t cword; |
81b20ccc | 361 | |
12d30aa7 | 362 | addr = flash_map (info, sect, offset); |
be60a902 HS |
363 | flash_make_cmd (info, cmd, &cword); |
364 | switch (info->portwidth) { | |
365 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 366 | debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, |
be60a902 | 367 | cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
cdbaefb5 | 368 | flash_write8(cword.c, addr); |
be60a902 HS |
369 | break; |
370 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 371 | debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, |
be60a902 HS |
372 | cmd, cword.w, |
373 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
cdbaefb5 | 374 | flash_write16(cword.w, addr); |
be60a902 HS |
375 | break; |
376 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 377 | debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, |
be60a902 HS |
378 | cmd, cword.l, |
379 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
cdbaefb5 | 380 | flash_write32(cword.l, addr); |
be60a902 HS |
381 | break; |
382 | case FLASH_CFI_64BIT: | |
383 | #ifdef DEBUG | |
384 | { | |
385 | char str[20]; | |
7e5b9b47 | 386 | |
be60a902 HS |
387 | print_longlong (str, cword.ll); |
388 | ||
389 | debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", | |
cdbaefb5 | 390 | addr, cmd, str, |
be60a902 | 391 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
81b20ccc | 392 | } |
be60a902 | 393 | #endif |
cdbaefb5 | 394 | flash_write64(cword.ll, addr); |
be60a902 | 395 | break; |
81b20ccc | 396 | } |
be60a902 HS |
397 | |
398 | /* Ensure all the instructions are fully finished */ | |
399 | sync(); | |
12d30aa7 HS |
400 | |
401 | flash_unmap(info, sect, offset, addr); | |
81b20ccc | 402 | } |
be60a902 HS |
403 | |
404 | static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) | |
81b20ccc | 405 | { |
be60a902 HS |
406 | flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); |
407 | flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); | |
81b20ccc | 408 | } |
81b20ccc | 409 | |
5653fc33 WD |
410 | /*----------------------------------------------------------------------- |
411 | */ | |
be60a902 HS |
412 | static int flash_isequal (flash_info_t * info, flash_sect_t sect, |
413 | uint offset, uchar cmd) | |
5653fc33 | 414 | { |
cdbaefb5 | 415 | void *addr; |
be60a902 HS |
416 | cfiword_t cword; |
417 | int retval; | |
5653fc33 | 418 | |
12d30aa7 | 419 | addr = flash_map (info, sect, offset); |
be60a902 | 420 | flash_make_cmd (info, cmd, &cword); |
2662b40c | 421 | |
cdbaefb5 | 422 | debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); |
be60a902 HS |
423 | switch (info->portwidth) { |
424 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
425 | debug ("is= %x %x\n", flash_read8(addr), cword.c); |
426 | retval = (flash_read8(addr) == cword.c); | |
be60a902 HS |
427 | break; |
428 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
429 | debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); |
430 | retval = (flash_read16(addr) == cword.w); | |
be60a902 HS |
431 | break; |
432 | case FLASH_CFI_32BIT: | |
52514699 | 433 | debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l); |
cdbaefb5 | 434 | retval = (flash_read32(addr) == cword.l); |
be60a902 HS |
435 | break; |
436 | case FLASH_CFI_64BIT: | |
437 | #ifdef DEBUG | |
438 | { | |
439 | char str1[20]; | |
440 | char str2[20]; | |
81b20ccc | 441 | |
cdbaefb5 | 442 | print_longlong (str1, flash_read64(addr)); |
be60a902 HS |
443 | print_longlong (str2, cword.ll); |
444 | debug ("is= %s %s\n", str1, str2); | |
5653fc33 | 445 | } |
be60a902 | 446 | #endif |
cdbaefb5 | 447 | retval = (flash_read64(addr) == cword.ll); |
be60a902 HS |
448 | break; |
449 | default: | |
450 | retval = 0; | |
451 | break; | |
452 | } | |
12d30aa7 HS |
453 | flash_unmap(info, sect, offset, addr); |
454 | ||
be60a902 HS |
455 | return retval; |
456 | } | |
79b4cda0 | 457 | |
be60a902 HS |
458 | /*----------------------------------------------------------------------- |
459 | */ | |
460 | static int flash_isset (flash_info_t * info, flash_sect_t sect, | |
461 | uint offset, uchar cmd) | |
462 | { | |
cdbaefb5 | 463 | void *addr; |
be60a902 HS |
464 | cfiword_t cword; |
465 | int retval; | |
2662b40c | 466 | |
12d30aa7 | 467 | addr = flash_map (info, sect, offset); |
be60a902 HS |
468 | flash_make_cmd (info, cmd, &cword); |
469 | switch (info->portwidth) { | |
470 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 471 | retval = ((flash_read8(addr) & cword.c) == cword.c); |
be60a902 HS |
472 | break; |
473 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 474 | retval = ((flash_read16(addr) & cword.w) == cword.w); |
be60a902 HS |
475 | break; |
476 | case FLASH_CFI_32BIT: | |
47cc23cb | 477 | retval = ((flash_read32(addr) & cword.l) == cword.l); |
be60a902 HS |
478 | break; |
479 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 480 | retval = ((flash_read64(addr) & cword.ll) == cword.ll); |
be60a902 HS |
481 | break; |
482 | default: | |
483 | retval = 0; | |
484 | break; | |
485 | } | |
12d30aa7 HS |
486 | flash_unmap(info, sect, offset, addr); |
487 | ||
be60a902 HS |
488 | return retval; |
489 | } | |
2662b40c | 490 | |
be60a902 HS |
491 | /*----------------------------------------------------------------------- |
492 | */ | |
493 | static int flash_toggle (flash_info_t * info, flash_sect_t sect, | |
494 | uint offset, uchar cmd) | |
495 | { | |
cdbaefb5 | 496 | void *addr; |
be60a902 HS |
497 | cfiword_t cword; |
498 | int retval; | |
656658dd | 499 | |
12d30aa7 | 500 | addr = flash_map (info, sect, offset); |
be60a902 HS |
501 | flash_make_cmd (info, cmd, &cword); |
502 | switch (info->portwidth) { | |
503 | case FLASH_CFI_8BIT: | |
fb8c061e | 504 | retval = flash_read8(addr) != flash_read8(addr); |
be60a902 HS |
505 | break; |
506 | case FLASH_CFI_16BIT: | |
fb8c061e | 507 | retval = flash_read16(addr) != flash_read16(addr); |
be60a902 HS |
508 | break; |
509 | case FLASH_CFI_32BIT: | |
fb8c061e | 510 | retval = flash_read32(addr) != flash_read32(addr); |
be60a902 HS |
511 | break; |
512 | case FLASH_CFI_64BIT: | |
9abda6ba WD |
513 | retval = ( (flash_read32( addr ) != flash_read32( addr )) || |
514 | (flash_read32(addr+4) != flash_read32(addr+4)) ); | |
be60a902 HS |
515 | break; |
516 | default: | |
517 | retval = 0; | |
518 | break; | |
519 | } | |
12d30aa7 HS |
520 | flash_unmap(info, sect, offset, addr); |
521 | ||
be60a902 | 522 | return retval; |
5653fc33 WD |
523 | } |
524 | ||
be60a902 HS |
525 | /* |
526 | * flash_is_busy - check to see if the flash is busy | |
527 | * | |
528 | * This routine checks the status of the chip and returns true if the | |
529 | * chip is busy. | |
7680c140 | 530 | */ |
be60a902 | 531 | static int flash_is_busy (flash_info_t * info, flash_sect_t sect) |
7680c140 | 532 | { |
be60a902 | 533 | int retval; |
7680c140 | 534 | |
be60a902 | 535 | switch (info->vendor) { |
9c048b52 | 536 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
537 | case CFI_CMDSET_INTEL_STANDARD: |
538 | case CFI_CMDSET_INTEL_EXTENDED: | |
539 | retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); | |
540 | break; | |
541 | case CFI_CMDSET_AMD_STANDARD: | |
542 | case CFI_CMDSET_AMD_EXTENDED: | |
543 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
544 | case CFI_CMDSET_AMD_LEGACY: | |
545 | #endif | |
546 | retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); | |
547 | break; | |
548 | default: | |
549 | retval = 0; | |
7680c140 | 550 | } |
be60a902 HS |
551 | debug ("flash_is_busy: %d\n", retval); |
552 | return retval; | |
7680c140 WD |
553 | } |
554 | ||
5653fc33 | 555 | /*----------------------------------------------------------------------- |
be60a902 HS |
556 | * wait for XSR.7 to be set. Time out with an error if it does not. |
557 | * This routine does not set the flash to read-array mode. | |
5653fc33 | 558 | */ |
be60a902 HS |
559 | static int flash_status_check (flash_info_t * info, flash_sect_t sector, |
560 | ulong tout, char *prompt) | |
5653fc33 | 561 | { |
be60a902 | 562 | ulong start; |
5653fc33 | 563 | |
6d0f6bcf | 564 | #if CONFIG_SYS_HZ != 1000 |
c40c94a3 RA |
565 | if ((ulong)CONFIG_SYS_HZ > 100000) |
566 | tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ | |
567 | else | |
568 | tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); | |
be60a902 | 569 | #endif |
5653fc33 | 570 | |
be60a902 | 571 | /* Wait for command completion */ |
22d6c8fa | 572 | reset_timer(); |
be60a902 HS |
573 | start = get_timer (0); |
574 | while (flash_is_busy (info, sector)) { | |
575 | if (get_timer (start) > tout) { | |
576 | printf ("Flash %s timeout at address %lx data %lx\n", | |
577 | prompt, info->start[sector], | |
578 | flash_read_long (info, sector, 0)); | |
579 | flash_write_cmd (info, sector, 0, info->cmd_reset); | |
580 | return ERR_TIMOUT; | |
5653fc33 | 581 | } |
be60a902 | 582 | udelay (1); /* also triggers watchdog */ |
5653fc33 | 583 | } |
be60a902 HS |
584 | return ERR_OK; |
585 | } | |
5653fc33 | 586 | |
be60a902 HS |
587 | /*----------------------------------------------------------------------- |
588 | * Wait for XSR.7 to be set, if it times out print an error, otherwise | |
589 | * do a full status check. | |
590 | * | |
591 | * This routine sets the flash to read-array mode. | |
592 | */ | |
593 | static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, | |
594 | ulong tout, char *prompt) | |
595 | { | |
596 | int retcode; | |
5653fc33 | 597 | |
be60a902 HS |
598 | retcode = flash_status_check (info, sector, tout, prompt); |
599 | switch (info->vendor) { | |
9c048b52 | 600 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
601 | case CFI_CMDSET_INTEL_EXTENDED: |
602 | case CFI_CMDSET_INTEL_STANDARD: | |
0d01f66d | 603 | if ((retcode != ERR_OK) |
be60a902 HS |
604 | && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { |
605 | retcode = ERR_INVAL; | |
606 | printf ("Flash %s error at address %lx\n", prompt, | |
607 | info->start[sector]); | |
608 | if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | | |
609 | FLASH_STATUS_PSLBS)) { | |
610 | puts ("Command Sequence Error.\n"); | |
611 | } else if (flash_isset (info, sector, 0, | |
612 | FLASH_STATUS_ECLBS)) { | |
613 | puts ("Block Erase Error.\n"); | |
614 | retcode = ERR_NOT_ERASED; | |
615 | } else if (flash_isset (info, sector, 0, | |
616 | FLASH_STATUS_PSLBS)) { | |
617 | puts ("Locking Error\n"); | |
5653fc33 | 618 | } |
be60a902 HS |
619 | if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { |
620 | puts ("Block locked.\n"); | |
621 | retcode = ERR_PROTECTED; | |
622 | } | |
623 | if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) | |
624 | puts ("Vpp Low Error.\n"); | |
5653fc33 | 625 | } |
be60a902 HS |
626 | flash_write_cmd (info, sector, 0, info->cmd_reset); |
627 | break; | |
628 | default: | |
629 | break; | |
5653fc33 | 630 | } |
be60a902 | 631 | return retcode; |
5653fc33 WD |
632 | } |
633 | ||
e5720823 TC |
634 | static int use_flash_status_poll(flash_info_t *info) |
635 | { | |
636 | #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
637 | if (info->vendor == CFI_CMDSET_AMD_EXTENDED || | |
638 | info->vendor == CFI_CMDSET_AMD_STANDARD) | |
639 | return 1; | |
640 | #endif | |
641 | return 0; | |
642 | } | |
643 | ||
644 | static int flash_status_poll(flash_info_t *info, void *src, void *dst, | |
645 | ulong tout, char *prompt) | |
646 | { | |
647 | #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
648 | ulong start; | |
649 | int ready; | |
650 | ||
651 | #if CONFIG_SYS_HZ != 1000 | |
652 | if ((ulong)CONFIG_SYS_HZ > 100000) | |
653 | tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ | |
654 | else | |
655 | tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); | |
656 | #endif | |
657 | ||
658 | /* Wait for command completion */ | |
22d6c8fa | 659 | reset_timer(); |
e5720823 TC |
660 | start = get_timer(0); |
661 | while (1) { | |
662 | switch (info->portwidth) { | |
663 | case FLASH_CFI_8BIT: | |
664 | ready = flash_read8(dst) == flash_read8(src); | |
665 | break; | |
666 | case FLASH_CFI_16BIT: | |
667 | ready = flash_read16(dst) == flash_read16(src); | |
668 | break; | |
669 | case FLASH_CFI_32BIT: | |
670 | ready = flash_read32(dst) == flash_read32(src); | |
671 | break; | |
672 | case FLASH_CFI_64BIT: | |
673 | ready = flash_read64(dst) == flash_read64(src); | |
674 | break; | |
675 | default: | |
676 | ready = 0; | |
677 | break; | |
678 | } | |
679 | if (ready) | |
680 | break; | |
681 | if (get_timer(start) > tout) { | |
682 | printf("Flash %s timeout at address %lx data %lx\n", | |
683 | prompt, (ulong)dst, (ulong)flash_read8(dst)); | |
684 | return ERR_TIMOUT; | |
685 | } | |
686 | udelay(1); /* also triggers watchdog */ | |
687 | } | |
688 | #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ | |
689 | return ERR_OK; | |
690 | } | |
691 | ||
5653fc33 WD |
692 | /*----------------------------------------------------------------------- |
693 | */ | |
be60a902 | 694 | static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) |
5653fc33 | 695 | { |
6d0f6bcf | 696 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
697 | unsigned short w; |
698 | unsigned int l; | |
699 | unsigned long long ll; | |
700 | #endif | |
5653fc33 | 701 | |
be60a902 HS |
702 | switch (info->portwidth) { |
703 | case FLASH_CFI_8BIT: | |
704 | cword->c = c; | |
705 | break; | |
706 | case FLASH_CFI_16BIT: | |
6d0f6bcf | 707 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
708 | w = c; |
709 | w <<= 8; | |
710 | cword->w = (cword->w >> 8) | w; | |
711 | #else | |
712 | cword->w = (cword->w << 8) | c; | |
81b20ccc | 713 | #endif |
be60a902 HS |
714 | break; |
715 | case FLASH_CFI_32BIT: | |
6d0f6bcf | 716 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
717 | l = c; |
718 | l <<= 24; | |
719 | cword->l = (cword->l >> 8) | l; | |
720 | #else | |
721 | cword->l = (cword->l << 8) | c; | |
722 | #endif | |
723 | break; | |
724 | case FLASH_CFI_64BIT: | |
6d0f6bcf | 725 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
726 | ll = c; |
727 | ll <<= 56; | |
728 | cword->ll = (cword->ll >> 8) | ll; | |
729 | #else | |
730 | cword->ll = (cword->ll << 8) | c; | |
731 | #endif | |
732 | break; | |
260421a2 | 733 | } |
be60a902 | 734 | } |
5653fc33 | 735 | |
0f8e851e JG |
736 | /* |
737 | * Loop through the sector table starting from the previously found sector. | |
738 | * Searches forwards or backwards, dependent on the passed address. | |
be60a902 HS |
739 | */ |
740 | static flash_sect_t find_sector (flash_info_t * info, ulong addr) | |
741 | { | |
0f8e851e JG |
742 | static flash_sect_t saved_sector = 0; /* previously found sector */ |
743 | flash_sect_t sector = saved_sector; | |
744 | ||
745 | while ((info->start[sector] < addr) | |
746 | && (sector < info->sector_count - 1)) | |
747 | sector++; | |
748 | while ((info->start[sector] > addr) && (sector > 0)) | |
749 | /* | |
750 | * also decrements the sector in case of an overshot | |
751 | * in the first loop | |
752 | */ | |
753 | sector--; | |
754 | ||
755 | saved_sector = sector; | |
be60a902 | 756 | return sector; |
5653fc33 WD |
757 | } |
758 | ||
759 | /*----------------------------------------------------------------------- | |
5653fc33 | 760 | */ |
be60a902 HS |
761 | static int flash_write_cfiword (flash_info_t * info, ulong dest, |
762 | cfiword_t cword) | |
5653fc33 | 763 | { |
09ce9921 | 764 | void *dstaddr = (void *)dest; |
be60a902 | 765 | int flag; |
a7292871 JG |
766 | flash_sect_t sect = 0; |
767 | char sect_found = 0; | |
5653fc33 | 768 | |
be60a902 HS |
769 | /* Check if Flash is (sufficiently) erased */ |
770 | switch (info->portwidth) { | |
771 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 772 | flag = ((flash_read8(dstaddr) & cword.c) == cword.c); |
be60a902 HS |
773 | break; |
774 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 775 | flag = ((flash_read16(dstaddr) & cword.w) == cword.w); |
be60a902 HS |
776 | break; |
777 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 778 | flag = ((flash_read32(dstaddr) & cword.l) == cword.l); |
be60a902 HS |
779 | break; |
780 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 781 | flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); |
be60a902 HS |
782 | break; |
783 | default: | |
12d30aa7 HS |
784 | flag = 0; |
785 | break; | |
5653fc33 | 786 | } |
09ce9921 | 787 | if (!flag) |
0dc80e27 | 788 | return ERR_NOT_ERASED; |
5653fc33 | 789 | |
be60a902 HS |
790 | /* Disable interrupts which might cause a timeout here */ |
791 | flag = disable_interrupts (); | |
79b4cda0 | 792 | |
be60a902 | 793 | switch (info->vendor) { |
9c048b52 | 794 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
795 | case CFI_CMDSET_INTEL_EXTENDED: |
796 | case CFI_CMDSET_INTEL_STANDARD: | |
797 | flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); | |
798 | flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); | |
799 | break; | |
800 | case CFI_CMDSET_AMD_EXTENDED: | |
801 | case CFI_CMDSET_AMD_STANDARD: | |
0d01f66d ES |
802 | sect = find_sector(info, dest); |
803 | flash_unlock_seq (info, sect); | |
804 | flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE); | |
a7292871 | 805 | sect_found = 1; |
be60a902 | 806 | break; |
b4db4a76 PYC |
807 | #ifdef CONFIG_FLASH_CFI_LEGACY |
808 | case CFI_CMDSET_AMD_LEGACY: | |
809 | sect = find_sector(info, dest); | |
810 | flash_unlock_seq (info, 0); | |
811 | flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); | |
812 | sect_found = 1; | |
813 | break; | |
814 | #endif | |
5653fc33 WD |
815 | } |
816 | ||
be60a902 HS |
817 | switch (info->portwidth) { |
818 | case FLASH_CFI_8BIT: | |
cdbaefb5 | 819 | flash_write8(cword.c, dstaddr); |
be60a902 HS |
820 | break; |
821 | case FLASH_CFI_16BIT: | |
cdbaefb5 | 822 | flash_write16(cword.w, dstaddr); |
be60a902 HS |
823 | break; |
824 | case FLASH_CFI_32BIT: | |
cdbaefb5 | 825 | flash_write32(cword.l, dstaddr); |
be60a902 HS |
826 | break; |
827 | case FLASH_CFI_64BIT: | |
cdbaefb5 | 828 | flash_write64(cword.ll, dstaddr); |
be60a902 | 829 | break; |
5653fc33 WD |
830 | } |
831 | ||
be60a902 HS |
832 | /* re-enable interrupts if necessary */ |
833 | if (flag) | |
834 | enable_interrupts (); | |
5653fc33 | 835 | |
a7292871 JG |
836 | if (!sect_found) |
837 | sect = find_sector (info, dest); | |
838 | ||
e5720823 TC |
839 | if (use_flash_status_poll(info)) |
840 | return flash_status_poll(info, &cword, dstaddr, | |
841 | info->write_tout, "write"); | |
842 | else | |
843 | return flash_full_status_check(info, sect, | |
844 | info->write_tout, "write"); | |
5653fc33 WD |
845 | } |
846 | ||
6d0f6bcf | 847 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
5653fc33 | 848 | |
be60a902 HS |
849 | static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, |
850 | int len) | |
5653fc33 | 851 | { |
be60a902 HS |
852 | flash_sect_t sector; |
853 | int cnt; | |
854 | int retcode; | |
cdbaefb5 | 855 | void *src = cp; |
ec21d5cf | 856 | void *dst = (void *)dest; |
0dc80e27 SR |
857 | void *dst2 = dst; |
858 | int flag = 0; | |
96ef831f GL |
859 | uint offset = 0; |
860 | unsigned int shift; | |
9c048b52 | 861 | uchar write_cmd; |
cdbaefb5 | 862 | |
0dc80e27 SR |
863 | switch (info->portwidth) { |
864 | case FLASH_CFI_8BIT: | |
96ef831f | 865 | shift = 0; |
0dc80e27 SR |
866 | break; |
867 | case FLASH_CFI_16BIT: | |
96ef831f | 868 | shift = 1; |
0dc80e27 SR |
869 | break; |
870 | case FLASH_CFI_32BIT: | |
96ef831f | 871 | shift = 2; |
0dc80e27 SR |
872 | break; |
873 | case FLASH_CFI_64BIT: | |
96ef831f | 874 | shift = 3; |
0dc80e27 SR |
875 | break; |
876 | default: | |
877 | retcode = ERR_INVAL; | |
878 | goto out_unmap; | |
879 | } | |
880 | ||
96ef831f GL |
881 | cnt = len >> shift; |
882 | ||
0dc80e27 SR |
883 | while ((cnt-- > 0) && (flag == 0)) { |
884 | switch (info->portwidth) { | |
885 | case FLASH_CFI_8BIT: | |
886 | flag = ((flash_read8(dst2) & flash_read8(src)) == | |
887 | flash_read8(src)); | |
888 | src += 1, dst2 += 1; | |
889 | break; | |
890 | case FLASH_CFI_16BIT: | |
891 | flag = ((flash_read16(dst2) & flash_read16(src)) == | |
892 | flash_read16(src)); | |
893 | src += 2, dst2 += 2; | |
894 | break; | |
895 | case FLASH_CFI_32BIT: | |
896 | flag = ((flash_read32(dst2) & flash_read32(src)) == | |
897 | flash_read32(src)); | |
898 | src += 4, dst2 += 4; | |
899 | break; | |
900 | case FLASH_CFI_64BIT: | |
901 | flag = ((flash_read64(dst2) & flash_read64(src)) == | |
902 | flash_read64(src)); | |
903 | src += 8, dst2 += 8; | |
904 | break; | |
905 | } | |
906 | } | |
907 | if (!flag) { | |
908 | retcode = ERR_NOT_ERASED; | |
909 | goto out_unmap; | |
910 | } | |
911 | ||
912 | src = cp; | |
cdbaefb5 | 913 | sector = find_sector (info, dest); |
bf9e3b38 WD |
914 | |
915 | switch (info->vendor) { | |
9c048b52 | 916 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
5653fc33 WD |
917 | case CFI_CMDSET_INTEL_STANDARD: |
918 | case CFI_CMDSET_INTEL_EXTENDED: | |
9c048b52 VL |
919 | write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? |
920 | FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; | |
be60a902 | 921 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
9c048b52 VL |
922 | flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS); |
923 | flash_write_cmd (info, sector, 0, write_cmd); | |
be60a902 HS |
924 | retcode = flash_status_check (info, sector, |
925 | info->buffer_write_tout, | |
926 | "write to buffer"); | |
927 | if (retcode == ERR_OK) { | |
928 | /* reduce the number of loops by the width of | |
929 | * the port */ | |
96ef831f | 930 | cnt = len >> shift; |
93c56f21 | 931 | flash_write_cmd (info, sector, 0, cnt - 1); |
be60a902 HS |
932 | while (cnt-- > 0) { |
933 | switch (info->portwidth) { | |
934 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
935 | flash_write8(flash_read8(src), dst); |
936 | src += 1, dst += 1; | |
be60a902 HS |
937 | break; |
938 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
939 | flash_write16(flash_read16(src), dst); |
940 | src += 2, dst += 2; | |
be60a902 HS |
941 | break; |
942 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
943 | flash_write32(flash_read32(src), dst); |
944 | src += 4, dst += 4; | |
be60a902 HS |
945 | break; |
946 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
947 | flash_write64(flash_read64(src), dst); |
948 | src += 8, dst += 8; | |
be60a902 HS |
949 | break; |
950 | default: | |
12d30aa7 HS |
951 | retcode = ERR_INVAL; |
952 | goto out_unmap; | |
be60a902 HS |
953 | } |
954 | } | |
955 | flash_write_cmd (info, sector, 0, | |
956 | FLASH_CMD_WRITE_BUFFER_CONFIRM); | |
957 | retcode = flash_full_status_check ( | |
958 | info, sector, info->buffer_write_tout, | |
959 | "buffer write"); | |
960 | } | |
12d30aa7 HS |
961 | |
962 | break; | |
be60a902 | 963 | |
5653fc33 WD |
964 | case CFI_CMDSET_AMD_STANDARD: |
965 | case CFI_CMDSET_AMD_EXTENDED: | |
be60a902 | 966 | flash_unlock_seq(info,0); |
96ef831f GL |
967 | |
968 | #ifdef CONFIG_FLASH_SPANSION_S29WS_N | |
969 | offset = ((unsigned long)dst - info->start[sector]) >> shift; | |
970 | #endif | |
971 | flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); | |
972 | cnt = len >> shift; | |
7dedefdf | 973 | flash_write_cmd(info, sector, offset, cnt - 1); |
be60a902 HS |
974 | |
975 | switch (info->portwidth) { | |
976 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
977 | while (cnt-- > 0) { |
978 | flash_write8(flash_read8(src), dst); | |
979 | src += 1, dst += 1; | |
980 | } | |
be60a902 HS |
981 | break; |
982 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
983 | while (cnt-- > 0) { |
984 | flash_write16(flash_read16(src), dst); | |
985 | src += 2, dst += 2; | |
986 | } | |
be60a902 HS |
987 | break; |
988 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
989 | while (cnt-- > 0) { |
990 | flash_write32(flash_read32(src), dst); | |
991 | src += 4, dst += 4; | |
992 | } | |
be60a902 HS |
993 | break; |
994 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
995 | while (cnt-- > 0) { |
996 | flash_write64(flash_read64(src), dst); | |
997 | src += 8, dst += 8; | |
998 | } | |
be60a902 HS |
999 | break; |
1000 | default: | |
12d30aa7 HS |
1001 | retcode = ERR_INVAL; |
1002 | goto out_unmap; | |
be60a902 HS |
1003 | } |
1004 | ||
1005 | flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); | |
e5720823 TC |
1006 | if (use_flash_status_poll(info)) |
1007 | retcode = flash_status_poll(info, src - (1 << shift), | |
1008 | dst - (1 << shift), | |
1009 | info->buffer_write_tout, | |
1010 | "buffer write"); | |
1011 | else | |
1012 | retcode = flash_full_status_check(info, sector, | |
1013 | info->buffer_write_tout, | |
1014 | "buffer write"); | |
12d30aa7 | 1015 | break; |
be60a902 | 1016 | |
5653fc33 | 1017 | default: |
be60a902 | 1018 | debug ("Unknown Command Set\n"); |
12d30aa7 HS |
1019 | retcode = ERR_INVAL; |
1020 | break; | |
5653fc33 | 1021 | } |
12d30aa7 HS |
1022 | |
1023 | out_unmap: | |
12d30aa7 | 1024 | return retcode; |
5653fc33 | 1025 | } |
6d0f6bcf | 1026 | #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
be60a902 | 1027 | |
bf9e3b38 | 1028 | |
5653fc33 | 1029 | /*----------------------------------------------------------------------- |
5653fc33 | 1030 | */ |
be60a902 | 1031 | int flash_erase (flash_info_t * info, int s_first, int s_last) |
5653fc33 | 1032 | { |
be60a902 HS |
1033 | int rcode = 0; |
1034 | int prot; | |
1035 | flash_sect_t sect; | |
e5720823 | 1036 | int st; |
5653fc33 | 1037 | |
be60a902 HS |
1038 | if (info->flash_id != FLASH_MAN_CFI) { |
1039 | puts ("Can't erase unknown flash type - aborted\n"); | |
1040 | return 1; | |
1041 | } | |
1042 | if ((s_first < 0) || (s_first > s_last)) { | |
1043 | puts ("- no sectors to erase\n"); | |
1044 | return 1; | |
1045 | } | |
2662b40c | 1046 | |
be60a902 HS |
1047 | prot = 0; |
1048 | for (sect = s_first; sect <= s_last; ++sect) { | |
1049 | if (info->protect[sect]) { | |
1050 | prot++; | |
5653fc33 WD |
1051 | } |
1052 | } | |
be60a902 HS |
1053 | if (prot) { |
1054 | printf ("- Warning: %d protected sectors will not be erased!\n", | |
1055 | prot); | |
6ea808ef | 1056 | } else if (flash_verbose) { |
be60a902 HS |
1057 | putc ('\n'); |
1058 | } | |
bf9e3b38 | 1059 | |
bf9e3b38 | 1060 | |
be60a902 HS |
1061 | for (sect = s_first; sect <= s_last; sect++) { |
1062 | if (info->protect[sect] == 0) { /* not protected */ | |
1063 | switch (info->vendor) { | |
9c048b52 | 1064 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
1065 | case CFI_CMDSET_INTEL_STANDARD: |
1066 | case CFI_CMDSET_INTEL_EXTENDED: | |
1067 | flash_write_cmd (info, sect, 0, | |
1068 | FLASH_CMD_CLEAR_STATUS); | |
1069 | flash_write_cmd (info, sect, 0, | |
1070 | FLASH_CMD_BLOCK_ERASE); | |
1071 | flash_write_cmd (info, sect, 0, | |
1072 | FLASH_CMD_ERASE_CONFIRM); | |
1073 | break; | |
1074 | case CFI_CMDSET_AMD_STANDARD: | |
1075 | case CFI_CMDSET_AMD_EXTENDED: | |
1076 | flash_unlock_seq (info, sect); | |
1077 | flash_write_cmd (info, sect, | |
1078 | info->addr_unlock1, | |
1079 | AMD_CMD_ERASE_START); | |
1080 | flash_unlock_seq (info, sect); | |
1081 | flash_write_cmd (info, sect, 0, | |
1082 | AMD_CMD_ERASE_SECTOR); | |
1083 | break; | |
1084 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1085 | case CFI_CMDSET_AMD_LEGACY: | |
1086 | flash_unlock_seq (info, 0); | |
1087 | flash_write_cmd (info, 0, info->addr_unlock1, | |
1088 | AMD_CMD_ERASE_START); | |
1089 | flash_unlock_seq (info, 0); | |
1090 | flash_write_cmd (info, sect, 0, | |
1091 | AMD_CMD_ERASE_SECTOR); | |
1092 | break; | |
1093 | #endif | |
1094 | default: | |
1095 | debug ("Unkown flash vendor %d\n", | |
1096 | info->vendor); | |
1097 | break; | |
bf9e3b38 | 1098 | } |
be60a902 | 1099 | |
e5720823 TC |
1100 | if (use_flash_status_poll(info)) { |
1101 | cfiword_t cword = (cfiword_t)0xffffffffffffffffULL; | |
1102 | void *dest; | |
1103 | dest = flash_map(info, sect, 0); | |
1104 | st = flash_status_poll(info, &cword, dest, | |
1105 | info->erase_blk_tout, "erase"); | |
1106 | flash_unmap(info, sect, 0, dest); | |
1107 | } else | |
1108 | st = flash_full_status_check(info, sect, | |
1109 | info->erase_blk_tout, | |
1110 | "erase"); | |
1111 | if (st) | |
be60a902 | 1112 | rcode = 1; |
e5720823 | 1113 | else if (flash_verbose) |
be60a902 | 1114 | putc ('.'); |
5653fc33 | 1115 | } |
5653fc33 | 1116 | } |
6ea808ef PZ |
1117 | |
1118 | if (flash_verbose) | |
1119 | puts (" done\n"); | |
1120 | ||
be60a902 | 1121 | return rcode; |
5653fc33 | 1122 | } |
bf9e3b38 | 1123 | |
70084df7 SR |
1124 | #ifdef CONFIG_SYS_FLASH_EMPTY_INFO |
1125 | static int sector_erased(flash_info_t *info, int i) | |
1126 | { | |
1127 | int k; | |
1128 | int size; | |
4d2ca9d6 | 1129 | u32 *flash; |
70084df7 SR |
1130 | |
1131 | /* | |
1132 | * Check if whole sector is erased | |
1133 | */ | |
1134 | size = flash_sector_size(info, i); | |
4d2ca9d6 | 1135 | flash = (u32 *)info->start[i]; |
70084df7 SR |
1136 | /* divide by 4 for longword access */ |
1137 | size = size >> 2; | |
1138 | ||
1139 | for (k = 0; k < size; k++) { | |
4d2ca9d6 | 1140 | if (flash_read32(flash++) != 0xffffffff) |
70084df7 SR |
1141 | return 0; /* not erased */ |
1142 | } | |
1143 | ||
1144 | return 1; /* erased */ | |
1145 | } | |
1146 | #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */ | |
1147 | ||
be60a902 | 1148 | void flash_print_info (flash_info_t * info) |
5653fc33 | 1149 | { |
be60a902 | 1150 | int i; |
4d13cbad | 1151 | |
be60a902 HS |
1152 | if (info->flash_id != FLASH_MAN_CFI) { |
1153 | puts ("missing or unknown FLASH type\n"); | |
1154 | return; | |
1155 | } | |
1156 | ||
1157 | printf ("%s FLASH (%d x %d)", | |
1158 | info->name, | |
1159 | (info->portwidth << 3), (info->chipwidth << 3)); | |
1160 | if (info->size < 1024*1024) | |
1161 | printf (" Size: %ld kB in %d Sectors\n", | |
1162 | info->size >> 10, info->sector_count); | |
1163 | else | |
1164 | printf (" Size: %ld MB in %d Sectors\n", | |
1165 | info->size >> 20, info->sector_count); | |
1166 | printf (" "); | |
1167 | switch (info->vendor) { | |
9c048b52 VL |
1168 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
1169 | printf ("Intel Prog Regions"); | |
1170 | break; | |
be60a902 HS |
1171 | case CFI_CMDSET_INTEL_STANDARD: |
1172 | printf ("Intel Standard"); | |
1173 | break; | |
1174 | case CFI_CMDSET_INTEL_EXTENDED: | |
1175 | printf ("Intel Extended"); | |
1176 | break; | |
1177 | case CFI_CMDSET_AMD_STANDARD: | |
1178 | printf ("AMD Standard"); | |
1179 | break; | |
1180 | case CFI_CMDSET_AMD_EXTENDED: | |
1181 | printf ("AMD Extended"); | |
1182 | break; | |
1183 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1184 | case CFI_CMDSET_AMD_LEGACY: | |
1185 | printf ("AMD Legacy"); | |
1186 | break; | |
4d13cbad | 1187 | #endif |
be60a902 HS |
1188 | default: |
1189 | printf ("Unknown (%d)", info->vendor); | |
1190 | break; | |
1191 | } | |
d77c7ac4 PDM |
1192 | printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x", |
1193 | info->manufacturer_id); | |
1194 | printf (info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", | |
1195 | info->device_id); | |
be60a902 HS |
1196 | if (info->device_id == 0x7E) { |
1197 | printf("%04X", info->device_id2); | |
1198 | } | |
1199 | printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", | |
1200 | info->erase_blk_tout, | |
1201 | info->write_tout); | |
1202 | if (info->buffer_size > 1) { | |
1203 | printf (" Buffer write timeout: %ld ms, " | |
1204 | "buffer size: %d bytes\n", | |
1205 | info->buffer_write_tout, | |
1206 | info->buffer_size); | |
5653fc33 | 1207 | } |
5653fc33 | 1208 | |
be60a902 HS |
1209 | puts ("\n Sector Start Addresses:"); |
1210 | for (i = 0; i < info->sector_count; ++i) { | |
2e97394a | 1211 | if (ctrlc()) |
70084df7 | 1212 | break; |
be60a902 | 1213 | if ((i % 5) == 0) |
70084df7 | 1214 | putc('\n'); |
6d0f6bcf | 1215 | #ifdef CONFIG_SYS_FLASH_EMPTY_INFO |
be60a902 HS |
1216 | /* print empty and read-only info */ |
1217 | printf (" %08lX %c %s ", | |
1218 | info->start[i], | |
70084df7 | 1219 | sector_erased(info, i) ? 'E' : ' ', |
be60a902 | 1220 | info->protect[i] ? "RO" : " "); |
6d0f6bcf | 1221 | #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ |
be60a902 HS |
1222 | printf (" %08lX %s ", |
1223 | info->start[i], | |
1224 | info->protect[i] ? "RO" : " "); | |
bf9e3b38 | 1225 | #endif |
be60a902 HS |
1226 | } |
1227 | putc ('\n'); | |
1228 | return; | |
5653fc33 WD |
1229 | } |
1230 | ||
9a042e9c JVB |
1231 | /*----------------------------------------------------------------------- |
1232 | * This is used in a few places in write_buf() to show programming | |
1233 | * progress. Making it a function is nasty because it needs to do side | |
1234 | * effect updates to digit and dots. Repeated code is nasty too, so | |
1235 | * we define it once here. | |
1236 | */ | |
f0105727 SR |
1237 | #ifdef CONFIG_FLASH_SHOW_PROGRESS |
1238 | #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ | |
6ea808ef PZ |
1239 | if (flash_verbose) { \ |
1240 | dots -= dots_sub; \ | |
1241 | if ((scale > 0) && (dots <= 0)) { \ | |
1242 | if ((digit % 5) == 0) \ | |
1243 | printf ("%d", digit / 5); \ | |
1244 | else \ | |
1245 | putc ('.'); \ | |
1246 | digit--; \ | |
1247 | dots += scale; \ | |
1248 | } \ | |
9a042e9c | 1249 | } |
f0105727 SR |
1250 | #else |
1251 | #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) | |
1252 | #endif | |
9a042e9c | 1253 | |
be60a902 HS |
1254 | /*----------------------------------------------------------------------- |
1255 | * Copy memory to flash, returns: | |
1256 | * 0 - OK | |
1257 | * 1 - write timeout | |
1258 | * 2 - Flash not erased | |
5653fc33 | 1259 | */ |
be60a902 | 1260 | int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
5653fc33 | 1261 | { |
be60a902 | 1262 | ulong wp; |
12d30aa7 | 1263 | uchar *p; |
be60a902 | 1264 | int aln; |
5653fc33 | 1265 | cfiword_t cword; |
be60a902 | 1266 | int i, rc; |
6d0f6bcf | 1267 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be60a902 | 1268 | int buffered_size; |
5653fc33 | 1269 | #endif |
9a042e9c JVB |
1270 | #ifdef CONFIG_FLASH_SHOW_PROGRESS |
1271 | int digit = CONFIG_FLASH_SHOW_PROGRESS; | |
1272 | int scale = 0; | |
1273 | int dots = 0; | |
1274 | ||
1275 | /* | |
1276 | * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. | |
1277 | */ | |
1278 | if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { | |
1279 | scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / | |
1280 | CONFIG_FLASH_SHOW_PROGRESS); | |
1281 | } | |
1282 | #endif | |
1283 | ||
be60a902 HS |
1284 | /* get lower aligned address */ |
1285 | wp = (addr & ~(info->portwidth - 1)); | |
3a197b2f | 1286 | |
be60a902 HS |
1287 | /* handle unaligned start */ |
1288 | if ((aln = addr - wp) != 0) { | |
1289 | cword.l = 0; | |
09ce9921 | 1290 | p = (uchar *)wp; |
12d30aa7 HS |
1291 | for (i = 0; i < aln; ++i) |
1292 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
5653fc33 | 1293 | |
be60a902 HS |
1294 | for (; (i < info->portwidth) && (cnt > 0); i++) { |
1295 | flash_add_byte (info, &cword, *src++); | |
1296 | cnt--; | |
be60a902 | 1297 | } |
12d30aa7 HS |
1298 | for (; (cnt == 0) && (i < info->portwidth); ++i) |
1299 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
1300 | ||
1301 | rc = flash_write_cfiword (info, wp, cword); | |
12d30aa7 | 1302 | if (rc != 0) |
be60a902 | 1303 | return rc; |
12d30aa7 HS |
1304 | |
1305 | wp += i; | |
f0105727 | 1306 | FLASH_SHOW_PROGRESS(scale, dots, digit, i); |
be60a902 HS |
1307 | } |
1308 | ||
1309 | /* handle the aligned part */ | |
6d0f6bcf | 1310 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be60a902 HS |
1311 | buffered_size = (info->portwidth / info->chipwidth); |
1312 | buffered_size *= info->buffer_size; | |
1313 | while (cnt >= info->portwidth) { | |
1314 | /* prohibit buffer write when buffer_size is 1 */ | |
1315 | if (info->buffer_size == 1) { | |
1316 | cword.l = 0; | |
1317 | for (i = 0; i < info->portwidth; i++) | |
1318 | flash_add_byte (info, &cword, *src++); | |
1319 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
1320 | return rc; | |
1321 | wp += info->portwidth; | |
1322 | cnt -= info->portwidth; | |
1323 | continue; | |
1324 | } | |
1325 | ||
1326 | /* write buffer until next buffered_size aligned boundary */ | |
1327 | i = buffered_size - (wp % buffered_size); | |
1328 | if (i > cnt) | |
1329 | i = cnt; | |
1330 | if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) | |
1331 | return rc; | |
1332 | i -= i & (info->portwidth - 1); | |
1333 | wp += i; | |
1334 | src += i; | |
1335 | cnt -= i; | |
f0105727 | 1336 | FLASH_SHOW_PROGRESS(scale, dots, digit, i); |
be60a902 HS |
1337 | } |
1338 | #else | |
1339 | while (cnt >= info->portwidth) { | |
1340 | cword.l = 0; | |
1341 | for (i = 0; i < info->portwidth; i++) { | |
1342 | flash_add_byte (info, &cword, *src++); | |
1343 | } | |
1344 | if ((rc = flash_write_cfiword (info, wp, cword)) != 0) | |
1345 | return rc; | |
1346 | wp += info->portwidth; | |
1347 | cnt -= info->portwidth; | |
f0105727 | 1348 | FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); |
be60a902 | 1349 | } |
6d0f6bcf | 1350 | #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
9a042e9c | 1351 | |
be60a902 HS |
1352 | if (cnt == 0) { |
1353 | return (0); | |
1354 | } | |
1355 | ||
1356 | /* | |
1357 | * handle unaligned tail bytes | |
1358 | */ | |
1359 | cword.l = 0; | |
09ce9921 | 1360 | p = (uchar *)wp; |
12d30aa7 | 1361 | for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { |
be60a902 HS |
1362 | flash_add_byte (info, &cword, *src++); |
1363 | --cnt; | |
1364 | } | |
12d30aa7 HS |
1365 | for (; i < info->portwidth; ++i) |
1366 | flash_add_byte (info, &cword, flash_read8(p + i)); | |
be60a902 HS |
1367 | |
1368 | return flash_write_cfiword (info, wp, cword); | |
5653fc33 | 1369 | } |
bf9e3b38 | 1370 | |
5653fc33 WD |
1371 | /*----------------------------------------------------------------------- |
1372 | */ | |
6d0f6bcf | 1373 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
be60a902 HS |
1374 | |
1375 | int flash_real_protect (flash_info_t * info, long sector, int prot) | |
5653fc33 | 1376 | { |
be60a902 | 1377 | int retcode = 0; |
5653fc33 | 1378 | |
bc9019e1 RC |
1379 | switch (info->vendor) { |
1380 | case CFI_CMDSET_INTEL_PROG_REGIONS: | |
1381 | case CFI_CMDSET_INTEL_STANDARD: | |
9e8e63cc | 1382 | case CFI_CMDSET_INTEL_EXTENDED: |
54652991 PDM |
1383 | /* |
1384 | * see errata called | |
1385 | * "Numonyx Axcell P33/P30 Specification Update" :) | |
1386 | */ | |
1387 | flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID); | |
1388 | if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT, | |
1389 | prot)) { | |
1390 | /* | |
1391 | * cmd must come before FLASH_CMD_PROTECT + 20us | |
1392 | * Disable interrupts which might cause a timeout here. | |
1393 | */ | |
1394 | int flag = disable_interrupts (); | |
1395 | unsigned short cmd; | |
1396 | ||
1397 | if (prot) | |
1398 | cmd = FLASH_CMD_PROTECT_SET; | |
1399 | else | |
1400 | cmd = FLASH_CMD_PROTECT_CLEAR; | |
1401 | ||
bc9019e1 | 1402 | flash_write_cmd (info, sector, 0, |
54652991 PDM |
1403 | FLASH_CMD_PROTECT); |
1404 | flash_write_cmd (info, sector, 0, cmd); | |
1405 | /* re-enable interrupts if necessary */ | |
1406 | if (flag) | |
1407 | enable_interrupts (); | |
1408 | } | |
bc9019e1 RC |
1409 | break; |
1410 | case CFI_CMDSET_AMD_EXTENDED: | |
1411 | case CFI_CMDSET_AMD_STANDARD: | |
bc9019e1 RC |
1412 | /* U-Boot only checks the first byte */ |
1413 | if (info->manufacturer_id == (uchar)ATM_MANUFACT) { | |
1414 | if (prot) { | |
1415 | flash_unlock_seq (info, 0); | |
1416 | flash_write_cmd (info, 0, | |
1417 | info->addr_unlock1, | |
1418 | ATM_CMD_SOFTLOCK_START); | |
1419 | flash_unlock_seq (info, 0); | |
1420 | flash_write_cmd (info, sector, 0, | |
1421 | ATM_CMD_LOCK_SECT); | |
1422 | } else { | |
1423 | flash_write_cmd (info, 0, | |
1424 | info->addr_unlock1, | |
1425 | AMD_CMD_UNLOCK_START); | |
1426 | if (info->device_id == ATM_ID_BV6416) | |
1427 | flash_write_cmd (info, sector, | |
1428 | 0, ATM_CMD_UNLOCK_SECT); | |
1429 | } | |
1430 | } | |
1431 | break; | |
4e00acde TL |
1432 | #ifdef CONFIG_FLASH_CFI_LEGACY |
1433 | case CFI_CMDSET_AMD_LEGACY: | |
1434 | flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); | |
1435 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); | |
1436 | if (prot) | |
1437 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); | |
1438 | else | |
1439 | flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); | |
1440 | #endif | |
bc9019e1 | 1441 | }; |
bf9e3b38 | 1442 | |
df4e813b SR |
1443 | /* |
1444 | * Flash needs to be in status register read mode for | |
1445 | * flash_full_status_check() to work correctly | |
1446 | */ | |
1447 | flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); | |
be60a902 HS |
1448 | if ((retcode = |
1449 | flash_full_status_check (info, sector, info->erase_blk_tout, | |
1450 | prot ? "protect" : "unprotect")) == 0) { | |
bf9e3b38 | 1451 | |
be60a902 HS |
1452 | info->protect[sector] = prot; |
1453 | ||
1454 | /* | |
1455 | * On some of Intel's flash chips (marked via legacy_unlock) | |
1456 | * unprotect unprotects all locking. | |
1457 | */ | |
1458 | if ((prot == 0) && (info->legacy_unlock)) { | |
1459 | flash_sect_t i; | |
1460 | ||
1461 | for (i = 0; i < info->sector_count; i++) { | |
1462 | if (info->protect[i]) | |
1463 | flash_real_protect (info, i, 1); | |
1464 | } | |
5653fc33 | 1465 | } |
5653fc33 | 1466 | } |
be60a902 | 1467 | return retcode; |
5653fc33 | 1468 | } |
bf9e3b38 | 1469 | |
5653fc33 | 1470 | /*----------------------------------------------------------------------- |
be60a902 | 1471 | * flash_read_user_serial - read the OneTimeProgramming cells |
5653fc33 | 1472 | */ |
be60a902 HS |
1473 | void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, |
1474 | int len) | |
5653fc33 | 1475 | { |
be60a902 HS |
1476 | uchar *src; |
1477 | uchar *dst; | |
bf9e3b38 | 1478 | |
be60a902 | 1479 | dst = buffer; |
12d30aa7 | 1480 | src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION); |
be60a902 HS |
1481 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); |
1482 | memcpy (dst, src + offset, len); | |
1483 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
12d30aa7 | 1484 | flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); |
5653fc33 WD |
1485 | } |
1486 | ||
be60a902 HS |
1487 | /* |
1488 | * flash_read_factory_serial - read the device Id from the protection area | |
5653fc33 | 1489 | */ |
be60a902 HS |
1490 | void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, |
1491 | int len) | |
5653fc33 | 1492 | { |
be60a902 | 1493 | uchar *src; |
bf9e3b38 | 1494 | |
12d30aa7 | 1495 | src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION); |
be60a902 HS |
1496 | flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); |
1497 | memcpy (buffer, src + offset, len); | |
1498 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
12d30aa7 | 1499 | flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); |
5653fc33 WD |
1500 | } |
1501 | ||
6d0f6bcf | 1502 | #endif /* CONFIG_SYS_FLASH_PROTECTION */ |
be60a902 | 1503 | |
0ddf06dd HS |
1504 | /*----------------------------------------------------------------------- |
1505 | * Reverse the order of the erase regions in the CFI QRY structure. | |
1506 | * This is needed for chips that are either a) correctly detected as | |
1507 | * top-boot, or b) buggy. | |
1508 | */ | |
1509 | static void cfi_reverse_geometry(struct cfi_qry *qry) | |
1510 | { | |
1511 | unsigned int i, j; | |
1512 | u32 tmp; | |
1513 | ||
1514 | for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { | |
1515 | tmp = qry->erase_region_info[i]; | |
1516 | qry->erase_region_info[i] = qry->erase_region_info[j]; | |
1517 | qry->erase_region_info[j] = tmp; | |
1518 | } | |
1519 | } | |
be60a902 | 1520 | |
260421a2 SR |
1521 | /*----------------------------------------------------------------------- |
1522 | * read jedec ids from device and set corresponding fields in info struct | |
1523 | * | |
1524 | * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct | |
1525 | * | |
0ddf06dd HS |
1526 | */ |
1527 | static void cmdset_intel_read_jedec_ids(flash_info_t *info) | |
1528 | { | |
1529 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1530 | flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); | |
1531 | udelay(1000); /* some flash are slow to respond */ | |
1532 | info->manufacturer_id = flash_read_uchar (info, | |
1533 | FLASH_OFFSET_MANUFACTURER_ID); | |
d77c7ac4 PDM |
1534 | info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ? |
1535 | flash_read_word (info, FLASH_OFFSET_DEVICE_ID) : | |
1536 | flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID); | |
0ddf06dd HS |
1537 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
1538 | } | |
1539 | ||
1540 | static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) | |
1541 | { | |
1542 | info->cmd_reset = FLASH_CMD_RESET; | |
1543 | ||
1544 | cmdset_intel_read_jedec_ids(info); | |
1545 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1546 | ||
6d0f6bcf | 1547 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
0ddf06dd HS |
1548 | /* read legacy lock/unlock bit from intel flash */ |
1549 | if (info->ext_addr) { | |
1550 | info->legacy_unlock = flash_read_uchar (info, | |
1551 | info->ext_addr + 5) & 0x08; | |
1552 | } | |
1553 | #endif | |
1554 | ||
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | static void cmdset_amd_read_jedec_ids(flash_info_t *info) | |
1559 | { | |
3a7b2c21 NG |
1560 | ushort bankId = 0; |
1561 | uchar manuId; | |
1562 | ||
0ddf06dd HS |
1563 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); |
1564 | flash_unlock_seq(info, 0); | |
1565 | flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); | |
1566 | udelay(1000); /* some flash are slow to respond */ | |
90447ecb | 1567 | |
3a7b2c21 NG |
1568 | manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); |
1569 | /* JEDEC JEP106Z specifies ID codes up to bank 7 */ | |
1570 | while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { | |
1571 | bankId += 0x100; | |
1572 | manuId = flash_read_uchar (info, | |
1573 | bankId | FLASH_OFFSET_MANUFACTURER_ID); | |
1574 | } | |
1575 | info->manufacturer_id = manuId; | |
90447ecb TK |
1576 | |
1577 | switch (info->chipwidth){ | |
1578 | case FLASH_CFI_8BIT: | |
1579 | info->device_id = flash_read_uchar (info, | |
1580 | FLASH_OFFSET_DEVICE_ID); | |
1581 | if (info->device_id == 0x7E) { | |
1582 | /* AMD 3-byte (expanded) device ids */ | |
1583 | info->device_id2 = flash_read_uchar (info, | |
1584 | FLASH_OFFSET_DEVICE_ID2); | |
1585 | info->device_id2 <<= 8; | |
1586 | info->device_id2 |= flash_read_uchar (info, | |
1587 | FLASH_OFFSET_DEVICE_ID3); | |
1588 | } | |
1589 | break; | |
1590 | case FLASH_CFI_16BIT: | |
1591 | info->device_id = flash_read_word (info, | |
1592 | FLASH_OFFSET_DEVICE_ID); | |
1593 | break; | |
1594 | default: | |
1595 | break; | |
0ddf06dd HS |
1596 | } |
1597 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
1598 | } | |
1599 | ||
1600 | static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) | |
1601 | { | |
1602 | info->cmd_reset = AMD_CMD_RESET; | |
1603 | ||
1604 | cmdset_amd_read_jedec_ids(info); | |
1605 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1606 | ||
0ddf06dd HS |
1607 | return 0; |
1608 | } | |
1609 | ||
1610 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
260421a2 SR |
1611 | static void flash_read_jedec_ids (flash_info_t * info) |
1612 | { | |
1613 | info->manufacturer_id = 0; | |
1614 | info->device_id = 0; | |
1615 | info->device_id2 = 0; | |
1616 | ||
1617 | switch (info->vendor) { | |
9c048b52 | 1618 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
260421a2 SR |
1619 | case CFI_CMDSET_INTEL_STANDARD: |
1620 | case CFI_CMDSET_INTEL_EXTENDED: | |
8225d1e3 | 1621 | cmdset_intel_read_jedec_ids(info); |
260421a2 SR |
1622 | break; |
1623 | case CFI_CMDSET_AMD_STANDARD: | |
1624 | case CFI_CMDSET_AMD_EXTENDED: | |
8225d1e3 | 1625 | cmdset_amd_read_jedec_ids(info); |
260421a2 SR |
1626 | break; |
1627 | default: | |
1628 | break; | |
1629 | } | |
1630 | } | |
1631 | ||
5653fc33 | 1632 | /*----------------------------------------------------------------------- |
be60a902 HS |
1633 | * Call board code to request info about non-CFI flash. |
1634 | * board_flash_get_legacy needs to fill in at least: | |
1635 | * info->portwidth, info->chipwidth and info->interface for Jedec probing. | |
7e5b9b47 | 1636 | */ |
09ce9921 | 1637 | static int flash_detect_legacy(phys_addr_t base, int banknum) |
5653fc33 | 1638 | { |
be60a902 | 1639 | flash_info_t *info = &flash_info[banknum]; |
7e5b9b47 | 1640 | |
be60a902 HS |
1641 | if (board_flash_get_legacy(base, banknum, info)) { |
1642 | /* board code may have filled info completely. If not, we | |
1643 | use JEDEC ID probing. */ | |
1644 | if (!info->vendor) { | |
1645 | int modes[] = { | |
1646 | CFI_CMDSET_AMD_STANDARD, | |
1647 | CFI_CMDSET_INTEL_STANDARD | |
1648 | }; | |
1649 | int i; | |
7e5b9b47 | 1650 | |
be60a902 HS |
1651 | for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) { |
1652 | info->vendor = modes[i]; | |
09ce9921 BB |
1653 | info->start[0] = |
1654 | (ulong)map_physmem(base, | |
e1fb6d0d | 1655 | info->portwidth, |
09ce9921 | 1656 | MAP_NOCACHE); |
be60a902 HS |
1657 | if (info->portwidth == FLASH_CFI_8BIT |
1658 | && info->interface == FLASH_CFI_X8X16) { | |
1659 | info->addr_unlock1 = 0x2AAA; | |
1660 | info->addr_unlock2 = 0x5555; | |
1661 | } else { | |
1662 | info->addr_unlock1 = 0x5555; | |
1663 | info->addr_unlock2 = 0x2AAA; | |
1664 | } | |
1665 | flash_read_jedec_ids(info); | |
1666 | debug("JEDEC PROBE: ID %x %x %x\n", | |
1667 | info->manufacturer_id, | |
1668 | info->device_id, | |
1669 | info->device_id2); | |
09ce9921 | 1670 | if (jedec_flash_match(info, info->start[0])) |
be60a902 | 1671 | break; |
09ce9921 | 1672 | else |
e1fb6d0d | 1673 | unmap_physmem((void *)info->start[0], |
09ce9921 | 1674 | MAP_NOCACHE); |
be60a902 HS |
1675 | } |
1676 | } | |
1677 | ||
1678 | switch(info->vendor) { | |
9c048b52 | 1679 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
1680 | case CFI_CMDSET_INTEL_STANDARD: |
1681 | case CFI_CMDSET_INTEL_EXTENDED: | |
1682 | info->cmd_reset = FLASH_CMD_RESET; | |
1683 | break; | |
1684 | case CFI_CMDSET_AMD_STANDARD: | |
1685 | case CFI_CMDSET_AMD_EXTENDED: | |
1686 | case CFI_CMDSET_AMD_LEGACY: | |
1687 | info->cmd_reset = AMD_CMD_RESET; | |
1688 | break; | |
1689 | } | |
1690 | info->flash_id = FLASH_MAN_CFI; | |
1691 | return 1; | |
1692 | } | |
1693 | return 0; /* use CFI */ | |
1694 | } | |
1695 | #else | |
09ce9921 | 1696 | static inline int flash_detect_legacy(phys_addr_t base, int banknum) |
be60a902 HS |
1697 | { |
1698 | return 0; /* use CFI */ | |
1699 | } | |
1700 | #endif | |
1701 | ||
1702 | /*----------------------------------------------------------------------- | |
1703 | * detect if flash is compatible with the Common Flash Interface (CFI) | |
1704 | * http://www.jedec.org/download/search/jesd68.pdf | |
1705 | */ | |
e23741f4 HS |
1706 | static void flash_read_cfi (flash_info_t *info, void *buf, |
1707 | unsigned int start, size_t len) | |
1708 | { | |
1709 | u8 *p = buf; | |
1710 | unsigned int i; | |
1711 | ||
1712 | for (i = 0; i < len; i++) | |
1713 | p[i] = flash_read_uchar(info, start + i); | |
1714 | } | |
1715 | ||
fa36ae79 SR |
1716 | void __flash_cmd_reset(flash_info_t *info) |
1717 | { | |
1718 | /* | |
1719 | * We do not yet know what kind of commandset to use, so we issue | |
1720 | * the reset command in both Intel and AMD variants, in the hope | |
1721 | * that AMD flash roms ignore the Intel command. | |
1722 | */ | |
1723 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
1724 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1725 | } | |
1726 | void flash_cmd_reset(flash_info_t *info) | |
1727 | __attribute__((weak,alias("__flash_cmd_reset"))); | |
1728 | ||
e23741f4 | 1729 | static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) |
be60a902 HS |
1730 | { |
1731 | int cfi_offset; | |
1732 | ||
fa36ae79 SR |
1733 | /* Issue FLASH reset command */ |
1734 | flash_cmd_reset(info); | |
1ba639da | 1735 | |
be60a902 HS |
1736 | for (cfi_offset=0; |
1737 | cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); | |
1738 | cfi_offset++) { | |
1739 | flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], | |
1740 | FLASH_CMD_CFI); | |
1741 | if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') | |
1742 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') | |
1743 | && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { | |
e23741f4 HS |
1744 | flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, |
1745 | sizeof(struct cfi_qry)); | |
1746 | info->interface = le16_to_cpu(qry->interface_desc); | |
1747 | ||
be60a902 HS |
1748 | info->cfi_offset = flash_offset_cfi[cfi_offset]; |
1749 | debug ("device interface is %d\n", | |
1750 | info->interface); | |
1751 | debug ("found port %d chip %d ", | |
1752 | info->portwidth, info->chipwidth); | |
1753 | debug ("port %d bits chip %d bits\n", | |
1754 | info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1755 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1756 | ||
1757 | /* calculate command offsets as in the Linux driver */ | |
1758 | info->addr_unlock1 = 0x555; | |
7e5b9b47 HS |
1759 | info->addr_unlock2 = 0x2aa; |
1760 | ||
1761 | /* | |
1762 | * modify the unlock address if we are | |
1763 | * in compatibility mode | |
1764 | */ | |
1765 | if ( /* x8/x16 in x8 mode */ | |
1766 | ((info->chipwidth == FLASH_CFI_BY8) && | |
1767 | (info->interface == FLASH_CFI_X8X16)) || | |
1768 | /* x16/x32 in x16 mode */ | |
1769 | ((info->chipwidth == FLASH_CFI_BY16) && | |
1770 | (info->interface == FLASH_CFI_X16X32))) | |
1771 | { | |
1772 | info->addr_unlock1 = 0xaaa; | |
1773 | info->addr_unlock2 = 0x555; | |
1774 | } | |
1775 | ||
1776 | info->name = "CFI conformant"; | |
1777 | return 1; | |
1778 | } | |
1779 | } | |
1780 | ||
1781 | return 0; | |
1782 | } | |
1783 | ||
e23741f4 | 1784 | static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) |
7e5b9b47 | 1785 | { |
bf9e3b38 WD |
1786 | debug ("flash detect cfi\n"); |
1787 | ||
6d0f6bcf | 1788 | for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; |
bf9e3b38 WD |
1789 | info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { |
1790 | for (info->chipwidth = FLASH_CFI_BY8; | |
1791 | info->chipwidth <= info->portwidth; | |
7e5b9b47 | 1792 | info->chipwidth <<= 1) |
e23741f4 | 1793 | if (__flash_detect_cfi(info, qry)) |
7e5b9b47 | 1794 | return 1; |
5653fc33 | 1795 | } |
bf9e3b38 | 1796 | debug ("not found\n"); |
5653fc33 WD |
1797 | return 0; |
1798 | } | |
bf9e3b38 | 1799 | |
467bcee1 HS |
1800 | /* |
1801 | * Manufacturer-specific quirks. Add workarounds for geometry | |
1802 | * reversal, etc. here. | |
1803 | */ | |
1804 | static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) | |
1805 | { | |
1806 | /* check if flash geometry needs reversal */ | |
1807 | if (qry->num_erase_regions > 1) { | |
1808 | /* reverse geometry if top boot part */ | |
1809 | if (info->cfi_version < 0x3131) { | |
1810 | /* CFI < 1.1, try to guess from device id */ | |
1811 | if ((info->device_id & 0x80) != 0) | |
1812 | cfi_reverse_geometry(qry); | |
1813 | } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { | |
1814 | /* CFI >= 1.1, deduct from top/bottom flag */ | |
1815 | /* note: ext_addr is valid since cfi_version > 0 */ | |
1816 | cfi_reverse_geometry(qry); | |
1817 | } | |
1818 | } | |
1819 | } | |
1820 | ||
1821 | static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) | |
1822 | { | |
1823 | int reverse_geometry = 0; | |
1824 | ||
1825 | /* Check the "top boot" bit in the PRI */ | |
1826 | if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) | |
1827 | reverse_geometry = 1; | |
1828 | ||
1829 | /* AT49BV6416(T) list the erase regions in the wrong order. | |
1830 | * However, the device ID is identical with the non-broken | |
cb82a532 | 1831 | * AT49BV642D they differ in the high byte. |
467bcee1 | 1832 | */ |
467bcee1 HS |
1833 | if (info->device_id == 0xd6 || info->device_id == 0xd2) |
1834 | reverse_geometry = !reverse_geometry; | |
467bcee1 HS |
1835 | |
1836 | if (reverse_geometry) | |
1837 | cfi_reverse_geometry(qry); | |
1838 | } | |
1839 | ||
e8eac437 RR |
1840 | static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) |
1841 | { | |
1842 | /* check if flash geometry needs reversal */ | |
1843 | if (qry->num_erase_regions > 1) { | |
1844 | /* reverse geometry if top boot part */ | |
1845 | if (info->cfi_version < 0x3131) { | |
7a88601a RR |
1846 | /* CFI < 1.1, guess by device id (M29W320{DT,ET} only) */ |
1847 | if (info->device_id == 0x22CA || | |
1848 | info->device_id == 0x2256) { | |
e8eac437 RR |
1849 | cfi_reverse_geometry(qry); |
1850 | } | |
1851 | } | |
1852 | } | |
1853 | } | |
1854 | ||
5653fc33 WD |
1855 | /* |
1856 | * The following code cannot be run from FLASH! | |
1857 | * | |
1858 | */ | |
34bbb8fb | 1859 | ulong flash_get_size (phys_addr_t base, int banknum) |
5653fc33 | 1860 | { |
bf9e3b38 | 1861 | flash_info_t *info = &flash_info[banknum]; |
5653fc33 WD |
1862 | int i, j; |
1863 | flash_sect_t sect_cnt; | |
09ce9921 | 1864 | phys_addr_t sector; |
5653fc33 WD |
1865 | unsigned long tmp; |
1866 | int size_ratio; | |
1867 | uchar num_erase_regions; | |
bf9e3b38 WD |
1868 | int erase_region_size; |
1869 | int erase_region_count; | |
e23741f4 | 1870 | struct cfi_qry qry; |
34bbb8fb | 1871 | unsigned long max_size; |
260421a2 | 1872 | |
f979690e KG |
1873 | memset(&qry, 0, sizeof(qry)); |
1874 | ||
260421a2 SR |
1875 | info->ext_addr = 0; |
1876 | info->cfi_version = 0; | |
6d0f6bcf | 1877 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
2662b40c SR |
1878 | info->legacy_unlock = 0; |
1879 | #endif | |
5653fc33 | 1880 | |
09ce9921 | 1881 | info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); |
5653fc33 | 1882 | |
e23741f4 HS |
1883 | if (flash_detect_cfi (info, &qry)) { |
1884 | info->vendor = le16_to_cpu(qry.p_id); | |
1885 | info->ext_addr = le16_to_cpu(qry.p_adr); | |
1886 | num_erase_regions = qry.num_erase_regions; | |
1887 | ||
260421a2 SR |
1888 | if (info->ext_addr) { |
1889 | info->cfi_version = (ushort) flash_read_uchar (info, | |
1890 | info->ext_addr + 3) << 8; | |
1891 | info->cfi_version |= (ushort) flash_read_uchar (info, | |
1892 | info->ext_addr + 4); | |
1893 | } | |
0ddf06dd | 1894 | |
bf9e3b38 | 1895 | #ifdef DEBUG |
e23741f4 | 1896 | flash_printqry (&qry); |
bf9e3b38 | 1897 | #endif |
0ddf06dd | 1898 | |
bf9e3b38 | 1899 | switch (info->vendor) { |
9c048b52 | 1900 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
5653fc33 WD |
1901 | case CFI_CMDSET_INTEL_STANDARD: |
1902 | case CFI_CMDSET_INTEL_EXTENDED: | |
0ddf06dd | 1903 | cmdset_intel_init(info, &qry); |
5653fc33 WD |
1904 | break; |
1905 | case CFI_CMDSET_AMD_STANDARD: | |
1906 | case CFI_CMDSET_AMD_EXTENDED: | |
0ddf06dd | 1907 | cmdset_amd_init(info, &qry); |
5653fc33 | 1908 | break; |
0ddf06dd HS |
1909 | default: |
1910 | printf("CFI: Unknown command set 0x%x\n", | |
1911 | info->vendor); | |
1912 | /* | |
1913 | * Unfortunately, this means we don't know how | |
1914 | * to get the chip back to Read mode. Might | |
1915 | * as well try an Intel-style reset... | |
1916 | */ | |
1917 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
1918 | return 0; | |
5653fc33 | 1919 | } |
cd37d9e6 | 1920 | |
467bcee1 HS |
1921 | /* Do manufacturer-specific fixups */ |
1922 | switch (info->manufacturer_id) { | |
1923 | case 0x0001: | |
1924 | flash_fixup_amd(info, &qry); | |
1925 | break; | |
1926 | case 0x001f: | |
1927 | flash_fixup_atmel(info, &qry); | |
1928 | break; | |
e8eac437 RR |
1929 | case 0x0020: |
1930 | flash_fixup_stm(info, &qry); | |
1931 | break; | |
467bcee1 HS |
1932 | } |
1933 | ||
bf9e3b38 | 1934 | debug ("manufacturer is %d\n", info->vendor); |
260421a2 SR |
1935 | debug ("manufacturer id is 0x%x\n", info->manufacturer_id); |
1936 | debug ("device id is 0x%x\n", info->device_id); | |
1937 | debug ("device id2 is 0x%x\n", info->device_id2); | |
1938 | debug ("cfi version is 0x%04x\n", info->cfi_version); | |
1939 | ||
5653fc33 | 1940 | size_ratio = info->portwidth / info->chipwidth; |
bf9e3b38 WD |
1941 | /* if the chip is x8/x16 reduce the ratio by half */ |
1942 | if ((info->interface == FLASH_CFI_X8X16) | |
1943 | && (info->chipwidth == FLASH_CFI_BY8)) { | |
1944 | size_ratio >>= 1; | |
1945 | } | |
bf9e3b38 WD |
1946 | debug ("size_ratio %d port %d bits chip %d bits\n", |
1947 | size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, | |
1948 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
ec50a8e3 IY |
1949 | info->size = 1 << qry.dev_size; |
1950 | /* multiply the size by the number of chips */ | |
1951 | info->size *= size_ratio; | |
34bbb8fb | 1952 | max_size = cfi_flash_bank_size(banknum); |
ec50a8e3 IY |
1953 | if (max_size && (info->size > max_size)) { |
1954 | debug("[truncated from %ldMiB]", info->size >> 20); | |
1955 | info->size = max_size; | |
1956 | } | |
bf9e3b38 | 1957 | debug ("found %d erase regions\n", num_erase_regions); |
5653fc33 WD |
1958 | sect_cnt = 0; |
1959 | sector = base; | |
bf9e3b38 WD |
1960 | for (i = 0; i < num_erase_regions; i++) { |
1961 | if (i > NUM_ERASE_REGIONS) { | |
028ab6b5 WD |
1962 | printf ("%d erase regions found, only %d used\n", |
1963 | num_erase_regions, NUM_ERASE_REGIONS); | |
5653fc33 WD |
1964 | break; |
1965 | } | |
e23741f4 | 1966 | |
0ddf06dd HS |
1967 | tmp = le32_to_cpu(qry.erase_region_info[i]); |
1968 | debug("erase region %u: 0x%08lx\n", i, tmp); | |
e23741f4 HS |
1969 | |
1970 | erase_region_count = (tmp & 0xffff) + 1; | |
1971 | tmp >>= 16; | |
bf9e3b38 WD |
1972 | erase_region_size = |
1973 | (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; | |
4c0d4c3b | 1974 | debug ("erase_region_count = %d erase_region_size = %d\n", |
028ab6b5 | 1975 | erase_region_count, erase_region_size); |
bf9e3b38 | 1976 | for (j = 0; j < erase_region_count; j++) { |
ec50a8e3 IY |
1977 | if (sector - base >= info->size) |
1978 | break; | |
6d0f6bcf | 1979 | if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { |
81b20ccc MS |
1980 | printf("ERROR: too many flash sectors\n"); |
1981 | break; | |
1982 | } | |
09ce9921 BB |
1983 | info->start[sect_cnt] = |
1984 | (ulong)map_physmem(sector, | |
1985 | info->portwidth, | |
1986 | MAP_NOCACHE); | |
5653fc33 | 1987 | sector += (erase_region_size * size_ratio); |
a1191902 WD |
1988 | |
1989 | /* | |
7e5b9b47 HS |
1990 | * Only read protection status from |
1991 | * supported devices (intel...) | |
a1191902 WD |
1992 | */ |
1993 | switch (info->vendor) { | |
9c048b52 | 1994 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
a1191902 WD |
1995 | case CFI_CMDSET_INTEL_EXTENDED: |
1996 | case CFI_CMDSET_INTEL_STANDARD: | |
df4e813b SR |
1997 | /* |
1998 | * Set flash to read-id mode. Otherwise | |
1999 | * reading protected status is not | |
2000 | * guaranteed. | |
2001 | */ | |
2002 | flash_write_cmd(info, sect_cnt, 0, | |
2003 | FLASH_CMD_READ_ID); | |
a1191902 WD |
2004 | info->protect[sect_cnt] = |
2005 | flash_isset (info, sect_cnt, | |
2006 | FLASH_OFFSET_PROTECT, | |
2007 | FLASH_STATUS_PROTECT); | |
2008 | break; | |
2009 | default: | |
7e5b9b47 HS |
2010 | /* default: not protected */ |
2011 | info->protect[sect_cnt] = 0; | |
a1191902 WD |
2012 | } |
2013 | ||
5653fc33 WD |
2014 | sect_cnt++; |
2015 | } | |
2016 | } | |
2017 | ||
2018 | info->sector_count = sect_cnt; | |
e23741f4 HS |
2019 | info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); |
2020 | tmp = 1 << qry.block_erase_timeout_typ; | |
7e5b9b47 | 2021 | info->erase_blk_tout = tmp * |
e23741f4 HS |
2022 | (1 << qry.block_erase_timeout_max); |
2023 | tmp = (1 << qry.buf_write_timeout_typ) * | |
2024 | (1 << qry.buf_write_timeout_max); | |
2025 | ||
7e5b9b47 | 2026 | /* round up when converting to ms */ |
e23741f4 HS |
2027 | info->buffer_write_tout = (tmp + 999) / 1000; |
2028 | tmp = (1 << qry.word_write_timeout_typ) * | |
2029 | (1 << qry.word_write_timeout_max); | |
7e5b9b47 | 2030 | /* round up when converting to ms */ |
e23741f4 | 2031 | info->write_tout = (tmp + 999) / 1000; |
5653fc33 | 2032 | info->flash_id = FLASH_MAN_CFI; |
7e5b9b47 HS |
2033 | if ((info->interface == FLASH_CFI_X8X16) && |
2034 | (info->chipwidth == FLASH_CFI_BY8)) { | |
2035 | /* XXX - Need to test on x8/x16 in parallel. */ | |
2036 | info->portwidth >>= 1; | |
855a496f | 2037 | } |
2215987e MF |
2038 | |
2039 | flash_write_cmd (info, 0, 0, info->cmd_reset); | |
5653fc33 WD |
2040 | } |
2041 | ||
bf9e3b38 | 2042 | return (info->size); |
5653fc33 WD |
2043 | } |
2044 | ||
6ea808ef PZ |
2045 | void flash_set_verbose(uint v) |
2046 | { | |
2047 | flash_verbose = v; | |
2048 | } | |
2049 | ||
6f726f95 SR |
2050 | static void cfi_flash_set_config_reg(u32 base, u16 val) |
2051 | { | |
2052 | #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS | |
2053 | /* | |
2054 | * Only set this config register if really defined | |
2055 | * to a valid value (0xffff is invalid) | |
2056 | */ | |
2057 | if (val == 0xffff) | |
2058 | return; | |
2059 | ||
2060 | /* | |
2061 | * Set configuration register. Data is "encrypted" in the 16 lower | |
2062 | * address bits. | |
2063 | */ | |
2064 | flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); | |
2065 | flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); | |
2066 | ||
2067 | /* | |
2068 | * Finally issue reset-command to bring device back to | |
2069 | * read-array mode | |
2070 | */ | |
2071 | flash_write16(FLASH_CMD_RESET, (void *)base); | |
2072 | #endif | |
2073 | } | |
2074 | ||
5653fc33 WD |
2075 | /*----------------------------------------------------------------------- |
2076 | */ | |
be60a902 | 2077 | unsigned long flash_init (void) |
5653fc33 | 2078 | { |
be60a902 HS |
2079 | unsigned long size = 0; |
2080 | int i; | |
6d0f6bcf | 2081 | #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) |
c63ad632 MF |
2082 | struct apl_s { |
2083 | ulong start; | |
2084 | ulong size; | |
6d0f6bcf | 2085 | } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; |
c63ad632 | 2086 | #endif |
5653fc33 | 2087 | |
6d0f6bcf | 2088 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
3a3baf3e ES |
2089 | /* read environment from EEPROM */ |
2090 | char s[64]; | |
cdb74977 | 2091 | getenv_f("unlock", s, sizeof(s)); |
81b20ccc | 2092 | #endif |
5653fc33 | 2093 | |
be60a902 | 2094 | /* Init: no FLASHes known */ |
6d0f6bcf | 2095 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
be60a902 | 2096 | flash_info[i].flash_id = FLASH_UNKNOWN; |
5653fc33 | 2097 | |
6f726f95 SR |
2098 | /* Optionally write flash configuration register */ |
2099 | cfi_flash_set_config_reg(cfi_flash_bank_addr(i), | |
2100 | cfi_flash_config_reg(i)); | |
2101 | ||
b00e19cc | 2102 | if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) |
34bbb8fb | 2103 | flash_get_size(cfi_flash_bank_addr(i), i); |
be60a902 HS |
2104 | size += flash_info[i].size; |
2105 | if (flash_info[i].flash_id == FLASH_UNKNOWN) { | |
6d0f6bcf | 2106 | #ifndef CONFIG_SYS_FLASH_QUIET_TEST |
be60a902 HS |
2107 | printf ("## Unknown FLASH on Bank %d " |
2108 | "- Size = 0x%08lx = %ld MB\n", | |
2109 | i+1, flash_info[i].size, | |
0e3fa01a | 2110 | flash_info[i].size >> 20); |
6d0f6bcf | 2111 | #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ |
be60a902 | 2112 | } |
6d0f6bcf | 2113 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
be60a902 HS |
2114 | else if ((s != NULL) && (strcmp(s, "yes") == 0)) { |
2115 | /* | |
2116 | * Only the U-Boot image and it's environment | |
2117 | * is protected, all other sectors are | |
2118 | * unprotected (unlocked) if flash hardware | |
6d0f6bcf | 2119 | * protection is used (CONFIG_SYS_FLASH_PROTECTION) |
be60a902 HS |
2120 | * and the environment variable "unlock" is |
2121 | * set to "yes". | |
2122 | */ | |
2123 | if (flash_info[i].legacy_unlock) { | |
2124 | int k; | |
5653fc33 | 2125 | |
be60a902 HS |
2126 | /* |
2127 | * Disable legacy_unlock temporarily, | |
2128 | * since flash_real_protect would | |
2129 | * relock all other sectors again | |
2130 | * otherwise. | |
2131 | */ | |
2132 | flash_info[i].legacy_unlock = 0; | |
5653fc33 | 2133 | |
be60a902 HS |
2134 | /* |
2135 | * Legacy unlocking (e.g. Intel J3) -> | |
2136 | * unlock only one sector. This will | |
2137 | * unlock all sectors. | |
2138 | */ | |
2139 | flash_real_protect (&flash_info[i], 0, 0); | |
5653fc33 | 2140 | |
be60a902 | 2141 | flash_info[i].legacy_unlock = 1; |
5653fc33 | 2142 | |
be60a902 HS |
2143 | /* |
2144 | * Manually mark other sectors as | |
2145 | * unlocked (unprotected) | |
2146 | */ | |
2147 | for (k = 1; k < flash_info[i].sector_count; k++) | |
2148 | flash_info[i].protect[k] = 0; | |
2149 | } else { | |
2150 | /* | |
2151 | * No legancy unlocking -> unlock all sectors | |
2152 | */ | |
2153 | flash_protect (FLAG_PROTECT_CLEAR, | |
2154 | flash_info[i].start[0], | |
2155 | flash_info[i].start[0] | |
2156 | + flash_info[i].size - 1, | |
2157 | &flash_info[i]); | |
79b4cda0 | 2158 | } |
79b4cda0 | 2159 | } |
6d0f6bcf | 2160 | #endif /* CONFIG_SYS_FLASH_PROTECTION */ |
be60a902 | 2161 | } |
79b4cda0 | 2162 | |
be60a902 | 2163 | /* Monitor protection ON by default */ |
8f9a2210 WW |
2164 | #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ |
2165 | (!defined(CONFIG_MONITOR_IS_IN_RAM)) | |
be60a902 | 2166 | flash_protect (FLAG_PROTECT_SET, |
6d0f6bcf JCPV |
2167 | CONFIG_SYS_MONITOR_BASE, |
2168 | CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, | |
2169 | flash_get_info(CONFIG_SYS_MONITOR_BASE)); | |
be60a902 | 2170 | #endif |
79b4cda0 | 2171 | |
be60a902 | 2172 | /* Environment protection ON by default */ |
5a1aceb0 | 2173 | #ifdef CONFIG_ENV_IS_IN_FLASH |
be60a902 | 2174 | flash_protect (FLAG_PROTECT_SET, |
0e8d1586 JCPV |
2175 | CONFIG_ENV_ADDR, |
2176 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, | |
2177 | flash_get_info(CONFIG_ENV_ADDR)); | |
be60a902 | 2178 | #endif |
79b4cda0 | 2179 | |
be60a902 | 2180 | /* Redundant environment protection ON by default */ |
0e8d1586 | 2181 | #ifdef CONFIG_ENV_ADDR_REDUND |
be60a902 | 2182 | flash_protect (FLAG_PROTECT_SET, |
0e8d1586 | 2183 | CONFIG_ENV_ADDR_REDUND, |
dfcd7f21 | 2184 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
0e8d1586 | 2185 | flash_get_info(CONFIG_ENV_ADDR_REDUND)); |
be60a902 | 2186 | #endif |
c63ad632 | 2187 | |
6d0f6bcf | 2188 | #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) |
c63ad632 MF |
2189 | for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) { |
2190 | debug("autoprotecting from %08x to %08x\n", | |
2191 | apl[i].start, apl[i].start + apl[i].size - 1); | |
2192 | flash_protect (FLAG_PROTECT_SET, | |
2193 | apl[i].start, | |
2194 | apl[i].start + apl[i].size - 1, | |
2195 | flash_get_info(apl[i].start)); | |
2196 | } | |
2197 | #endif | |
91809ed5 PZ |
2198 | |
2199 | #ifdef CONFIG_FLASH_CFI_MTD | |
2200 | cfi_mtd_init(); | |
2201 | #endif | |
2202 | ||
be60a902 | 2203 | return (size); |
5653fc33 | 2204 | } |