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[people/ms/u-boot.git] / drivers / mtd / cfi_flash.c
CommitLineData
5653fc33 1/*
bf9e3b38 2 * (C) Copyright 2002-2004
5653fc33
WD		 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
5653fc33 7 *
bf9e3b38
WD		 8 * Copyright (C) 2004
9 * Ed Okerson
260421a2
SR		 10 *
11 * Copyright (C) 2006
12 * Tolunay Orkun <listmember@orkun.us>
bf9e3b38 13 *
5653fc33
WD		 14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 *
5653fc33
WD		 32 */
33
34/* The DEBUG define must be before common to enable debugging */
2d1a537d
WD		 35/* #define DEBUG */
36
5653fc33
WD		 37#include <common.h>
38#include <asm/processor.h>
3a197b2f 39#include <asm/io.h>
4c0d4c3b 40#include <asm/byteorder.h>
2a8af187 41#include <environment.h>
fa36ae79 42#include <mtd/cfi_flash.h>
028ab6b5 43
5653fc33 44/*
7e5b9b47
HS		 45 * This file implements a Common Flash Interface (CFI) driver for
46 * U-Boot.
47 *
48 * The width of the port and the width of the chips are determined at
49 * initialization. These widths are used to calculate the address for
50 * access CFI data structures.
5653fc33
WD		 51 *
52 * References
53 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
54 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
55 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
56 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
260421a2
SR		 57 * AMD CFI Specification, Release 2.0 December 1, 2001
58 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
59 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
5653fc33 60 *
6d0f6bcf 61 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
d0b6e140 62 * reading and writing ... (yes there is such a Hardware).
5653fc33
WD		 63 */
64
7e5b9b47 65static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
4ffeab2c 66#ifdef CONFIG_FLASH_CFI_MTD
6ea808ef 67static uint flash_verbose = 1;
4ffeab2c
MF		 68#else
69#define flash_verbose 1
70#endif
92eb729b 71
2a112b23
WD		 72flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
73
79b4cda0
SR		 74/*
75 * Check if chip width is defined. If not, start detecting with 8bit.
76 */
6d0f6bcf
JCPV		 77#ifndef CONFIG_SYS_FLASH_CFI_WIDTH
78#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
79b4cda0
SR		 79#endif
80
6f726f95
SR		 81/*
82 * 0xffff is an undefined value for the configuration register. When
83 * this value is returned, the configuration register shall not be
84 * written at all (default mode).
85 */
86static u16 cfi_flash_config_reg(int i)
87{
88#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
89 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i];
90#else
91 return 0xffff;
92#endif
93}
94
ca5def3f
SR		 95#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
96int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
97#endif
98
b00e19cc
SR		 99static phys_addr_t __cfi_flash_bank_addr(int i)
100{
101 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
102}
103phys_addr_t cfi_flash_bank_addr(int i)
104 __attribute__((weak, alias("__cfi_flash_bank_addr")));
105
ec50a8e3
IY		 106static unsigned long __cfi_flash_bank_size(int i)
107{
108#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
109 return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
110#else
111 return 0;
112#endif
113}
114unsigned long cfi_flash_bank_size(int i)
115 __attribute__((weak, alias("__cfi_flash_bank_size")));
116
45aa5a7f 117static void __flash_write8(u8 value, void *addr)
cdbaefb5
HS		 118{
119 __raw_writeb(value, addr);
120}
121
45aa5a7f 122static void __flash_write16(u16 value, void *addr)
cdbaefb5
HS		 123{
124 __raw_writew(value, addr);
125}
126
45aa5a7f 127static void __flash_write32(u32 value, void *addr)
cdbaefb5
HS		 128{
129 __raw_writel(value, addr);
130}
131
45aa5a7f 132static void __flash_write64(u64 value, void *addr)
cdbaefb5
HS		 133{
134 /* No architectures currently implement __raw_writeq() */
135 *(volatile u64 *)addr = value;
136}
137
45aa5a7f 138static u8 __flash_read8(void *addr)
cdbaefb5
HS		 139{
140 return __raw_readb(addr);
141}
142
45aa5a7f 143static u16 __flash_read16(void *addr)
cdbaefb5
HS		 144{
145 return __raw_readw(addr);
146}
147
45aa5a7f 148static u32 __flash_read32(void *addr)
cdbaefb5
HS		 149{
150 return __raw_readl(addr);
151}
152
97bf85d7 153static u64 __flash_read64(void *addr)
cdbaefb5
HS		 154{
155 /* No architectures currently implement __raw_readq() */
156 return *(volatile u64 *)addr;
157}
158
45aa5a7f
SR		 159#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
160void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8")));
161void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16")));
162void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32")));
163void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64")));
164u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8")));
165u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16")));
166u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32")));
97bf85d7 167u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
45aa5a7f
SR		 168#else
169#define flash_write8 __flash_write8
170#define flash_write16 __flash_write16
171#define flash_write32 __flash_write32
172#define flash_write64 __flash_write64
173#define flash_read8 __flash_read8
174#define flash_read16 __flash_read16
175#define flash_read32 __flash_read32
176#define flash_read64 __flash_read64
177#endif
97bf85d7 178
5653fc33 179/*-----------------------------------------------------------------------
5653fc33 180 */
6d0f6bcf 181#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
4f975678 182flash_info_t *flash_get_info(ulong base)
be60a902
HS		 183{
184 int i;
cba34aaf 185 flash_info_t *info = NULL;
5653fc33 186
6d0f6bcf 187 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
be60a902
HS		 188 info = & flash_info[i];
189 if (info->size && info->start[0] <= base &&
190 base <= info->start[0] + info->size - 1)
191 break;
192 }
5653fc33 193
cba34aaf 194 return info;
be60a902 195}
5653fc33
WD		 196#endif
197
12d30aa7
HS		 198unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
199{
200 if (sect != (info->sector_count - 1))
201 return info->start[sect + 1] - info->start[sect];
202 else
203 return info->start[0] + info->size - info->start[sect];
204}
205
bf9e3b38
WD		 206/*-----------------------------------------------------------------------
207 * create an address based on the offset and the port width
208 */
12d30aa7
HS		 209static inline void *
210flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
bf9e3b38 211{
12d30aa7
HS		 212 unsigned int byte_offset = offset * info->portwidth;
213
09ce9921 214 return (void *)(info->start[sect] + byte_offset);
12d30aa7
HS		 215}
216
217static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
218 unsigned int offset, void *addr)
219{
bf9e3b38
WD		 220}
221
be60a902
HS		 222/*-----------------------------------------------------------------------
223 * make a proper sized command based on the port and chip widths
224 */
7288f972 225static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
be60a902
HS		 226{
227 int i;
93c56f21
VL		 228 int cword_offset;
229 int cp_offset;
6d0f6bcf 230#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
340ccb26
SS		 231 u32 cmd_le = cpu_to_le32(cmd);
232#endif
93c56f21 233 uchar val;
be60a902
HS		 234 uchar *cp = (uchar *) cmdbuf;
235
93c56f21
VL		 236 for (i = info->portwidth; i > 0; i--){
237 cword_offset = (info->portwidth-i)%info->chipwidth;
6d0f6bcf 238#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
93c56f21 239 cp_offset = info->portwidth - i;
340ccb26 240 val = *((uchar*)&cmd_le + cword_offset);
be60a902 241#else
93c56f21 242 cp_offset = i - 1;
7288f972 243 val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1);
be60a902 244#endif
7288f972 245 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
93c56f21 246 }
be60a902
HS		 247}
248
5653fc33 249#ifdef DEBUG
bf9e3b38
WD		 250/*-----------------------------------------------------------------------
251 * Debug support
252 */
3055793b 253static void print_longlong (char *str, unsigned long long data)
5653fc33
WD		 254{
255 int i;
256 char *cp;
bf9e3b38 257
657f2062 258 cp = (char *) &data;
bf9e3b38
WD		 259 for (i = 0; i < 8; i++)
260 sprintf (&str[i * 2], "%2.2x", *cp++);
261}
be60a902 262
e23741f4 263static void flash_printqry (struct cfi_qry *qry)
bf9e3b38 264{
e23741f4 265 u8 *p = (u8 *)qry;
bf9e3b38
WD		 266 int x, y;
267
e23741f4
HS		 268 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
269 debug("%02x : ", x);
270 for (y = 0; y < 16; y++)
271 debug("%2.2x ", p[x + y]);
272 debug(" ");
bf9e3b38 273 for (y = 0; y < 16; y++) {
e23741f4
HS		 274 unsigned char c = p[x + y];
275 if (c >= 0x20 && c <= 0x7e)
276 debug("%c", c);
277 else
278 debug(".");
bf9e3b38 279 }
e23741f4 280 debug("\n");
bf9e3b38 281 }
5653fc33
WD		 282}
283#endif
284
285
5653fc33
WD		 286/*-----------------------------------------------------------------------
287 * read a character at a port width address
288 */
3055793b 289static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
5653fc33
WD		 290{
291 uchar *cp;
12d30aa7 292 uchar retval;
bf9e3b38 293
12d30aa7 294 cp = flash_map (info, 0, offset);
6d0f6bcf 295#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
12d30aa7 296 retval = flash_read8(cp);
bf9e3b38 297#else
12d30aa7 298 retval = flash_read8(cp + info->portwidth - 1);
bf9e3b38 299#endif
12d30aa7
HS		 300 flash_unmap (info, 0, offset, cp);
301 return retval;
5653fc33
WD		 302}
303
90447ecb
TK		 304/*-----------------------------------------------------------------------
305 * read a word at a port width address, assume 16bit bus
306 */
307static inline ushort flash_read_word (flash_info_t * info, uint offset)
308{
309 ushort *addr, retval;
310
311 addr = flash_map (info, 0, offset);
312 retval = flash_read16 (addr);
313 flash_unmap (info, 0, offset, addr);
314 return retval;
315}
316
317
5653fc33 318/*-----------------------------------------------------------------------
260421a2 319 * read a long word by picking the least significant byte of each maximum
5653fc33
WD		 320 * port size word. Swap for ppc format.
321 */
3055793b
HS		 322static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
323 uint offset)
5653fc33 324{
bf9e3b38
WD		 325 uchar *addr;
326 ulong retval;
327
328#ifdef DEBUG
329 int x;
330#endif
12d30aa7 331 addr = flash_map (info, sect, offset);
5653fc33 332
bf9e3b38
WD		 333#ifdef DEBUG
334 debug ("long addr is at %p info->portwidth = %d\n", addr,
335 info->portwidth);
336 for (x = 0; x < 4 * info->portwidth; x++) {
12d30aa7 337 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
bf9e3b38
WD		 338 }
339#endif
6d0f6bcf 340#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
12d30aa7
HS		 341 retval = ((flash_read8(addr) << 16) |
342 (flash_read8(addr + info->portwidth) << 24) |
343 (flash_read8(addr + 2 * info->portwidth)) |
344 (flash_read8(addr + 3 * info->portwidth) << 8));
bf9e3b38 345#else
12d30aa7
HS		 346 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
347 (flash_read8(addr + info->portwidth - 1) << 16) |
348 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
349 (flash_read8(addr + 3 * info->portwidth - 1)));
bf9e3b38 350#endif
12d30aa7
HS		 351 flash_unmap(info, sect, offset, addr);
352
bf9e3b38 353 return retval;
5653fc33
WD		 354}
355
be60a902
HS		 356/*
357 * Write a proper sized command to the correct address
81b20ccc 358 */
fa36ae79
SR		 359void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
360 uint offset, u32 cmd)
81b20ccc 361{
7e5b9b47 362
cdbaefb5 363 void *addr;
be60a902 364 cfiword_t cword;
81b20ccc 365
12d30aa7 366 addr = flash_map (info, sect, offset);
be60a902
HS		 367 flash_make_cmd (info, cmd, &cword);
368 switch (info->portwidth) {
369 case FLASH_CFI_8BIT:
cdbaefb5 370 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
be60a902 371 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 372 flash_write8(cword.c, addr);
be60a902
HS		 373 break;
374 case FLASH_CFI_16BIT:
cdbaefb5 375 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
be60a902
HS		 376 cmd, cword.w,
377 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 378 flash_write16(cword.w, addr);
be60a902
HS		 379 break;
380 case FLASH_CFI_32BIT:
cdbaefb5 381 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
be60a902
HS		 382 cmd, cword.l,
383 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 384 flash_write32(cword.l, addr);
be60a902
HS		 385 break;
386 case FLASH_CFI_64BIT:
387#ifdef DEBUG
388 {
389 char str[20];
7e5b9b47 390
be60a902
HS		 391 print_longlong (str, cword.ll);
392
393 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
cdbaefb5 394 addr, cmd, str,
be60a902 395 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
81b20ccc 396 }
be60a902 397#endif
cdbaefb5 398 flash_write64(cword.ll, addr);
be60a902 399 break;
81b20ccc 400 }
be60a902
HS		 401
402 /* Ensure all the instructions are fully finished */
403 sync();
12d30aa7
HS		 404
405 flash_unmap(info, sect, offset, addr);
81b20ccc 406}
be60a902
HS		 407
408static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
81b20ccc 409{
be60a902
HS		 410 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
411 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
81b20ccc 412}
81b20ccc 413
5653fc33
WD		 414/*-----------------------------------------------------------------------
415 */
be60a902
HS		 416static int flash_isequal (flash_info_t * info, flash_sect_t sect,
417 uint offset, uchar cmd)
5653fc33 418{
cdbaefb5 419 void *addr;
be60a902
HS		 420 cfiword_t cword;
421 int retval;
5653fc33 422
12d30aa7 423 addr = flash_map (info, sect, offset);
be60a902 424 flash_make_cmd (info, cmd, &cword);
2662b40c 425
cdbaefb5 426 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
be60a902
HS		 427 switch (info->portwidth) {
428 case FLASH_CFI_8BIT:
cdbaefb5
HS		 429 debug ("is= %x %x\n", flash_read8(addr), cword.c);
430 retval = (flash_read8(addr) == cword.c);
be60a902
HS		 431 break;
432 case FLASH_CFI_16BIT:
cdbaefb5
HS		 433 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
434 retval = (flash_read16(addr) == cword.w);
be60a902
HS		 435 break;
436 case FLASH_CFI_32BIT:
52514699 437 debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l);
cdbaefb5 438 retval = (flash_read32(addr) == cword.l);
be60a902
HS		 439 break;
440 case FLASH_CFI_64BIT:
441#ifdef DEBUG
442 {
443 char str1[20];
444 char str2[20];
81b20ccc 445
cdbaefb5 446 print_longlong (str1, flash_read64(addr));
be60a902
HS		 447 print_longlong (str2, cword.ll);
448 debug ("is= %s %s\n", str1, str2);
5653fc33 449 }
be60a902 450#endif
cdbaefb5 451 retval = (flash_read64(addr) == cword.ll);
be60a902
HS		 452 break;
453 default:
454 retval = 0;
455 break;
456 }
12d30aa7
HS		 457 flash_unmap(info, sect, offset, addr);
458
be60a902
HS		 459 return retval;
460}
79b4cda0 461
be60a902
HS		 462/*-----------------------------------------------------------------------
463 */
464static int flash_isset (flash_info_t * info, flash_sect_t sect,
465 uint offset, uchar cmd)
466{
cdbaefb5 467 void *addr;
be60a902
HS		 468 cfiword_t cword;
469 int retval;
2662b40c 470
12d30aa7 471 addr = flash_map (info, sect, offset);
be60a902
HS		 472 flash_make_cmd (info, cmd, &cword);
473 switch (info->portwidth) {
474 case FLASH_CFI_8BIT:
cdbaefb5 475 retval = ((flash_read8(addr) & cword.c) == cword.c);
be60a902
HS		 476 break;
477 case FLASH_CFI_16BIT:
cdbaefb5 478 retval = ((flash_read16(addr) & cword.w) == cword.w);
be60a902
HS		 479 break;
480 case FLASH_CFI_32BIT:
47cc23cb 481 retval = ((flash_read32(addr) & cword.l) == cword.l);
be60a902
HS		 482 break;
483 case FLASH_CFI_64BIT:
cdbaefb5 484 retval = ((flash_read64(addr) & cword.ll) == cword.ll);
be60a902
HS		 485 break;
486 default:
487 retval = 0;
488 break;
489 }
12d30aa7
HS		 490 flash_unmap(info, sect, offset, addr);
491
be60a902
HS		 492 return retval;
493}
2662b40c 494
be60a902
HS		 495/*-----------------------------------------------------------------------
496 */
497static int flash_toggle (flash_info_t * info, flash_sect_t sect,
498 uint offset, uchar cmd)
499{
cdbaefb5 500 void *addr;
be60a902
HS		 501 cfiword_t cword;
502 int retval;
656658dd 503
12d30aa7 504 addr = flash_map (info, sect, offset);
be60a902
HS		 505 flash_make_cmd (info, cmd, &cword);
506 switch (info->portwidth) {
507 case FLASH_CFI_8BIT:
fb8c061e 508 retval = flash_read8(addr) != flash_read8(addr);
be60a902
HS		 509 break;
510 case FLASH_CFI_16BIT:
fb8c061e 511 retval = flash_read16(addr) != flash_read16(addr);
be60a902
HS		 512 break;
513 case FLASH_CFI_32BIT:
fb8c061e 514 retval = flash_read32(addr) != flash_read32(addr);
be60a902
HS		 515 break;
516 case FLASH_CFI_64BIT:
9abda6ba
WD		 517 retval = ( (flash_read32( addr ) != flash_read32( addr )) ||
518 (flash_read32(addr+4) != flash_read32(addr+4)) );
be60a902
HS		 519 break;
520 default:
521 retval = 0;
522 break;
523 }
12d30aa7
HS		 524 flash_unmap(info, sect, offset, addr);
525
be60a902 526 return retval;
5653fc33
WD		 527}
528
be60a902
HS		 529/*
530 * flash_is_busy - check to see if the flash is busy
531 *
532 * This routine checks the status of the chip and returns true if the
533 * chip is busy.
7680c140 534 */
be60a902 535static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
7680c140 536{
be60a902 537 int retval;
7680c140 538
be60a902 539 switch (info->vendor) {
9c048b52 540 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 541 case CFI_CMDSET_INTEL_STANDARD:
542 case CFI_CMDSET_INTEL_EXTENDED:
543 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
544 break;
545 case CFI_CMDSET_AMD_STANDARD:
546 case CFI_CMDSET_AMD_EXTENDED:
547#ifdef CONFIG_FLASH_CFI_LEGACY
548 case CFI_CMDSET_AMD_LEGACY:
549#endif
550 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
551 break;
552 default:
553 retval = 0;
7680c140 554 }
be60a902
HS		 555 debug ("flash_is_busy: %d\n", retval);
556 return retval;
7680c140
WD		 557}
558
5653fc33 559/*-----------------------------------------------------------------------
be60a902
HS		 560 * wait for XSR.7 to be set. Time out with an error if it does not.
561 * This routine does not set the flash to read-array mode.
5653fc33 562 */
be60a902
HS		 563static int flash_status_check (flash_info_t * info, flash_sect_t sector,
564 ulong tout, char *prompt)
5653fc33 565{
be60a902 566 ulong start;
5653fc33 567
6d0f6bcf 568#if CONFIG_SYS_HZ != 1000
c40c94a3
RA		 569 if ((ulong)CONFIG_SYS_HZ > 100000)
570 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
571 else
572 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
be60a902 573#endif
5653fc33 574
be60a902 575 /* Wait for command completion */
22d6c8fa 576 reset_timer();
be60a902
HS		 577 start = get_timer (0);
578 while (flash_is_busy (info, sector)) {
579 if (get_timer (start) > tout) {
580 printf ("Flash %s timeout at address %lx data %lx\n",
581 prompt, info->start[sector],
582 flash_read_long (info, sector, 0));
583 flash_write_cmd (info, sector, 0, info->cmd_reset);
a90b9575 584 udelay(1);
be60a902 585 return ERR_TIMOUT;
5653fc33 586 }
be60a902 587 udelay (1); /* also triggers watchdog */
5653fc33 588 }
be60a902
HS		 589 return ERR_OK;
590}
5653fc33 591
be60a902
HS		 592/*-----------------------------------------------------------------------
593 * Wait for XSR.7 to be set, if it times out print an error, otherwise
594 * do a full status check.
595 *
596 * This routine sets the flash to read-array mode.
597 */
598static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
599 ulong tout, char *prompt)
600{
601 int retcode;
5653fc33 602
be60a902
HS		 603 retcode = flash_status_check (info, sector, tout, prompt);
604 switch (info->vendor) {
9c048b52 605 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 606 case CFI_CMDSET_INTEL_EXTENDED:
607 case CFI_CMDSET_INTEL_STANDARD:
0d01f66d 608 if ((retcode != ERR_OK)
be60a902
HS		 609 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
610 retcode = ERR_INVAL;
611 printf ("Flash %s error at address %lx\n", prompt,
612 info->start[sector]);
613 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
614 FLASH_STATUS_PSLBS)) {
615 puts ("Command Sequence Error.\n");
616 } else if (flash_isset (info, sector, 0,
617 FLASH_STATUS_ECLBS)) {
618 puts ("Block Erase Error.\n");
619 retcode = ERR_NOT_ERASED;
620 } else if (flash_isset (info, sector, 0,
621 FLASH_STATUS_PSLBS)) {
622 puts ("Locking Error\n");
5653fc33 623 }
be60a902
HS		 624 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
625 puts ("Block locked.\n");
626 retcode = ERR_PROTECTED;
627 }
628 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
629 puts ("Vpp Low Error.\n");
5653fc33 630 }
be60a902 631 flash_write_cmd (info, sector, 0, info->cmd_reset);
a90b9575 632 udelay(1);
be60a902
HS		 633 break;
634 default:
635 break;
5653fc33 636 }
be60a902 637 return retcode;
5653fc33
WD		 638}
639
e5720823
TC		 640static int use_flash_status_poll(flash_info_t *info)
641{
642#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
643 if (info->vendor == CFI_CMDSET_AMD_EXTENDED ||
644 info->vendor == CFI_CMDSET_AMD_STANDARD)
645 return 1;
646#endif
647 return 0;
648}
649
650static int flash_status_poll(flash_info_t *info, void *src, void *dst,
651 ulong tout, char *prompt)
652{
653#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
654 ulong start;
655 int ready;
656
657#if CONFIG_SYS_HZ != 1000
658 if ((ulong)CONFIG_SYS_HZ > 100000)
659 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
660 else
661 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
662#endif
663
664 /* Wait for command completion */
22d6c8fa 665 reset_timer();
e5720823
TC		 666 start = get_timer(0);
667 while (1) {
668 switch (info->portwidth) {
669 case FLASH_CFI_8BIT:
670 ready = flash_read8(dst) == flash_read8(src);
671 break;
672 case FLASH_CFI_16BIT:
673 ready = flash_read16(dst) == flash_read16(src);
674 break;
675 case FLASH_CFI_32BIT:
676 ready = flash_read32(dst) == flash_read32(src);
677 break;
678 case FLASH_CFI_64BIT:
679 ready = flash_read64(dst) == flash_read64(src);
680 break;
681 default:
682 ready = 0;
683 break;
684 }
685 if (ready)
686 break;
687 if (get_timer(start) > tout) {
688 printf("Flash %s timeout at address %lx data %lx\n",
689 prompt, (ulong)dst, (ulong)flash_read8(dst));
690 return ERR_TIMOUT;
691 }
692 udelay(1); /* also triggers watchdog */
693 }
694#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
695 return ERR_OK;
696}
697
5653fc33
WD		 698/*-----------------------------------------------------------------------
699 */
be60a902 700static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
5653fc33 701{
6d0f6bcf 702#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 703 unsigned short w;
704 unsigned int l;
705 unsigned long long ll;
706#endif
5653fc33 707
be60a902
HS		 708 switch (info->portwidth) {
709 case FLASH_CFI_8BIT:
710 cword->c = c;
711 break;
712 case FLASH_CFI_16BIT:
6d0f6bcf 713#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 714 w = c;
715 w <<= 8;
716 cword->w = (cword->w >> 8) | w;
717#else
718 cword->w = (cword->w << 8) | c;
81b20ccc 719#endif
be60a902
HS		 720 break;
721 case FLASH_CFI_32BIT:
6d0f6bcf 722#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 723 l = c;
724 l <<= 24;
725 cword->l = (cword->l >> 8) | l;
726#else
727 cword->l = (cword->l << 8) | c;
728#endif
729 break;
730 case FLASH_CFI_64BIT:
6d0f6bcf 731#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 732 ll = c;
733 ll <<= 56;
734 cword->ll = (cword->ll >> 8) | ll;
735#else
736 cword->ll = (cword->ll << 8) | c;
737#endif
738 break;
260421a2 739 }
be60a902 740}
5653fc33 741
0f8e851e
JG		 742/*
743 * Loop through the sector table starting from the previously found sector.
744 * Searches forwards or backwards, dependent on the passed address.
be60a902
HS		 745 */
746static flash_sect_t find_sector (flash_info_t * info, ulong addr)
747{
0f8e851e 748 static flash_sect_t saved_sector = 0; /* previously found sector */
af567301 749 static flash_info_t *saved_info = 0; /* previously used flash bank */
0f8e851e
JG		 750 flash_sect_t sector = saved_sector;
751
af567301
MK		 752 if ((info != saved_info) || (sector >= info->sector_count))
753 sector = 0;
754
0f8e851e
JG		 755 while ((info->start[sector] < addr)
756 && (sector < info->sector_count - 1))
757 sector++;
758 while ((info->start[sector] > addr) && (sector > 0))
759 /*
760 * also decrements the sector in case of an overshot
761 * in the first loop
762 */
763 sector--;
764
765 saved_sector = sector;
af567301 766 saved_info = info;
be60a902 767 return sector;
5653fc33
WD		 768}
769
770/*-----------------------------------------------------------------------
5653fc33 771 */
be60a902
HS		 772static int flash_write_cfiword (flash_info_t * info, ulong dest,
773 cfiword_t cword)
5653fc33 774{
09ce9921 775 void *dstaddr = (void *)dest;
be60a902 776 int flag;
a7292871
JG		 777 flash_sect_t sect = 0;
778 char sect_found = 0;
5653fc33 779
be60a902
HS		 780 /* Check if Flash is (sufficiently) erased */
781 switch (info->portwidth) {
782 case FLASH_CFI_8BIT:
cdbaefb5 783 flag = ((flash_read8(dstaddr) & cword.c) == cword.c);
be60a902
HS		 784 break;
785 case FLASH_CFI_16BIT:
cdbaefb5 786 flag = ((flash_read16(dstaddr) & cword.w) == cword.w);
be60a902
HS		 787 break;
788 case FLASH_CFI_32BIT:
cdbaefb5 789 flag = ((flash_read32(dstaddr) & cword.l) == cword.l);
be60a902
HS		 790 break;
791 case FLASH_CFI_64BIT:
cdbaefb5 792 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll);
be60a902
HS		 793 break;
794 default:
12d30aa7
HS		 795 flag = 0;
796 break;
5653fc33 797 }
09ce9921 798 if (!flag)
0dc80e27 799 return ERR_NOT_ERASED;
5653fc33 800
be60a902
HS		 801 /* Disable interrupts which might cause a timeout here */
802 flag = disable_interrupts ();
79b4cda0 803
be60a902 804 switch (info->vendor) {
9c048b52 805 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 806 case CFI_CMDSET_INTEL_EXTENDED:
807 case CFI_CMDSET_INTEL_STANDARD:
808 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
809 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
810 break;
811 case CFI_CMDSET_AMD_EXTENDED:
812 case CFI_CMDSET_AMD_STANDARD:
0d01f66d
ES		 813 sect = find_sector(info, dest);
814 flash_unlock_seq (info, sect);
815 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE);
a7292871 816 sect_found = 1;
be60a902 817 break;
b4db4a76
PYC		 818#ifdef CONFIG_FLASH_CFI_LEGACY
819 case CFI_CMDSET_AMD_LEGACY:
820 sect = find_sector(info, dest);
821 flash_unlock_seq (info, 0);
822 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
823 sect_found = 1;
824 break;
825#endif
5653fc33
WD		 826 }
827
be60a902
HS		 828 switch (info->portwidth) {
829 case FLASH_CFI_8BIT:
cdbaefb5 830 flash_write8(cword.c, dstaddr);
be60a902
HS		 831 break;
832 case FLASH_CFI_16BIT:
cdbaefb5 833 flash_write16(cword.w, dstaddr);
be60a902
HS		 834 break;
835 case FLASH_CFI_32BIT:
cdbaefb5 836 flash_write32(cword.l, dstaddr);
be60a902
HS		 837 break;
838 case FLASH_CFI_64BIT:
cdbaefb5 839 flash_write64(cword.ll, dstaddr);
be60a902 840 break;
5653fc33
WD		 841 }
842
be60a902
HS		 843 /* re-enable interrupts if necessary */
844 if (flag)
845 enable_interrupts ();
5653fc33 846
a7292871
JG		 847 if (!sect_found)
848 sect = find_sector (info, dest);
849
e5720823
TC		 850 if (use_flash_status_poll(info))
851 return flash_status_poll(info, &cword, dstaddr,
852 info->write_tout, "write");
853 else
854 return flash_full_status_check(info, sect,
855 info->write_tout, "write");
5653fc33
WD		 856}
857
6d0f6bcf 858#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
5653fc33 859
be60a902
HS		 860static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
861 int len)
5653fc33 862{
be60a902
HS		 863 flash_sect_t sector;
864 int cnt;
865 int retcode;
cdbaefb5 866 void *src = cp;
ec21d5cf 867 void *dst = (void *)dest;
0dc80e27
SR		 868 void *dst2 = dst;
869 int flag = 0;
96ef831f
GL		 870 uint offset = 0;
871 unsigned int shift;
9c048b52 872 uchar write_cmd;
cdbaefb5 873
0dc80e27
SR		 874 switch (info->portwidth) {
875 case FLASH_CFI_8BIT:
96ef831f 876 shift = 0;
0dc80e27
SR		 877 break;
878 case FLASH_CFI_16BIT:
96ef831f 879 shift = 1;
0dc80e27
SR		 880 break;
881 case FLASH_CFI_32BIT:
96ef831f 882 shift = 2;
0dc80e27
SR		 883 break;
884 case FLASH_CFI_64BIT:
96ef831f 885 shift = 3;
0dc80e27
SR		 886 break;
887 default:
888 retcode = ERR_INVAL;
889 goto out_unmap;
890 }
891
96ef831f
GL		 892 cnt = len >> shift;
893
0dc80e27
SR		 894 while ((cnt-- > 0) && (flag == 0)) {
895 switch (info->portwidth) {
896 case FLASH_CFI_8BIT:
897 flag = ((flash_read8(dst2) & flash_read8(src)) ==
898 flash_read8(src));
899 src += 1, dst2 += 1;
900 break;
901 case FLASH_CFI_16BIT:
902 flag = ((flash_read16(dst2) & flash_read16(src)) ==
903 flash_read16(src));
904 src += 2, dst2 += 2;
905 break;
906 case FLASH_CFI_32BIT:
907 flag = ((flash_read32(dst2) & flash_read32(src)) ==
908 flash_read32(src));
909 src += 4, dst2 += 4;
910 break;
911 case FLASH_CFI_64BIT:
912 flag = ((flash_read64(dst2) & flash_read64(src)) ==
913 flash_read64(src));
914 src += 8, dst2 += 8;
915 break;
916 }
917 }
918 if (!flag) {
919 retcode = ERR_NOT_ERASED;
920 goto out_unmap;
921 }
922
923 src = cp;
cdbaefb5 924 sector = find_sector (info, dest);
bf9e3b38
WD		 925
926 switch (info->vendor) {
9c048b52 927 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 928 case CFI_CMDSET_INTEL_STANDARD:
929 case CFI_CMDSET_INTEL_EXTENDED:
9c048b52
VL		 930 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
931 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER;
be60a902 932 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
9c048b52
VL		 933 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS);
934 flash_write_cmd (info, sector, 0, write_cmd);
be60a902
HS		 935 retcode = flash_status_check (info, sector,
936 info->buffer_write_tout,
937 "write to buffer");
938 if (retcode == ERR_OK) {
939 /* reduce the number of loops by the width of
940 * the port */
96ef831f 941 cnt = len >> shift;
93c56f21 942 flash_write_cmd (info, sector, 0, cnt - 1);
be60a902
HS		 943 while (cnt-- > 0) {
944 switch (info->portwidth) {
945 case FLASH_CFI_8BIT:
cdbaefb5
HS		 946 flash_write8(flash_read8(src), dst);
947 src += 1, dst += 1;
be60a902
HS		 948 break;
949 case FLASH_CFI_16BIT:
cdbaefb5
HS		 950 flash_write16(flash_read16(src), dst);
951 src += 2, dst += 2;
be60a902
HS		 952 break;
953 case FLASH_CFI_32BIT:
cdbaefb5
HS		 954 flash_write32(flash_read32(src), dst);
955 src += 4, dst += 4;
be60a902
HS		 956 break;
957 case FLASH_CFI_64BIT:
cdbaefb5
HS		 958 flash_write64(flash_read64(src), dst);
959 src += 8, dst += 8;
be60a902
HS		 960 break;
961 default:
12d30aa7
HS		 962 retcode = ERR_INVAL;
963 goto out_unmap;
be60a902
HS		 964 }
965 }
966 flash_write_cmd (info, sector, 0,
967 FLASH_CMD_WRITE_BUFFER_CONFIRM);
968 retcode = flash_full_status_check (
969 info, sector, info->buffer_write_tout,
970 "buffer write");
971 }
12d30aa7
HS		 972
973 break;
be60a902 974
5653fc33
WD		 975 case CFI_CMDSET_AMD_STANDARD:
976 case CFI_CMDSET_AMD_EXTENDED:
be60a902 977 flash_unlock_seq(info,0);
96ef831f
GL		 978
979#ifdef CONFIG_FLASH_SPANSION_S29WS_N
980 offset = ((unsigned long)dst - info->start[sector]) >> shift;
981#endif
982 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
983 cnt = len >> shift;
7dedefdf 984 flash_write_cmd(info, sector, offset, cnt - 1);
be60a902
HS		 985
986 switch (info->portwidth) {
987 case FLASH_CFI_8BIT:
cdbaefb5
HS		 988 while (cnt-- > 0) {
989 flash_write8(flash_read8(src), dst);
990 src += 1, dst += 1;
991 }
be60a902
HS		 992 break;
993 case FLASH_CFI_16BIT:
cdbaefb5
HS		 994 while (cnt-- > 0) {
995 flash_write16(flash_read16(src), dst);
996 src += 2, dst += 2;
997 }
be60a902
HS		 998 break;
999 case FLASH_CFI_32BIT:
cdbaefb5
HS		 1000 while (cnt-- > 0) {
1001 flash_write32(flash_read32(src), dst);
1002 src += 4, dst += 4;
1003 }
be60a902
HS		 1004 break;
1005 case FLASH_CFI_64BIT:
cdbaefb5
HS		 1006 while (cnt-- > 0) {
1007 flash_write64(flash_read64(src), dst);
1008 src += 8, dst += 8;
1009 }
be60a902
HS		 1010 break;
1011 default:
12d30aa7
HS		 1012 retcode = ERR_INVAL;
1013 goto out_unmap;
be60a902
HS		 1014 }
1015
1016 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
e5720823
TC		 1017 if (use_flash_status_poll(info))
1018 retcode = flash_status_poll(info, src - (1 << shift),
1019 dst - (1 << shift),
1020 info->buffer_write_tout,
1021 "buffer write");
1022 else
1023 retcode = flash_full_status_check(info, sector,
1024 info->buffer_write_tout,
1025 "buffer write");
12d30aa7 1026 break;
be60a902 1027
5653fc33 1028 default:
be60a902 1029 debug ("Unknown Command Set\n");
12d30aa7
HS		 1030 retcode = ERR_INVAL;
1031 break;
5653fc33 1032 }
12d30aa7
HS		 1033
1034out_unmap:
12d30aa7 1035 return retcode;
5653fc33 1036}
6d0f6bcf 1037#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
be60a902 1038
bf9e3b38 1039
5653fc33 1040/*-----------------------------------------------------------------------
5653fc33 1041 */
be60a902 1042int flash_erase (flash_info_t * info, int s_first, int s_last)
5653fc33 1043{
be60a902
HS		 1044 int rcode = 0;
1045 int prot;
1046 flash_sect_t sect;
e5720823 1047 int st;
5653fc33 1048
be60a902
HS		 1049 if (info->flash_id != FLASH_MAN_CFI) {
1050 puts ("Can't erase unknown flash type - aborted\n");
1051 return 1;
1052 }
1053 if ((s_first < 0) || (s_first > s_last)) {
1054 puts ("- no sectors to erase\n");
1055 return 1;
1056 }
2662b40c 1057
be60a902
HS		 1058 prot = 0;
1059 for (sect = s_first; sect <= s_last; ++sect) {
1060 if (info->protect[sect]) {
1061 prot++;
5653fc33
WD		 1062 }
1063 }
be60a902
HS		 1064 if (prot) {
1065 printf ("- Warning: %d protected sectors will not be erased!\n",
1066 prot);
6ea808ef 1067 } else if (flash_verbose) {
be60a902
HS		 1068 putc ('\n');
1069 }
bf9e3b38 1070
bf9e3b38 1071
be60a902
HS		 1072 for (sect = s_first; sect <= s_last; sect++) {
1073 if (info->protect[sect] == 0) { /* not protected */
1074 switch (info->vendor) {
9c048b52 1075 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1076 case CFI_CMDSET_INTEL_STANDARD:
1077 case CFI_CMDSET_INTEL_EXTENDED:
1078 flash_write_cmd (info, sect, 0,
1079 FLASH_CMD_CLEAR_STATUS);
1080 flash_write_cmd (info, sect, 0,
1081 FLASH_CMD_BLOCK_ERASE);
1082 flash_write_cmd (info, sect, 0,
1083 FLASH_CMD_ERASE_CONFIRM);
1084 break;
1085 case CFI_CMDSET_AMD_STANDARD:
1086 case CFI_CMDSET_AMD_EXTENDED:
1087 flash_unlock_seq (info, sect);
1088 flash_write_cmd (info, sect,
1089 info->addr_unlock1,
1090 AMD_CMD_ERASE_START);
1091 flash_unlock_seq (info, sect);
1092 flash_write_cmd (info, sect, 0,
1093 AMD_CMD_ERASE_SECTOR);
1094 break;
1095#ifdef CONFIG_FLASH_CFI_LEGACY
1096 case CFI_CMDSET_AMD_LEGACY:
1097 flash_unlock_seq (info, 0);
1098 flash_write_cmd (info, 0, info->addr_unlock1,
1099 AMD_CMD_ERASE_START);
1100 flash_unlock_seq (info, 0);
1101 flash_write_cmd (info, sect, 0,
1102 AMD_CMD_ERASE_SECTOR);
1103 break;
1104#endif
1105 default:
1106 debug ("Unkown flash vendor %d\n",
1107 info->vendor);
1108 break;
bf9e3b38 1109 }
be60a902 1110
e5720823
TC		 1111 if (use_flash_status_poll(info)) {
1112 cfiword_t cword = (cfiword_t)0xffffffffffffffffULL;
1113 void *dest;
1114 dest = flash_map(info, sect, 0);
1115 st = flash_status_poll(info, &cword, dest,
1116 info->erase_blk_tout, "erase");
1117 flash_unmap(info, sect, 0, dest);
1118 } else
1119 st = flash_full_status_check(info, sect,
1120 info->erase_blk_tout,
1121 "erase");
1122 if (st)
be60a902 1123 rcode = 1;
e5720823 1124 else if (flash_verbose)
be60a902 1125 putc ('.');
5653fc33 1126 }
5653fc33 1127 }
6ea808ef
PZ		 1128
1129 if (flash_verbose)
1130 puts (" done\n");
1131
be60a902 1132 return rcode;
5653fc33 1133}
bf9e3b38 1134
70084df7
SR		 1135#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
1136static int sector_erased(flash_info_t *info, int i)
1137{
1138 int k;
1139 int size;
4d2ca9d6 1140 u32 *flash;
70084df7
SR		 1141
1142 /*
1143 * Check if whole sector is erased
1144 */
1145 size = flash_sector_size(info, i);
4d2ca9d6 1146 flash = (u32 *)info->start[i];
70084df7
SR		 1147 /* divide by 4 for longword access */
1148 size = size >> 2;
1149
1150 for (k = 0; k < size; k++) {
4d2ca9d6 1151 if (flash_read32(flash++) != 0xffffffff)
70084df7
SR		 1152 return 0; /* not erased */
1153 }
1154
1155 return 1; /* erased */
1156}
1157#endif /* CONFIG_SYS_FLASH_EMPTY_INFO */
1158
be60a902 1159void flash_print_info (flash_info_t * info)
5653fc33 1160{
be60a902 1161 int i;
4d13cbad 1162
be60a902
HS		 1163 if (info->flash_id != FLASH_MAN_CFI) {
1164 puts ("missing or unknown FLASH type\n");
1165 return;
1166 }
1167
eddf52b5 1168 printf ("%s flash (%d x %d)",
be60a902
HS		 1169 info->name,
1170 (info->portwidth << 3), (info->chipwidth << 3));
1171 if (info->size < 1024*1024)
1172 printf (" Size: %ld kB in %d Sectors\n",
1173 info->size >> 10, info->sector_count);
1174 else
1175 printf (" Size: %ld MB in %d Sectors\n",
1176 info->size >> 20, info->sector_count);
1177 printf (" ");
1178 switch (info->vendor) {
9c048b52
VL		 1179 case CFI_CMDSET_INTEL_PROG_REGIONS:
1180 printf ("Intel Prog Regions");
1181 break;
be60a902
HS		 1182 case CFI_CMDSET_INTEL_STANDARD:
1183 printf ("Intel Standard");
1184 break;
1185 case CFI_CMDSET_INTEL_EXTENDED:
1186 printf ("Intel Extended");
1187 break;
1188 case CFI_CMDSET_AMD_STANDARD:
1189 printf ("AMD Standard");
1190 break;
1191 case CFI_CMDSET_AMD_EXTENDED:
1192 printf ("AMD Extended");
1193 break;
1194#ifdef CONFIG_FLASH_CFI_LEGACY
1195 case CFI_CMDSET_AMD_LEGACY:
1196 printf ("AMD Legacy");
1197 break;
4d13cbad 1198#endif
be60a902
HS		 1199 default:
1200 printf ("Unknown (%d)", info->vendor);
1201 break;
1202 }
d77c7ac4
PDM		 1203 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x",
1204 info->manufacturer_id);
1205 printf (info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
1206 info->device_id);
5b448adb
HS		 1207 if ((info->device_id & 0xff) == 0x7E) {
1208 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
1209 info->device_id2);
be60a902
HS		 1210 }
1211 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
1212 info->erase_blk_tout,
1213 info->write_tout);
1214 if (info->buffer_size > 1) {
1215 printf (" Buffer write timeout: %ld ms, "
1216 "buffer size: %d bytes\n",
1217 info->buffer_write_tout,
1218 info->buffer_size);
5653fc33 1219 }
5653fc33 1220
be60a902
HS		 1221 puts ("\n Sector Start Addresses:");
1222 for (i = 0; i < info->sector_count; ++i) {
2e97394a 1223 if (ctrlc())
70084df7 1224 break;
be60a902 1225 if ((i % 5) == 0)
70084df7 1226 putc('\n');
6d0f6bcf 1227#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
be60a902
HS		 1228 /* print empty and read-only info */
1229 printf (" %08lX %c %s ",
1230 info->start[i],
70084df7 1231 sector_erased(info, i) ? 'E' : ' ',
be60a902 1232 info->protect[i] ? "RO" : " ");
6d0f6bcf 1233#else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */
be60a902
HS		 1234 printf (" %08lX %s ",
1235 info->start[i],
1236 info->protect[i] ? "RO" : " ");
bf9e3b38 1237#endif
be60a902
HS		 1238 }
1239 putc ('\n');
1240 return;
5653fc33
WD		 1241}
1242
9a042e9c
JVB		 1243/*-----------------------------------------------------------------------
1244 * This is used in a few places in write_buf() to show programming
1245 * progress. Making it a function is nasty because it needs to do side
1246 * effect updates to digit and dots. Repeated code is nasty too, so
1247 * we define it once here.
1248 */
f0105727
SR		 1249#ifdef CONFIG_FLASH_SHOW_PROGRESS
1250#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
6ea808ef
PZ		 1251 if (flash_verbose) { \
1252 dots -= dots_sub; \
1253 if ((scale > 0) && (dots <= 0)) { \
1254 if ((digit % 5) == 0) \
1255 printf ("%d", digit / 5); \
1256 else \
1257 putc ('.'); \
1258 digit--; \
1259 dots += scale; \
1260 } \
9a042e9c 1261 }
f0105727
SR		 1262#else
1263#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1264#endif
9a042e9c 1265
be60a902
HS		 1266/*-----------------------------------------------------------------------
1267 * Copy memory to flash, returns:
1268 * 0 - OK
1269 * 1 - write timeout
1270 * 2 - Flash not erased
5653fc33 1271 */
be60a902 1272int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
5653fc33 1273{
be60a902 1274 ulong wp;
12d30aa7 1275 uchar *p;
be60a902 1276 int aln;
5653fc33 1277 cfiword_t cword;
be60a902 1278 int i, rc;
6d0f6bcf 1279#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902 1280 int buffered_size;
5653fc33 1281#endif
9a042e9c
JVB		 1282#ifdef CONFIG_FLASH_SHOW_PROGRESS
1283 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1284 int scale = 0;
1285 int dots = 0;
1286
1287 /*
1288 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1289 */
1290 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1291 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1292 CONFIG_FLASH_SHOW_PROGRESS);
1293 }
1294#endif
1295
be60a902
HS		 1296 /* get lower aligned address */
1297 wp = (addr & ~(info->portwidth - 1));
3a197b2f 1298
be60a902
HS		 1299 /* handle unaligned start */
1300 if ((aln = addr - wp) != 0) {
1301 cword.l = 0;
09ce9921 1302 p = (uchar *)wp;
12d30aa7
HS		 1303 for (i = 0; i < aln; ++i)
1304 flash_add_byte (info, &cword, flash_read8(p + i));
5653fc33 1305
be60a902
HS		 1306 for (; (i < info->portwidth) && (cnt > 0); i++) {
1307 flash_add_byte (info, &cword, *src++);
1308 cnt--;
be60a902 1309 }
12d30aa7
HS		 1310 for (; (cnt == 0) && (i < info->portwidth); ++i)
1311 flash_add_byte (info, &cword, flash_read8(p + i));
1312
1313 rc = flash_write_cfiword (info, wp, cword);
12d30aa7 1314 if (rc != 0)
be60a902 1315 return rc;
12d30aa7
HS		 1316
1317 wp += i;
f0105727 1318 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1319 }
1320
1321 /* handle the aligned part */
6d0f6bcf 1322#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902
HS		 1323 buffered_size = (info->portwidth / info->chipwidth);
1324 buffered_size *= info->buffer_size;
1325 while (cnt >= info->portwidth) {
1326 /* prohibit buffer write when buffer_size is 1 */
1327 if (info->buffer_size == 1) {
1328 cword.l = 0;
1329 for (i = 0; i < info->portwidth; i++)
1330 flash_add_byte (info, &cword, *src++);
1331 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1332 return rc;
1333 wp += info->portwidth;
1334 cnt -= info->portwidth;
1335 continue;
1336 }
1337
1338 /* write buffer until next buffered_size aligned boundary */
1339 i = buffered_size - (wp % buffered_size);
1340 if (i > cnt)
1341 i = cnt;
1342 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
1343 return rc;
1344 i -= i & (info->portwidth - 1);
1345 wp += i;
1346 src += i;
1347 cnt -= i;
f0105727 1348 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1349 }
1350#else
1351 while (cnt >= info->portwidth) {
1352 cword.l = 0;
1353 for (i = 0; i < info->portwidth; i++) {
1354 flash_add_byte (info, &cword, *src++);
1355 }
1356 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1357 return rc;
1358 wp += info->portwidth;
1359 cnt -= info->portwidth;
f0105727 1360 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
be60a902 1361 }
6d0f6bcf 1362#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
9a042e9c 1363
be60a902
HS		 1364 if (cnt == 0) {
1365 return (0);
1366 }
1367
1368 /*
1369 * handle unaligned tail bytes
1370 */
1371 cword.l = 0;
09ce9921 1372 p = (uchar *)wp;
12d30aa7 1373 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
be60a902
HS		 1374 flash_add_byte (info, &cword, *src++);
1375 --cnt;
1376 }
12d30aa7
HS		 1377 for (; i < info->portwidth; ++i)
1378 flash_add_byte (info, &cword, flash_read8(p + i));
be60a902
HS		 1379
1380 return flash_write_cfiword (info, wp, cword);
5653fc33 1381}
bf9e3b38 1382
5653fc33
WD		 1383/*-----------------------------------------------------------------------
1384 */
6d0f6bcf 1385#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902
HS		 1386
1387int flash_real_protect (flash_info_t * info, long sector, int prot)
5653fc33 1388{
be60a902 1389 int retcode = 0;
5653fc33 1390
bc9019e1
RC		 1391 switch (info->vendor) {
1392 case CFI_CMDSET_INTEL_PROG_REGIONS:
1393 case CFI_CMDSET_INTEL_STANDARD:
9e8e63cc 1394 case CFI_CMDSET_INTEL_EXTENDED:
54652991
PDM		 1395 /*
1396 * see errata called
1397 * "Numonyx Axcell P33/P30 Specification Update" :)
1398 */
1399 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID);
1400 if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT,
1401 prot)) {
1402 /*
1403 * cmd must come before FLASH_CMD_PROTECT + 20us
1404 * Disable interrupts which might cause a timeout here.
1405 */
1406 int flag = disable_interrupts ();
1407 unsigned short cmd;
1408
1409 if (prot)
1410 cmd = FLASH_CMD_PROTECT_SET;
1411 else
1412 cmd = FLASH_CMD_PROTECT_CLEAR;
1413
bc9019e1 1414 flash_write_cmd (info, sector, 0,
54652991
PDM		 1415 FLASH_CMD_PROTECT);
1416 flash_write_cmd (info, sector, 0, cmd);
1417 /* re-enable interrupts if necessary */
1418 if (flag)
1419 enable_interrupts ();
1420 }
bc9019e1
RC		 1421 break;
1422 case CFI_CMDSET_AMD_EXTENDED:
1423 case CFI_CMDSET_AMD_STANDARD:
bc9019e1
RC		 1424 /* U-Boot only checks the first byte */
1425 if (info->manufacturer_id == (uchar)ATM_MANUFACT) {
1426 if (prot) {
1427 flash_unlock_seq (info, 0);
1428 flash_write_cmd (info, 0,
1429 info->addr_unlock1,
1430 ATM_CMD_SOFTLOCK_START);
1431 flash_unlock_seq (info, 0);
1432 flash_write_cmd (info, sector, 0,
1433 ATM_CMD_LOCK_SECT);
1434 } else {
1435 flash_write_cmd (info, 0,
1436 info->addr_unlock1,
1437 AMD_CMD_UNLOCK_START);
1438 if (info->device_id == ATM_ID_BV6416)
1439 flash_write_cmd (info, sector,
1440 0, ATM_CMD_UNLOCK_SECT);
1441 }
1442 }
1443 break;
4e00acde
TL		 1444#ifdef CONFIG_FLASH_CFI_LEGACY
1445 case CFI_CMDSET_AMD_LEGACY:
1446 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1447 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1448 if (prot)
1449 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
1450 else
1451 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
1452#endif
bc9019e1 1453 };
bf9e3b38 1454
df4e813b
SR		 1455 /*
1456 * Flash needs to be in status register read mode for
1457 * flash_full_status_check() to work correctly
1458 */
1459 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
be60a902
HS		 1460 if ((retcode =
1461 flash_full_status_check (info, sector, info->erase_blk_tout,
1462 prot ? "protect" : "unprotect")) == 0) {
bf9e3b38 1463
be60a902
HS		 1464 info->protect[sector] = prot;
1465
1466 /*
1467 * On some of Intel's flash chips (marked via legacy_unlock)
1468 * unprotect unprotects all locking.
1469 */
1470 if ((prot == 0) && (info->legacy_unlock)) {
1471 flash_sect_t i;
1472
1473 for (i = 0; i < info->sector_count; i++) {
1474 if (info->protect[i])
1475 flash_real_protect (info, i, 1);
1476 }
5653fc33 1477 }
5653fc33 1478 }
be60a902 1479 return retcode;
5653fc33 1480}
bf9e3b38 1481
5653fc33 1482/*-----------------------------------------------------------------------
be60a902 1483 * flash_read_user_serial - read the OneTimeProgramming cells
5653fc33 1484 */
be60a902
HS		 1485void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
1486 int len)
5653fc33 1487{
be60a902
HS		 1488 uchar *src;
1489 uchar *dst;
bf9e3b38 1490
be60a902 1491 dst = buffer;
12d30aa7 1492 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION);
be60a902
HS		 1493 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1494 memcpy (dst, src + offset, len);
1495 flash_write_cmd (info, 0, 0, info->cmd_reset);
a90b9575 1496 udelay(1);
12d30aa7 1497 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
5653fc33
WD		 1498}
1499
be60a902
HS		 1500/*
1501 * flash_read_factory_serial - read the device Id from the protection area
5653fc33 1502 */
be60a902
HS		 1503void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
1504 int len)
5653fc33 1505{
be60a902 1506 uchar *src;
bf9e3b38 1507
12d30aa7 1508 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
be60a902
HS		 1509 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1510 memcpy (buffer, src + offset, len);
1511 flash_write_cmd (info, 0, 0, info->cmd_reset);
a90b9575 1512 udelay(1);
12d30aa7 1513 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
5653fc33
WD		 1514}
1515
6d0f6bcf 1516#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 1517
0ddf06dd
HS		 1518/*-----------------------------------------------------------------------
1519 * Reverse the order of the erase regions in the CFI QRY structure.
1520 * This is needed for chips that are either a) correctly detected as
1521 * top-boot, or b) buggy.
1522 */
1523static void cfi_reverse_geometry(struct cfi_qry *qry)
1524{
1525 unsigned int i, j;
1526 u32 tmp;
1527
1528 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
1529 tmp = qry->erase_region_info[i];
1530 qry->erase_region_info[i] = qry->erase_region_info[j];
1531 qry->erase_region_info[j] = tmp;
1532 }
1533}
be60a902 1534
260421a2
SR		 1535/*-----------------------------------------------------------------------
1536 * read jedec ids from device and set corresponding fields in info struct
1537 *
1538 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1539 *
0ddf06dd
HS		 1540 */
1541static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1542{
1543 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
a90b9575 1544 udelay(1);
0ddf06dd
HS		 1545 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1546 udelay(1000); /* some flash are slow to respond */
1547 info->manufacturer_id = flash_read_uchar (info,
1548 FLASH_OFFSET_MANUFACTURER_ID);
d77c7ac4
PDM		 1549 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ?
1550 flash_read_word (info, FLASH_OFFSET_DEVICE_ID) :
1551 flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID);
0ddf06dd
HS		 1552 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1553}
1554
1555static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1556{
1557 info->cmd_reset = FLASH_CMD_RESET;
1558
1559 cmdset_intel_read_jedec_ids(info);
1560 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1561
6d0f6bcf 1562#ifdef CONFIG_SYS_FLASH_PROTECTION
0ddf06dd
HS		 1563 /* read legacy lock/unlock bit from intel flash */
1564 if (info->ext_addr) {
1565 info->legacy_unlock = flash_read_uchar (info,
1566 info->ext_addr + 5) & 0x08;
1567 }
1568#endif
1569
1570 return 0;
1571}
1572
1573static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1574{
3a7b2c21
NG		 1575 ushort bankId = 0;
1576 uchar manuId;
1577
0ddf06dd
HS		 1578 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1579 flash_unlock_seq(info, 0);
1580 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1581 udelay(1000); /* some flash are slow to respond */
90447ecb 1582
3a7b2c21
NG		 1583 manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID);
1584 /* JEDEC JEP106Z specifies ID codes up to bank 7 */
1585 while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) {
1586 bankId += 0x100;
1587 manuId = flash_read_uchar (info,
1588 bankId | FLASH_OFFSET_MANUFACTURER_ID);
1589 }
1590 info->manufacturer_id = manuId;
90447ecb
TK		 1591
1592 switch (info->chipwidth){
1593 case FLASH_CFI_8BIT:
1594 info->device_id = flash_read_uchar (info,
1595 FLASH_OFFSET_DEVICE_ID);
1596 if (info->device_id == 0x7E) {
1597 /* AMD 3-byte (expanded) device ids */
1598 info->device_id2 = flash_read_uchar (info,
1599 FLASH_OFFSET_DEVICE_ID2);
1600 info->device_id2 <<= 8;
1601 info->device_id2 |= flash_read_uchar (info,
1602 FLASH_OFFSET_DEVICE_ID3);
1603 }
1604 break;
1605 case FLASH_CFI_16BIT:
1606 info->device_id = flash_read_word (info,
1607 FLASH_OFFSET_DEVICE_ID);
5b448adb
HS		 1608 if ((info->device_id & 0xff) == 0x7E) {
1609 /* AMD 3-byte (expanded) device ids */
1610 info->device_id2 = flash_read_uchar (info,
1611 FLASH_OFFSET_DEVICE_ID2);
1612 info->device_id2 <<= 8;
1613 info->device_id2 |= flash_read_uchar (info,
1614 FLASH_OFFSET_DEVICE_ID3);
1615 }
90447ecb
TK		 1616 break;
1617 default:
1618 break;
0ddf06dd
HS		 1619 }
1620 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
a90b9575 1621 udelay(1);
0ddf06dd
HS		 1622}
1623
1624static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1625{
1626 info->cmd_reset = AMD_CMD_RESET;
1627
1628 cmdset_amd_read_jedec_ids(info);
1629 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1630
0ddf06dd
HS		 1631 return 0;
1632}
1633
1634#ifdef CONFIG_FLASH_CFI_LEGACY
260421a2
SR		 1635static void flash_read_jedec_ids (flash_info_t * info)
1636{
1637 info->manufacturer_id = 0;
1638 info->device_id = 0;
1639 info->device_id2 = 0;
1640
1641 switch (info->vendor) {
9c048b52 1642 case CFI_CMDSET_INTEL_PROG_REGIONS:
260421a2
SR		 1643 case CFI_CMDSET_INTEL_STANDARD:
1644 case CFI_CMDSET_INTEL_EXTENDED:
8225d1e3 1645 cmdset_intel_read_jedec_ids(info);
260421a2
SR		 1646 break;
1647 case CFI_CMDSET_AMD_STANDARD:
1648 case CFI_CMDSET_AMD_EXTENDED:
8225d1e3 1649 cmdset_amd_read_jedec_ids(info);
260421a2
SR		 1650 break;
1651 default:
1652 break;
1653 }
1654}
1655
5653fc33 1656/*-----------------------------------------------------------------------
be60a902
HS		 1657 * Call board code to request info about non-CFI flash.
1658 * board_flash_get_legacy needs to fill in at least:
1659 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
7e5b9b47 1660 */
09ce9921 1661static int flash_detect_legacy(phys_addr_t base, int banknum)
5653fc33 1662{
be60a902 1663 flash_info_t *info = &flash_info[banknum];
7e5b9b47 1664
be60a902
HS		 1665 if (board_flash_get_legacy(base, banknum, info)) {
1666 /* board code may have filled info completely. If not, we
1667 use JEDEC ID probing. */
1668 if (!info->vendor) {
1669 int modes[] = {
1670 CFI_CMDSET_AMD_STANDARD,
1671 CFI_CMDSET_INTEL_STANDARD
1672 };
1673 int i;
7e5b9b47 1674
be60a902
HS		 1675 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
1676 info->vendor = modes[i];
09ce9921
BB		 1677 info->start[0] =
1678 (ulong)map_physmem(base,
e1fb6d0d 1679 info->portwidth,
09ce9921 1680 MAP_NOCACHE);
be60a902
HS		 1681 if (info->portwidth == FLASH_CFI_8BIT
1682 && info->interface == FLASH_CFI_X8X16) {
1683 info->addr_unlock1 = 0x2AAA;
1684 info->addr_unlock2 = 0x5555;
1685 } else {
1686 info->addr_unlock1 = 0x5555;
1687 info->addr_unlock2 = 0x2AAA;
1688 }
1689 flash_read_jedec_ids(info);
1690 debug("JEDEC PROBE: ID %x %x %x\n",
1691 info->manufacturer_id,
1692 info->device_id,
1693 info->device_id2);
09ce9921 1694 if (jedec_flash_match(info, info->start[0]))
be60a902 1695 break;
09ce9921 1696 else
e1fb6d0d 1697 unmap_physmem((void *)info->start[0],
09ce9921 1698 MAP_NOCACHE);
be60a902
HS		 1699 }
1700 }
1701
1702 switch(info->vendor) {
9c048b52 1703 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1704 case CFI_CMDSET_INTEL_STANDARD:
1705 case CFI_CMDSET_INTEL_EXTENDED:
1706 info->cmd_reset = FLASH_CMD_RESET;
1707 break;
1708 case CFI_CMDSET_AMD_STANDARD:
1709 case CFI_CMDSET_AMD_EXTENDED:
1710 case CFI_CMDSET_AMD_LEGACY:
1711 info->cmd_reset = AMD_CMD_RESET;
1712 break;
1713 }
1714 info->flash_id = FLASH_MAN_CFI;
1715 return 1;
1716 }
1717 return 0; /* use CFI */
1718}
1719#else
09ce9921 1720static inline int flash_detect_legacy(phys_addr_t base, int banknum)
be60a902
HS		 1721{
1722 return 0; /* use CFI */
1723}
1724#endif
1725
1726/*-----------------------------------------------------------------------
1727 * detect if flash is compatible with the Common Flash Interface (CFI)
1728 * http://www.jedec.org/download/search/jesd68.pdf
1729 */
e23741f4
HS		 1730static void flash_read_cfi (flash_info_t *info, void *buf,
1731 unsigned int start, size_t len)
1732{
1733 u8 *p = buf;
1734 unsigned int i;
1735
1736 for (i = 0; i < len; i++)
1737 p[i] = flash_read_uchar(info, start + i);
1738}
1739
fa36ae79
SR		 1740void __flash_cmd_reset(flash_info_t *info)
1741{
1742 /*
1743 * We do not yet know what kind of commandset to use, so we issue
1744 * the reset command in both Intel and AMD variants, in the hope
1745 * that AMD flash roms ignore the Intel command.
1746 */
1747 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
a90b9575 1748 udelay(1);
fa36ae79
SR		 1749 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1750}
1751void flash_cmd_reset(flash_info_t *info)
1752 __attribute__((weak,alias("__flash_cmd_reset")));
1753
e23741f4 1754static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
be60a902
HS		 1755{
1756 int cfi_offset;
1757
fa36ae79
SR		 1758 /* Issue FLASH reset command */
1759 flash_cmd_reset(info);
1ba639da 1760
be60a902
HS		 1761 for (cfi_offset=0;
1762 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);
1763 cfi_offset++) {
1764 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
1765 FLASH_CMD_CFI);
1766 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
1767 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
1768 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
e23741f4
HS		 1769 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1770 sizeof(struct cfi_qry));
1771 info->interface = le16_to_cpu(qry->interface_desc);
1772
be60a902
HS		 1773 info->cfi_offset = flash_offset_cfi[cfi_offset];
1774 debug ("device interface is %d\n",
1775 info->interface);
1776 debug ("found port %d chip %d ",
1777 info->portwidth, info->chipwidth);
1778 debug ("port %d bits chip %d bits\n",
1779 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1780 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1781
1782 /* calculate command offsets as in the Linux driver */
1783 info->addr_unlock1 = 0x555;
7e5b9b47
HS		 1784 info->addr_unlock2 = 0x2aa;
1785
1786 /*
1787 * modify the unlock address if we are
1788 * in compatibility mode
1789 */
1790 if ( /* x8/x16 in x8 mode */
1791 ((info->chipwidth == FLASH_CFI_BY8) &&
1792 (info->interface == FLASH_CFI_X8X16)) ||
1793 /* x16/x32 in x16 mode */
1794 ((info->chipwidth == FLASH_CFI_BY16) &&
1795 (info->interface == FLASH_CFI_X16X32)))
1796 {
1797 info->addr_unlock1 = 0xaaa;
1798 info->addr_unlock2 = 0x555;
1799 }
1800
1801 info->name = "CFI conformant";
1802 return 1;
1803 }
1804 }
1805
1806 return 0;
1807}
1808
e23741f4 1809static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
7e5b9b47 1810{
bf9e3b38
WD		 1811 debug ("flash detect cfi\n");
1812
6d0f6bcf 1813 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
bf9e3b38
WD		 1814 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1815 for (info->chipwidth = FLASH_CFI_BY8;
1816 info->chipwidth <= info->portwidth;
7e5b9b47 1817 info->chipwidth <<= 1)
e23741f4 1818 if (__flash_detect_cfi(info, qry))
7e5b9b47 1819 return 1;
5653fc33 1820 }
bf9e3b38 1821 debug ("not found\n");
5653fc33
WD		 1822 return 0;
1823}
bf9e3b38 1824
467bcee1
HS		 1825/*
1826 * Manufacturer-specific quirks. Add workarounds for geometry
1827 * reversal, etc. here.
1828 */
1829static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
1830{
1831 /* check if flash geometry needs reversal */
1832 if (qry->num_erase_regions > 1) {
1833 /* reverse geometry if top boot part */
1834 if (info->cfi_version < 0x3131) {
1835 /* CFI < 1.1, try to guess from device id */
1836 if ((info->device_id & 0x80) != 0)
1837 cfi_reverse_geometry(qry);
1838 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1839 /* CFI >= 1.1, deduct from top/bottom flag */
1840 /* note: ext_addr is valid since cfi_version > 0 */
1841 cfi_reverse_geometry(qry);
1842 }
1843 }
1844}
1845
1846static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
1847{
1848 int reverse_geometry = 0;
1849
1850 /* Check the "top boot" bit in the PRI */
1851 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
1852 reverse_geometry = 1;
1853
1854 /* AT49BV6416(T) list the erase regions in the wrong order.
1855 * However, the device ID is identical with the non-broken
cb82a532 1856 * AT49BV642D they differ in the high byte.
467bcee1 1857 */
467bcee1
HS		 1858 if (info->device_id == 0xd6 || info->device_id == 0xd2)
1859 reverse_geometry = !reverse_geometry;
467bcee1
HS		 1860
1861 if (reverse_geometry)
1862 cfi_reverse_geometry(qry);
1863}
1864
e8eac437
RR		 1865static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
1866{
1867 /* check if flash geometry needs reversal */
1868 if (qry->num_erase_regions > 1) {
1869 /* reverse geometry if top boot part */
1870 if (info->cfi_version < 0x3131) {
6a011ce8
MF		 1871 /* CFI < 1.1, guess by device id */
1872 if (info->device_id == 0x22CA || /* M29W320DT */
1873 info->device_id == 0x2256 || /* M29W320ET */
1874 info->device_id == 0x22D7) { /* M29W800DT */
e8eac437
RR		 1875 cfi_reverse_geometry(qry);
1876 }
1877 }
1878 }
1879}
1880
5653fc33
WD		 1881/*
1882 * The following code cannot be run from FLASH!
1883 *
1884 */
34bbb8fb 1885ulong flash_get_size (phys_addr_t base, int banknum)
5653fc33 1886{
bf9e3b38 1887 flash_info_t *info = &flash_info[banknum];
5653fc33
WD		 1888 int i, j;
1889 flash_sect_t sect_cnt;
09ce9921 1890 phys_addr_t sector;
5653fc33
WD		 1891 unsigned long tmp;
1892 int size_ratio;
1893 uchar num_erase_regions;
bf9e3b38
WD		 1894 int erase_region_size;
1895 int erase_region_count;
e23741f4 1896 struct cfi_qry qry;
34bbb8fb 1897 unsigned long max_size;
260421a2 1898
f979690e
KG		 1899 memset(&qry, 0, sizeof(qry));
1900
260421a2
SR		 1901 info->ext_addr = 0;
1902 info->cfi_version = 0;
6d0f6bcf 1903#ifdef CONFIG_SYS_FLASH_PROTECTION
2662b40c
SR		 1904 info->legacy_unlock = 0;
1905#endif
5653fc33 1906
09ce9921 1907 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
5653fc33 1908
e23741f4
HS		 1909 if (flash_detect_cfi (info, &qry)) {
1910 info->vendor = le16_to_cpu(qry.p_id);
1911 info->ext_addr = le16_to_cpu(qry.p_adr);
1912 num_erase_regions = qry.num_erase_regions;
1913
260421a2
SR		 1914 if (info->ext_addr) {
1915 info->cfi_version = (ushort) flash_read_uchar (info,
1916 info->ext_addr + 3) << 8;
1917 info->cfi_version |= (ushort) flash_read_uchar (info,
1918 info->ext_addr + 4);
1919 }
0ddf06dd 1920
bf9e3b38 1921#ifdef DEBUG
e23741f4 1922 flash_printqry (&qry);
bf9e3b38 1923#endif
0ddf06dd 1924
bf9e3b38 1925 switch (info->vendor) {
9c048b52 1926 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 1927 case CFI_CMDSET_INTEL_STANDARD:
1928 case CFI_CMDSET_INTEL_EXTENDED:
0ddf06dd 1929 cmdset_intel_init(info, &qry);
5653fc33
WD		 1930 break;
1931 case CFI_CMDSET_AMD_STANDARD:
1932 case CFI_CMDSET_AMD_EXTENDED:
0ddf06dd 1933 cmdset_amd_init(info, &qry);
5653fc33 1934 break;
0ddf06dd
HS		 1935 default:
1936 printf("CFI: Unknown command set 0x%x\n",
1937 info->vendor);
1938 /*
1939 * Unfortunately, this means we don't know how
1940 * to get the chip back to Read mode. Might
1941 * as well try an Intel-style reset...
1942 */
1943 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1944 return 0;
5653fc33 1945 }
cd37d9e6 1946
467bcee1
HS		 1947 /* Do manufacturer-specific fixups */
1948 switch (info->manufacturer_id) {
2c9f48af
MS		 1949 case 0x0001: /* AMD */
1950 case 0x0037: /* AMIC */
467bcee1
HS		 1951 flash_fixup_amd(info, &qry);
1952 break;
1953 case 0x001f:
1954 flash_fixup_atmel(info, &qry);
1955 break;
e8eac437
RR		 1956 case 0x0020:
1957 flash_fixup_stm(info, &qry);
1958 break;
467bcee1
HS		 1959 }
1960
bf9e3b38 1961 debug ("manufacturer is %d\n", info->vendor);
260421a2
SR		 1962 debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
1963 debug ("device id is 0x%x\n", info->device_id);
1964 debug ("device id2 is 0x%x\n", info->device_id2);
1965 debug ("cfi version is 0x%04x\n", info->cfi_version);
1966
5653fc33 1967 size_ratio = info->portwidth / info->chipwidth;
bf9e3b38
WD		 1968 /* if the chip is x8/x16 reduce the ratio by half */
1969 if ((info->interface == FLASH_CFI_X8X16)
1970 && (info->chipwidth == FLASH_CFI_BY8)) {
1971 size_ratio >>= 1;
1972 }
bf9e3b38
WD		 1973 debug ("size_ratio %d port %d bits chip %d bits\n",
1974 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1975 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
ec50a8e3
IY		 1976 info->size = 1 << qry.dev_size;
1977 /* multiply the size by the number of chips */
1978 info->size *= size_ratio;
34bbb8fb 1979 max_size = cfi_flash_bank_size(banknum);
ec50a8e3
IY		 1980 if (max_size && (info->size > max_size)) {
1981 debug("[truncated from %ldMiB]", info->size >> 20);
1982 info->size = max_size;
1983 }
bf9e3b38 1984 debug ("found %d erase regions\n", num_erase_regions);
5653fc33
WD		 1985 sect_cnt = 0;
1986 sector = base;
bf9e3b38
WD		 1987 for (i = 0; i < num_erase_regions; i++) {
1988 if (i > NUM_ERASE_REGIONS) {
028ab6b5
WD		 1989 printf ("%d erase regions found, only %d used\n",
1990 num_erase_regions, NUM_ERASE_REGIONS);
5653fc33
WD		 1991 break;
1992 }
e23741f4 1993
0ddf06dd
HS		 1994 tmp = le32_to_cpu(qry.erase_region_info[i]);
1995 debug("erase region %u: 0x%08lx\n", i, tmp);
e23741f4
HS		 1996
1997 erase_region_count = (tmp & 0xffff) + 1;
1998 tmp >>= 16;
bf9e3b38
WD		 1999 erase_region_size =
2000 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
4c0d4c3b 2001 debug ("erase_region_count = %d erase_region_size = %d\n",
028ab6b5 2002 erase_region_count, erase_region_size);
bf9e3b38 2003 for (j = 0; j < erase_region_count; j++) {
ec50a8e3
IY		 2004 if (sector - base >= info->size)
2005 break;
6d0f6bcf 2006 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
81b20ccc
MS		 2007 printf("ERROR: too many flash sectors\n");
2008 break;
2009 }
09ce9921
BB		 2010 info->start[sect_cnt] =
2011 (ulong)map_physmem(sector,
2012 info->portwidth,
2013 MAP_NOCACHE);
5653fc33 2014 sector += (erase_region_size * size_ratio);
a1191902
WD		 2015
2016 /*
7e5b9b47
HS		 2017 * Only read protection status from
2018 * supported devices (intel...)
a1191902
WD		 2019 */
2020 switch (info->vendor) {
9c048b52 2021 case CFI_CMDSET_INTEL_PROG_REGIONS:
a1191902
WD		 2022 case CFI_CMDSET_INTEL_EXTENDED:
2023 case CFI_CMDSET_INTEL_STANDARD:
df4e813b
SR		 2024 /*
2025 * Set flash to read-id mode. Otherwise
2026 * reading protected status is not
2027 * guaranteed.
2028 */
2029 flash_write_cmd(info, sect_cnt, 0,
2030 FLASH_CMD_READ_ID);
a1191902
WD		 2031 info->protect[sect_cnt] =
2032 flash_isset (info, sect_cnt,
2033 FLASH_OFFSET_PROTECT,
2034 FLASH_STATUS_PROTECT);
2035 break;
2036 default:
7e5b9b47
HS		 2037 /* default: not protected */
2038 info->protect[sect_cnt] = 0;
a1191902
WD		 2039 }
2040
5653fc33
WD		 2041 sect_cnt++;
2042 }
2043 }
2044
2045 info->sector_count = sect_cnt;
e23741f4
HS		 2046 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
2047 tmp = 1 << qry.block_erase_timeout_typ;
7e5b9b47 2048 info->erase_blk_tout = tmp *
e23741f4
HS		 2049 (1 << qry.block_erase_timeout_max);
2050 tmp = (1 << qry.buf_write_timeout_typ) *
2051 (1 << qry.buf_write_timeout_max);
2052
7e5b9b47 2053 /* round up when converting to ms */
e23741f4
HS		 2054 info->buffer_write_tout = (tmp + 999) / 1000;
2055 tmp = (1 << qry.word_write_timeout_typ) *
2056 (1 << qry.word_write_timeout_max);
7e5b9b47 2057 /* round up when converting to ms */
e23741f4 2058 info->write_tout = (tmp + 999) / 1000;
5653fc33 2059 info->flash_id = FLASH_MAN_CFI;
7e5b9b47
HS		 2060 if ((info->interface == FLASH_CFI_X8X16) &&
2061 (info->chipwidth == FLASH_CFI_BY8)) {
2062 /* XXX - Need to test on x8/x16 in parallel. */
2063 info->portwidth >>= 1;
855a496f 2064 }
2215987e
MF		 2065
2066 flash_write_cmd (info, 0, 0, info->cmd_reset);
5653fc33
WD		 2067 }
2068
bf9e3b38 2069 return (info->size);
5653fc33
WD		 2070}
2071
4ffeab2c 2072#ifdef CONFIG_FLASH_CFI_MTD
6ea808ef
PZ		 2073void flash_set_verbose(uint v)
2074{
2075 flash_verbose = v;
2076}
4ffeab2c 2077#endif
6ea808ef 2078
6f726f95
SR		 2079static void cfi_flash_set_config_reg(u32 base, u16 val)
2080{
2081#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
2082 /*
2083 * Only set this config register if really defined
2084 * to a valid value (0xffff is invalid)
2085 */
2086 if (val == 0xffff)
2087 return;
2088
2089 /*
2090 * Set configuration register. Data is "encrypted" in the 16 lower
2091 * address bits.
2092 */
2093 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1)));
2094 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1)));
2095
2096 /*
2097 * Finally issue reset-command to bring device back to
2098 * read-array mode
2099 */
2100 flash_write16(FLASH_CMD_RESET, (void *)base);
2101#endif
2102}
2103
5653fc33
WD		 2104/*-----------------------------------------------------------------------
2105 */
6ee1416e
HS		 2106
2107void flash_protect_default(void)
2108{
2c51983b
PT		 2109#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
2110 int i;
2111 struct apl_s {
2112 ulong start;
2113 ulong size;
2114 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST;
2115#endif
2116
6ee1416e
HS		 2117 /* Monitor protection ON by default */
2118#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
2119 (!defined(CONFIG_MONITOR_IS_IN_RAM))
2120 flash_protect(FLAG_PROTECT_SET,
2121 CONFIG_SYS_MONITOR_BASE,
2122 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
2123 flash_get_info(CONFIG_SYS_MONITOR_BASE));
2124#endif
2125
2126 /* Environment protection ON by default */
2127#ifdef CONFIG_ENV_IS_IN_FLASH
2128 flash_protect(FLAG_PROTECT_SET,
2129 CONFIG_ENV_ADDR,
2130 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
2131 flash_get_info(CONFIG_ENV_ADDR));
2132#endif
2133
2134 /* Redundant environment protection ON by default */
2135#ifdef CONFIG_ENV_ADDR_REDUND
2136 flash_protect(FLAG_PROTECT_SET,
2137 CONFIG_ENV_ADDR_REDUND,
2138 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
2139 flash_get_info(CONFIG_ENV_ADDR_REDUND));
2140#endif
2141
2142#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
2143 for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) {
2144 debug("autoprotecting from %08x to %08x\n",
2145 apl[i].start, apl[i].start + apl[i].size - 1);
2146 flash_protect(FLAG_PROTECT_SET,
2147 apl[i].start,
2148 apl[i].start + apl[i].size - 1,
2149 flash_get_info(apl[i].start));
2150 }
2151#endif
2152}
2153
be60a902 2154unsigned long flash_init (void)
5653fc33 2155{
be60a902
HS		 2156 unsigned long size = 0;
2157 int i;
5653fc33 2158
6d0f6bcf 2159#ifdef CONFIG_SYS_FLASH_PROTECTION
3a3baf3e
ES		 2160 /* read environment from EEPROM */
2161 char s[64];
cdb74977 2162 getenv_f("unlock", s, sizeof(s));
81b20ccc 2163#endif
5653fc33 2164
be60a902 2165 /* Init: no FLASHes known */
6d0f6bcf 2166 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
be60a902 2167 flash_info[i].flash_id = FLASH_UNKNOWN;
5653fc33 2168
6f726f95
SR		 2169 /* Optionally write flash configuration register */
2170 cfi_flash_set_config_reg(cfi_flash_bank_addr(i),
2171 cfi_flash_config_reg(i));
2172
b00e19cc 2173 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
34bbb8fb 2174 flash_get_size(cfi_flash_bank_addr(i), i);
be60a902
HS		 2175 size += flash_info[i].size;
2176 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
6d0f6bcf 2177#ifndef CONFIG_SYS_FLASH_QUIET_TEST
eddf52b5 2178 printf ("## Unknown flash on Bank %d "
be60a902
HS		 2179 "- Size = 0x%08lx = %ld MB\n",
2180 i+1, flash_info[i].size,
0e3fa01a 2181 flash_info[i].size >> 20);
6d0f6bcf 2182#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
be60a902 2183 }
6d0f6bcf 2184#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902
HS		 2185 else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
2186 /*
2187 * Only the U-Boot image and it's environment
2188 * is protected, all other sectors are
2189 * unprotected (unlocked) if flash hardware
6d0f6bcf 2190 * protection is used (CONFIG_SYS_FLASH_PROTECTION)
be60a902
HS		 2191 * and the environment variable "unlock" is
2192 * set to "yes".
2193 */
2194 if (flash_info[i].legacy_unlock) {
2195 int k;
5653fc33 2196
be60a902
HS		 2197 /*
2198 * Disable legacy_unlock temporarily,
2199 * since flash_real_protect would
2200 * relock all other sectors again
2201 * otherwise.
2202 */
2203 flash_info[i].legacy_unlock = 0;
5653fc33 2204
be60a902
HS		 2205 /*
2206 * Legacy unlocking (e.g. Intel J3) ->
2207 * unlock only one sector. This will
2208 * unlock all sectors.
2209 */
2210 flash_real_protect (&flash_info[i], 0, 0);
5653fc33 2211
be60a902 2212 flash_info[i].legacy_unlock = 1;
5653fc33 2213
be60a902
HS		 2214 /*
2215 * Manually mark other sectors as
2216 * unlocked (unprotected)
2217 */
2218 for (k = 1; k < flash_info[i].sector_count; k++)
2219 flash_info[i].protect[k] = 0;
2220 } else {
2221 /*
2222 * No legancy unlocking -> unlock all sectors
2223 */
2224 flash_protect (FLAG_PROTECT_CLEAR,
2225 flash_info[i].start[0],
2226 flash_info[i].start[0]
2227 + flash_info[i].size - 1,
2228 &flash_info[i]);
79b4cda0 2229 }
79b4cda0 2230 }
6d0f6bcf 2231#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 2232 }
79b4cda0 2233
6ee1416e 2234 flash_protect_default();
91809ed5
PZ		 2235#ifdef CONFIG_FLASH_CFI_MTD
2236 cfi_mtd_init();
2237#endif
2238
be60a902 2239 return (size);
5653fc33 2240}
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