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Merge branch 'master' of ssh://10.10.0.7/home/wd/git/u-boot/master
[people/ms/u-boot.git] / drivers / mtd / cfi_flash.c
CommitLineData
5653fc33 1/*
bf9e3b38 2 * (C) Copyright 2002-2004
5653fc33
WD		 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
5653fc33 7 *
bf9e3b38
WD		 8 * Copyright (C) 2004
9 * Ed Okerson
260421a2
SR		 10 *
11 * Copyright (C) 2006
12 * Tolunay Orkun <listmember@orkun.us>
bf9e3b38 13 *
5653fc33
WD		 14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 *
5653fc33
WD		 32 */
33
34/* The DEBUG define must be before common to enable debugging */
2d1a537d
WD		 35/* #define DEBUG */
36
5653fc33
WD		 37#include <common.h>
38#include <asm/processor.h>
3a197b2f 39#include <asm/io.h>
4c0d4c3b 40#include <asm/byteorder.h>
2a8af187 41#include <environment.h>
028ab6b5 42
5653fc33 43/*
7e5b9b47
HS		 44 * This file implements a Common Flash Interface (CFI) driver for
45 * U-Boot.
46 *
47 * The width of the port and the width of the chips are determined at
48 * initialization. These widths are used to calculate the address for
49 * access CFI data structures.
5653fc33
WD		 50 *
51 * References
52 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
53 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
54 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
55 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
260421a2
SR		 56 * AMD CFI Specification, Release 2.0 December 1, 2001
57 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
58 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
5653fc33 59 *
7e5b9b47 60 * Define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
d0b6e140 61 * reading and writing ... (yes there is such a Hardware).
5653fc33
WD		 62 */
63
bf9e3b38
WD		 64#ifndef CFG_FLASH_BANKS_LIST
65#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
66#endif
67
5653fc33
WD		 68#define FLASH_CMD_CFI 0x98
69#define FLASH_CMD_READ_ID 0x90
70#define FLASH_CMD_RESET 0xff
71#define FLASH_CMD_BLOCK_ERASE 0x20
72#define FLASH_CMD_ERASE_CONFIRM 0xD0
73#define FLASH_CMD_WRITE 0x40
74#define FLASH_CMD_PROTECT 0x60
75#define FLASH_CMD_PROTECT_SET 0x01
76#define FLASH_CMD_PROTECT_CLEAR 0xD0
77#define FLASH_CMD_CLEAR_STATUS 0x50
9c048b52 78#define FLASH_CMD_READ_STATUS 0x70
bf9e3b38 79#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
9c048b52 80#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
bf9e3b38 81#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
5653fc33
WD		 82
83#define FLASH_STATUS_DONE 0x80
84#define FLASH_STATUS_ESS 0x40
85#define FLASH_STATUS_ECLBS 0x20
86#define FLASH_STATUS_PSLBS 0x10
87#define FLASH_STATUS_VPENS 0x08
88#define FLASH_STATUS_PSS 0x04
89#define FLASH_STATUS_DPS 0x02
90#define FLASH_STATUS_R 0x01
91#define FLASH_STATUS_PROTECT 0x01
92
93#define AMD_CMD_RESET 0xF0
94#define AMD_CMD_WRITE 0xA0
95#define AMD_CMD_ERASE_START 0x80
96#define AMD_CMD_ERASE_SECTOR 0x30
855a496f
WD		 97#define AMD_CMD_UNLOCK_START 0xAA
98#define AMD_CMD_UNLOCK_ACK 0x55
79b4cda0
SR		 99#define AMD_CMD_WRITE_TO_BUFFER 0x25
100#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
5653fc33
WD		 101
102#define AMD_STATUS_TOGGLE 0x40
103#define AMD_STATUS_ERROR 0x20
79b4cda0 104
bc9019e1
RC		 105#define ATM_CMD_UNLOCK_SECT 0x70
106#define ATM_CMD_SOFTLOCK_START 0x80
107#define ATM_CMD_LOCK_SECT 0x40
108
260421a2
SR		 109#define FLASH_OFFSET_MANUFACTURER_ID 0x00
110#define FLASH_OFFSET_DEVICE_ID 0x01
111#define FLASH_OFFSET_DEVICE_ID2 0x0E
112#define FLASH_OFFSET_DEVICE_ID3 0x0F
5653fc33 113#define FLASH_OFFSET_CFI 0x55
92eb729b 114#define FLASH_OFFSET_CFI_ALT 0x555
5653fc33 115#define FLASH_OFFSET_CFI_RESP 0x10
bf9e3b38 116#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
7e5b9b47
HS		 117/* extended query table primary address */
118#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
5653fc33 119#define FLASH_OFFSET_WTOUT 0x1F
bf9e3b38 120#define FLASH_OFFSET_WBTOUT 0x20
5653fc33 121#define FLASH_OFFSET_ETOUT 0x21
bf9e3b38 122#define FLASH_OFFSET_CETOUT 0x22
5653fc33 123#define FLASH_OFFSET_WMAX_TOUT 0x23
bf9e3b38 124#define FLASH_OFFSET_WBMAX_TOUT 0x24
5653fc33 125#define FLASH_OFFSET_EMAX_TOUT 0x25
bf9e3b38 126#define FLASH_OFFSET_CEMAX_TOUT 0x26
5653fc33 127#define FLASH_OFFSET_SIZE 0x27
bf9e3b38
WD		 128#define FLASH_OFFSET_INTERFACE 0x28
129#define FLASH_OFFSET_BUFFER_SIZE 0x2A
5653fc33
WD		 130#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
131#define FLASH_OFFSET_ERASE_REGIONS 0x2D
132#define FLASH_OFFSET_PROTECT 0x02
bf9e3b38
WD		 133#define FLASH_OFFSET_USER_PROTECTION 0x85
134#define FLASH_OFFSET_INTEL_PROTECTION 0x81
5653fc33 135
260421a2
SR		 136#define CFI_CMDSET_NONE 0
137#define CFI_CMDSET_INTEL_EXTENDED 1
138#define CFI_CMDSET_AMD_STANDARD 2
139#define CFI_CMDSET_INTEL_STANDARD 3
140#define CFI_CMDSET_AMD_EXTENDED 4
141#define CFI_CMDSET_MITSU_STANDARD 256
142#define CFI_CMDSET_MITSU_EXTENDED 257
143#define CFI_CMDSET_SST 258
9c048b52 144#define CFI_CMDSET_INTEL_PROG_REGIONS 512
5653fc33 145
f7d1572b
WD		 146#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
147# undef FLASH_CMD_RESET
260421a2 148# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
f7d1572b
WD		 149#endif
150
5653fc33
WD		 151typedef union {
152 unsigned char c;
153 unsigned short w;
154 unsigned long l;
155 unsigned long long ll;
156} cfiword_t;
157
260421a2 158#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
5653fc33 159
7e5b9b47 160static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
92eb729b 161
e6f2e902
MB		 162/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
163#ifdef CFG_MAX_FLASH_BANKS_DETECT
2a112b23 164# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS_DETECT
e6f2e902 165#else
2a112b23 166# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS
e6f2e902 167#endif
5653fc33 168
2a112b23
WD		 169flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
170
79b4cda0
SR		 171/*
172 * Check if chip width is defined. If not, start detecting with 8bit.
173 */
174#ifndef CFG_FLASH_CFI_WIDTH
175#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
176#endif
177
be60a902 178typedef unsigned long flash_sect_t;
5653fc33 179
e23741f4
HS		 180/* CFI standard query structure */
181struct cfi_qry {
182 u8 qry[3];
183 u16 p_id;
184 u16 p_adr;
185 u16 a_id;
186 u16 a_adr;
187 u8 vcc_min;
188 u8 vcc_max;
189 u8 vpp_min;
190 u8 vpp_max;
191 u8 word_write_timeout_typ;
192 u8 buf_write_timeout_typ;
193 u8 block_erase_timeout_typ;
194 u8 chip_erase_timeout_typ;
195 u8 word_write_timeout_max;
196 u8 buf_write_timeout_max;
197 u8 block_erase_timeout_max;
198 u8 chip_erase_timeout_max;
199 u8 dev_size;
200 u16 interface_desc;
201 u16 max_buf_write_size;
202 u8 num_erase_regions;
203 u32 erase_region_info[NUM_ERASE_REGIONS];
204} __attribute__((packed));
205
206struct cfi_pri_hdr {
207 u8 pri[3];
208 u8 major_version;
209 u8 minor_version;
210} __attribute__((packed));
211
cdbaefb5
HS		 212static void flash_write8(u8 value, void *addr)
213{
214 __raw_writeb(value, addr);
215}
216
217static void flash_write16(u16 value, void *addr)
218{
219 __raw_writew(value, addr);
220}
221
222static void flash_write32(u32 value, void *addr)
223{
224 __raw_writel(value, addr);
225}
226
227static void flash_write64(u64 value, void *addr)
228{
229 /* No architectures currently implement __raw_writeq() */
230 *(volatile u64 *)addr = value;
231}
232
233static u8 flash_read8(void *addr)
234{
235 return __raw_readb(addr);
236}
237
238static u16 flash_read16(void *addr)
239{
240 return __raw_readw(addr);
241}
242
243static u32 flash_read32(void *addr)
244{
245 return __raw_readl(addr);
246}
247
97bf85d7 248static u64 __flash_read64(void *addr)
cdbaefb5
HS		 249{
250 /* No architectures currently implement __raw_readq() */
251 return *(volatile u64 *)addr;
252}
253
97bf85d7
DH		 254u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
255
5653fc33 256/*-----------------------------------------------------------------------
5653fc33 257 */
0e8d1586 258#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
be60a902
HS		 259static flash_info_t *flash_get_info(ulong base)
260{
261 int i;
262 flash_info_t * info = 0;
5653fc33 263
be60a902
HS		 264 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
265 info = & flash_info[i];
266 if (info->size && info->start[0] <= base &&
267 base <= info->start[0] + info->size - 1)
268 break;
269 }
5653fc33 270
be60a902
HS		 271 return i == CFG_MAX_FLASH_BANKS ? 0 : info;
272}
5653fc33
WD		 273#endif
274
12d30aa7
HS		 275unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
276{
277 if (sect != (info->sector_count - 1))
278 return info->start[sect + 1] - info->start[sect];
279 else
280 return info->start[0] + info->size - info->start[sect];
281}
282
bf9e3b38
WD		 283/*-----------------------------------------------------------------------
284 * create an address based on the offset and the port width
285 */
12d30aa7
HS		 286static inline void *
287flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
bf9e3b38 288{
12d30aa7
HS		 289 unsigned int byte_offset = offset * info->portwidth;
290
291 return map_physmem(info->start[sect] + byte_offset,
292 flash_sector_size(info, sect) - byte_offset,
293 MAP_NOCACHE);
294}
295
296static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
297 unsigned int offset, void *addr)
298{
299 unsigned int byte_offset = offset * info->portwidth;
300
301 unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset);
bf9e3b38
WD		 302}
303
be60a902
HS		 304/*-----------------------------------------------------------------------
305 * make a proper sized command based on the port and chip widths
306 */
7288f972 307static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
be60a902
HS		 308{
309 int i;
93c56f21
VL		 310 int cword_offset;
311 int cp_offset;
340ccb26
SS		 312#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
313 u32 cmd_le = cpu_to_le32(cmd);
314#endif
93c56f21 315 uchar val;
be60a902
HS		 316 uchar *cp = (uchar *) cmdbuf;
317
93c56f21
VL		 318 for (i = info->portwidth; i > 0; i--){
319 cword_offset = (info->portwidth-i)%info->chipwidth;
be60a902 320#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
93c56f21 321 cp_offset = info->portwidth - i;
340ccb26 322 val = *((uchar*)&cmd_le + cword_offset);
be60a902 323#else
93c56f21 324 cp_offset = i - 1;
7288f972 325 val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1);
be60a902 326#endif
7288f972 327 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
93c56f21 328 }
be60a902
HS		 329}
330
5653fc33 331#ifdef DEBUG
bf9e3b38
WD		 332/*-----------------------------------------------------------------------
333 * Debug support
334 */
3055793b 335static void print_longlong (char *str, unsigned long long data)
5653fc33
WD		 336{
337 int i;
338 char *cp;
bf9e3b38
WD		 339
340 cp = (unsigned char *) &data;
341 for (i = 0; i < 8; i++)
342 sprintf (&str[i * 2], "%2.2x", *cp++);
343}
be60a902 344
e23741f4 345static void flash_printqry (struct cfi_qry *qry)
bf9e3b38 346{
e23741f4 347 u8 *p = (u8 *)qry;
bf9e3b38
WD		 348 int x, y;
349
e23741f4
HS		 350 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
351 debug("%02x : ", x);
352 for (y = 0; y < 16; y++)
353 debug("%2.2x ", p[x + y]);
354 debug(" ");
bf9e3b38 355 for (y = 0; y < 16; y++) {
e23741f4
HS		 356 unsigned char c = p[x + y];
357 if (c >= 0x20 && c <= 0x7e)
358 debug("%c", c);
359 else
360 debug(".");
bf9e3b38 361 }
e23741f4 362 debug("\n");
bf9e3b38 363 }
5653fc33
WD		 364}
365#endif
366
367
5653fc33
WD		 368/*-----------------------------------------------------------------------
369 * read a character at a port width address
370 */
3055793b 371static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
5653fc33
WD		 372{
373 uchar *cp;
12d30aa7 374 uchar retval;
bf9e3b38 375
12d30aa7 376 cp = flash_map (info, 0, offset);
d0b6e140 377#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
12d30aa7 378 retval = flash_read8(cp);
bf9e3b38 379#else
12d30aa7 380 retval = flash_read8(cp + info->portwidth - 1);
bf9e3b38 381#endif
12d30aa7
HS		 382 flash_unmap (info, 0, offset, cp);
383 return retval;
5653fc33
WD		 384}
385
90447ecb
TK		 386/*-----------------------------------------------------------------------
387 * read a word at a port width address, assume 16bit bus
388 */
389static inline ushort flash_read_word (flash_info_t * info, uint offset)
390{
391 ushort *addr, retval;
392
393 addr = flash_map (info, 0, offset);
394 retval = flash_read16 (addr);
395 flash_unmap (info, 0, offset, addr);
396 return retval;
397}
398
399
5653fc33 400/*-----------------------------------------------------------------------
260421a2 401 * read a long word by picking the least significant byte of each maximum
5653fc33
WD		 402 * port size word. Swap for ppc format.
403 */
3055793b
HS		 404static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
405 uint offset)
5653fc33 406{
bf9e3b38
WD		 407 uchar *addr;
408 ulong retval;
409
410#ifdef DEBUG
411 int x;
412#endif
12d30aa7 413 addr = flash_map (info, sect, offset);
5653fc33 414
bf9e3b38
WD		 415#ifdef DEBUG
416 debug ("long addr is at %p info->portwidth = %d\n", addr,
417 info->portwidth);
418 for (x = 0; x < 4 * info->portwidth; x++) {
12d30aa7 419 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
bf9e3b38
WD		 420 }
421#endif
d0b6e140 422#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
12d30aa7
HS		 423 retval = ((flash_read8(addr) << 16) |
424 (flash_read8(addr + info->portwidth) << 24) |
425 (flash_read8(addr + 2 * info->portwidth)) |
426 (flash_read8(addr + 3 * info->portwidth) << 8));
bf9e3b38 427#else
12d30aa7
HS		 428 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
429 (flash_read8(addr + info->portwidth - 1) << 16) |
430 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
431 (flash_read8(addr + 3 * info->portwidth - 1)));
bf9e3b38 432#endif
12d30aa7
HS		 433 flash_unmap(info, sect, offset, addr);
434
bf9e3b38 435 return retval;
5653fc33
WD		 436}
437
be60a902
HS		 438/*
439 * Write a proper sized command to the correct address
81b20ccc 440 */
be60a902 441static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
7288f972 442 uint offset, u32 cmd)
81b20ccc 443{
7e5b9b47 444
cdbaefb5 445 void *addr;
be60a902 446 cfiword_t cword;
81b20ccc 447
12d30aa7 448 addr = flash_map (info, sect, offset);
be60a902
HS		 449 flash_make_cmd (info, cmd, &cword);
450 switch (info->portwidth) {
451 case FLASH_CFI_8BIT:
cdbaefb5 452 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
be60a902 453 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 454 flash_write8(cword.c, addr);
be60a902
HS		 455 break;
456 case FLASH_CFI_16BIT:
cdbaefb5 457 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
be60a902
HS		 458 cmd, cword.w,
459 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 460 flash_write16(cword.w, addr);
be60a902
HS		 461 break;
462 case FLASH_CFI_32BIT:
cdbaefb5 463 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
be60a902
HS		 464 cmd, cword.l,
465 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 466 flash_write32(cword.l, addr);
be60a902
HS		 467 break;
468 case FLASH_CFI_64BIT:
469#ifdef DEBUG
470 {
471 char str[20];
7e5b9b47 472
be60a902
HS		 473 print_longlong (str, cword.ll);
474
475 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
cdbaefb5 476 addr, cmd, str,
be60a902 477 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
81b20ccc 478 }
be60a902 479#endif
cdbaefb5 480 flash_write64(cword.ll, addr);
be60a902 481 break;
81b20ccc 482 }
be60a902
HS		 483
484 /* Ensure all the instructions are fully finished */
485 sync();
12d30aa7
HS		 486
487 flash_unmap(info, sect, offset, addr);
81b20ccc 488}
be60a902
HS		 489
490static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
81b20ccc 491{
be60a902
HS		 492 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
493 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
81b20ccc 494}
81b20ccc 495
5653fc33
WD		 496/*-----------------------------------------------------------------------
497 */
be60a902
HS		 498static int flash_isequal (flash_info_t * info, flash_sect_t sect,
499 uint offset, uchar cmd)
5653fc33 500{
cdbaefb5 501 void *addr;
be60a902
HS		 502 cfiword_t cword;
503 int retval;
5653fc33 504
12d30aa7 505 addr = flash_map (info, sect, offset);
be60a902 506 flash_make_cmd (info, cmd, &cword);
2662b40c 507
cdbaefb5 508 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
be60a902
HS		 509 switch (info->portwidth) {
510 case FLASH_CFI_8BIT:
cdbaefb5
HS		 511 debug ("is= %x %x\n", flash_read8(addr), cword.c);
512 retval = (flash_read8(addr) == cword.c);
be60a902
HS		 513 break;
514 case FLASH_CFI_16BIT:
cdbaefb5
HS		 515 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
516 retval = (flash_read16(addr) == cword.w);
be60a902
HS		 517 break;
518 case FLASH_CFI_32BIT:
52514699 519 debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l);
cdbaefb5 520 retval = (flash_read32(addr) == cword.l);
be60a902
HS		 521 break;
522 case FLASH_CFI_64BIT:
523#ifdef DEBUG
524 {
525 char str1[20];
526 char str2[20];
81b20ccc 527
cdbaefb5 528 print_longlong (str1, flash_read64(addr));
be60a902
HS		 529 print_longlong (str2, cword.ll);
530 debug ("is= %s %s\n", str1, str2);
5653fc33 531 }
be60a902 532#endif
cdbaefb5 533 retval = (flash_read64(addr) == cword.ll);
be60a902
HS		 534 break;
535 default:
536 retval = 0;
537 break;
538 }
12d30aa7
HS		 539 flash_unmap(info, sect, offset, addr);
540
be60a902
HS		 541 return retval;
542}
79b4cda0 543
be60a902
HS		 544/*-----------------------------------------------------------------------
545 */
546static int flash_isset (flash_info_t * info, flash_sect_t sect,
547 uint offset, uchar cmd)
548{
cdbaefb5 549 void *addr;
be60a902
HS		 550 cfiword_t cword;
551 int retval;
2662b40c 552
12d30aa7 553 addr = flash_map (info, sect, offset);
be60a902
HS		 554 flash_make_cmd (info, cmd, &cword);
555 switch (info->portwidth) {
556 case FLASH_CFI_8BIT:
cdbaefb5 557 retval = ((flash_read8(addr) & cword.c) == cword.c);
be60a902
HS		 558 break;
559 case FLASH_CFI_16BIT:
cdbaefb5 560 retval = ((flash_read16(addr) & cword.w) == cword.w);
be60a902
HS		 561 break;
562 case FLASH_CFI_32BIT:
47cc23cb 563 retval = ((flash_read32(addr) & cword.l) == cword.l);
be60a902
HS		 564 break;
565 case FLASH_CFI_64BIT:
cdbaefb5 566 retval = ((flash_read64(addr) & cword.ll) == cword.ll);
be60a902
HS		 567 break;
568 default:
569 retval = 0;
570 break;
571 }
12d30aa7
HS		 572 flash_unmap(info, sect, offset, addr);
573
be60a902
HS		 574 return retval;
575}
2662b40c 576
be60a902
HS		 577/*-----------------------------------------------------------------------
578 */
579static int flash_toggle (flash_info_t * info, flash_sect_t sect,
580 uint offset, uchar cmd)
581{
cdbaefb5 582 void *addr;
be60a902
HS		 583 cfiword_t cword;
584 int retval;
656658dd 585
12d30aa7 586 addr = flash_map (info, sect, offset);
be60a902
HS		 587 flash_make_cmd (info, cmd, &cword);
588 switch (info->portwidth) {
589 case FLASH_CFI_8BIT:
fb8c061e 590 retval = flash_read8(addr) != flash_read8(addr);
be60a902
HS		 591 break;
592 case FLASH_CFI_16BIT:
fb8c061e 593 retval = flash_read16(addr) != flash_read16(addr);
be60a902
HS		 594 break;
595 case FLASH_CFI_32BIT:
fb8c061e 596 retval = flash_read32(addr) != flash_read32(addr);
be60a902
HS		 597 break;
598 case FLASH_CFI_64BIT:
fb8c061e 599 retval = flash_read64(addr) != flash_read64(addr);
be60a902
HS		 600 break;
601 default:
602 retval = 0;
603 break;
604 }
12d30aa7
HS		 605 flash_unmap(info, sect, offset, addr);
606
be60a902 607 return retval;
5653fc33
WD		 608}
609
be60a902
HS		 610/*
611 * flash_is_busy - check to see if the flash is busy
612 *
613 * This routine checks the status of the chip and returns true if the
614 * chip is busy.
7680c140 615 */
be60a902 616static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
7680c140 617{
be60a902 618 int retval;
7680c140 619
be60a902 620 switch (info->vendor) {
9c048b52 621 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 622 case CFI_CMDSET_INTEL_STANDARD:
623 case CFI_CMDSET_INTEL_EXTENDED:
624 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
625 break;
626 case CFI_CMDSET_AMD_STANDARD:
627 case CFI_CMDSET_AMD_EXTENDED:
628#ifdef CONFIG_FLASH_CFI_LEGACY
629 case CFI_CMDSET_AMD_LEGACY:
630#endif
631 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
632 break;
633 default:
634 retval = 0;
7680c140 635 }
be60a902
HS		 636 debug ("flash_is_busy: %d\n", retval);
637 return retval;
7680c140
WD		 638}
639
5653fc33 640/*-----------------------------------------------------------------------
be60a902
HS		 641 * wait for XSR.7 to be set. Time out with an error if it does not.
642 * This routine does not set the flash to read-array mode.
5653fc33 643 */
be60a902
HS		 644static int flash_status_check (flash_info_t * info, flash_sect_t sector,
645 ulong tout, char *prompt)
5653fc33 646{
be60a902 647 ulong start;
5653fc33 648
be60a902
HS		 649#if CFG_HZ != 1000
650 tout *= CFG_HZ/1000;
651#endif
5653fc33 652
be60a902
HS		 653 /* Wait for command completion */
654 start = get_timer (0);
655 while (flash_is_busy (info, sector)) {
656 if (get_timer (start) > tout) {
657 printf ("Flash %s timeout at address %lx data %lx\n",
658 prompt, info->start[sector],
659 flash_read_long (info, sector, 0));
660 flash_write_cmd (info, sector, 0, info->cmd_reset);
661 return ERR_TIMOUT;
5653fc33 662 }
be60a902 663 udelay (1); /* also triggers watchdog */
5653fc33 664 }
be60a902
HS		 665 return ERR_OK;
666}
5653fc33 667
be60a902
HS		 668/*-----------------------------------------------------------------------
669 * Wait for XSR.7 to be set, if it times out print an error, otherwise
670 * do a full status check.
671 *
672 * This routine sets the flash to read-array mode.
673 */
674static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
675 ulong tout, char *prompt)
676{
677 int retcode;
5653fc33 678
be60a902
HS		 679 retcode = flash_status_check (info, sector, tout, prompt);
680 switch (info->vendor) {
9c048b52 681 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 682 case CFI_CMDSET_INTEL_EXTENDED:
683 case CFI_CMDSET_INTEL_STANDARD:
684 if ((retcode == ERR_OK)
685 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
686 retcode = ERR_INVAL;
687 printf ("Flash %s error at address %lx\n", prompt,
688 info->start[sector]);
689 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
690 FLASH_STATUS_PSLBS)) {
691 puts ("Command Sequence Error.\n");
692 } else if (flash_isset (info, sector, 0,
693 FLASH_STATUS_ECLBS)) {
694 puts ("Block Erase Error.\n");
695 retcode = ERR_NOT_ERASED;
696 } else if (flash_isset (info, sector, 0,
697 FLASH_STATUS_PSLBS)) {
698 puts ("Locking Error\n");
5653fc33 699 }
be60a902
HS		 700 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
701 puts ("Block locked.\n");
702 retcode = ERR_PROTECTED;
703 }
704 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
705 puts ("Vpp Low Error.\n");
5653fc33 706 }
be60a902
HS		 707 flash_write_cmd (info, sector, 0, info->cmd_reset);
708 break;
709 default:
710 break;
5653fc33 711 }
be60a902 712 return retcode;
5653fc33
WD		 713}
714
715/*-----------------------------------------------------------------------
716 */
be60a902 717static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
5653fc33 718{
be60a902
HS		 719#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
720 unsigned short w;
721 unsigned int l;
722 unsigned long long ll;
723#endif
5653fc33 724
be60a902
HS		 725 switch (info->portwidth) {
726 case FLASH_CFI_8BIT:
727 cword->c = c;
728 break;
729 case FLASH_CFI_16BIT:
730#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
731 w = c;
732 w <<= 8;
733 cword->w = (cword->w >> 8) | w;
734#else
735 cword->w = (cword->w << 8) | c;
81b20ccc 736#endif
be60a902
HS		 737 break;
738 case FLASH_CFI_32BIT:
739#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
740 l = c;
741 l <<= 24;
742 cword->l = (cword->l >> 8) | l;
743#else
744 cword->l = (cword->l << 8) | c;
745#endif
746 break;
747 case FLASH_CFI_64BIT:
748#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
749 ll = c;
750 ll <<= 56;
751 cword->ll = (cword->ll >> 8) | ll;
752#else
753 cword->ll = (cword->ll << 8) | c;
754#endif
755 break;
260421a2 756 }
be60a902 757}
5653fc33 758
be60a902
HS		 759/* loop through the sectors from the highest address when the passed
760 * address is greater or equal to the sector address we have a match
761 */
762static flash_sect_t find_sector (flash_info_t * info, ulong addr)
763{
764 flash_sect_t sector;
5653fc33 765
be60a902
HS		 766 for (sector = info->sector_count - 1; sector >= 0; sector--) {
767 if (addr >= info->start[sector])
768 break;
5653fc33 769 }
be60a902 770 return sector;
5653fc33
WD		 771}
772
773/*-----------------------------------------------------------------------
5653fc33 774 */
be60a902
HS		 775static int flash_write_cfiword (flash_info_t * info, ulong dest,
776 cfiword_t cword)
5653fc33 777{
cdbaefb5 778 void *dstaddr;
be60a902 779 int flag;
5653fc33 780
12d30aa7 781 dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE);
5653fc33 782
be60a902
HS		 783 /* Check if Flash is (sufficiently) erased */
784 switch (info->portwidth) {
785 case FLASH_CFI_8BIT:
cdbaefb5 786 flag = ((flash_read8(dstaddr) & cword.c) == cword.c);
be60a902
HS		 787 break;
788 case FLASH_CFI_16BIT:
cdbaefb5 789 flag = ((flash_read16(dstaddr) & cword.w) == cword.w);
be60a902
HS		 790 break;
791 case FLASH_CFI_32BIT:
cdbaefb5 792 flag = ((flash_read32(dstaddr) & cword.l) == cword.l);
be60a902
HS		 793 break;
794 case FLASH_CFI_64BIT:
cdbaefb5 795 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll);
be60a902
HS		 796 break;
797 default:
12d30aa7
HS		 798 flag = 0;
799 break;
5653fc33 800 }
12d30aa7
HS		 801 if (!flag) {
802 unmap_physmem(dstaddr, info->portwidth);
0dc80e27 803 return ERR_NOT_ERASED;
12d30aa7 804 }
5653fc33 805
be60a902
HS		 806 /* Disable interrupts which might cause a timeout here */
807 flag = disable_interrupts ();
79b4cda0 808
be60a902 809 switch (info->vendor) {
9c048b52 810 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 811 case CFI_CMDSET_INTEL_EXTENDED:
812 case CFI_CMDSET_INTEL_STANDARD:
813 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
814 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
815 break;
816 case CFI_CMDSET_AMD_EXTENDED:
817 case CFI_CMDSET_AMD_STANDARD:
818#ifdef CONFIG_FLASH_CFI_LEGACY
819 case CFI_CMDSET_AMD_LEGACY:
820#endif
821 flash_unlock_seq (info, 0);
822 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
823 break;
5653fc33
WD		 824 }
825
be60a902
HS		 826 switch (info->portwidth) {
827 case FLASH_CFI_8BIT:
cdbaefb5 828 flash_write8(cword.c, dstaddr);
be60a902
HS		 829 break;
830 case FLASH_CFI_16BIT:
cdbaefb5 831 flash_write16(cword.w, dstaddr);
be60a902
HS		 832 break;
833 case FLASH_CFI_32BIT:
cdbaefb5 834 flash_write32(cword.l, dstaddr);
be60a902
HS		 835 break;
836 case FLASH_CFI_64BIT:
cdbaefb5 837 flash_write64(cword.ll, dstaddr);
be60a902 838 break;
5653fc33
WD		 839 }
840
be60a902
HS		 841 /* re-enable interrupts if necessary */
842 if (flag)
843 enable_interrupts ();
5653fc33 844
12d30aa7
HS		 845 unmap_physmem(dstaddr, info->portwidth);
846
be60a902
HS		 847 return flash_full_status_check (info, find_sector (info, dest),
848 info->write_tout, "write");
5653fc33
WD		 849}
850
be60a902 851#ifdef CFG_FLASH_USE_BUFFER_WRITE
5653fc33 852
be60a902
HS		 853static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
854 int len)
5653fc33 855{
be60a902
HS		 856 flash_sect_t sector;
857 int cnt;
858 int retcode;
cdbaefb5 859 void *src = cp;
12d30aa7 860 void *dst = map_physmem(dest, len, MAP_NOCACHE);
0dc80e27
SR		 861 void *dst2 = dst;
862 int flag = 0;
96ef831f
GL		 863 uint offset = 0;
864 unsigned int shift;
9c048b52 865 uchar write_cmd;
cdbaefb5 866
0dc80e27
SR		 867 switch (info->portwidth) {
868 case FLASH_CFI_8BIT:
96ef831f 869 shift = 0;
0dc80e27
SR		 870 break;
871 case FLASH_CFI_16BIT:
96ef831f 872 shift = 1;
0dc80e27
SR		 873 break;
874 case FLASH_CFI_32BIT:
96ef831f 875 shift = 2;
0dc80e27
SR		 876 break;
877 case FLASH_CFI_64BIT:
96ef831f 878 shift = 3;
0dc80e27
SR		 879 break;
880 default:
881 retcode = ERR_INVAL;
882 goto out_unmap;
883 }
884
96ef831f
GL		 885 cnt = len >> shift;
886
0dc80e27
SR		 887 while ((cnt-- > 0) && (flag == 0)) {
888 switch (info->portwidth) {
889 case FLASH_CFI_8BIT:
890 flag = ((flash_read8(dst2) & flash_read8(src)) ==
891 flash_read8(src));
892 src += 1, dst2 += 1;
893 break;
894 case FLASH_CFI_16BIT:
895 flag = ((flash_read16(dst2) & flash_read16(src)) ==
896 flash_read16(src));
897 src += 2, dst2 += 2;
898 break;
899 case FLASH_CFI_32BIT:
900 flag = ((flash_read32(dst2) & flash_read32(src)) ==
901 flash_read32(src));
902 src += 4, dst2 += 4;
903 break;
904 case FLASH_CFI_64BIT:
905 flag = ((flash_read64(dst2) & flash_read64(src)) ==
906 flash_read64(src));
907 src += 8, dst2 += 8;
908 break;
909 }
910 }
911 if (!flag) {
912 retcode = ERR_NOT_ERASED;
913 goto out_unmap;
914 }
915
916 src = cp;
cdbaefb5 917 sector = find_sector (info, dest);
bf9e3b38
WD		 918
919 switch (info->vendor) {
9c048b52 920 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 921 case CFI_CMDSET_INTEL_STANDARD:
922 case CFI_CMDSET_INTEL_EXTENDED:
9c048b52
VL		 923 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
924 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER;
be60a902 925 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
9c048b52
VL		 926 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS);
927 flash_write_cmd (info, sector, 0, write_cmd);
be60a902
HS		 928 retcode = flash_status_check (info, sector,
929 info->buffer_write_tout,
930 "write to buffer");
931 if (retcode == ERR_OK) {
932 /* reduce the number of loops by the width of
933 * the port */
96ef831f 934 cnt = len >> shift;
93c56f21 935 flash_write_cmd (info, sector, 0, cnt - 1);
be60a902
HS		 936 while (cnt-- > 0) {
937 switch (info->portwidth) {
938 case FLASH_CFI_8BIT:
cdbaefb5
HS		 939 flash_write8(flash_read8(src), dst);
940 src += 1, dst += 1;
be60a902
HS		 941 break;
942 case FLASH_CFI_16BIT:
cdbaefb5
HS		 943 flash_write16(flash_read16(src), dst);
944 src += 2, dst += 2;
be60a902
HS		 945 break;
946 case FLASH_CFI_32BIT:
cdbaefb5
HS		 947 flash_write32(flash_read32(src), dst);
948 src += 4, dst += 4;
be60a902
HS		 949 break;
950 case FLASH_CFI_64BIT:
cdbaefb5
HS		 951 flash_write64(flash_read64(src), dst);
952 src += 8, dst += 8;
be60a902
HS		 953 break;
954 default:
12d30aa7
HS		 955 retcode = ERR_INVAL;
956 goto out_unmap;
be60a902
HS		 957 }
958 }
959 flash_write_cmd (info, sector, 0,
960 FLASH_CMD_WRITE_BUFFER_CONFIRM);
961 retcode = flash_full_status_check (
962 info, sector, info->buffer_write_tout,
963 "buffer write");
964 }
12d30aa7
HS		 965
966 break;
be60a902 967
5653fc33
WD		 968 case CFI_CMDSET_AMD_STANDARD:
969 case CFI_CMDSET_AMD_EXTENDED:
be60a902 970 flash_unlock_seq(info,0);
96ef831f
GL		 971
972#ifdef CONFIG_FLASH_SPANSION_S29WS_N
973 offset = ((unsigned long)dst - info->start[sector]) >> shift;
974#endif
975 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
976 cnt = len >> shift;
977 flash_write_cmd(info, sector, offset, (uchar)cnt - 1);
be60a902
HS		 978
979 switch (info->portwidth) {
980 case FLASH_CFI_8BIT:
cdbaefb5
HS		 981 while (cnt-- > 0) {
982 flash_write8(flash_read8(src), dst);
983 src += 1, dst += 1;
984 }
be60a902
HS		 985 break;
986 case FLASH_CFI_16BIT:
cdbaefb5
HS		 987 while (cnt-- > 0) {
988 flash_write16(flash_read16(src), dst);
989 src += 2, dst += 2;
990 }
be60a902
HS		 991 break;
992 case FLASH_CFI_32BIT:
cdbaefb5
HS		 993 while (cnt-- > 0) {
994 flash_write32(flash_read32(src), dst);
995 src += 4, dst += 4;
996 }
be60a902
HS		 997 break;
998 case FLASH_CFI_64BIT:
cdbaefb5
HS		 999 while (cnt-- > 0) {
1000 flash_write64(flash_read64(src), dst);
1001 src += 8, dst += 8;
1002 }
be60a902
HS		 1003 break;
1004 default:
12d30aa7
HS		 1005 retcode = ERR_INVAL;
1006 goto out_unmap;
be60a902
HS		 1007 }
1008
1009 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
1010 retcode = flash_full_status_check (info, sector,
1011 info->buffer_write_tout,
1012 "buffer write");
12d30aa7 1013 break;
be60a902 1014
5653fc33 1015 default:
be60a902 1016 debug ("Unknown Command Set\n");
12d30aa7
HS		 1017 retcode = ERR_INVAL;
1018 break;
5653fc33 1019 }
12d30aa7
HS		 1020
1021out_unmap:
1022 unmap_physmem(dst, len);
1023 return retcode;
5653fc33 1024}
be60a902
HS		 1025#endif /* CFG_FLASH_USE_BUFFER_WRITE */
1026
bf9e3b38 1027
5653fc33 1028/*-----------------------------------------------------------------------
5653fc33 1029 */
be60a902 1030int flash_erase (flash_info_t * info, int s_first, int s_last)
5653fc33 1031{
be60a902
HS		 1032 int rcode = 0;
1033 int prot;
1034 flash_sect_t sect;
5653fc33 1035
be60a902
HS		 1036 if (info->flash_id != FLASH_MAN_CFI) {
1037 puts ("Can't erase unknown flash type - aborted\n");
1038 return 1;
1039 }
1040 if ((s_first < 0) || (s_first > s_last)) {
1041 puts ("- no sectors to erase\n");
1042 return 1;
1043 }
2662b40c 1044
be60a902
HS		 1045 prot = 0;
1046 for (sect = s_first; sect <= s_last; ++sect) {
1047 if (info->protect[sect]) {
1048 prot++;
5653fc33
WD		 1049 }
1050 }
be60a902
HS		 1051 if (prot) {
1052 printf ("- Warning: %d protected sectors will not be erased!\n",
1053 prot);
1054 } else {
1055 putc ('\n');
1056 }
bf9e3b38 1057
bf9e3b38 1058
be60a902
HS		 1059 for (sect = s_first; sect <= s_last; sect++) {
1060 if (info->protect[sect] == 0) { /* not protected */
1061 switch (info->vendor) {
9c048b52 1062 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1063 case CFI_CMDSET_INTEL_STANDARD:
1064 case CFI_CMDSET_INTEL_EXTENDED:
1065 flash_write_cmd (info, sect, 0,
1066 FLASH_CMD_CLEAR_STATUS);
1067 flash_write_cmd (info, sect, 0,
1068 FLASH_CMD_BLOCK_ERASE);
1069 flash_write_cmd (info, sect, 0,
1070 FLASH_CMD_ERASE_CONFIRM);
1071 break;
1072 case CFI_CMDSET_AMD_STANDARD:
1073 case CFI_CMDSET_AMD_EXTENDED:
1074 flash_unlock_seq (info, sect);
1075 flash_write_cmd (info, sect,
1076 info->addr_unlock1,
1077 AMD_CMD_ERASE_START);
1078 flash_unlock_seq (info, sect);
1079 flash_write_cmd (info, sect, 0,
1080 AMD_CMD_ERASE_SECTOR);
1081 break;
1082#ifdef CONFIG_FLASH_CFI_LEGACY
1083 case CFI_CMDSET_AMD_LEGACY:
1084 flash_unlock_seq (info, 0);
1085 flash_write_cmd (info, 0, info->addr_unlock1,
1086 AMD_CMD_ERASE_START);
1087 flash_unlock_seq (info, 0);
1088 flash_write_cmd (info, sect, 0,
1089 AMD_CMD_ERASE_SECTOR);
1090 break;
1091#endif
1092 default:
1093 debug ("Unkown flash vendor %d\n",
1094 info->vendor);
1095 break;
bf9e3b38 1096 }
be60a902
HS		 1097
1098 if (flash_full_status_check
1099 (info, sect, info->erase_blk_tout, "erase")) {
1100 rcode = 1;
1101 } else
1102 putc ('.');
5653fc33 1103 }
5653fc33 1104 }
be60a902
HS		 1105 puts (" done\n");
1106 return rcode;
5653fc33 1107}
bf9e3b38 1108
5653fc33
WD		 1109/*-----------------------------------------------------------------------
1110 */
be60a902 1111void flash_print_info (flash_info_t * info)
5653fc33 1112{
be60a902 1113 int i;
4d13cbad 1114
be60a902
HS		 1115 if (info->flash_id != FLASH_MAN_CFI) {
1116 puts ("missing or unknown FLASH type\n");
1117 return;
1118 }
1119
1120 printf ("%s FLASH (%d x %d)",
1121 info->name,
1122 (info->portwidth << 3), (info->chipwidth << 3));
1123 if (info->size < 1024*1024)
1124 printf (" Size: %ld kB in %d Sectors\n",
1125 info->size >> 10, info->sector_count);
1126 else
1127 printf (" Size: %ld MB in %d Sectors\n",
1128 info->size >> 20, info->sector_count);
1129 printf (" ");
1130 switch (info->vendor) {
9c048b52
VL		 1131 case CFI_CMDSET_INTEL_PROG_REGIONS:
1132 printf ("Intel Prog Regions");
1133 break;
be60a902
HS		 1134 case CFI_CMDSET_INTEL_STANDARD:
1135 printf ("Intel Standard");
1136 break;
1137 case CFI_CMDSET_INTEL_EXTENDED:
1138 printf ("Intel Extended");
1139 break;
1140 case CFI_CMDSET_AMD_STANDARD:
1141 printf ("AMD Standard");
1142 break;
1143 case CFI_CMDSET_AMD_EXTENDED:
1144 printf ("AMD Extended");
1145 break;
1146#ifdef CONFIG_FLASH_CFI_LEGACY
1147 case CFI_CMDSET_AMD_LEGACY:
1148 printf ("AMD Legacy");
1149 break;
4d13cbad 1150#endif
be60a902
HS		 1151 default:
1152 printf ("Unknown (%d)", info->vendor);
1153 break;
1154 }
1155 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X",
1156 info->manufacturer_id, info->device_id);
1157 if (info->device_id == 0x7E) {
1158 printf("%04X", info->device_id2);
1159 }
1160 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
1161 info->erase_blk_tout,
1162 info->write_tout);
1163 if (info->buffer_size > 1) {
1164 printf (" Buffer write timeout: %ld ms, "
1165 "buffer size: %d bytes\n",
1166 info->buffer_write_tout,
1167 info->buffer_size);
5653fc33 1168 }
5653fc33 1169
be60a902
HS		 1170 puts ("\n Sector Start Addresses:");
1171 for (i = 0; i < info->sector_count; ++i) {
1172 if ((i % 5) == 0)
1173 printf ("\n");
1174#ifdef CFG_FLASH_EMPTY_INFO
1175 int k;
1176 int size;
1177 int erased;
1178 volatile unsigned long *flash;
5653fc33 1179
be60a902
HS		 1180 /*
1181 * Check if whole sector is erased
1182 */
12d30aa7 1183 size = flash_sector_size(info, i);
be60a902
HS		 1184 erased = 1;
1185 flash = (volatile unsigned long *) info->start[i];
1186 size = size >> 2; /* divide by 4 for longword access */
1187 for (k = 0; k < size; k++) {
1188 if (*flash++ != 0xffffffff) {
1189 erased = 0;
1190 break;
1191 }
1192 }
bf9e3b38 1193
be60a902
HS		 1194 /* print empty and read-only info */
1195 printf (" %08lX %c %s ",
1196 info->start[i],
1197 erased ? 'E' : ' ',
1198 info->protect[i] ? "RO" : " ");
1199#else /* ! CFG_FLASH_EMPTY_INFO */
1200 printf (" %08lX %s ",
1201 info->start[i],
1202 info->protect[i] ? "RO" : " ");
bf9e3b38 1203#endif
be60a902
HS		 1204 }
1205 putc ('\n');
1206 return;
5653fc33
WD		 1207}
1208
9a042e9c
JVB		 1209/*-----------------------------------------------------------------------
1210 * This is used in a few places in write_buf() to show programming
1211 * progress. Making it a function is nasty because it needs to do side
1212 * effect updates to digit and dots. Repeated code is nasty too, so
1213 * we define it once here.
1214 */
f0105727
SR		 1215#ifdef CONFIG_FLASH_SHOW_PROGRESS
1216#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
1217 dots -= dots_sub; \
9a042e9c
JVB		 1218 if ((scale > 0) && (dots <= 0)) { \
1219 if ((digit % 5) == 0) \
1220 printf ("%d", digit / 5); \
1221 else \
1222 putc ('.'); \
1223 digit--; \
1224 dots += scale; \
1225 }
f0105727
SR		 1226#else
1227#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1228#endif
9a042e9c 1229
be60a902
HS		 1230/*-----------------------------------------------------------------------
1231 * Copy memory to flash, returns:
1232 * 0 - OK
1233 * 1 - write timeout
1234 * 2 - Flash not erased
5653fc33 1235 */
be60a902 1236int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
5653fc33 1237{
be60a902 1238 ulong wp;
12d30aa7 1239 uchar *p;
be60a902 1240 int aln;
5653fc33 1241 cfiword_t cword;
be60a902 1242 int i, rc;
be60a902
HS		 1243#ifdef CFG_FLASH_USE_BUFFER_WRITE
1244 int buffered_size;
5653fc33 1245#endif
9a042e9c
JVB		 1246#ifdef CONFIG_FLASH_SHOW_PROGRESS
1247 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1248 int scale = 0;
1249 int dots = 0;
1250
1251 /*
1252 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1253 */
1254 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1255 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1256 CONFIG_FLASH_SHOW_PROGRESS);
1257 }
1258#endif
1259
be60a902
HS		 1260 /* get lower aligned address */
1261 wp = (addr & ~(info->portwidth - 1));
3a197b2f 1262
be60a902
HS		 1263 /* handle unaligned start */
1264 if ((aln = addr - wp) != 0) {
1265 cword.l = 0;
12d30aa7
HS		 1266 p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
1267 for (i = 0; i < aln; ++i)
1268 flash_add_byte (info, &cword, flash_read8(p + i));
5653fc33 1269
be60a902
HS		 1270 for (; (i < info->portwidth) && (cnt > 0); i++) {
1271 flash_add_byte (info, &cword, *src++);
1272 cnt--;
be60a902 1273 }
12d30aa7
HS		 1274 for (; (cnt == 0) && (i < info->portwidth); ++i)
1275 flash_add_byte (info, &cword, flash_read8(p + i));
1276
1277 rc = flash_write_cfiword (info, wp, cword);
1278 unmap_physmem(p, info->portwidth);
1279 if (rc != 0)
be60a902 1280 return rc;
12d30aa7
HS		 1281
1282 wp += i;
f0105727 1283 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1284 }
1285
1286 /* handle the aligned part */
1287#ifdef CFG_FLASH_USE_BUFFER_WRITE
1288 buffered_size = (info->portwidth / info->chipwidth);
1289 buffered_size *= info->buffer_size;
1290 while (cnt >= info->portwidth) {
1291 /* prohibit buffer write when buffer_size is 1 */
1292 if (info->buffer_size == 1) {
1293 cword.l = 0;
1294 for (i = 0; i < info->portwidth; i++)
1295 flash_add_byte (info, &cword, *src++);
1296 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1297 return rc;
1298 wp += info->portwidth;
1299 cnt -= info->portwidth;
1300 continue;
1301 }
1302
1303 /* write buffer until next buffered_size aligned boundary */
1304 i = buffered_size - (wp % buffered_size);
1305 if (i > cnt)
1306 i = cnt;
1307 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
1308 return rc;
1309 i -= i & (info->portwidth - 1);
1310 wp += i;
1311 src += i;
1312 cnt -= i;
f0105727 1313 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1314 }
1315#else
1316 while (cnt >= info->portwidth) {
1317 cword.l = 0;
1318 for (i = 0; i < info->portwidth; i++) {
1319 flash_add_byte (info, &cword, *src++);
1320 }
1321 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1322 return rc;
1323 wp += info->portwidth;
1324 cnt -= info->portwidth;
f0105727 1325 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
be60a902
HS		 1326 }
1327#endif /* CFG_FLASH_USE_BUFFER_WRITE */
9a042e9c 1328
be60a902
HS		 1329 if (cnt == 0) {
1330 return (0);
1331 }
1332
1333 /*
1334 * handle unaligned tail bytes
1335 */
1336 cword.l = 0;
12d30aa7
HS		 1337 p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
1338 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
be60a902
HS		 1339 flash_add_byte (info, &cword, *src++);
1340 --cnt;
1341 }
12d30aa7
HS		 1342 for (; i < info->portwidth; ++i)
1343 flash_add_byte (info, &cword, flash_read8(p + i));
1344 unmap_physmem(p, info->portwidth);
be60a902
HS		 1345
1346 return flash_write_cfiword (info, wp, cword);
5653fc33 1347}
bf9e3b38 1348
5653fc33
WD		 1349/*-----------------------------------------------------------------------
1350 */
be60a902
HS		 1351#ifdef CFG_FLASH_PROTECTION
1352
1353int flash_real_protect (flash_info_t * info, long sector, int prot)
5653fc33 1354{
be60a902 1355 int retcode = 0;
5653fc33 1356
bc9019e1
RC		 1357 switch (info->vendor) {
1358 case CFI_CMDSET_INTEL_PROG_REGIONS:
1359 case CFI_CMDSET_INTEL_STANDARD:
9e8e63cc 1360 case CFI_CMDSET_INTEL_EXTENDED:
bc9019e1
RC		 1361 flash_write_cmd (info, sector, 0,
1362 FLASH_CMD_CLEAR_STATUS);
1363 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1364 if (prot)
1365 flash_write_cmd (info, sector, 0,
1366 FLASH_CMD_PROTECT_SET);
1367 else
1368 flash_write_cmd (info, sector, 0,
1369 FLASH_CMD_PROTECT_CLEAR);
1370 break;
1371 case CFI_CMDSET_AMD_EXTENDED:
1372 case CFI_CMDSET_AMD_STANDARD:
bc9019e1
RC		 1373 /* U-Boot only checks the first byte */
1374 if (info->manufacturer_id == (uchar)ATM_MANUFACT) {
1375 if (prot) {
1376 flash_unlock_seq (info, 0);
1377 flash_write_cmd (info, 0,
1378 info->addr_unlock1,
1379 ATM_CMD_SOFTLOCK_START);
1380 flash_unlock_seq (info, 0);
1381 flash_write_cmd (info, sector, 0,
1382 ATM_CMD_LOCK_SECT);
1383 } else {
1384 flash_write_cmd (info, 0,
1385 info->addr_unlock1,
1386 AMD_CMD_UNLOCK_START);
1387 if (info->device_id == ATM_ID_BV6416)
1388 flash_write_cmd (info, sector,
1389 0, ATM_CMD_UNLOCK_SECT);
1390 }
1391 }
1392 break;
4e00acde
TL		 1393#ifdef CONFIG_FLASH_CFI_LEGACY
1394 case CFI_CMDSET_AMD_LEGACY:
1395 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1396 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1397 if (prot)
1398 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
1399 else
1400 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
1401#endif
bc9019e1 1402 };
bf9e3b38 1403
be60a902
HS		 1404 if ((retcode =
1405 flash_full_status_check (info, sector, info->erase_blk_tout,
1406 prot ? "protect" : "unprotect")) == 0) {
bf9e3b38 1407
be60a902
HS		 1408 info->protect[sector] = prot;
1409
1410 /*
1411 * On some of Intel's flash chips (marked via legacy_unlock)
1412 * unprotect unprotects all locking.
1413 */
1414 if ((prot == 0) && (info->legacy_unlock)) {
1415 flash_sect_t i;
1416
1417 for (i = 0; i < info->sector_count; i++) {
1418 if (info->protect[i])
1419 flash_real_protect (info, i, 1);
1420 }
5653fc33 1421 }
5653fc33 1422 }
be60a902 1423 return retcode;
5653fc33 1424}
bf9e3b38 1425
5653fc33 1426/*-----------------------------------------------------------------------
be60a902 1427 * flash_read_user_serial - read the OneTimeProgramming cells
5653fc33 1428 */
be60a902
HS		 1429void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
1430 int len)
5653fc33 1431{
be60a902
HS		 1432 uchar *src;
1433 uchar *dst;
bf9e3b38 1434
be60a902 1435 dst = buffer;
12d30aa7 1436 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION);
be60a902
HS		 1437 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1438 memcpy (dst, src + offset, len);
1439 flash_write_cmd (info, 0, 0, info->cmd_reset);
12d30aa7 1440 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
5653fc33
WD		 1441}
1442
be60a902
HS		 1443/*
1444 * flash_read_factory_serial - read the device Id from the protection area
5653fc33 1445 */
be60a902
HS		 1446void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
1447 int len)
5653fc33 1448{
be60a902 1449 uchar *src;
bf9e3b38 1450
12d30aa7 1451 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
be60a902
HS		 1452 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1453 memcpy (buffer, src + offset, len);
1454 flash_write_cmd (info, 0, 0, info->cmd_reset);
12d30aa7 1455 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
5653fc33
WD		 1456}
1457
be60a902
HS		 1458#endif /* CFG_FLASH_PROTECTION */
1459
0ddf06dd
HS		 1460/*-----------------------------------------------------------------------
1461 * Reverse the order of the erase regions in the CFI QRY structure.
1462 * This is needed for chips that are either a) correctly detected as
1463 * top-boot, or b) buggy.
1464 */
1465static void cfi_reverse_geometry(struct cfi_qry *qry)
1466{
1467 unsigned int i, j;
1468 u32 tmp;
1469
1470 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
1471 tmp = qry->erase_region_info[i];
1472 qry->erase_region_info[i] = qry->erase_region_info[j];
1473 qry->erase_region_info[j] = tmp;
1474 }
1475}
be60a902 1476
260421a2
SR		 1477/*-----------------------------------------------------------------------
1478 * read jedec ids from device and set corresponding fields in info struct
1479 *
1480 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1481 *
0ddf06dd
HS		 1482 */
1483static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1484{
1485 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1486 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1487 udelay(1000); /* some flash are slow to respond */
1488 info->manufacturer_id = flash_read_uchar (info,
1489 FLASH_OFFSET_MANUFACTURER_ID);
1490 info->device_id = flash_read_uchar (info,
1491 FLASH_OFFSET_DEVICE_ID);
1492 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1493}
1494
1495static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1496{
1497 info->cmd_reset = FLASH_CMD_RESET;
1498
1499 cmdset_intel_read_jedec_ids(info);
1500 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1501
1502#ifdef CFG_FLASH_PROTECTION
1503 /* read legacy lock/unlock bit from intel flash */
1504 if (info->ext_addr) {
1505 info->legacy_unlock = flash_read_uchar (info,
1506 info->ext_addr + 5) & 0x08;
1507 }
1508#endif
1509
1510 return 0;
1511}
1512
1513static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1514{
1515 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1516 flash_unlock_seq(info, 0);
1517 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1518 udelay(1000); /* some flash are slow to respond */
90447ecb 1519
0ddf06dd
HS		 1520 info->manufacturer_id = flash_read_uchar (info,
1521 FLASH_OFFSET_MANUFACTURER_ID);
90447ecb
TK		 1522
1523 switch (info->chipwidth){
1524 case FLASH_CFI_8BIT:
1525 info->device_id = flash_read_uchar (info,
1526 FLASH_OFFSET_DEVICE_ID);
1527 if (info->device_id == 0x7E) {
1528 /* AMD 3-byte (expanded) device ids */
1529 info->device_id2 = flash_read_uchar (info,
1530 FLASH_OFFSET_DEVICE_ID2);
1531 info->device_id2 <<= 8;
1532 info->device_id2 |= flash_read_uchar (info,
1533 FLASH_OFFSET_DEVICE_ID3);
1534 }
1535 break;
1536 case FLASH_CFI_16BIT:
1537 info->device_id = flash_read_word (info,
1538 FLASH_OFFSET_DEVICE_ID);
1539 break;
1540 default:
1541 break;
0ddf06dd
HS		 1542 }
1543 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1544}
1545
1546static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1547{
1548 info->cmd_reset = AMD_CMD_RESET;
1549
1550 cmdset_amd_read_jedec_ids(info);
1551 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1552
0ddf06dd
HS		 1553 return 0;
1554}
1555
1556#ifdef CONFIG_FLASH_CFI_LEGACY
260421a2
SR		 1557static void flash_read_jedec_ids (flash_info_t * info)
1558{
1559 info->manufacturer_id = 0;
1560 info->device_id = 0;
1561 info->device_id2 = 0;
1562
1563 switch (info->vendor) {
9c048b52 1564 case CFI_CMDSET_INTEL_PROG_REGIONS:
260421a2
SR		 1565 case CFI_CMDSET_INTEL_STANDARD:
1566 case CFI_CMDSET_INTEL_EXTENDED:
8225d1e3 1567 cmdset_intel_read_jedec_ids(info);
260421a2
SR		 1568 break;
1569 case CFI_CMDSET_AMD_STANDARD:
1570 case CFI_CMDSET_AMD_EXTENDED:
8225d1e3 1571 cmdset_amd_read_jedec_ids(info);
260421a2
SR		 1572 break;
1573 default:
1574 break;
1575 }
1576}
1577
5653fc33 1578/*-----------------------------------------------------------------------
be60a902
HS		 1579 * Call board code to request info about non-CFI flash.
1580 * board_flash_get_legacy needs to fill in at least:
1581 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
7e5b9b47 1582 */
be60a902 1583static int flash_detect_legacy(ulong base, int banknum)
5653fc33 1584{
be60a902 1585 flash_info_t *info = &flash_info[banknum];
7e5b9b47 1586
be60a902
HS		 1587 if (board_flash_get_legacy(base, banknum, info)) {
1588 /* board code may have filled info completely. If not, we
1589 use JEDEC ID probing. */
1590 if (!info->vendor) {
1591 int modes[] = {
1592 CFI_CMDSET_AMD_STANDARD,
1593 CFI_CMDSET_INTEL_STANDARD
1594 };
1595 int i;
7e5b9b47 1596
be60a902
HS		 1597 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
1598 info->vendor = modes[i];
1599 info->start[0] = base;
1600 if (info->portwidth == FLASH_CFI_8BIT
1601 && info->interface == FLASH_CFI_X8X16) {
1602 info->addr_unlock1 = 0x2AAA;
1603 info->addr_unlock2 = 0x5555;
1604 } else {
1605 info->addr_unlock1 = 0x5555;
1606 info->addr_unlock2 = 0x2AAA;
1607 }
1608 flash_read_jedec_ids(info);
1609 debug("JEDEC PROBE: ID %x %x %x\n",
1610 info->manufacturer_id,
1611 info->device_id,
1612 info->device_id2);
1613 if (jedec_flash_match(info, base))
1614 break;
1615 }
1616 }
1617
1618 switch(info->vendor) {
9c048b52 1619 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1620 case CFI_CMDSET_INTEL_STANDARD:
1621 case CFI_CMDSET_INTEL_EXTENDED:
1622 info->cmd_reset = FLASH_CMD_RESET;
1623 break;
1624 case CFI_CMDSET_AMD_STANDARD:
1625 case CFI_CMDSET_AMD_EXTENDED:
1626 case CFI_CMDSET_AMD_LEGACY:
1627 info->cmd_reset = AMD_CMD_RESET;
1628 break;
1629 }
1630 info->flash_id = FLASH_MAN_CFI;
1631 return 1;
1632 }
1633 return 0; /* use CFI */
1634}
1635#else
1636static inline int flash_detect_legacy(ulong base, int banknum)
1637{
1638 return 0; /* use CFI */
1639}
1640#endif
1641
1642/*-----------------------------------------------------------------------
1643 * detect if flash is compatible with the Common Flash Interface (CFI)
1644 * http://www.jedec.org/download/search/jesd68.pdf
1645 */
e23741f4
HS		 1646static void flash_read_cfi (flash_info_t *info, void *buf,
1647 unsigned int start, size_t len)
1648{
1649 u8 *p = buf;
1650 unsigned int i;
1651
1652 for (i = 0; i < len; i++)
1653 p[i] = flash_read_uchar(info, start + i);
1654}
1655
1656static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
be60a902
HS		 1657{
1658 int cfi_offset;
1659
1ba639da
MS		 1660 /* We do not yet know what kind of commandset to use, so we issue
1661 the reset command in both Intel and AMD variants, in the hope
1662 that AMD flash roms ignore the Intel command. */
1663 flash_write_cmd (info, 0, 0, AMD_CMD_RESET);
1664 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
1665
be60a902
HS		 1666 for (cfi_offset=0;
1667 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);
1668 cfi_offset++) {
1669 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
1670 FLASH_CMD_CFI);
1671 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
1672 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
1673 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
e23741f4
HS		 1674 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1675 sizeof(struct cfi_qry));
1676 info->interface = le16_to_cpu(qry->interface_desc);
1677
be60a902
HS		 1678 info->cfi_offset = flash_offset_cfi[cfi_offset];
1679 debug ("device interface is %d\n",
1680 info->interface);
1681 debug ("found port %d chip %d ",
1682 info->portwidth, info->chipwidth);
1683 debug ("port %d bits chip %d bits\n",
1684 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1685 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1686
1687 /* calculate command offsets as in the Linux driver */
1688 info->addr_unlock1 = 0x555;
7e5b9b47
HS		 1689 info->addr_unlock2 = 0x2aa;
1690
1691 /*
1692 * modify the unlock address if we are
1693 * in compatibility mode
1694 */
1695 if ( /* x8/x16 in x8 mode */
1696 ((info->chipwidth == FLASH_CFI_BY8) &&
1697 (info->interface == FLASH_CFI_X8X16)) ||
1698 /* x16/x32 in x16 mode */
1699 ((info->chipwidth == FLASH_CFI_BY16) &&
1700 (info->interface == FLASH_CFI_X16X32)))
1701 {
1702 info->addr_unlock1 = 0xaaa;
1703 info->addr_unlock2 = 0x555;
1704 }
1705
1706 info->name = "CFI conformant";
1707 return 1;
1708 }
1709 }
1710
1711 return 0;
1712}
1713
e23741f4 1714static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
7e5b9b47 1715{
bf9e3b38
WD		 1716 debug ("flash detect cfi\n");
1717
79b4cda0 1718 for (info->portwidth = CFG_FLASH_CFI_WIDTH;
bf9e3b38
WD		 1719 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1720 for (info->chipwidth = FLASH_CFI_BY8;
1721 info->chipwidth <= info->portwidth;
7e5b9b47 1722 info->chipwidth <<= 1)
e23741f4 1723 if (__flash_detect_cfi(info, qry))
7e5b9b47 1724 return 1;
5653fc33 1725 }
bf9e3b38 1726 debug ("not found\n");
5653fc33
WD		 1727 return 0;
1728}
bf9e3b38 1729
467bcee1
HS		 1730/*
1731 * Manufacturer-specific quirks. Add workarounds for geometry
1732 * reversal, etc. here.
1733 */
1734static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
1735{
1736 /* check if flash geometry needs reversal */
1737 if (qry->num_erase_regions > 1) {
1738 /* reverse geometry if top boot part */
1739 if (info->cfi_version < 0x3131) {
1740 /* CFI < 1.1, try to guess from device id */
1741 if ((info->device_id & 0x80) != 0)
1742 cfi_reverse_geometry(qry);
1743 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1744 /* CFI >= 1.1, deduct from top/bottom flag */
1745 /* note: ext_addr is valid since cfi_version > 0 */
1746 cfi_reverse_geometry(qry);
1747 }
1748 }
1749}
1750
1751static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
1752{
1753 int reverse_geometry = 0;
1754
1755 /* Check the "top boot" bit in the PRI */
1756 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
1757 reverse_geometry = 1;
1758
1759 /* AT49BV6416(T) list the erase regions in the wrong order.
1760 * However, the device ID is identical with the non-broken
1761 * AT49BV642D since u-boot only reads the low byte (they
1762 * differ in the high byte.) So leave out this fixup for now.
1763 */
1764#if 0
1765 if (info->device_id == 0xd6 || info->device_id == 0xd2)
1766 reverse_geometry = !reverse_geometry;
1767#endif
1768
1769 if (reverse_geometry)
1770 cfi_reverse_geometry(qry);
1771}
1772
5653fc33
WD		 1773/*
1774 * The following code cannot be run from FLASH!
1775 *
1776 */
e6f2e902 1777ulong flash_get_size (ulong base, int banknum)
5653fc33 1778{
bf9e3b38 1779 flash_info_t *info = &flash_info[banknum];
5653fc33
WD		 1780 int i, j;
1781 flash_sect_t sect_cnt;
1782 unsigned long sector;
1783 unsigned long tmp;
1784 int size_ratio;
1785 uchar num_erase_regions;
bf9e3b38
WD		 1786 int erase_region_size;
1787 int erase_region_count;
e23741f4 1788 struct cfi_qry qry;
260421a2 1789
f979690e
KG		 1790 memset(&qry, 0, sizeof(qry));
1791
260421a2
SR		 1792 info->ext_addr = 0;
1793 info->cfi_version = 0;
2662b40c 1794#ifdef CFG_FLASH_PROTECTION
2662b40c
SR		 1795 info->legacy_unlock = 0;
1796#endif
5653fc33
WD		 1797
1798 info->start[0] = base;
1799
e23741f4
HS		 1800 if (flash_detect_cfi (info, &qry)) {
1801 info->vendor = le16_to_cpu(qry.p_id);
1802 info->ext_addr = le16_to_cpu(qry.p_adr);
1803 num_erase_regions = qry.num_erase_regions;
1804
260421a2
SR		 1805 if (info->ext_addr) {
1806 info->cfi_version = (ushort) flash_read_uchar (info,
1807 info->ext_addr + 3) << 8;
1808 info->cfi_version |= (ushort) flash_read_uchar (info,
1809 info->ext_addr + 4);
1810 }
0ddf06dd 1811
bf9e3b38 1812#ifdef DEBUG
e23741f4 1813 flash_printqry (&qry);
bf9e3b38 1814#endif
0ddf06dd 1815
bf9e3b38 1816 switch (info->vendor) {
9c048b52 1817 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 1818 case CFI_CMDSET_INTEL_STANDARD:
1819 case CFI_CMDSET_INTEL_EXTENDED:
0ddf06dd 1820 cmdset_intel_init(info, &qry);
5653fc33
WD		 1821 break;
1822 case CFI_CMDSET_AMD_STANDARD:
1823 case CFI_CMDSET_AMD_EXTENDED:
0ddf06dd 1824 cmdset_amd_init(info, &qry);
5653fc33 1825 break;
0ddf06dd
HS		 1826 default:
1827 printf("CFI: Unknown command set 0x%x\n",
1828 info->vendor);
1829 /*
1830 * Unfortunately, this means we don't know how
1831 * to get the chip back to Read mode. Might
1832 * as well try an Intel-style reset...
1833 */
1834 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1835 return 0;
5653fc33 1836 }
cd37d9e6 1837
467bcee1
HS		 1838 /* Do manufacturer-specific fixups */
1839 switch (info->manufacturer_id) {
1840 case 0x0001:
1841 flash_fixup_amd(info, &qry);
1842 break;
1843 case 0x001f:
1844 flash_fixup_atmel(info, &qry);
1845 break;
1846 }
1847
bf9e3b38 1848 debug ("manufacturer is %d\n", info->vendor);
260421a2
SR		 1849 debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
1850 debug ("device id is 0x%x\n", info->device_id);
1851 debug ("device id2 is 0x%x\n", info->device_id2);
1852 debug ("cfi version is 0x%04x\n", info->cfi_version);
1853
5653fc33 1854 size_ratio = info->portwidth / info->chipwidth;
bf9e3b38
WD		 1855 /* if the chip is x8/x16 reduce the ratio by half */
1856 if ((info->interface == FLASH_CFI_X8X16)
1857 && (info->chipwidth == FLASH_CFI_BY8)) {
1858 size_ratio >>= 1;
1859 }
bf9e3b38
WD		 1860 debug ("size_ratio %d port %d bits chip %d bits\n",
1861 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1862 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1863 debug ("found %d erase regions\n", num_erase_regions);
5653fc33
WD		 1864 sect_cnt = 0;
1865 sector = base;
bf9e3b38
WD		 1866 for (i = 0; i < num_erase_regions; i++) {
1867 if (i > NUM_ERASE_REGIONS) {
028ab6b5
WD		 1868 printf ("%d erase regions found, only %d used\n",
1869 num_erase_regions, NUM_ERASE_REGIONS);
5653fc33
WD		 1870 break;
1871 }
e23741f4 1872
0ddf06dd
HS		 1873 tmp = le32_to_cpu(qry.erase_region_info[i]);
1874 debug("erase region %u: 0x%08lx\n", i, tmp);
e23741f4
HS		 1875
1876 erase_region_count = (tmp & 0xffff) + 1;
1877 tmp >>= 16;
bf9e3b38
WD		 1878 erase_region_size =
1879 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
4c0d4c3b 1880 debug ("erase_region_count = %d erase_region_size = %d\n",
028ab6b5 1881 erase_region_count, erase_region_size);
bf9e3b38 1882 for (j = 0; j < erase_region_count; j++) {
81b20ccc
MS		 1883 if (sect_cnt >= CFG_MAX_FLASH_SECT) {
1884 printf("ERROR: too many flash sectors\n");
1885 break;
1886 }
5653fc33
WD		 1887 info->start[sect_cnt] = sector;
1888 sector += (erase_region_size * size_ratio);
a1191902
WD		 1889
1890 /*
7e5b9b47
HS		 1891 * Only read protection status from
1892 * supported devices (intel...)
a1191902
WD		 1893 */
1894 switch (info->vendor) {
9c048b52 1895 case CFI_CMDSET_INTEL_PROG_REGIONS:
a1191902
WD		 1896 case CFI_CMDSET_INTEL_EXTENDED:
1897 case CFI_CMDSET_INTEL_STANDARD:
1898 info->protect[sect_cnt] =
1899 flash_isset (info, sect_cnt,
1900 FLASH_OFFSET_PROTECT,
1901 FLASH_STATUS_PROTECT);
1902 break;
1903 default:
7e5b9b47
HS		 1904 /* default: not protected */
1905 info->protect[sect_cnt] = 0;
a1191902
WD		 1906 }
1907
5653fc33
WD		 1908 sect_cnt++;
1909 }
1910 }
1911
1912 info->sector_count = sect_cnt;
e23741f4 1913 info->size = 1 << qry.dev_size;
5653fc33 1914 /* multiply the size by the number of chips */
7e5b9b47 1915 info->size *= size_ratio;
e23741f4
HS		 1916 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
1917 tmp = 1 << qry.block_erase_timeout_typ;
7e5b9b47 1918 info->erase_blk_tout = tmp *
e23741f4
HS		 1919 (1 << qry.block_erase_timeout_max);
1920 tmp = (1 << qry.buf_write_timeout_typ) *
1921 (1 << qry.buf_write_timeout_max);
1922
7e5b9b47 1923 /* round up when converting to ms */
e23741f4
HS		 1924 info->buffer_write_tout = (tmp + 999) / 1000;
1925 tmp = (1 << qry.word_write_timeout_typ) *
1926 (1 << qry.word_write_timeout_max);
7e5b9b47 1927 /* round up when converting to ms */
e23741f4 1928 info->write_tout = (tmp + 999) / 1000;
5653fc33 1929 info->flash_id = FLASH_MAN_CFI;
7e5b9b47
HS		 1930 if ((info->interface == FLASH_CFI_X8X16) &&
1931 (info->chipwidth == FLASH_CFI_BY8)) {
1932 /* XXX - Need to test on x8/x16 in parallel. */
1933 info->portwidth >>= 1;
855a496f 1934 }
2215987e
MF		 1935
1936 flash_write_cmd (info, 0, 0, info->cmd_reset);
5653fc33
WD		 1937 }
1938
bf9e3b38 1939 return (info->size);
5653fc33
WD		 1940}
1941
5653fc33
WD		 1942/*-----------------------------------------------------------------------
1943 */
be60a902 1944unsigned long flash_init (void)
5653fc33 1945{
be60a902
HS		 1946 unsigned long size = 0;
1947 int i;
c63ad632
MF		 1948#if defined(CFG_FLASH_AUTOPROTECT_LIST)
1949 struct apl_s {
1950 ulong start;
1951 ulong size;
1952 } apl[] = CFG_FLASH_AUTOPROTECT_LIST;
1953#endif
5653fc33 1954
be60a902
HS		 1955#ifdef CFG_FLASH_PROTECTION
1956 char *s = getenv("unlock");
81b20ccc 1957#endif
5653fc33 1958
2a112b23
WD		 1959#define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CFG_FLASH_BANKS_LIST)[i])
1960
be60a902
HS		 1961 /* Init: no FLASHes known */
1962 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
1963 flash_info[i].flash_id = FLASH_UNKNOWN;
5653fc33 1964
2a112b23
WD		 1965 if (!flash_detect_legacy (BANK_BASE(i), i))
1966 flash_get_size (BANK_BASE(i), i);
be60a902
HS		 1967 size += flash_info[i].size;
1968 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
1969#ifndef CFG_FLASH_QUIET_TEST
1970 printf ("## Unknown FLASH on Bank %d "
1971 "- Size = 0x%08lx = %ld MB\n",
1972 i+1, flash_info[i].size,
1973 flash_info[i].size << 20);
1974#endif /* CFG_FLASH_QUIET_TEST */
1975 }
1976#ifdef CFG_FLASH_PROTECTION
1977 else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
1978 /*
1979 * Only the U-Boot image and it's environment
1980 * is protected, all other sectors are
1981 * unprotected (unlocked) if flash hardware
1982 * protection is used (CFG_FLASH_PROTECTION)
1983 * and the environment variable "unlock" is
1984 * set to "yes".
1985 */
1986 if (flash_info[i].legacy_unlock) {
1987 int k;
5653fc33 1988
be60a902
HS		 1989 /*
1990 * Disable legacy_unlock temporarily,
1991 * since flash_real_protect would
1992 * relock all other sectors again
1993 * otherwise.
1994 */
1995 flash_info[i].legacy_unlock = 0;
5653fc33 1996
be60a902
HS		 1997 /*
1998 * Legacy unlocking (e.g. Intel J3) ->
1999 * unlock only one sector. This will
2000 * unlock all sectors.
2001 */
2002 flash_real_protect (&flash_info[i], 0, 0);
5653fc33 2003
be60a902 2004 flash_info[i].legacy_unlock = 1;
5653fc33 2005
be60a902
HS		 2006 /*
2007 * Manually mark other sectors as
2008 * unlocked (unprotected)
2009 */
2010 for (k = 1; k < flash_info[i].sector_count; k++)
2011 flash_info[i].protect[k] = 0;
2012 } else {
2013 /*
2014 * No legancy unlocking -> unlock all sectors
2015 */
2016 flash_protect (FLAG_PROTECT_CLEAR,
2017 flash_info[i].start[0],
2018 flash_info[i].start[0]
2019 + flash_info[i].size - 1,
2020 &flash_info[i]);
79b4cda0 2021 }
79b4cda0 2022 }
be60a902
HS		 2023#endif /* CFG_FLASH_PROTECTION */
2024 }
79b4cda0 2025
be60a902
HS		 2026 /* Monitor protection ON by default */
2027#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
2028 flash_protect (FLAG_PROTECT_SET,
2029 CFG_MONITOR_BASE,
2030 CFG_MONITOR_BASE + monitor_flash_len - 1,
2031 flash_get_info(CFG_MONITOR_BASE));
2032#endif
79b4cda0 2033
be60a902 2034 /* Environment protection ON by default */
5a1aceb0 2035#ifdef CONFIG_ENV_IS_IN_FLASH
be60a902 2036 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV		 2037 CONFIG_ENV_ADDR,
2038 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
2039 flash_get_info(CONFIG_ENV_ADDR));
be60a902 2040#endif
79b4cda0 2041
be60a902 2042 /* Redundant environment protection ON by default */
0e8d1586 2043#ifdef CONFIG_ENV_ADDR_REDUND
be60a902 2044 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV		 2045 CONFIG_ENV_ADDR_REDUND,
2046 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
2047 flash_get_info(CONFIG_ENV_ADDR_REDUND));
be60a902 2048#endif
c63ad632
MF		 2049
2050#if defined(CFG_FLASH_AUTOPROTECT_LIST)
2051 for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) {
2052 debug("autoprotecting from %08x to %08x\n",
2053 apl[i].start, apl[i].start + apl[i].size - 1);
2054 flash_protect (FLAG_PROTECT_SET,
2055 apl[i].start,
2056 apl[i].start + apl[i].size - 1,
2057 flash_get_info(apl[i].start));
2058 }
2059#endif
be60a902 2060 return (size);
5653fc33 2061}
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