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5653fc33 1/*
bf9e3b38 2 * (C) Copyright 2002-2004
5653fc33
WD
3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
5653fc33 7 *
bf9e3b38
WD
8 * Copyright (C) 2004
9 * Ed Okerson
260421a2
SR
10 *
11 * Copyright (C) 2006
12 * Tolunay Orkun <listmember@orkun.us>
bf9e3b38 13 *
5653fc33
WD
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 *
5653fc33
WD
32 */
33
34/* The DEBUG define must be before common to enable debugging */
2d1a537d
WD
35/* #define DEBUG */
36
5653fc33
WD
37#include <common.h>
38#include <asm/processor.h>
3a197b2f 39#include <asm/io.h>
4c0d4c3b 40#include <asm/byteorder.h>
2a8af187 41#include <environment.h>
fa36ae79 42#include <mtd/cfi_flash.h>
028ab6b5 43
5653fc33 44/*
7e5b9b47
HS
45 * This file implements a Common Flash Interface (CFI) driver for
46 * U-Boot.
47 *
48 * The width of the port and the width of the chips are determined at
49 * initialization. These widths are used to calculate the address for
50 * access CFI data structures.
5653fc33
WD
51 *
52 * References
53 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
54 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
55 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
56 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
260421a2
SR
57 * AMD CFI Specification, Release 2.0 December 1, 2001
58 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
59 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
5653fc33 60 *
6d0f6bcf 61 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
d0b6e140 62 * reading and writing ... (yes there is such a Hardware).
5653fc33
WD
63 */
64
7e5b9b47 65static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
6ea808ef 66static uint flash_verbose = 1;
92eb729b 67
2a112b23
WD
68flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
69
79b4cda0
SR
70/*
71 * Check if chip width is defined. If not, start detecting with 8bit.
72 */
6d0f6bcf
JCPV
73#ifndef CONFIG_SYS_FLASH_CFI_WIDTH
74#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
79b4cda0
SR
75#endif
76
ca5def3f
SR
77#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
78int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
79#endif
80
b00e19cc
SR
81static phys_addr_t __cfi_flash_bank_addr(int i)
82{
83 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
84}
85phys_addr_t cfi_flash_bank_addr(int i)
86 __attribute__((weak, alias("__cfi_flash_bank_addr")));
87
45aa5a7f 88static void __flash_write8(u8 value, void *addr)
cdbaefb5
HS
89{
90 __raw_writeb(value, addr);
91}
92
45aa5a7f 93static void __flash_write16(u16 value, void *addr)
cdbaefb5
HS
94{
95 __raw_writew(value, addr);
96}
97
45aa5a7f 98static void __flash_write32(u32 value, void *addr)
cdbaefb5
HS
99{
100 __raw_writel(value, addr);
101}
102
45aa5a7f 103static void __flash_write64(u64 value, void *addr)
cdbaefb5
HS
104{
105 /* No architectures currently implement __raw_writeq() */
106 *(volatile u64 *)addr = value;
107}
108
45aa5a7f 109static u8 __flash_read8(void *addr)
cdbaefb5
HS
110{
111 return __raw_readb(addr);
112}
113
45aa5a7f 114static u16 __flash_read16(void *addr)
cdbaefb5
HS
115{
116 return __raw_readw(addr);
117}
118
45aa5a7f 119static u32 __flash_read32(void *addr)
cdbaefb5
HS
120{
121 return __raw_readl(addr);
122}
123
97bf85d7 124static u64 __flash_read64(void *addr)
cdbaefb5
HS
125{
126 /* No architectures currently implement __raw_readq() */
127 return *(volatile u64 *)addr;
128}
129
45aa5a7f
SR
130#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
131void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8")));
132void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16")));
133void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32")));
134void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64")));
135u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8")));
136u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16")));
137u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32")));
97bf85d7 138u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
45aa5a7f
SR
139#else
140#define flash_write8 __flash_write8
141#define flash_write16 __flash_write16
142#define flash_write32 __flash_write32
143#define flash_write64 __flash_write64
144#define flash_read8 __flash_read8
145#define flash_read16 __flash_read16
146#define flash_read32 __flash_read32
147#define flash_read64 __flash_read64
148#endif
97bf85d7 149
5653fc33 150/*-----------------------------------------------------------------------
5653fc33 151 */
6d0f6bcf 152#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
4f975678 153flash_info_t *flash_get_info(ulong base)
be60a902
HS
154{
155 int i;
cba34aaf 156 flash_info_t *info = NULL;
5653fc33 157
6d0f6bcf 158 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
be60a902
HS
159 info = & flash_info[i];
160 if (info->size && info->start[0] <= base &&
161 base <= info->start[0] + info->size - 1)
162 break;
163 }
5653fc33 164
cba34aaf 165 return info;
be60a902 166}
5653fc33
WD
167#endif
168
12d30aa7
HS
169unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
170{
171 if (sect != (info->sector_count - 1))
172 return info->start[sect + 1] - info->start[sect];
173 else
174 return info->start[0] + info->size - info->start[sect];
175}
176
bf9e3b38
WD
177/*-----------------------------------------------------------------------
178 * create an address based on the offset and the port width
179 */
12d30aa7
HS
180static inline void *
181flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
bf9e3b38 182{
12d30aa7
HS
183 unsigned int byte_offset = offset * info->portwidth;
184
09ce9921 185 return (void *)(info->start[sect] + byte_offset);
12d30aa7
HS
186}
187
188static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
189 unsigned int offset, void *addr)
190{
bf9e3b38
WD
191}
192
be60a902
HS
193/*-----------------------------------------------------------------------
194 * make a proper sized command based on the port and chip widths
195 */
7288f972 196static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
be60a902
HS
197{
198 int i;
93c56f21
VL
199 int cword_offset;
200 int cp_offset;
6d0f6bcf 201#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
340ccb26
SS
202 u32 cmd_le = cpu_to_le32(cmd);
203#endif
93c56f21 204 uchar val;
be60a902
HS
205 uchar *cp = (uchar *) cmdbuf;
206
93c56f21
VL
207 for (i = info->portwidth; i > 0; i--){
208 cword_offset = (info->portwidth-i)%info->chipwidth;
6d0f6bcf 209#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
93c56f21 210 cp_offset = info->portwidth - i;
340ccb26 211 val = *((uchar*)&cmd_le + cword_offset);
be60a902 212#else
93c56f21 213 cp_offset = i - 1;
7288f972 214 val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1);
be60a902 215#endif
7288f972 216 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
93c56f21 217 }
be60a902
HS
218}
219
5653fc33 220#ifdef DEBUG
bf9e3b38
WD
221/*-----------------------------------------------------------------------
222 * Debug support
223 */
3055793b 224static void print_longlong (char *str, unsigned long long data)
5653fc33
WD
225{
226 int i;
227 char *cp;
bf9e3b38 228
657f2062 229 cp = (char *) &data;
bf9e3b38
WD
230 for (i = 0; i < 8; i++)
231 sprintf (&str[i * 2], "%2.2x", *cp++);
232}
be60a902 233
e23741f4 234static void flash_printqry (struct cfi_qry *qry)
bf9e3b38 235{
e23741f4 236 u8 *p = (u8 *)qry;
bf9e3b38
WD
237 int x, y;
238
e23741f4
HS
239 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
240 debug("%02x : ", x);
241 for (y = 0; y < 16; y++)
242 debug("%2.2x ", p[x + y]);
243 debug(" ");
bf9e3b38 244 for (y = 0; y < 16; y++) {
e23741f4
HS
245 unsigned char c = p[x + y];
246 if (c >= 0x20 && c <= 0x7e)
247 debug("%c", c);
248 else
249 debug(".");
bf9e3b38 250 }
e23741f4 251 debug("\n");
bf9e3b38 252 }
5653fc33
WD
253}
254#endif
255
256
5653fc33
WD
257/*-----------------------------------------------------------------------
258 * read a character at a port width address
259 */
3055793b 260static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
5653fc33
WD
261{
262 uchar *cp;
12d30aa7 263 uchar retval;
bf9e3b38 264
12d30aa7 265 cp = flash_map (info, 0, offset);
6d0f6bcf 266#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
12d30aa7 267 retval = flash_read8(cp);
bf9e3b38 268#else
12d30aa7 269 retval = flash_read8(cp + info->portwidth - 1);
bf9e3b38 270#endif
12d30aa7
HS
271 flash_unmap (info, 0, offset, cp);
272 return retval;
5653fc33
WD
273}
274
90447ecb
TK
275/*-----------------------------------------------------------------------
276 * read a word at a port width address, assume 16bit bus
277 */
278static inline ushort flash_read_word (flash_info_t * info, uint offset)
279{
280 ushort *addr, retval;
281
282 addr = flash_map (info, 0, offset);
283 retval = flash_read16 (addr);
284 flash_unmap (info, 0, offset, addr);
285 return retval;
286}
287
288
5653fc33 289/*-----------------------------------------------------------------------
260421a2 290 * read a long word by picking the least significant byte of each maximum
5653fc33
WD
291 * port size word. Swap for ppc format.
292 */
3055793b
HS
293static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
294 uint offset)
5653fc33 295{
bf9e3b38
WD
296 uchar *addr;
297 ulong retval;
298
299#ifdef DEBUG
300 int x;
301#endif
12d30aa7 302 addr = flash_map (info, sect, offset);
5653fc33 303
bf9e3b38
WD
304#ifdef DEBUG
305 debug ("long addr is at %p info->portwidth = %d\n", addr,
306 info->portwidth);
307 for (x = 0; x < 4 * info->portwidth; x++) {
12d30aa7 308 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
bf9e3b38
WD
309 }
310#endif
6d0f6bcf 311#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
12d30aa7
HS
312 retval = ((flash_read8(addr) << 16) |
313 (flash_read8(addr + info->portwidth) << 24) |
314 (flash_read8(addr + 2 * info->portwidth)) |
315 (flash_read8(addr + 3 * info->portwidth) << 8));
bf9e3b38 316#else
12d30aa7
HS
317 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
318 (flash_read8(addr + info->portwidth - 1) << 16) |
319 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
320 (flash_read8(addr + 3 * info->portwidth - 1)));
bf9e3b38 321#endif
12d30aa7
HS
322 flash_unmap(info, sect, offset, addr);
323
bf9e3b38 324 return retval;
5653fc33
WD
325}
326
be60a902
HS
327/*
328 * Write a proper sized command to the correct address
81b20ccc 329 */
fa36ae79
SR
330void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
331 uint offset, u32 cmd)
81b20ccc 332{
7e5b9b47 333
cdbaefb5 334 void *addr;
be60a902 335 cfiword_t cword;
81b20ccc 336
12d30aa7 337 addr = flash_map (info, sect, offset);
be60a902
HS
338 flash_make_cmd (info, cmd, &cword);
339 switch (info->portwidth) {
340 case FLASH_CFI_8BIT:
cdbaefb5 341 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
be60a902 342 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 343 flash_write8(cword.c, addr);
be60a902
HS
344 break;
345 case FLASH_CFI_16BIT:
cdbaefb5 346 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
be60a902
HS
347 cmd, cword.w,
348 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 349 flash_write16(cword.w, addr);
be60a902
HS
350 break;
351 case FLASH_CFI_32BIT:
cdbaefb5 352 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
be60a902
HS
353 cmd, cword.l,
354 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 355 flash_write32(cword.l, addr);
be60a902
HS
356 break;
357 case FLASH_CFI_64BIT:
358#ifdef DEBUG
359 {
360 char str[20];
7e5b9b47 361
be60a902
HS
362 print_longlong (str, cword.ll);
363
364 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
cdbaefb5 365 addr, cmd, str,
be60a902 366 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
81b20ccc 367 }
be60a902 368#endif
cdbaefb5 369 flash_write64(cword.ll, addr);
be60a902 370 break;
81b20ccc 371 }
be60a902
HS
372
373 /* Ensure all the instructions are fully finished */
374 sync();
12d30aa7
HS
375
376 flash_unmap(info, sect, offset, addr);
81b20ccc 377}
be60a902
HS
378
379static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
81b20ccc 380{
be60a902
HS
381 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
382 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
81b20ccc 383}
81b20ccc 384
5653fc33
WD
385/*-----------------------------------------------------------------------
386 */
be60a902
HS
387static int flash_isequal (flash_info_t * info, flash_sect_t sect,
388 uint offset, uchar cmd)
5653fc33 389{
cdbaefb5 390 void *addr;
be60a902
HS
391 cfiword_t cword;
392 int retval;
5653fc33 393
12d30aa7 394 addr = flash_map (info, sect, offset);
be60a902 395 flash_make_cmd (info, cmd, &cword);
2662b40c 396
cdbaefb5 397 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
be60a902
HS
398 switch (info->portwidth) {
399 case FLASH_CFI_8BIT:
cdbaefb5
HS
400 debug ("is= %x %x\n", flash_read8(addr), cword.c);
401 retval = (flash_read8(addr) == cword.c);
be60a902
HS
402 break;
403 case FLASH_CFI_16BIT:
cdbaefb5
HS
404 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
405 retval = (flash_read16(addr) == cword.w);
be60a902
HS
406 break;
407 case FLASH_CFI_32BIT:
52514699 408 debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l);
cdbaefb5 409 retval = (flash_read32(addr) == cword.l);
be60a902
HS
410 break;
411 case FLASH_CFI_64BIT:
412#ifdef DEBUG
413 {
414 char str1[20];
415 char str2[20];
81b20ccc 416
cdbaefb5 417 print_longlong (str1, flash_read64(addr));
be60a902
HS
418 print_longlong (str2, cword.ll);
419 debug ("is= %s %s\n", str1, str2);
5653fc33 420 }
be60a902 421#endif
cdbaefb5 422 retval = (flash_read64(addr) == cword.ll);
be60a902
HS
423 break;
424 default:
425 retval = 0;
426 break;
427 }
12d30aa7
HS
428 flash_unmap(info, sect, offset, addr);
429
be60a902
HS
430 return retval;
431}
79b4cda0 432
be60a902
HS
433/*-----------------------------------------------------------------------
434 */
435static int flash_isset (flash_info_t * info, flash_sect_t sect,
436 uint offset, uchar cmd)
437{
cdbaefb5 438 void *addr;
be60a902
HS
439 cfiword_t cword;
440 int retval;
2662b40c 441
12d30aa7 442 addr = flash_map (info, sect, offset);
be60a902
HS
443 flash_make_cmd (info, cmd, &cword);
444 switch (info->portwidth) {
445 case FLASH_CFI_8BIT:
cdbaefb5 446 retval = ((flash_read8(addr) & cword.c) == cword.c);
be60a902
HS
447 break;
448 case FLASH_CFI_16BIT:
cdbaefb5 449 retval = ((flash_read16(addr) & cword.w) == cword.w);
be60a902
HS
450 break;
451 case FLASH_CFI_32BIT:
47cc23cb 452 retval = ((flash_read32(addr) & cword.l) == cword.l);
be60a902
HS
453 break;
454 case FLASH_CFI_64BIT:
cdbaefb5 455 retval = ((flash_read64(addr) & cword.ll) == cword.ll);
be60a902
HS
456 break;
457 default:
458 retval = 0;
459 break;
460 }
12d30aa7
HS
461 flash_unmap(info, sect, offset, addr);
462
be60a902
HS
463 return retval;
464}
2662b40c 465
be60a902
HS
466/*-----------------------------------------------------------------------
467 */
468static int flash_toggle (flash_info_t * info, flash_sect_t sect,
469 uint offset, uchar cmd)
470{
cdbaefb5 471 void *addr;
be60a902
HS
472 cfiword_t cword;
473 int retval;
656658dd 474
12d30aa7 475 addr = flash_map (info, sect, offset);
be60a902
HS
476 flash_make_cmd (info, cmd, &cword);
477 switch (info->portwidth) {
478 case FLASH_CFI_8BIT:
fb8c061e 479 retval = flash_read8(addr) != flash_read8(addr);
be60a902
HS
480 break;
481 case FLASH_CFI_16BIT:
fb8c061e 482 retval = flash_read16(addr) != flash_read16(addr);
be60a902
HS
483 break;
484 case FLASH_CFI_32BIT:
fb8c061e 485 retval = flash_read32(addr) != flash_read32(addr);
be60a902
HS
486 break;
487 case FLASH_CFI_64BIT:
9abda6ba
WD
488 retval = ( (flash_read32( addr ) != flash_read32( addr )) ||
489 (flash_read32(addr+4) != flash_read32(addr+4)) );
be60a902
HS
490 break;
491 default:
492 retval = 0;
493 break;
494 }
12d30aa7
HS
495 flash_unmap(info, sect, offset, addr);
496
be60a902 497 return retval;
5653fc33
WD
498}
499
be60a902
HS
500/*
501 * flash_is_busy - check to see if the flash is busy
502 *
503 * This routine checks the status of the chip and returns true if the
504 * chip is busy.
7680c140 505 */
be60a902 506static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
7680c140 507{
be60a902 508 int retval;
7680c140 509
be60a902 510 switch (info->vendor) {
9c048b52 511 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS
512 case CFI_CMDSET_INTEL_STANDARD:
513 case CFI_CMDSET_INTEL_EXTENDED:
514 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
515 break;
516 case CFI_CMDSET_AMD_STANDARD:
517 case CFI_CMDSET_AMD_EXTENDED:
518#ifdef CONFIG_FLASH_CFI_LEGACY
519 case CFI_CMDSET_AMD_LEGACY:
520#endif
521 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
522 break;
523 default:
524 retval = 0;
7680c140 525 }
be60a902
HS
526 debug ("flash_is_busy: %d\n", retval);
527 return retval;
7680c140
WD
528}
529
5653fc33 530/*-----------------------------------------------------------------------
be60a902
HS
531 * wait for XSR.7 to be set. Time out with an error if it does not.
532 * This routine does not set the flash to read-array mode.
5653fc33 533 */
be60a902
HS
534static int flash_status_check (flash_info_t * info, flash_sect_t sector,
535 ulong tout, char *prompt)
5653fc33 536{
be60a902 537 ulong start;
5653fc33 538
6d0f6bcf 539#if CONFIG_SYS_HZ != 1000
c40c94a3
RA
540 if ((ulong)CONFIG_SYS_HZ > 100000)
541 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
542 else
543 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
be60a902 544#endif
5653fc33 545
be60a902 546 /* Wait for command completion */
22d6c8fa 547 reset_timer();
be60a902
HS
548 start = get_timer (0);
549 while (flash_is_busy (info, sector)) {
550 if (get_timer (start) > tout) {
551 printf ("Flash %s timeout at address %lx data %lx\n",
552 prompt, info->start[sector],
553 flash_read_long (info, sector, 0));
554 flash_write_cmd (info, sector, 0, info->cmd_reset);
555 return ERR_TIMOUT;
5653fc33 556 }
be60a902 557 udelay (1); /* also triggers watchdog */
5653fc33 558 }
be60a902
HS
559 return ERR_OK;
560}
5653fc33 561
be60a902
HS
562/*-----------------------------------------------------------------------
563 * Wait for XSR.7 to be set, if it times out print an error, otherwise
564 * do a full status check.
565 *
566 * This routine sets the flash to read-array mode.
567 */
568static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
569 ulong tout, char *prompt)
570{
571 int retcode;
5653fc33 572
be60a902
HS
573 retcode = flash_status_check (info, sector, tout, prompt);
574 switch (info->vendor) {
9c048b52 575 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS
576 case CFI_CMDSET_INTEL_EXTENDED:
577 case CFI_CMDSET_INTEL_STANDARD:
0d01f66d 578 if ((retcode != ERR_OK)
be60a902
HS
579 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
580 retcode = ERR_INVAL;
581 printf ("Flash %s error at address %lx\n", prompt,
582 info->start[sector]);
583 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
584 FLASH_STATUS_PSLBS)) {
585 puts ("Command Sequence Error.\n");
586 } else if (flash_isset (info, sector, 0,
587 FLASH_STATUS_ECLBS)) {
588 puts ("Block Erase Error.\n");
589 retcode = ERR_NOT_ERASED;
590 } else if (flash_isset (info, sector, 0,
591 FLASH_STATUS_PSLBS)) {
592 puts ("Locking Error\n");
5653fc33 593 }
be60a902
HS
594 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
595 puts ("Block locked.\n");
596 retcode = ERR_PROTECTED;
597 }
598 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
599 puts ("Vpp Low Error.\n");
5653fc33 600 }
be60a902
HS
601 flash_write_cmd (info, sector, 0, info->cmd_reset);
602 break;
603 default:
604 break;
5653fc33 605 }
be60a902 606 return retcode;
5653fc33
WD
607}
608
e5720823
TC
609static int use_flash_status_poll(flash_info_t *info)
610{
611#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
612 if (info->vendor == CFI_CMDSET_AMD_EXTENDED ||
613 info->vendor == CFI_CMDSET_AMD_STANDARD)
614 return 1;
615#endif
616 return 0;
617}
618
619static int flash_status_poll(flash_info_t *info, void *src, void *dst,
620 ulong tout, char *prompt)
621{
622#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
623 ulong start;
624 int ready;
625
626#if CONFIG_SYS_HZ != 1000
627 if ((ulong)CONFIG_SYS_HZ > 100000)
628 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */
629 else
630 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
631#endif
632
633 /* Wait for command completion */
22d6c8fa 634 reset_timer();
e5720823
TC
635 start = get_timer(0);
636 while (1) {
637 switch (info->portwidth) {
638 case FLASH_CFI_8BIT:
639 ready = flash_read8(dst) == flash_read8(src);
640 break;
641 case FLASH_CFI_16BIT:
642 ready = flash_read16(dst) == flash_read16(src);
643 break;
644 case FLASH_CFI_32BIT:
645 ready = flash_read32(dst) == flash_read32(src);
646 break;
647 case FLASH_CFI_64BIT:
648 ready = flash_read64(dst) == flash_read64(src);
649 break;
650 default:
651 ready = 0;
652 break;
653 }
654 if (ready)
655 break;
656 if (get_timer(start) > tout) {
657 printf("Flash %s timeout at address %lx data %lx\n",
658 prompt, (ulong)dst, (ulong)flash_read8(dst));
659 return ERR_TIMOUT;
660 }
661 udelay(1); /* also triggers watchdog */
662 }
663#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
664 return ERR_OK;
665}
666
5653fc33
WD
667/*-----------------------------------------------------------------------
668 */
be60a902 669static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
5653fc33 670{
6d0f6bcf 671#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS
672 unsigned short w;
673 unsigned int l;
674 unsigned long long ll;
675#endif
5653fc33 676
be60a902
HS
677 switch (info->portwidth) {
678 case FLASH_CFI_8BIT:
679 cword->c = c;
680 break;
681 case FLASH_CFI_16BIT:
6d0f6bcf 682#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS
683 w = c;
684 w <<= 8;
685 cword->w = (cword->w >> 8) | w;
686#else
687 cword->w = (cword->w << 8) | c;
81b20ccc 688#endif
be60a902
HS
689 break;
690 case FLASH_CFI_32BIT:
6d0f6bcf 691#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS
692 l = c;
693 l <<= 24;
694 cword->l = (cword->l >> 8) | l;
695#else
696 cword->l = (cword->l << 8) | c;
697#endif
698 break;
699 case FLASH_CFI_64BIT:
6d0f6bcf 700#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS
701 ll = c;
702 ll <<= 56;
703 cword->ll = (cword->ll >> 8) | ll;
704#else
705 cword->ll = (cword->ll << 8) | c;
706#endif
707 break;
260421a2 708 }
be60a902 709}
5653fc33 710
0f8e851e
JG
711/*
712 * Loop through the sector table starting from the previously found sector.
713 * Searches forwards or backwards, dependent on the passed address.
be60a902
HS
714 */
715static flash_sect_t find_sector (flash_info_t * info, ulong addr)
716{
0f8e851e
JG
717 static flash_sect_t saved_sector = 0; /* previously found sector */
718 flash_sect_t sector = saved_sector;
719
720 while ((info->start[sector] < addr)
721 && (sector < info->sector_count - 1))
722 sector++;
723 while ((info->start[sector] > addr) && (sector > 0))
724 /*
725 * also decrements the sector in case of an overshot
726 * in the first loop
727 */
728 sector--;
729
730 saved_sector = sector;
be60a902 731 return sector;
5653fc33
WD
732}
733
734/*-----------------------------------------------------------------------
5653fc33 735 */
be60a902
HS
736static int flash_write_cfiword (flash_info_t * info, ulong dest,
737 cfiword_t cword)
5653fc33 738{
09ce9921 739 void *dstaddr = (void *)dest;
be60a902 740 int flag;
a7292871
JG
741 flash_sect_t sect = 0;
742 char sect_found = 0;
5653fc33 743
be60a902
HS
744 /* Check if Flash is (sufficiently) erased */
745 switch (info->portwidth) {
746 case FLASH_CFI_8BIT:
cdbaefb5 747 flag = ((flash_read8(dstaddr) & cword.c) == cword.c);
be60a902
HS
748 break;
749 case FLASH_CFI_16BIT:
cdbaefb5 750 flag = ((flash_read16(dstaddr) & cword.w) == cword.w);
be60a902
HS
751 break;
752 case FLASH_CFI_32BIT:
cdbaefb5 753 flag = ((flash_read32(dstaddr) & cword.l) == cword.l);
be60a902
HS
754 break;
755 case FLASH_CFI_64BIT:
cdbaefb5 756 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll);
be60a902
HS
757 break;
758 default:
12d30aa7
HS
759 flag = 0;
760 break;
5653fc33 761 }
09ce9921 762 if (!flag)
0dc80e27 763 return ERR_NOT_ERASED;
5653fc33 764
be60a902
HS
765 /* Disable interrupts which might cause a timeout here */
766 flag = disable_interrupts ();
79b4cda0 767
be60a902 768 switch (info->vendor) {
9c048b52 769 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS
770 case CFI_CMDSET_INTEL_EXTENDED:
771 case CFI_CMDSET_INTEL_STANDARD:
772 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
773 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
774 break;
775 case CFI_CMDSET_AMD_EXTENDED:
776 case CFI_CMDSET_AMD_STANDARD:
0d01f66d
ES
777 sect = find_sector(info, dest);
778 flash_unlock_seq (info, sect);
779 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE);
a7292871 780 sect_found = 1;
be60a902 781 break;
b4db4a76
PYC
782#ifdef CONFIG_FLASH_CFI_LEGACY
783 case CFI_CMDSET_AMD_LEGACY:
784 sect = find_sector(info, dest);
785 flash_unlock_seq (info, 0);
786 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
787 sect_found = 1;
788 break;
789#endif
5653fc33
WD
790 }
791
be60a902
HS
792 switch (info->portwidth) {
793 case FLASH_CFI_8BIT:
cdbaefb5 794 flash_write8(cword.c, dstaddr);
be60a902
HS
795 break;
796 case FLASH_CFI_16BIT:
cdbaefb5 797 flash_write16(cword.w, dstaddr);
be60a902
HS
798 break;
799 case FLASH_CFI_32BIT:
cdbaefb5 800 flash_write32(cword.l, dstaddr);
be60a902
HS
801 break;
802 case FLASH_CFI_64BIT:
cdbaefb5 803 flash_write64(cword.ll, dstaddr);
be60a902 804 break;
5653fc33
WD
805 }
806
be60a902
HS
807 /* re-enable interrupts if necessary */
808 if (flag)
809 enable_interrupts ();
5653fc33 810
a7292871
JG
811 if (!sect_found)
812 sect = find_sector (info, dest);
813
e5720823
TC
814 if (use_flash_status_poll(info))
815 return flash_status_poll(info, &cword, dstaddr,
816 info->write_tout, "write");
817 else
818 return flash_full_status_check(info, sect,
819 info->write_tout, "write");
5653fc33
WD
820}
821
6d0f6bcf 822#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
5653fc33 823
be60a902
HS
824static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
825 int len)
5653fc33 826{
be60a902
HS
827 flash_sect_t sector;
828 int cnt;
829 int retcode;
cdbaefb5 830 void *src = cp;
ec21d5cf 831 void *dst = (void *)dest;
0dc80e27
SR
832 void *dst2 = dst;
833 int flag = 0;
96ef831f
GL
834 uint offset = 0;
835 unsigned int shift;
9c048b52 836 uchar write_cmd;
cdbaefb5 837
0dc80e27
SR
838 switch (info->portwidth) {
839 case FLASH_CFI_8BIT:
96ef831f 840 shift = 0;
0dc80e27
SR
841 break;
842 case FLASH_CFI_16BIT:
96ef831f 843 shift = 1;
0dc80e27
SR
844 break;
845 case FLASH_CFI_32BIT:
96ef831f 846 shift = 2;
0dc80e27
SR
847 break;
848 case FLASH_CFI_64BIT:
96ef831f 849 shift = 3;
0dc80e27
SR
850 break;
851 default:
852 retcode = ERR_INVAL;
853 goto out_unmap;
854 }
855
96ef831f
GL
856 cnt = len >> shift;
857
0dc80e27
SR
858 while ((cnt-- > 0) && (flag == 0)) {
859 switch (info->portwidth) {
860 case FLASH_CFI_8BIT:
861 flag = ((flash_read8(dst2) & flash_read8(src)) ==
862 flash_read8(src));
863 src += 1, dst2 += 1;
864 break;
865 case FLASH_CFI_16BIT:
866 flag = ((flash_read16(dst2) & flash_read16(src)) ==
867 flash_read16(src));
868 src += 2, dst2 += 2;
869 break;
870 case FLASH_CFI_32BIT:
871 flag = ((flash_read32(dst2) & flash_read32(src)) ==
872 flash_read32(src));
873 src += 4, dst2 += 4;
874 break;
875 case FLASH_CFI_64BIT:
876 flag = ((flash_read64(dst2) & flash_read64(src)) ==
877 flash_read64(src));
878 src += 8, dst2 += 8;
879 break;
880 }
881 }
882 if (!flag) {
883 retcode = ERR_NOT_ERASED;
884 goto out_unmap;
885 }
886
887 src = cp;
cdbaefb5 888 sector = find_sector (info, dest);
bf9e3b38
WD
889
890 switch (info->vendor) {
9c048b52 891 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD
892 case CFI_CMDSET_INTEL_STANDARD:
893 case CFI_CMDSET_INTEL_EXTENDED:
9c048b52
VL
894 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
895 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER;
be60a902 896 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
9c048b52
VL
897 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS);
898 flash_write_cmd (info, sector, 0, write_cmd);
be60a902
HS
899 retcode = flash_status_check (info, sector,
900 info->buffer_write_tout,
901 "write to buffer");
902 if (retcode == ERR_OK) {
903 /* reduce the number of loops by the width of
904 * the port */
96ef831f 905 cnt = len >> shift;
93c56f21 906 flash_write_cmd (info, sector, 0, cnt - 1);
be60a902
HS
907 while (cnt-- > 0) {
908 switch (info->portwidth) {
909 case FLASH_CFI_8BIT:
cdbaefb5
HS
910 flash_write8(flash_read8(src), dst);
911 src += 1, dst += 1;
be60a902
HS
912 break;
913 case FLASH_CFI_16BIT:
cdbaefb5
HS
914 flash_write16(flash_read16(src), dst);
915 src += 2, dst += 2;
be60a902
HS
916 break;
917 case FLASH_CFI_32BIT:
cdbaefb5
HS
918 flash_write32(flash_read32(src), dst);
919 src += 4, dst += 4;
be60a902
HS
920 break;
921 case FLASH_CFI_64BIT:
cdbaefb5
HS
922 flash_write64(flash_read64(src), dst);
923 src += 8, dst += 8;
be60a902
HS
924 break;
925 default:
12d30aa7
HS
926 retcode = ERR_INVAL;
927 goto out_unmap;
be60a902
HS
928 }
929 }
930 flash_write_cmd (info, sector, 0,
931 FLASH_CMD_WRITE_BUFFER_CONFIRM);
932 retcode = flash_full_status_check (
933 info, sector, info->buffer_write_tout,
934 "buffer write");
935 }
12d30aa7
HS
936
937 break;
be60a902 938
5653fc33
WD
939 case CFI_CMDSET_AMD_STANDARD:
940 case CFI_CMDSET_AMD_EXTENDED:
be60a902 941 flash_unlock_seq(info,0);
96ef831f
GL
942
943#ifdef CONFIG_FLASH_SPANSION_S29WS_N
944 offset = ((unsigned long)dst - info->start[sector]) >> shift;
945#endif
946 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
947 cnt = len >> shift;
7dedefdf 948 flash_write_cmd(info, sector, offset, cnt - 1);
be60a902
HS
949
950 switch (info->portwidth) {
951 case FLASH_CFI_8BIT:
cdbaefb5
HS
952 while (cnt-- > 0) {
953 flash_write8(flash_read8(src), dst);
954 src += 1, dst += 1;
955 }
be60a902
HS
956 break;
957 case FLASH_CFI_16BIT:
cdbaefb5
HS
958 while (cnt-- > 0) {
959 flash_write16(flash_read16(src), dst);
960 src += 2, dst += 2;
961 }
be60a902
HS
962 break;
963 case FLASH_CFI_32BIT:
cdbaefb5
HS
964 while (cnt-- > 0) {
965 flash_write32(flash_read32(src), dst);
966 src += 4, dst += 4;
967 }
be60a902
HS
968 break;
969 case FLASH_CFI_64BIT:
cdbaefb5
HS
970 while (cnt-- > 0) {
971 flash_write64(flash_read64(src), dst);
972 src += 8, dst += 8;
973 }
be60a902
HS
974 break;
975 default:
12d30aa7
HS
976 retcode = ERR_INVAL;
977 goto out_unmap;
be60a902
HS
978 }
979
980 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
e5720823
TC
981 if (use_flash_status_poll(info))
982 retcode = flash_status_poll(info, src - (1 << shift),
983 dst - (1 << shift),
984 info->buffer_write_tout,
985 "buffer write");
986 else
987 retcode = flash_full_status_check(info, sector,
988 info->buffer_write_tout,
989 "buffer write");
12d30aa7 990 break;
be60a902 991
5653fc33 992 default:
be60a902 993 debug ("Unknown Command Set\n");
12d30aa7
HS
994 retcode = ERR_INVAL;
995 break;
5653fc33 996 }
12d30aa7
HS
997
998out_unmap:
12d30aa7 999 return retcode;
5653fc33 1000}
6d0f6bcf 1001#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
be60a902 1002
bf9e3b38 1003
5653fc33 1004/*-----------------------------------------------------------------------
5653fc33 1005 */
be60a902 1006int flash_erase (flash_info_t * info, int s_first, int s_last)
5653fc33 1007{
be60a902
HS
1008 int rcode = 0;
1009 int prot;
1010 flash_sect_t sect;
e5720823 1011 int st;
5653fc33 1012
be60a902
HS
1013 if (info->flash_id != FLASH_MAN_CFI) {
1014 puts ("Can't erase unknown flash type - aborted\n");
1015 return 1;
1016 }
1017 if ((s_first < 0) || (s_first > s_last)) {
1018 puts ("- no sectors to erase\n");
1019 return 1;
1020 }
2662b40c 1021
be60a902
HS
1022 prot = 0;
1023 for (sect = s_first; sect <= s_last; ++sect) {
1024 if (info->protect[sect]) {
1025 prot++;
5653fc33
WD
1026 }
1027 }
be60a902
HS
1028 if (prot) {
1029 printf ("- Warning: %d protected sectors will not be erased!\n",
1030 prot);
6ea808ef 1031 } else if (flash_verbose) {
be60a902
HS
1032 putc ('\n');
1033 }
bf9e3b38 1034
bf9e3b38 1035
be60a902
HS
1036 for (sect = s_first; sect <= s_last; sect++) {
1037 if (info->protect[sect] == 0) { /* not protected */
1038 switch (info->vendor) {
9c048b52 1039 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS
1040 case CFI_CMDSET_INTEL_STANDARD:
1041 case CFI_CMDSET_INTEL_EXTENDED:
1042 flash_write_cmd (info, sect, 0,
1043 FLASH_CMD_CLEAR_STATUS);
1044 flash_write_cmd (info, sect, 0,
1045 FLASH_CMD_BLOCK_ERASE);
1046 flash_write_cmd (info, sect, 0,
1047 FLASH_CMD_ERASE_CONFIRM);
1048 break;
1049 case CFI_CMDSET_AMD_STANDARD:
1050 case CFI_CMDSET_AMD_EXTENDED:
1051 flash_unlock_seq (info, sect);
1052 flash_write_cmd (info, sect,
1053 info->addr_unlock1,
1054 AMD_CMD_ERASE_START);
1055 flash_unlock_seq (info, sect);
1056 flash_write_cmd (info, sect, 0,
1057 AMD_CMD_ERASE_SECTOR);
1058 break;
1059#ifdef CONFIG_FLASH_CFI_LEGACY
1060 case CFI_CMDSET_AMD_LEGACY:
1061 flash_unlock_seq (info, 0);
1062 flash_write_cmd (info, 0, info->addr_unlock1,
1063 AMD_CMD_ERASE_START);
1064 flash_unlock_seq (info, 0);
1065 flash_write_cmd (info, sect, 0,
1066 AMD_CMD_ERASE_SECTOR);
1067 break;
1068#endif
1069 default:
1070 debug ("Unkown flash vendor %d\n",
1071 info->vendor);
1072 break;
bf9e3b38 1073 }
be60a902 1074
e5720823
TC
1075 if (use_flash_status_poll(info)) {
1076 cfiword_t cword = (cfiword_t)0xffffffffffffffffULL;
1077 void *dest;
1078 dest = flash_map(info, sect, 0);
1079 st = flash_status_poll(info, &cword, dest,
1080 info->erase_blk_tout, "erase");
1081 flash_unmap(info, sect, 0, dest);
1082 } else
1083 st = flash_full_status_check(info, sect,
1084 info->erase_blk_tout,
1085 "erase");
1086 if (st)
be60a902 1087 rcode = 1;
e5720823 1088 else if (flash_verbose)
be60a902 1089 putc ('.');
5653fc33 1090 }
5653fc33 1091 }
6ea808ef
PZ
1092
1093 if (flash_verbose)
1094 puts (" done\n");
1095
be60a902 1096 return rcode;
5653fc33 1097}
bf9e3b38 1098
70084df7
SR
1099#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
1100static int sector_erased(flash_info_t *info, int i)
1101{
1102 int k;
1103 int size;
1104 volatile unsigned long *flash;
1105
1106 /*
1107 * Check if whole sector is erased
1108 */
1109 size = flash_sector_size(info, i);
1110 flash = (volatile unsigned long *) info->start[i];
1111 /* divide by 4 for longword access */
1112 size = size >> 2;
1113
1114 for (k = 0; k < size; k++) {
1115 if (*flash++ != 0xffffffff)
1116 return 0; /* not erased */
1117 }
1118
1119 return 1; /* erased */
1120}
1121#endif /* CONFIG_SYS_FLASH_EMPTY_INFO */
1122
be60a902 1123void flash_print_info (flash_info_t * info)
5653fc33 1124{
be60a902 1125 int i;
4d13cbad 1126
be60a902
HS
1127 if (info->flash_id != FLASH_MAN_CFI) {
1128 puts ("missing or unknown FLASH type\n");
1129 return;
1130 }
1131
1132 printf ("%s FLASH (%d x %d)",
1133 info->name,
1134 (info->portwidth << 3), (info->chipwidth << 3));
1135 if (info->size < 1024*1024)
1136 printf (" Size: %ld kB in %d Sectors\n",
1137 info->size >> 10, info->sector_count);
1138 else
1139 printf (" Size: %ld MB in %d Sectors\n",
1140 info->size >> 20, info->sector_count);
1141 printf (" ");
1142 switch (info->vendor) {
9c048b52
VL
1143 case CFI_CMDSET_INTEL_PROG_REGIONS:
1144 printf ("Intel Prog Regions");
1145 break;
be60a902
HS
1146 case CFI_CMDSET_INTEL_STANDARD:
1147 printf ("Intel Standard");
1148 break;
1149 case CFI_CMDSET_INTEL_EXTENDED:
1150 printf ("Intel Extended");
1151 break;
1152 case CFI_CMDSET_AMD_STANDARD:
1153 printf ("AMD Standard");
1154 break;
1155 case CFI_CMDSET_AMD_EXTENDED:
1156 printf ("AMD Extended");
1157 break;
1158#ifdef CONFIG_FLASH_CFI_LEGACY
1159 case CFI_CMDSET_AMD_LEGACY:
1160 printf ("AMD Legacy");
1161 break;
4d13cbad 1162#endif
be60a902
HS
1163 default:
1164 printf ("Unknown (%d)", info->vendor);
1165 break;
1166 }
d77c7ac4
PDM
1167 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x",
1168 info->manufacturer_id);
1169 printf (info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
1170 info->device_id);
be60a902
HS
1171 if (info->device_id == 0x7E) {
1172 printf("%04X", info->device_id2);
1173 }
1174 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
1175 info->erase_blk_tout,
1176 info->write_tout);
1177 if (info->buffer_size > 1) {
1178 printf (" Buffer write timeout: %ld ms, "
1179 "buffer size: %d bytes\n",
1180 info->buffer_write_tout,
1181 info->buffer_size);
5653fc33 1182 }
5653fc33 1183
be60a902
HS
1184 puts ("\n Sector Start Addresses:");
1185 for (i = 0; i < info->sector_count; ++i) {
2e97394a 1186 if (ctrlc())
70084df7 1187 break;
be60a902 1188 if ((i % 5) == 0)
70084df7 1189 putc('\n');
6d0f6bcf 1190#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
be60a902
HS
1191 /* print empty and read-only info */
1192 printf (" %08lX %c %s ",
1193 info->start[i],
70084df7 1194 sector_erased(info, i) ? 'E' : ' ',
be60a902 1195 info->protect[i] ? "RO" : " ");
6d0f6bcf 1196#else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */
be60a902
HS
1197 printf (" %08lX %s ",
1198 info->start[i],
1199 info->protect[i] ? "RO" : " ");
bf9e3b38 1200#endif
be60a902
HS
1201 }
1202 putc ('\n');
1203 return;
5653fc33
WD
1204}
1205
9a042e9c
JVB
1206/*-----------------------------------------------------------------------
1207 * This is used in a few places in write_buf() to show programming
1208 * progress. Making it a function is nasty because it needs to do side
1209 * effect updates to digit and dots. Repeated code is nasty too, so
1210 * we define it once here.
1211 */
f0105727
SR
1212#ifdef CONFIG_FLASH_SHOW_PROGRESS
1213#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
6ea808ef
PZ
1214 if (flash_verbose) { \
1215 dots -= dots_sub; \
1216 if ((scale > 0) && (dots <= 0)) { \
1217 if ((digit % 5) == 0) \
1218 printf ("%d", digit / 5); \
1219 else \
1220 putc ('.'); \
1221 digit--; \
1222 dots += scale; \
1223 } \
9a042e9c 1224 }
f0105727
SR
1225#else
1226#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1227#endif
9a042e9c 1228
be60a902
HS
1229/*-----------------------------------------------------------------------
1230 * Copy memory to flash, returns:
1231 * 0 - OK
1232 * 1 - write timeout
1233 * 2 - Flash not erased
5653fc33 1234 */
be60a902 1235int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
5653fc33 1236{
be60a902 1237 ulong wp;
12d30aa7 1238 uchar *p;
be60a902 1239 int aln;
5653fc33 1240 cfiword_t cword;
be60a902 1241 int i, rc;
6d0f6bcf 1242#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902 1243 int buffered_size;
5653fc33 1244#endif
9a042e9c
JVB
1245#ifdef CONFIG_FLASH_SHOW_PROGRESS
1246 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1247 int scale = 0;
1248 int dots = 0;
1249
1250 /*
1251 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1252 */
1253 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1254 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1255 CONFIG_FLASH_SHOW_PROGRESS);
1256 }
1257#endif
1258
be60a902
HS
1259 /* get lower aligned address */
1260 wp = (addr & ~(info->portwidth - 1));
3a197b2f 1261
be60a902
HS
1262 /* handle unaligned start */
1263 if ((aln = addr - wp) != 0) {
1264 cword.l = 0;
09ce9921 1265 p = (uchar *)wp;
12d30aa7
HS
1266 for (i = 0; i < aln; ++i)
1267 flash_add_byte (info, &cword, flash_read8(p + i));
5653fc33 1268
be60a902
HS
1269 for (; (i < info->portwidth) && (cnt > 0); i++) {
1270 flash_add_byte (info, &cword, *src++);
1271 cnt--;
be60a902 1272 }
12d30aa7
HS
1273 for (; (cnt == 0) && (i < info->portwidth); ++i)
1274 flash_add_byte (info, &cword, flash_read8(p + i));
1275
1276 rc = flash_write_cfiword (info, wp, cword);
12d30aa7 1277 if (rc != 0)
be60a902 1278 return rc;
12d30aa7
HS
1279
1280 wp += i;
f0105727 1281 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS
1282 }
1283
1284 /* handle the aligned part */
6d0f6bcf 1285#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902
HS
1286 buffered_size = (info->portwidth / info->chipwidth);
1287 buffered_size *= info->buffer_size;
1288 while (cnt >= info->portwidth) {
1289 /* prohibit buffer write when buffer_size is 1 */
1290 if (info->buffer_size == 1) {
1291 cword.l = 0;
1292 for (i = 0; i < info->portwidth; i++)
1293 flash_add_byte (info, &cword, *src++);
1294 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1295 return rc;
1296 wp += info->portwidth;
1297 cnt -= info->portwidth;
1298 continue;
1299 }
1300
1301 /* write buffer until next buffered_size aligned boundary */
1302 i = buffered_size - (wp % buffered_size);
1303 if (i > cnt)
1304 i = cnt;
1305 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
1306 return rc;
1307 i -= i & (info->portwidth - 1);
1308 wp += i;
1309 src += i;
1310 cnt -= i;
f0105727 1311 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS
1312 }
1313#else
1314 while (cnt >= info->portwidth) {
1315 cword.l = 0;
1316 for (i = 0; i < info->portwidth; i++) {
1317 flash_add_byte (info, &cword, *src++);
1318 }
1319 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1320 return rc;
1321 wp += info->portwidth;
1322 cnt -= info->portwidth;
f0105727 1323 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
be60a902 1324 }
6d0f6bcf 1325#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
9a042e9c 1326
be60a902
HS
1327 if (cnt == 0) {
1328 return (0);
1329 }
1330
1331 /*
1332 * handle unaligned tail bytes
1333 */
1334 cword.l = 0;
09ce9921 1335 p = (uchar *)wp;
12d30aa7 1336 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
be60a902
HS
1337 flash_add_byte (info, &cword, *src++);
1338 --cnt;
1339 }
12d30aa7
HS
1340 for (; i < info->portwidth; ++i)
1341 flash_add_byte (info, &cword, flash_read8(p + i));
be60a902
HS
1342
1343 return flash_write_cfiword (info, wp, cword);
5653fc33 1344}
bf9e3b38 1345
5653fc33
WD
1346/*-----------------------------------------------------------------------
1347 */
6d0f6bcf 1348#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902
HS
1349
1350int flash_real_protect (flash_info_t * info, long sector, int prot)
5653fc33 1351{
be60a902 1352 int retcode = 0;
5653fc33 1353
bc9019e1
RC
1354 switch (info->vendor) {
1355 case CFI_CMDSET_INTEL_PROG_REGIONS:
1356 case CFI_CMDSET_INTEL_STANDARD:
9e8e63cc 1357 case CFI_CMDSET_INTEL_EXTENDED:
54652991
PDM
1358 /*
1359 * see errata called
1360 * "Numonyx Axcell P33/P30 Specification Update" :)
1361 */
1362 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID);
1363 if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT,
1364 prot)) {
1365 /*
1366 * cmd must come before FLASH_CMD_PROTECT + 20us
1367 * Disable interrupts which might cause a timeout here.
1368 */
1369 int flag = disable_interrupts ();
1370 unsigned short cmd;
1371
1372 if (prot)
1373 cmd = FLASH_CMD_PROTECT_SET;
1374 else
1375 cmd = FLASH_CMD_PROTECT_CLEAR;
1376
bc9019e1 1377 flash_write_cmd (info, sector, 0,
54652991
PDM
1378 FLASH_CMD_PROTECT);
1379 flash_write_cmd (info, sector, 0, cmd);
1380 /* re-enable interrupts if necessary */
1381 if (flag)
1382 enable_interrupts ();
1383 }
bc9019e1
RC
1384 break;
1385 case CFI_CMDSET_AMD_EXTENDED:
1386 case CFI_CMDSET_AMD_STANDARD:
bc9019e1
RC
1387 /* U-Boot only checks the first byte */
1388 if (info->manufacturer_id == (uchar)ATM_MANUFACT) {
1389 if (prot) {
1390 flash_unlock_seq (info, 0);
1391 flash_write_cmd (info, 0,
1392 info->addr_unlock1,
1393 ATM_CMD_SOFTLOCK_START);
1394 flash_unlock_seq (info, 0);
1395 flash_write_cmd (info, sector, 0,
1396 ATM_CMD_LOCK_SECT);
1397 } else {
1398 flash_write_cmd (info, 0,
1399 info->addr_unlock1,
1400 AMD_CMD_UNLOCK_START);
1401 if (info->device_id == ATM_ID_BV6416)
1402 flash_write_cmd (info, sector,
1403 0, ATM_CMD_UNLOCK_SECT);
1404 }
1405 }
1406 break;
4e00acde
TL
1407#ifdef CONFIG_FLASH_CFI_LEGACY
1408 case CFI_CMDSET_AMD_LEGACY:
1409 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1410 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1411 if (prot)
1412 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
1413 else
1414 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
1415#endif
bc9019e1 1416 };
bf9e3b38 1417
be60a902
HS
1418 if ((retcode =
1419 flash_full_status_check (info, sector, info->erase_blk_tout,
1420 prot ? "protect" : "unprotect")) == 0) {
bf9e3b38 1421
be60a902
HS
1422 info->protect[sector] = prot;
1423
1424 /*
1425 * On some of Intel's flash chips (marked via legacy_unlock)
1426 * unprotect unprotects all locking.
1427 */
1428 if ((prot == 0) && (info->legacy_unlock)) {
1429 flash_sect_t i;
1430
1431 for (i = 0; i < info->sector_count; i++) {
1432 if (info->protect[i])
1433 flash_real_protect (info, i, 1);
1434 }
5653fc33 1435 }
5653fc33 1436 }
be60a902 1437 return retcode;
5653fc33 1438}
bf9e3b38 1439
5653fc33 1440/*-----------------------------------------------------------------------
be60a902 1441 * flash_read_user_serial - read the OneTimeProgramming cells
5653fc33 1442 */
be60a902
HS
1443void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
1444 int len)
5653fc33 1445{
be60a902
HS
1446 uchar *src;
1447 uchar *dst;
bf9e3b38 1448
be60a902 1449 dst = buffer;
12d30aa7 1450 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION);
be60a902
HS
1451 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1452 memcpy (dst, src + offset, len);
1453 flash_write_cmd (info, 0, 0, info->cmd_reset);
12d30aa7 1454 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
5653fc33
WD
1455}
1456
be60a902
HS
1457/*
1458 * flash_read_factory_serial - read the device Id from the protection area
5653fc33 1459 */
be60a902
HS
1460void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
1461 int len)
5653fc33 1462{
be60a902 1463 uchar *src;
bf9e3b38 1464
12d30aa7 1465 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
be60a902
HS
1466 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1467 memcpy (buffer, src + offset, len);
1468 flash_write_cmd (info, 0, 0, info->cmd_reset);
12d30aa7 1469 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
5653fc33
WD
1470}
1471
6d0f6bcf 1472#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 1473
0ddf06dd
HS
1474/*-----------------------------------------------------------------------
1475 * Reverse the order of the erase regions in the CFI QRY structure.
1476 * This is needed for chips that are either a) correctly detected as
1477 * top-boot, or b) buggy.
1478 */
1479static void cfi_reverse_geometry(struct cfi_qry *qry)
1480{
1481 unsigned int i, j;
1482 u32 tmp;
1483
1484 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
1485 tmp = qry->erase_region_info[i];
1486 qry->erase_region_info[i] = qry->erase_region_info[j];
1487 qry->erase_region_info[j] = tmp;
1488 }
1489}
be60a902 1490
260421a2
SR
1491/*-----------------------------------------------------------------------
1492 * read jedec ids from device and set corresponding fields in info struct
1493 *
1494 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1495 *
0ddf06dd
HS
1496 */
1497static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1498{
1499 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1500 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1501 udelay(1000); /* some flash are slow to respond */
1502 info->manufacturer_id = flash_read_uchar (info,
1503 FLASH_OFFSET_MANUFACTURER_ID);
d77c7ac4
PDM
1504 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ?
1505 flash_read_word (info, FLASH_OFFSET_DEVICE_ID) :
1506 flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID);
0ddf06dd
HS
1507 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1508}
1509
1510static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1511{
1512 info->cmd_reset = FLASH_CMD_RESET;
1513
1514 cmdset_intel_read_jedec_ids(info);
1515 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1516
6d0f6bcf 1517#ifdef CONFIG_SYS_FLASH_PROTECTION
0ddf06dd
HS
1518 /* read legacy lock/unlock bit from intel flash */
1519 if (info->ext_addr) {
1520 info->legacy_unlock = flash_read_uchar (info,
1521 info->ext_addr + 5) & 0x08;
1522 }
1523#endif
1524
1525 return 0;
1526}
1527
1528static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1529{
3a7b2c21
NG
1530 ushort bankId = 0;
1531 uchar manuId;
1532
0ddf06dd
HS
1533 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1534 flash_unlock_seq(info, 0);
1535 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1536 udelay(1000); /* some flash are slow to respond */
90447ecb 1537
3a7b2c21
NG
1538 manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID);
1539 /* JEDEC JEP106Z specifies ID codes up to bank 7 */
1540 while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) {
1541 bankId += 0x100;
1542 manuId = flash_read_uchar (info,
1543 bankId | FLASH_OFFSET_MANUFACTURER_ID);
1544 }
1545 info->manufacturer_id = manuId;
90447ecb
TK
1546
1547 switch (info->chipwidth){
1548 case FLASH_CFI_8BIT:
1549 info->device_id = flash_read_uchar (info,
1550 FLASH_OFFSET_DEVICE_ID);
1551 if (info->device_id == 0x7E) {
1552 /* AMD 3-byte (expanded) device ids */
1553 info->device_id2 = flash_read_uchar (info,
1554 FLASH_OFFSET_DEVICE_ID2);
1555 info->device_id2 <<= 8;
1556 info->device_id2 |= flash_read_uchar (info,
1557 FLASH_OFFSET_DEVICE_ID3);
1558 }
1559 break;
1560 case FLASH_CFI_16BIT:
1561 info->device_id = flash_read_word (info,
1562 FLASH_OFFSET_DEVICE_ID);
1563 break;
1564 default:
1565 break;
0ddf06dd
HS
1566 }
1567 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1568}
1569
1570static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1571{
1572 info->cmd_reset = AMD_CMD_RESET;
1573
1574 cmdset_amd_read_jedec_ids(info);
1575 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1576
0ddf06dd
HS
1577 return 0;
1578}
1579
1580#ifdef CONFIG_FLASH_CFI_LEGACY
260421a2
SR
1581static void flash_read_jedec_ids (flash_info_t * info)
1582{
1583 info->manufacturer_id = 0;
1584 info->device_id = 0;
1585 info->device_id2 = 0;
1586
1587 switch (info->vendor) {
9c048b52 1588 case CFI_CMDSET_INTEL_PROG_REGIONS:
260421a2
SR
1589 case CFI_CMDSET_INTEL_STANDARD:
1590 case CFI_CMDSET_INTEL_EXTENDED:
8225d1e3 1591 cmdset_intel_read_jedec_ids(info);
260421a2
SR
1592 break;
1593 case CFI_CMDSET_AMD_STANDARD:
1594 case CFI_CMDSET_AMD_EXTENDED:
8225d1e3 1595 cmdset_amd_read_jedec_ids(info);
260421a2
SR
1596 break;
1597 default:
1598 break;
1599 }
1600}
1601
5653fc33 1602/*-----------------------------------------------------------------------
be60a902
HS
1603 * Call board code to request info about non-CFI flash.
1604 * board_flash_get_legacy needs to fill in at least:
1605 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
7e5b9b47 1606 */
09ce9921 1607static int flash_detect_legacy(phys_addr_t base, int banknum)
5653fc33 1608{
be60a902 1609 flash_info_t *info = &flash_info[banknum];
7e5b9b47 1610
be60a902
HS
1611 if (board_flash_get_legacy(base, banknum, info)) {
1612 /* board code may have filled info completely. If not, we
1613 use JEDEC ID probing. */
1614 if (!info->vendor) {
1615 int modes[] = {
1616 CFI_CMDSET_AMD_STANDARD,
1617 CFI_CMDSET_INTEL_STANDARD
1618 };
1619 int i;
7e5b9b47 1620
be60a902
HS
1621 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
1622 info->vendor = modes[i];
09ce9921
BB
1623 info->start[0] =
1624 (ulong)map_physmem(base,
e1fb6d0d 1625 info->portwidth,
09ce9921 1626 MAP_NOCACHE);
be60a902
HS
1627 if (info->portwidth == FLASH_CFI_8BIT
1628 && info->interface == FLASH_CFI_X8X16) {
1629 info->addr_unlock1 = 0x2AAA;
1630 info->addr_unlock2 = 0x5555;
1631 } else {
1632 info->addr_unlock1 = 0x5555;
1633 info->addr_unlock2 = 0x2AAA;
1634 }
1635 flash_read_jedec_ids(info);
1636 debug("JEDEC PROBE: ID %x %x %x\n",
1637 info->manufacturer_id,
1638 info->device_id,
1639 info->device_id2);
09ce9921 1640 if (jedec_flash_match(info, info->start[0]))
be60a902 1641 break;
09ce9921 1642 else
e1fb6d0d 1643 unmap_physmem((void *)info->start[0],
09ce9921 1644 MAP_NOCACHE);
be60a902
HS
1645 }
1646 }
1647
1648 switch(info->vendor) {
9c048b52 1649 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS
1650 case CFI_CMDSET_INTEL_STANDARD:
1651 case CFI_CMDSET_INTEL_EXTENDED:
1652 info->cmd_reset = FLASH_CMD_RESET;
1653 break;
1654 case CFI_CMDSET_AMD_STANDARD:
1655 case CFI_CMDSET_AMD_EXTENDED:
1656 case CFI_CMDSET_AMD_LEGACY:
1657 info->cmd_reset = AMD_CMD_RESET;
1658 break;
1659 }
1660 info->flash_id = FLASH_MAN_CFI;
1661 return 1;
1662 }
1663 return 0; /* use CFI */
1664}
1665#else
09ce9921 1666static inline int flash_detect_legacy(phys_addr_t base, int banknum)
be60a902
HS
1667{
1668 return 0; /* use CFI */
1669}
1670#endif
1671
1672/*-----------------------------------------------------------------------
1673 * detect if flash is compatible with the Common Flash Interface (CFI)
1674 * http://www.jedec.org/download/search/jesd68.pdf
1675 */
e23741f4
HS
1676static void flash_read_cfi (flash_info_t *info, void *buf,
1677 unsigned int start, size_t len)
1678{
1679 u8 *p = buf;
1680 unsigned int i;
1681
1682 for (i = 0; i < len; i++)
1683 p[i] = flash_read_uchar(info, start + i);
1684}
1685
fa36ae79
SR
1686void __flash_cmd_reset(flash_info_t *info)
1687{
1688 /*
1689 * We do not yet know what kind of commandset to use, so we issue
1690 * the reset command in both Intel and AMD variants, in the hope
1691 * that AMD flash roms ignore the Intel command.
1692 */
1693 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1694 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1695}
1696void flash_cmd_reset(flash_info_t *info)
1697 __attribute__((weak,alias("__flash_cmd_reset")));
1698
e23741f4 1699static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
be60a902
HS
1700{
1701 int cfi_offset;
1702
fa36ae79
SR
1703 /* Issue FLASH reset command */
1704 flash_cmd_reset(info);
1ba639da 1705
be60a902
HS
1706 for (cfi_offset=0;
1707 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);
1708 cfi_offset++) {
1709 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
1710 FLASH_CMD_CFI);
1711 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
1712 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
1713 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
e23741f4
HS
1714 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1715 sizeof(struct cfi_qry));
1716 info->interface = le16_to_cpu(qry->interface_desc);
1717
be60a902
HS
1718 info->cfi_offset = flash_offset_cfi[cfi_offset];
1719 debug ("device interface is %d\n",
1720 info->interface);
1721 debug ("found port %d chip %d ",
1722 info->portwidth, info->chipwidth);
1723 debug ("port %d bits chip %d bits\n",
1724 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1725 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1726
1727 /* calculate command offsets as in the Linux driver */
1728 info->addr_unlock1 = 0x555;
7e5b9b47
HS
1729 info->addr_unlock2 = 0x2aa;
1730
1731 /*
1732 * modify the unlock address if we are
1733 * in compatibility mode
1734 */
1735 if ( /* x8/x16 in x8 mode */
1736 ((info->chipwidth == FLASH_CFI_BY8) &&
1737 (info->interface == FLASH_CFI_X8X16)) ||
1738 /* x16/x32 in x16 mode */
1739 ((info->chipwidth == FLASH_CFI_BY16) &&
1740 (info->interface == FLASH_CFI_X16X32)))
1741 {
1742 info->addr_unlock1 = 0xaaa;
1743 info->addr_unlock2 = 0x555;
1744 }
1745
1746 info->name = "CFI conformant";
1747 return 1;
1748 }
1749 }
1750
1751 return 0;
1752}
1753
e23741f4 1754static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
7e5b9b47 1755{
bf9e3b38
WD
1756 debug ("flash detect cfi\n");
1757
6d0f6bcf 1758 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
bf9e3b38
WD
1759 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1760 for (info->chipwidth = FLASH_CFI_BY8;
1761 info->chipwidth <= info->portwidth;
7e5b9b47 1762 info->chipwidth <<= 1)
e23741f4 1763 if (__flash_detect_cfi(info, qry))
7e5b9b47 1764 return 1;
5653fc33 1765 }
bf9e3b38 1766 debug ("not found\n");
5653fc33
WD
1767 return 0;
1768}
bf9e3b38 1769
467bcee1
HS
1770/*
1771 * Manufacturer-specific quirks. Add workarounds for geometry
1772 * reversal, etc. here.
1773 */
1774static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
1775{
1776 /* check if flash geometry needs reversal */
1777 if (qry->num_erase_regions > 1) {
1778 /* reverse geometry if top boot part */
1779 if (info->cfi_version < 0x3131) {
1780 /* CFI < 1.1, try to guess from device id */
1781 if ((info->device_id & 0x80) != 0)
1782 cfi_reverse_geometry(qry);
1783 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1784 /* CFI >= 1.1, deduct from top/bottom flag */
1785 /* note: ext_addr is valid since cfi_version > 0 */
1786 cfi_reverse_geometry(qry);
1787 }
1788 }
1789}
1790
1791static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
1792{
1793 int reverse_geometry = 0;
1794
1795 /* Check the "top boot" bit in the PRI */
1796 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
1797 reverse_geometry = 1;
1798
1799 /* AT49BV6416(T) list the erase regions in the wrong order.
1800 * However, the device ID is identical with the non-broken
cb82a532 1801 * AT49BV642D they differ in the high byte.
467bcee1 1802 */
467bcee1
HS
1803 if (info->device_id == 0xd6 || info->device_id == 0xd2)
1804 reverse_geometry = !reverse_geometry;
467bcee1
HS
1805
1806 if (reverse_geometry)
1807 cfi_reverse_geometry(qry);
1808}
1809
e8eac437
RR
1810static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
1811{
1812 /* check if flash geometry needs reversal */
1813 if (qry->num_erase_regions > 1) {
1814 /* reverse geometry if top boot part */
1815 if (info->cfi_version < 0x3131) {
7a88601a
RR
1816 /* CFI < 1.1, guess by device id (M29W320{DT,ET} only) */
1817 if (info->device_id == 0x22CA ||
1818 info->device_id == 0x2256) {
e8eac437
RR
1819 cfi_reverse_geometry(qry);
1820 }
1821 }
1822 }
1823}
1824
5653fc33
WD
1825/*
1826 * The following code cannot be run from FLASH!
1827 *
1828 */
09ce9921 1829ulong flash_get_size (phys_addr_t base, int banknum)
5653fc33 1830{
bf9e3b38 1831 flash_info_t *info = &flash_info[banknum];
5653fc33
WD
1832 int i, j;
1833 flash_sect_t sect_cnt;
09ce9921 1834 phys_addr_t sector;
5653fc33
WD
1835 unsigned long tmp;
1836 int size_ratio;
1837 uchar num_erase_regions;
bf9e3b38
WD
1838 int erase_region_size;
1839 int erase_region_count;
e23741f4 1840 struct cfi_qry qry;
260421a2 1841
f979690e
KG
1842 memset(&qry, 0, sizeof(qry));
1843
260421a2
SR
1844 info->ext_addr = 0;
1845 info->cfi_version = 0;
6d0f6bcf 1846#ifdef CONFIG_SYS_FLASH_PROTECTION
2662b40c
SR
1847 info->legacy_unlock = 0;
1848#endif
5653fc33 1849
09ce9921 1850 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
5653fc33 1851
e23741f4
HS
1852 if (flash_detect_cfi (info, &qry)) {
1853 info->vendor = le16_to_cpu(qry.p_id);
1854 info->ext_addr = le16_to_cpu(qry.p_adr);
1855 num_erase_regions = qry.num_erase_regions;
1856
260421a2
SR
1857 if (info->ext_addr) {
1858 info->cfi_version = (ushort) flash_read_uchar (info,
1859 info->ext_addr + 3) << 8;
1860 info->cfi_version |= (ushort) flash_read_uchar (info,
1861 info->ext_addr + 4);
1862 }
0ddf06dd 1863
bf9e3b38 1864#ifdef DEBUG
e23741f4 1865 flash_printqry (&qry);
bf9e3b38 1866#endif
0ddf06dd 1867
bf9e3b38 1868 switch (info->vendor) {
9c048b52 1869 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD
1870 case CFI_CMDSET_INTEL_STANDARD:
1871 case CFI_CMDSET_INTEL_EXTENDED:
0ddf06dd 1872 cmdset_intel_init(info, &qry);
5653fc33
WD
1873 break;
1874 case CFI_CMDSET_AMD_STANDARD:
1875 case CFI_CMDSET_AMD_EXTENDED:
0ddf06dd 1876 cmdset_amd_init(info, &qry);
5653fc33 1877 break;
0ddf06dd
HS
1878 default:
1879 printf("CFI: Unknown command set 0x%x\n",
1880 info->vendor);
1881 /*
1882 * Unfortunately, this means we don't know how
1883 * to get the chip back to Read mode. Might
1884 * as well try an Intel-style reset...
1885 */
1886 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1887 return 0;
5653fc33 1888 }
cd37d9e6 1889
467bcee1
HS
1890 /* Do manufacturer-specific fixups */
1891 switch (info->manufacturer_id) {
1892 case 0x0001:
1893 flash_fixup_amd(info, &qry);
1894 break;
1895 case 0x001f:
1896 flash_fixup_atmel(info, &qry);
1897 break;
e8eac437
RR
1898 case 0x0020:
1899 flash_fixup_stm(info, &qry);
1900 break;
467bcee1
HS
1901 }
1902
bf9e3b38 1903 debug ("manufacturer is %d\n", info->vendor);
260421a2
SR
1904 debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
1905 debug ("device id is 0x%x\n", info->device_id);
1906 debug ("device id2 is 0x%x\n", info->device_id2);
1907 debug ("cfi version is 0x%04x\n", info->cfi_version);
1908
5653fc33 1909 size_ratio = info->portwidth / info->chipwidth;
bf9e3b38
WD
1910 /* if the chip is x8/x16 reduce the ratio by half */
1911 if ((info->interface == FLASH_CFI_X8X16)
1912 && (info->chipwidth == FLASH_CFI_BY8)) {
1913 size_ratio >>= 1;
1914 }
bf9e3b38
WD
1915 debug ("size_ratio %d port %d bits chip %d bits\n",
1916 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1917 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1918 debug ("found %d erase regions\n", num_erase_regions);
5653fc33
WD
1919 sect_cnt = 0;
1920 sector = base;
bf9e3b38
WD
1921 for (i = 0; i < num_erase_regions; i++) {
1922 if (i > NUM_ERASE_REGIONS) {
028ab6b5
WD
1923 printf ("%d erase regions found, only %d used\n",
1924 num_erase_regions, NUM_ERASE_REGIONS);
5653fc33
WD
1925 break;
1926 }
e23741f4 1927
0ddf06dd
HS
1928 tmp = le32_to_cpu(qry.erase_region_info[i]);
1929 debug("erase region %u: 0x%08lx\n", i, tmp);
e23741f4
HS
1930
1931 erase_region_count = (tmp & 0xffff) + 1;
1932 tmp >>= 16;
bf9e3b38
WD
1933 erase_region_size =
1934 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
4c0d4c3b 1935 debug ("erase_region_count = %d erase_region_size = %d\n",
028ab6b5 1936 erase_region_count, erase_region_size);
bf9e3b38 1937 for (j = 0; j < erase_region_count; j++) {
6d0f6bcf 1938 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
81b20ccc
MS
1939 printf("ERROR: too many flash sectors\n");
1940 break;
1941 }
09ce9921
BB
1942 info->start[sect_cnt] =
1943 (ulong)map_physmem(sector,
1944 info->portwidth,
1945 MAP_NOCACHE);
5653fc33 1946 sector += (erase_region_size * size_ratio);
a1191902
WD
1947
1948 /*
7e5b9b47
HS
1949 * Only read protection status from
1950 * supported devices (intel...)
a1191902
WD
1951 */
1952 switch (info->vendor) {
9c048b52 1953 case CFI_CMDSET_INTEL_PROG_REGIONS:
a1191902
WD
1954 case CFI_CMDSET_INTEL_EXTENDED:
1955 case CFI_CMDSET_INTEL_STANDARD:
1956 info->protect[sect_cnt] =
1957 flash_isset (info, sect_cnt,
1958 FLASH_OFFSET_PROTECT,
1959 FLASH_STATUS_PROTECT);
1960 break;
1961 default:
7e5b9b47
HS
1962 /* default: not protected */
1963 info->protect[sect_cnt] = 0;
a1191902
WD
1964 }
1965
5653fc33
WD
1966 sect_cnt++;
1967 }
1968 }
1969
1970 info->sector_count = sect_cnt;
e23741f4 1971 info->size = 1 << qry.dev_size;
5653fc33 1972 /* multiply the size by the number of chips */
7e5b9b47 1973 info->size *= size_ratio;
e23741f4
HS
1974 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
1975 tmp = 1 << qry.block_erase_timeout_typ;
7e5b9b47 1976 info->erase_blk_tout = tmp *
e23741f4
HS
1977 (1 << qry.block_erase_timeout_max);
1978 tmp = (1 << qry.buf_write_timeout_typ) *
1979 (1 << qry.buf_write_timeout_max);
1980
7e5b9b47 1981 /* round up when converting to ms */
e23741f4
HS
1982 info->buffer_write_tout = (tmp + 999) / 1000;
1983 tmp = (1 << qry.word_write_timeout_typ) *
1984 (1 << qry.word_write_timeout_max);
7e5b9b47 1985 /* round up when converting to ms */
e23741f4 1986 info->write_tout = (tmp + 999) / 1000;
5653fc33 1987 info->flash_id = FLASH_MAN_CFI;
7e5b9b47
HS
1988 if ((info->interface == FLASH_CFI_X8X16) &&
1989 (info->chipwidth == FLASH_CFI_BY8)) {
1990 /* XXX - Need to test on x8/x16 in parallel. */
1991 info->portwidth >>= 1;
855a496f 1992 }
2215987e
MF
1993
1994 flash_write_cmd (info, 0, 0, info->cmd_reset);
5653fc33
WD
1995 }
1996
bf9e3b38 1997 return (info->size);
5653fc33
WD
1998}
1999
6ea808ef
PZ
2000void flash_set_verbose(uint v)
2001{
2002 flash_verbose = v;
2003}
2004
5653fc33
WD
2005/*-----------------------------------------------------------------------
2006 */
be60a902 2007unsigned long flash_init (void)
5653fc33 2008{
be60a902
HS
2009 unsigned long size = 0;
2010 int i;
6d0f6bcf 2011#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
c63ad632
MF
2012 struct apl_s {
2013 ulong start;
2014 ulong size;
6d0f6bcf 2015 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST;
c63ad632 2016#endif
5653fc33 2017
6d0f6bcf 2018#ifdef CONFIG_SYS_FLASH_PROTECTION
3a3baf3e
ES
2019 /* read environment from EEPROM */
2020 char s[64];
cdb74977 2021 getenv_f("unlock", s, sizeof(s));
81b20ccc 2022#endif
5653fc33 2023
be60a902 2024 /* Init: no FLASHes known */
6d0f6bcf 2025 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
be60a902 2026 flash_info[i].flash_id = FLASH_UNKNOWN;
5653fc33 2027
b00e19cc
SR
2028 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
2029 flash_get_size(cfi_flash_bank_addr(i), i);
be60a902
HS
2030 size += flash_info[i].size;
2031 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
6d0f6bcf 2032#ifndef CONFIG_SYS_FLASH_QUIET_TEST
be60a902
HS
2033 printf ("## Unknown FLASH on Bank %d "
2034 "- Size = 0x%08lx = %ld MB\n",
2035 i+1, flash_info[i].size,
0e3fa01a 2036 flash_info[i].size >> 20);
6d0f6bcf 2037#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
be60a902 2038 }
6d0f6bcf 2039#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902
HS
2040 else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
2041 /*
2042 * Only the U-Boot image and it's environment
2043 * is protected, all other sectors are
2044 * unprotected (unlocked) if flash hardware
6d0f6bcf 2045 * protection is used (CONFIG_SYS_FLASH_PROTECTION)
be60a902
HS
2046 * and the environment variable "unlock" is
2047 * set to "yes".
2048 */
2049 if (flash_info[i].legacy_unlock) {
2050 int k;
5653fc33 2051
be60a902
HS
2052 /*
2053 * Disable legacy_unlock temporarily,
2054 * since flash_real_protect would
2055 * relock all other sectors again
2056 * otherwise.
2057 */
2058 flash_info[i].legacy_unlock = 0;
5653fc33 2059
be60a902
HS
2060 /*
2061 * Legacy unlocking (e.g. Intel J3) ->
2062 * unlock only one sector. This will
2063 * unlock all sectors.
2064 */
2065 flash_real_protect (&flash_info[i], 0, 0);
5653fc33 2066
be60a902 2067 flash_info[i].legacy_unlock = 1;
5653fc33 2068
be60a902
HS
2069 /*
2070 * Manually mark other sectors as
2071 * unlocked (unprotected)
2072 */
2073 for (k = 1; k < flash_info[i].sector_count; k++)
2074 flash_info[i].protect[k] = 0;
2075 } else {
2076 /*
2077 * No legancy unlocking -> unlock all sectors
2078 */
2079 flash_protect (FLAG_PROTECT_CLEAR,
2080 flash_info[i].start[0],
2081 flash_info[i].start[0]
2082 + flash_info[i].size - 1,
2083 &flash_info[i]);
79b4cda0 2084 }
79b4cda0 2085 }
6d0f6bcf 2086#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 2087 }
79b4cda0 2088
be60a902 2089 /* Monitor protection ON by default */
8f9a2210
WW
2090#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
2091 (!defined(CONFIG_MONITOR_IS_IN_RAM))
be60a902 2092 flash_protect (FLAG_PROTECT_SET,
6d0f6bcf
JCPV
2093 CONFIG_SYS_MONITOR_BASE,
2094 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
2095 flash_get_info(CONFIG_SYS_MONITOR_BASE));
be60a902 2096#endif
79b4cda0 2097
be60a902 2098 /* Environment protection ON by default */
5a1aceb0 2099#ifdef CONFIG_ENV_IS_IN_FLASH
be60a902 2100 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV
2101 CONFIG_ENV_ADDR,
2102 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
2103 flash_get_info(CONFIG_ENV_ADDR));
be60a902 2104#endif
79b4cda0 2105
be60a902 2106 /* Redundant environment protection ON by default */
0e8d1586 2107#ifdef CONFIG_ENV_ADDR_REDUND
be60a902 2108 flash_protect (FLAG_PROTECT_SET,
0e8d1586 2109 CONFIG_ENV_ADDR_REDUND,
dfcd7f21 2110 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
0e8d1586 2111 flash_get_info(CONFIG_ENV_ADDR_REDUND));
be60a902 2112#endif
c63ad632 2113
6d0f6bcf 2114#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
c63ad632
MF
2115 for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) {
2116 debug("autoprotecting from %08x to %08x\n",
2117 apl[i].start, apl[i].start + apl[i].size - 1);
2118 flash_protect (FLAG_PROTECT_SET,
2119 apl[i].start,
2120 apl[i].start + apl[i].size - 1,
2121 flash_get_info(apl[i].start));
2122 }
2123#endif
91809ed5
PZ
2124
2125#ifdef CONFIG_FLASH_CFI_MTD
2126 cfi_mtd_init();
2127#endif
2128
be60a902 2129 return (size);
5653fc33 2130}