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Commit | Line | Data |
---|---|---|
1f948b43 | 1 | /* |
1da177e4 LT |
2 | Common Flash Interface probe code. |
3 | (C) 2000 Red Hat. GPL'd. | |
1da177e4 LT |
4 | See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5) |
5 | for the standard this probe goes back to. | |
6 | ||
7 | Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/module.h> |
11 | #include <linux/init.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <asm/io.h> | |
15 | #include <asm/byteorder.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/interrupt.h> | |
1da177e4 LT |
19 | |
20 | #include <linux/mtd/mtd.h> | |
21 | #include <linux/mtd/map.h> | |
22 | #include <linux/mtd/cfi.h> | |
23 | #include <linux/mtd/gen_probe.h> | |
24 | ||
1da177e4 | 25 | /* AMD */ |
4a22442f | 26 | #define AM29DL800BB 0x22CB |
1da177e4 LT |
27 | #define AM29DL800BT 0x224A |
28 | ||
29 | #define AM29F800BB 0x2258 | |
30 | #define AM29F800BT 0x22D6 | |
31 | #define AM29LV400BB 0x22BA | |
32 | #define AM29LV400BT 0x22B9 | |
33 | #define AM29LV800BB 0x225B | |
34 | #define AM29LV800BT 0x22DA | |
35 | #define AM29LV160DT 0x22C4 | |
36 | #define AM29LV160DB 0x2249 | |
37 | #define AM29F017D 0x003D | |
38 | #define AM29F016D 0x00AD | |
39 | #define AM29F080 0x00D5 | |
40 | #define AM29F040 0x00A4 | |
41 | #define AM29LV040B 0x004F | |
42 | #define AM29F032B 0x0041 | |
43 | #define AM29F002T 0x00B0 | |
8fd310a1 MR |
44 | #define AM29SL800DB 0x226B |
45 | #define AM29SL800DT 0x22EA | |
1da177e4 LT |
46 | |
47 | /* Atmel */ | |
48 | #define AT49BV512 0x0003 | |
49 | #define AT29LV512 0x003d | |
50 | #define AT49BV16X 0x00C0 | |
51 | #define AT49BV16XT 0x00C2 | |
52 | #define AT49BV32X 0x00C8 | |
53 | #define AT49BV32XT 0x00C9 | |
54 | ||
1b0b30ac | 55 | /* Eon */ |
974f2936 LW |
56 | #define EN29LV400AT 0x22B9 |
57 | #define EN29LV400AB 0x22BA | |
1b0b30ac MR |
58 | #define EN29SL800BB 0x226B |
59 | #define EN29SL800BT 0x22EA | |
60 | ||
1da177e4 LT |
61 | /* Fujitsu */ |
62 | #define MBM29F040C 0x00A4 | |
c9856e39 | 63 | #define MBM29F800BA 0x2258 |
1da177e4 LT |
64 | #define MBM29LV650UE 0x22D7 |
65 | #define MBM29LV320TE 0x22F6 | |
66 | #define MBM29LV320BE 0x22F9 | |
67 | #define MBM29LV160TE 0x22C4 | |
68 | #define MBM29LV160BE 0x2249 | |
69 | #define MBM29LV800BA 0x225B | |
70 | #define MBM29LV800TA 0x22DA | |
71 | #define MBM29LV400TC 0x22B9 | |
72 | #define MBM29LV400BC 0x22BA | |
73 | ||
74 | /* Hyundai */ | |
75 | #define HY29F002T 0x00B0 | |
76 | ||
77 | /* Intel */ | |
78 | #define I28F004B3T 0x00d4 | |
79 | #define I28F004B3B 0x00d5 | |
80 | #define I28F400B3T 0x8894 | |
81 | #define I28F400B3B 0x8895 | |
82 | #define I28F008S5 0x00a6 | |
83 | #define I28F016S5 0x00a0 | |
84 | #define I28F008SA 0x00a2 | |
85 | #define I28F008B3T 0x00d2 | |
86 | #define I28F008B3B 0x00d3 | |
87 | #define I28F800B3T 0x8892 | |
88 | #define I28F800B3B 0x8893 | |
89 | #define I28F016S3 0x00aa | |
90 | #define I28F016B3T 0x00d0 | |
91 | #define I28F016B3B 0x00d1 | |
92 | #define I28F160B3T 0x8890 | |
93 | #define I28F160B3B 0x8891 | |
94 | #define I28F320B3T 0x8896 | |
95 | #define I28F320B3B 0x8897 | |
96 | #define I28F640B3T 0x8898 | |
97 | #define I28F640B3B 0x8899 | |
b4c8c8cf SR |
98 | #define I28F640C3B 0x88CD |
99 | #define I28F160F3T 0x88F3 | |
100 | #define I28F160F3B 0x88F4 | |
101 | #define I28F160C3T 0x88C2 | |
102 | #define I28F160C3B 0x88C3 | |
1da177e4 LT |
103 | #define I82802AB 0x00ad |
104 | #define I82802AC 0x00ac | |
105 | ||
106 | /* Macronix */ | |
107 | #define MX29LV040C 0x004F | |
108 | #define MX29LV160T 0x22C4 | |
109 | #define MX29LV160B 0x2249 | |
c4e6952f | 110 | #define MX29F040 0x00A4 |
1da177e4 LT |
111 | #define MX29F016 0x00AD |
112 | #define MX29F002T 0x00B0 | |
113 | #define MX29F004T 0x0045 | |
114 | #define MX29F004B 0x0046 | |
115 | ||
116 | /* NEC */ | |
117 | #define UPD29F064115 0x221C | |
118 | ||
119 | /* PMC */ | |
120 | #define PM49FL002 0x006D | |
121 | #define PM49FL004 0x006E | |
122 | #define PM49FL008 0x006A | |
123 | ||
a63ec1b7 | 124 | /* Sharp */ |
fe2f4c8e | 125 | #define LH28F640BF 0x00B0 |
a63ec1b7 | 126 | |
1da177e4 | 127 | /* ST - www.st.com */ |
c9856e39 | 128 | #define M29F800AB 0x0058 |
db5432db LM |
129 | #define M29W800DT 0x22D7 |
130 | #define M29W800DB 0x225B | |
30d6a24e GF |
131 | #define M29W400DT 0x00EE |
132 | #define M29W400DB 0x00EF | |
1da177e4 LT |
133 | #define M29W160DT 0x22C4 |
134 | #define M29W160DB 0x2249 | |
135 | #define M29W040B 0x00E3 | |
136 | #define M50FW040 0x002C | |
137 | #define M50FW080 0x002D | |
138 | #define M50FW016 0x002E | |
139 | #define M50LPW080 0x002F | |
deb1a5f1 NC |
140 | #define M50FLW080A 0x0080 |
141 | #define M50FLW080B 0x0081 | |
e1070211 | 142 | #define PSD4256G6V 0x00e9 |
1da177e4 LT |
143 | |
144 | /* SST */ | |
145 | #define SST29EE020 0x0010 | |
146 | #define SST29LE020 0x0012 | |
147 | #define SST29EE512 0x005d | |
148 | #define SST29LE512 0x003d | |
149 | #define SST39LF800 0x2781 | |
150 | #define SST39LF160 0x2782 | |
88ec7c50 | 151 | #define SST39VF1601 0x234b |
bd50a0ff | 152 | #define SST39VF3201 0x235b |
087acaf1 WS |
153 | #define SST39WF1601 0x274b |
154 | #define SST39WF1602 0x274a | |
1da177e4 LT |
155 | #define SST39LF512 0x00D4 |
156 | #define SST39LF010 0x00D5 | |
157 | #define SST39LF020 0x00D6 | |
158 | #define SST39LF040 0x00D7 | |
159 | #define SST39SF010A 0x00B5 | |
160 | #define SST39SF020A 0x00B6 | |
a0645ce9 | 161 | #define SST39SF040 0x00B7 |
1da177e4 | 162 | #define SST49LF004B 0x0060 |
89072ef9 | 163 | #define SST49LF040B 0x0050 |
1da177e4 LT |
164 | #define SST49LF008A 0x005a |
165 | #define SST49LF030A 0x001C | |
166 | #define SST49LF040A 0x0051 | |
167 | #define SST49LF080A 0x005B | |
1b0a062b | 168 | #define SST36VF3203 0x7354 |
1da177e4 LT |
169 | |
170 | /* Toshiba */ | |
171 | #define TC58FVT160 0x00C2 | |
172 | #define TC58FVB160 0x0043 | |
173 | #define TC58FVT321 0x009A | |
174 | #define TC58FVB321 0x009C | |
175 | #define TC58FVT641 0x0093 | |
176 | #define TC58FVB641 0x0095 | |
177 | ||
178 | /* Winbond */ | |
179 | #define W49V002A 0x00b0 | |
180 | ||
181 | ||
182 | /* | |
183 | * Unlock address sets for AMD command sets. | |
184 | * Intel command sets use the MTD_UADDR_UNNECESSARY. | |
185 | * Each identifier, except MTD_UADDR_UNNECESSARY, and | |
186 | * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. | |
187 | * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure | |
188 | * initialization need not require initializing all of the | |
189 | * unlock addresses for all bit widths. | |
190 | */ | |
191 | enum uaddr { | |
192 | MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ | |
193 | MTD_UADDR_0x0555_0x02AA, | |
194 | MTD_UADDR_0x0555_0x0AAA, | |
195 | MTD_UADDR_0x5555_0x2AAA, | |
e1070211 | 196 | MTD_UADDR_0x0AAA_0x0554, |
1da177e4 | 197 | MTD_UADDR_0x0AAA_0x0555, |
ca6f12c6 | 198 | MTD_UADDR_0xAAAA_0x5555, |
1da177e4 LT |
199 | MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ |
200 | MTD_UADDR_UNNECESSARY, /* Does not require any address */ | |
201 | }; | |
202 | ||
203 | ||
204 | struct unlock_addr { | |
5d3cce3b DW |
205 | uint32_t addr1; |
206 | uint32_t addr2; | |
1da177e4 LT |
207 | }; |
208 | ||
209 | ||
210 | /* | |
211 | * I don't like the fact that the first entry in unlock_addrs[] | |
212 | * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, | |
213 | * should not be used. The problem is that structures with | |
214 | * initializers have extra fields initialized to 0. It is _very_ | |
3ad2f3fb | 215 | * desirable to have the unlock address entries for unsupported |
1da177e4 LT |
216 | * data widths automatically initialized - that means that |
217 | * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here | |
218 | * must go unused. | |
219 | */ | |
220 | static const struct unlock_addr unlock_addrs[] = { | |
221 | [MTD_UADDR_NOT_SUPPORTED] = { | |
222 | .addr1 = 0xffff, | |
223 | .addr2 = 0xffff | |
224 | }, | |
225 | ||
226 | [MTD_UADDR_0x0555_0x02AA] = { | |
227 | .addr1 = 0x0555, | |
228 | .addr2 = 0x02aa | |
229 | }, | |
230 | ||
231 | [MTD_UADDR_0x0555_0x0AAA] = { | |
232 | .addr1 = 0x0555, | |
233 | .addr2 = 0x0aaa | |
234 | }, | |
235 | ||
236 | [MTD_UADDR_0x5555_0x2AAA] = { | |
237 | .addr1 = 0x5555, | |
238 | .addr2 = 0x2aaa | |
239 | }, | |
240 | ||
e1070211 MF |
241 | [MTD_UADDR_0x0AAA_0x0554] = { |
242 | .addr1 = 0x0AAA, | |
243 | .addr2 = 0x0554 | |
244 | }, | |
245 | ||
1da177e4 LT |
246 | [MTD_UADDR_0x0AAA_0x0555] = { |
247 | .addr1 = 0x0AAA, | |
248 | .addr2 = 0x0555 | |
249 | }, | |
250 | ||
ca6f12c6 AN |
251 | [MTD_UADDR_0xAAAA_0x5555] = { |
252 | .addr1 = 0xaaaa, | |
253 | .addr2 = 0x5555 | |
254 | }, | |
255 | ||
1da177e4 LT |
256 | [MTD_UADDR_DONT_CARE] = { |
257 | .addr1 = 0x0000, /* Doesn't matter which address */ | |
258 | .addr2 = 0x0000 /* is used - must be last entry */ | |
259 | }, | |
260 | ||
261 | [MTD_UADDR_UNNECESSARY] = { | |
262 | .addr1 = 0x0000, | |
263 | .addr2 = 0x0000 | |
264 | } | |
265 | }; | |
266 | ||
1da177e4 | 267 | struct amd_flash_info { |
1da177e4 | 268 | const char *name; |
5d3cce3b DW |
269 | const uint16_t mfr_id; |
270 | const uint16_t dev_id; | |
271 | const uint8_t dev_size; | |
272 | const uint8_t nr_regions; | |
273 | const uint16_t cmd_set; | |
274 | const uint32_t regions[6]; | |
275 | const uint8_t devtypes; /* Bitmask for x8, x16 etc. */ | |
276 | const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */ | |
1da177e4 LT |
277 | }; |
278 | ||
279 | #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) | |
280 | ||
281 | #define SIZE_64KiB 16 | |
282 | #define SIZE_128KiB 17 | |
283 | #define SIZE_256KiB 18 | |
284 | #define SIZE_512KiB 19 | |
285 | #define SIZE_1MiB 20 | |
286 | #define SIZE_2MiB 21 | |
287 | #define SIZE_4MiB 22 | |
288 | #define SIZE_8MiB 23 | |
289 | ||
290 | ||
291 | /* | |
292 | * Please keep this list ordered by manufacturer! | |
293 | * Fortunately, the list isn't searched often and so a | |
294 | * slow, linear search isn't so bad. | |
295 | */ | |
296 | static const struct amd_flash_info jedec_table[] = { | |
297 | { | |
ae731822 | 298 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
299 | .dev_id = AM29F032B, |
300 | .name = "AMD AM29F032B", | |
5d3cce3b DW |
301 | .uaddr = MTD_UADDR_0x0555_0x02AA, |
302 | .devtypes = CFI_DEVICETYPE_X8, | |
303 | .dev_size = SIZE_4MiB, | |
304 | .cmd_set = P_ID_AMD_STD, | |
305 | .nr_regions = 1, | |
1da177e4 LT |
306 | .regions = { |
307 | ERASEINFO(0x10000,64) | |
308 | } | |
309 | }, { | |
ae731822 | 310 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
311 | .dev_id = AM29LV160DT, |
312 | .name = "AMD AM29LV160DT", | |
5d3cce3b DW |
313 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
314 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
315 | .dev_size = SIZE_2MiB, |
316 | .cmd_set = P_ID_AMD_STD, | |
317 | .nr_regions = 4, | |
1da177e4 LT |
318 | .regions = { |
319 | ERASEINFO(0x10000,31), | |
320 | ERASEINFO(0x08000,1), | |
321 | ERASEINFO(0x02000,2), | |
322 | ERASEINFO(0x04000,1) | |
323 | } | |
324 | }, { | |
ae731822 | 325 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
326 | .dev_id = AM29LV160DB, |
327 | .name = "AMD AM29LV160DB", | |
5d3cce3b DW |
328 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
329 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
330 | .dev_size = SIZE_2MiB, |
331 | .cmd_set = P_ID_AMD_STD, | |
332 | .nr_regions = 4, | |
1da177e4 LT |
333 | .regions = { |
334 | ERASEINFO(0x04000,1), | |
335 | ERASEINFO(0x02000,2), | |
336 | ERASEINFO(0x08000,1), | |
337 | ERASEINFO(0x10000,31) | |
338 | } | |
339 | }, { | |
ae731822 | 340 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
341 | .dev_id = AM29LV400BB, |
342 | .name = "AMD AM29LV400BB", | |
5d3cce3b DW |
343 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
344 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
345 | .dev_size = SIZE_512KiB, |
346 | .cmd_set = P_ID_AMD_STD, | |
347 | .nr_regions = 4, | |
1da177e4 LT |
348 | .regions = { |
349 | ERASEINFO(0x04000,1), | |
350 | ERASEINFO(0x02000,2), | |
351 | ERASEINFO(0x08000,1), | |
352 | ERASEINFO(0x10000,7) | |
353 | } | |
354 | }, { | |
ae731822 | 355 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
356 | .dev_id = AM29LV400BT, |
357 | .name = "AMD AM29LV400BT", | |
5d3cce3b DW |
358 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
359 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
360 | .dev_size = SIZE_512KiB, |
361 | .cmd_set = P_ID_AMD_STD, | |
362 | .nr_regions = 4, | |
1da177e4 LT |
363 | .regions = { |
364 | ERASEINFO(0x10000,7), | |
365 | ERASEINFO(0x08000,1), | |
366 | ERASEINFO(0x02000,2), | |
367 | ERASEINFO(0x04000,1) | |
368 | } | |
369 | }, { | |
ae731822 | 370 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
371 | .dev_id = AM29LV800BB, |
372 | .name = "AMD AM29LV800BB", | |
5d3cce3b DW |
373 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
374 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
375 | .dev_size = SIZE_1MiB, |
376 | .cmd_set = P_ID_AMD_STD, | |
377 | .nr_regions = 4, | |
1da177e4 LT |
378 | .regions = { |
379 | ERASEINFO(0x04000,1), | |
380 | ERASEINFO(0x02000,2), | |
381 | ERASEINFO(0x08000,1), | |
382 | ERASEINFO(0x10000,15), | |
383 | } | |
384 | }, { | |
385 | /* add DL */ | |
ae731822 | 386 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
387 | .dev_id = AM29DL800BB, |
388 | .name = "AMD AM29DL800BB", | |
5d3cce3b DW |
389 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
390 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
391 | .dev_size = SIZE_1MiB, |
392 | .cmd_set = P_ID_AMD_STD, | |
393 | .nr_regions = 6, | |
1da177e4 LT |
394 | .regions = { |
395 | ERASEINFO(0x04000,1), | |
396 | ERASEINFO(0x08000,1), | |
397 | ERASEINFO(0x02000,4), | |
398 | ERASEINFO(0x08000,1), | |
399 | ERASEINFO(0x04000,1), | |
400 | ERASEINFO(0x10000,14) | |
401 | } | |
402 | }, { | |
ae731822 | 403 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
404 | .dev_id = AM29DL800BT, |
405 | .name = "AMD AM29DL800BT", | |
5d3cce3b DW |
406 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
407 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
408 | .dev_size = SIZE_1MiB, |
409 | .cmd_set = P_ID_AMD_STD, | |
410 | .nr_regions = 6, | |
1da177e4 LT |
411 | .regions = { |
412 | ERASEINFO(0x10000,14), | |
413 | ERASEINFO(0x04000,1), | |
414 | ERASEINFO(0x08000,1), | |
415 | ERASEINFO(0x02000,4), | |
416 | ERASEINFO(0x08000,1), | |
417 | ERASEINFO(0x04000,1) | |
418 | } | |
419 | }, { | |
ae731822 | 420 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
421 | .dev_id = AM29F800BB, |
422 | .name = "AMD AM29F800BB", | |
5d3cce3b DW |
423 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
424 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
425 | .dev_size = SIZE_1MiB, |
426 | .cmd_set = P_ID_AMD_STD, | |
427 | .nr_regions = 4, | |
1da177e4 LT |
428 | .regions = { |
429 | ERASEINFO(0x04000,1), | |
430 | ERASEINFO(0x02000,2), | |
431 | ERASEINFO(0x08000,1), | |
432 | ERASEINFO(0x10000,15), | |
433 | } | |
434 | }, { | |
ae731822 | 435 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
436 | .dev_id = AM29LV800BT, |
437 | .name = "AMD AM29LV800BT", | |
5d3cce3b DW |
438 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
439 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
440 | .dev_size = SIZE_1MiB, |
441 | .cmd_set = P_ID_AMD_STD, | |
442 | .nr_regions = 4, | |
1da177e4 LT |
443 | .regions = { |
444 | ERASEINFO(0x10000,15), | |
445 | ERASEINFO(0x08000,1), | |
446 | ERASEINFO(0x02000,2), | |
447 | ERASEINFO(0x04000,1) | |
448 | } | |
449 | }, { | |
ae731822 | 450 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
451 | .dev_id = AM29F800BT, |
452 | .name = "AMD AM29F800BT", | |
5d3cce3b DW |
453 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
454 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
455 | .dev_size = SIZE_1MiB, |
456 | .cmd_set = P_ID_AMD_STD, | |
457 | .nr_regions = 4, | |
1da177e4 LT |
458 | .regions = { |
459 | ERASEINFO(0x10000,15), | |
460 | ERASEINFO(0x08000,1), | |
461 | ERASEINFO(0x02000,2), | |
462 | ERASEINFO(0x04000,1) | |
463 | } | |
464 | }, { | |
ae731822 | 465 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
466 | .dev_id = AM29F017D, |
467 | .name = "AMD AM29F017D", | |
5d3cce3b DW |
468 | .devtypes = CFI_DEVICETYPE_X8, |
469 | .uaddr = MTD_UADDR_DONT_CARE, | |
470 | .dev_size = SIZE_2MiB, | |
471 | .cmd_set = P_ID_AMD_STD, | |
472 | .nr_regions = 1, | |
1da177e4 LT |
473 | .regions = { |
474 | ERASEINFO(0x10000,32), | |
475 | } | |
476 | }, { | |
ae731822 | 477 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
478 | .dev_id = AM29F016D, |
479 | .name = "AMD AM29F016D", | |
5d3cce3b DW |
480 | .devtypes = CFI_DEVICETYPE_X8, |
481 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
482 | .dev_size = SIZE_2MiB, | |
483 | .cmd_set = P_ID_AMD_STD, | |
484 | .nr_regions = 1, | |
1da177e4 LT |
485 | .regions = { |
486 | ERASEINFO(0x10000,32), | |
487 | } | |
488 | }, { | |
ae731822 | 489 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
490 | .dev_id = AM29F080, |
491 | .name = "AMD AM29F080", | |
5d3cce3b DW |
492 | .devtypes = CFI_DEVICETYPE_X8, |
493 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
494 | .dev_size = SIZE_1MiB, | |
495 | .cmd_set = P_ID_AMD_STD, | |
496 | .nr_regions = 1, | |
1da177e4 LT |
497 | .regions = { |
498 | ERASEINFO(0x10000,16), | |
499 | } | |
500 | }, { | |
ae731822 | 501 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
502 | .dev_id = AM29F040, |
503 | .name = "AMD AM29F040", | |
5d3cce3b DW |
504 | .devtypes = CFI_DEVICETYPE_X8, |
505 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
506 | .dev_size = SIZE_512KiB, | |
507 | .cmd_set = P_ID_AMD_STD, | |
508 | .nr_regions = 1, | |
1da177e4 LT |
509 | .regions = { |
510 | ERASEINFO(0x10000,8), | |
511 | } | |
512 | }, { | |
ae731822 | 513 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
514 | .dev_id = AM29LV040B, |
515 | .name = "AMD AM29LV040B", | |
5d3cce3b DW |
516 | .devtypes = CFI_DEVICETYPE_X8, |
517 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
518 | .dev_size = SIZE_512KiB, | |
519 | .cmd_set = P_ID_AMD_STD, | |
520 | .nr_regions = 1, | |
1da177e4 LT |
521 | .regions = { |
522 | ERASEINFO(0x10000,8), | |
523 | } | |
524 | }, { | |
ae731822 | 525 | .mfr_id = CFI_MFR_AMD, |
1da177e4 LT |
526 | .dev_id = AM29F002T, |
527 | .name = "AMD AM29F002T", | |
5d3cce3b DW |
528 | .devtypes = CFI_DEVICETYPE_X8, |
529 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
530 | .dev_size = SIZE_256KiB, | |
531 | .cmd_set = P_ID_AMD_STD, | |
532 | .nr_regions = 4, | |
1da177e4 LT |
533 | .regions = { |
534 | ERASEINFO(0x10000,3), | |
535 | ERASEINFO(0x08000,1), | |
536 | ERASEINFO(0x02000,2), | |
537 | ERASEINFO(0x04000,1), | |
538 | } | |
8fd310a1 | 539 | }, { |
ae731822 | 540 | .mfr_id = CFI_MFR_AMD, |
8fd310a1 MR |
541 | .dev_id = AM29SL800DT, |
542 | .name = "AMD AM29SL800DT", | |
543 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
544 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
545 | .dev_size = SIZE_1MiB, | |
546 | .cmd_set = P_ID_AMD_STD, | |
547 | .nr_regions = 4, | |
548 | .regions = { | |
549 | ERASEINFO(0x10000,15), | |
550 | ERASEINFO(0x08000,1), | |
551 | ERASEINFO(0x02000,2), | |
552 | ERASEINFO(0x04000,1), | |
553 | } | |
554 | }, { | |
ae731822 | 555 | .mfr_id = CFI_MFR_AMD, |
8fd310a1 MR |
556 | .dev_id = AM29SL800DB, |
557 | .name = "AMD AM29SL800DB", | |
558 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
559 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
560 | .dev_size = SIZE_1MiB, | |
561 | .cmd_set = P_ID_AMD_STD, | |
562 | .nr_regions = 4, | |
563 | .regions = { | |
564 | ERASEINFO(0x04000,1), | |
565 | ERASEINFO(0x02000,2), | |
566 | ERASEINFO(0x08000,1), | |
567 | ERASEINFO(0x10000,15), | |
568 | } | |
1da177e4 | 569 | }, { |
ae731822 | 570 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
571 | .dev_id = AT49BV512, |
572 | .name = "Atmel AT49BV512", | |
5d3cce3b DW |
573 | .devtypes = CFI_DEVICETYPE_X8, |
574 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
575 | .dev_size = SIZE_64KiB, | |
576 | .cmd_set = P_ID_AMD_STD, | |
577 | .nr_regions = 1, | |
1da177e4 LT |
578 | .regions = { |
579 | ERASEINFO(0x10000,1) | |
580 | } | |
581 | }, { | |
ae731822 | 582 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
583 | .dev_id = AT29LV512, |
584 | .name = "Atmel AT29LV512", | |
5d3cce3b DW |
585 | .devtypes = CFI_DEVICETYPE_X8, |
586 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
587 | .dev_size = SIZE_64KiB, | |
588 | .cmd_set = P_ID_AMD_STD, | |
589 | .nr_regions = 1, | |
1da177e4 LT |
590 | .regions = { |
591 | ERASEINFO(0x80,256), | |
592 | ERASEINFO(0x80,256) | |
593 | } | |
594 | }, { | |
ae731822 | 595 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
596 | .dev_id = AT49BV16X, |
597 | .name = "Atmel AT49BV16X", | |
5d3cce3b | 598 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 599 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
600 | .dev_size = SIZE_2MiB, |
601 | .cmd_set = P_ID_AMD_STD, | |
602 | .nr_regions = 2, | |
1da177e4 LT |
603 | .regions = { |
604 | ERASEINFO(0x02000,8), | |
605 | ERASEINFO(0x10000,31) | |
606 | } | |
607 | }, { | |
ae731822 | 608 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
609 | .dev_id = AT49BV16XT, |
610 | .name = "Atmel AT49BV16XT", | |
5d3cce3b | 611 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 612 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
613 | .dev_size = SIZE_2MiB, |
614 | .cmd_set = P_ID_AMD_STD, | |
615 | .nr_regions = 2, | |
1da177e4 LT |
616 | .regions = { |
617 | ERASEINFO(0x10000,31), | |
618 | ERASEINFO(0x02000,8) | |
619 | } | |
620 | }, { | |
ae731822 | 621 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
622 | .dev_id = AT49BV32X, |
623 | .name = "Atmel AT49BV32X", | |
5d3cce3b | 624 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 625 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
626 | .dev_size = SIZE_4MiB, |
627 | .cmd_set = P_ID_AMD_STD, | |
628 | .nr_regions = 2, | |
1da177e4 LT |
629 | .regions = { |
630 | ERASEINFO(0x02000,8), | |
631 | ERASEINFO(0x10000,63) | |
632 | } | |
633 | }, { | |
ae731822 | 634 | .mfr_id = CFI_MFR_ATMEL, |
1da177e4 LT |
635 | .dev_id = AT49BV32XT, |
636 | .name = "Atmel AT49BV32XT", | |
5d3cce3b | 637 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 638 | .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ |
5d3cce3b DW |
639 | .dev_size = SIZE_4MiB, |
640 | .cmd_set = P_ID_AMD_STD, | |
641 | .nr_regions = 2, | |
1da177e4 LT |
642 | .regions = { |
643 | ERASEINFO(0x10000,63), | |
644 | ERASEINFO(0x02000,8) | |
645 | } | |
974f2936 LW |
646 | }, { |
647 | .mfr_id = CFI_MFR_EON, | |
648 | .dev_id = EN29LV400AT, | |
649 | .name = "Eon EN29LV400AT", | |
650 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
651 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
652 | .dev_size = SIZE_512KiB, | |
653 | .cmd_set = P_ID_AMD_STD, | |
654 | .nr_regions = 4, | |
655 | .regions = { | |
656 | ERASEINFO(0x10000,7), | |
657 | ERASEINFO(0x08000,1), | |
658 | ERASEINFO(0x02000,2), | |
659 | ERASEINFO(0x04000,1), | |
660 | } | |
661 | }, { | |
662 | .mfr_id = CFI_MFR_EON, | |
663 | .dev_id = EN29LV400AB, | |
664 | .name = "Eon EN29LV400AB", | |
665 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
666 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
667 | .dev_size = SIZE_512KiB, | |
668 | .cmd_set = P_ID_AMD_STD, | |
669 | .nr_regions = 4, | |
670 | .regions = { | |
671 | ERASEINFO(0x04000,1), | |
672 | ERASEINFO(0x02000,2), | |
673 | ERASEINFO(0x08000,1), | |
674 | ERASEINFO(0x10000,7), | |
675 | } | |
1b0b30ac | 676 | }, { |
ae731822 | 677 | .mfr_id = CFI_MFR_EON, |
1b0b30ac MR |
678 | .dev_id = EN29SL800BT, |
679 | .name = "Eon EN29SL800BT", | |
680 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
681 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
682 | .dev_size = SIZE_1MiB, | |
683 | .cmd_set = P_ID_AMD_STD, | |
684 | .nr_regions = 4, | |
685 | .regions = { | |
686 | ERASEINFO(0x10000,15), | |
687 | ERASEINFO(0x08000,1), | |
688 | ERASEINFO(0x02000,2), | |
689 | ERASEINFO(0x04000,1), | |
690 | } | |
691 | }, { | |
ae731822 | 692 | .mfr_id = CFI_MFR_EON, |
1b0b30ac MR |
693 | .dev_id = EN29SL800BB, |
694 | .name = "Eon EN29SL800BB", | |
695 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
696 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
697 | .dev_size = SIZE_1MiB, | |
698 | .cmd_set = P_ID_AMD_STD, | |
699 | .nr_regions = 4, | |
700 | .regions = { | |
701 | ERASEINFO(0x04000,1), | |
702 | ERASEINFO(0x02000,2), | |
703 | ERASEINFO(0x08000,1), | |
704 | ERASEINFO(0x10000,15), | |
705 | } | |
1da177e4 | 706 | }, { |
ae731822 | 707 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
708 | .dev_id = MBM29F040C, |
709 | .name = "Fujitsu MBM29F040C", | |
5d3cce3b DW |
710 | .devtypes = CFI_DEVICETYPE_X8, |
711 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
712 | .dev_size = SIZE_512KiB, | |
713 | .cmd_set = P_ID_AMD_STD, | |
714 | .nr_regions = 1, | |
1da177e4 LT |
715 | .regions = { |
716 | ERASEINFO(0x10000,8) | |
717 | } | |
c9856e39 | 718 | }, { |
ae731822 | 719 | .mfr_id = CFI_MFR_FUJITSU, |
c9856e39 PDM |
720 | .dev_id = MBM29F800BA, |
721 | .name = "Fujitsu MBM29F800BA", | |
5d3cce3b DW |
722 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
723 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
724 | .dev_size = SIZE_1MiB, |
725 | .cmd_set = P_ID_AMD_STD, | |
726 | .nr_regions = 4, | |
c9856e39 PDM |
727 | .regions = { |
728 | ERASEINFO(0x04000,1), | |
729 | ERASEINFO(0x02000,2), | |
730 | ERASEINFO(0x08000,1), | |
731 | ERASEINFO(0x10000,15), | |
732 | } | |
1da177e4 | 733 | }, { |
ae731822 | 734 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
735 | .dev_id = MBM29LV650UE, |
736 | .name = "Fujitsu MBM29LV650UE", | |
5d3cce3b DW |
737 | .devtypes = CFI_DEVICETYPE_X8, |
738 | .uaddr = MTD_UADDR_DONT_CARE, | |
739 | .dev_size = SIZE_8MiB, | |
740 | .cmd_set = P_ID_AMD_STD, | |
741 | .nr_regions = 1, | |
1da177e4 LT |
742 | .regions = { |
743 | ERASEINFO(0x10000,128) | |
744 | } | |
745 | }, { | |
ae731822 | 746 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
747 | .dev_id = MBM29LV320TE, |
748 | .name = "Fujitsu MBM29LV320TE", | |
5d3cce3b DW |
749 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
750 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
751 | .dev_size = SIZE_4MiB, |
752 | .cmd_set = P_ID_AMD_STD, | |
753 | .nr_regions = 2, | |
1da177e4 LT |
754 | .regions = { |
755 | ERASEINFO(0x10000,63), | |
756 | ERASEINFO(0x02000,8) | |
757 | } | |
758 | }, { | |
ae731822 | 759 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
760 | .dev_id = MBM29LV320BE, |
761 | .name = "Fujitsu MBM29LV320BE", | |
5d3cce3b DW |
762 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
763 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
764 | .dev_size = SIZE_4MiB, |
765 | .cmd_set = P_ID_AMD_STD, | |
766 | .nr_regions = 2, | |
1da177e4 LT |
767 | .regions = { |
768 | ERASEINFO(0x02000,8), | |
769 | ERASEINFO(0x10000,63) | |
770 | } | |
771 | }, { | |
ae731822 | 772 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
773 | .dev_id = MBM29LV160TE, |
774 | .name = "Fujitsu MBM29LV160TE", | |
5d3cce3b DW |
775 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
776 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
777 | .dev_size = SIZE_2MiB, |
778 | .cmd_set = P_ID_AMD_STD, | |
779 | .nr_regions = 4, | |
1da177e4 LT |
780 | .regions = { |
781 | ERASEINFO(0x10000,31), | |
782 | ERASEINFO(0x08000,1), | |
783 | ERASEINFO(0x02000,2), | |
784 | ERASEINFO(0x04000,1) | |
785 | } | |
786 | }, { | |
ae731822 | 787 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
788 | .dev_id = MBM29LV160BE, |
789 | .name = "Fujitsu MBM29LV160BE", | |
5d3cce3b DW |
790 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
791 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
792 | .dev_size = SIZE_2MiB, |
793 | .cmd_set = P_ID_AMD_STD, | |
794 | .nr_regions = 4, | |
1da177e4 LT |
795 | .regions = { |
796 | ERASEINFO(0x04000,1), | |
797 | ERASEINFO(0x02000,2), | |
798 | ERASEINFO(0x08000,1), | |
799 | ERASEINFO(0x10000,31) | |
800 | } | |
801 | }, { | |
ae731822 | 802 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
803 | .dev_id = MBM29LV800BA, |
804 | .name = "Fujitsu MBM29LV800BA", | |
5d3cce3b DW |
805 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
806 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
807 | .dev_size = SIZE_1MiB, |
808 | .cmd_set = P_ID_AMD_STD, | |
809 | .nr_regions = 4, | |
1da177e4 LT |
810 | .regions = { |
811 | ERASEINFO(0x04000,1), | |
812 | ERASEINFO(0x02000,2), | |
813 | ERASEINFO(0x08000,1), | |
814 | ERASEINFO(0x10000,15) | |
815 | } | |
816 | }, { | |
ae731822 | 817 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
818 | .dev_id = MBM29LV800TA, |
819 | .name = "Fujitsu MBM29LV800TA", | |
5d3cce3b DW |
820 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
821 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
822 | .dev_size = SIZE_1MiB, |
823 | .cmd_set = P_ID_AMD_STD, | |
824 | .nr_regions = 4, | |
1da177e4 LT |
825 | .regions = { |
826 | ERASEINFO(0x10000,15), | |
827 | ERASEINFO(0x08000,1), | |
828 | ERASEINFO(0x02000,2), | |
829 | ERASEINFO(0x04000,1) | |
830 | } | |
831 | }, { | |
ae731822 | 832 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
833 | .dev_id = MBM29LV400BC, |
834 | .name = "Fujitsu MBM29LV400BC", | |
5d3cce3b DW |
835 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
836 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
837 | .dev_size = SIZE_512KiB, |
838 | .cmd_set = P_ID_AMD_STD, | |
839 | .nr_regions = 4, | |
1da177e4 LT |
840 | .regions = { |
841 | ERASEINFO(0x04000,1), | |
842 | ERASEINFO(0x02000,2), | |
843 | ERASEINFO(0x08000,1), | |
844 | ERASEINFO(0x10000,7) | |
845 | } | |
846 | }, { | |
ae731822 | 847 | .mfr_id = CFI_MFR_FUJITSU, |
1da177e4 LT |
848 | .dev_id = MBM29LV400TC, |
849 | .name = "Fujitsu MBM29LV400TC", | |
5d3cce3b DW |
850 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
851 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
852 | .dev_size = SIZE_512KiB, |
853 | .cmd_set = P_ID_AMD_STD, | |
854 | .nr_regions = 4, | |
1da177e4 LT |
855 | .regions = { |
856 | ERASEINFO(0x10000,7), | |
857 | ERASEINFO(0x08000,1), | |
858 | ERASEINFO(0x02000,2), | |
859 | ERASEINFO(0x04000,1) | |
860 | } | |
861 | }, { | |
ae731822 | 862 | .mfr_id = CFI_MFR_HYUNDAI, |
1da177e4 LT |
863 | .dev_id = HY29F002T, |
864 | .name = "Hyundai HY29F002T", | |
5d3cce3b DW |
865 | .devtypes = CFI_DEVICETYPE_X8, |
866 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
867 | .dev_size = SIZE_256KiB, | |
868 | .cmd_set = P_ID_AMD_STD, | |
869 | .nr_regions = 4, | |
1da177e4 LT |
870 | .regions = { |
871 | ERASEINFO(0x10000,3), | |
872 | ERASEINFO(0x08000,1), | |
873 | ERASEINFO(0x02000,2), | |
874 | ERASEINFO(0x04000,1), | |
875 | } | |
876 | }, { | |
ae731822 | 877 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
878 | .dev_id = I28F004B3B, |
879 | .name = "Intel 28F004B3B", | |
5d3cce3b DW |
880 | .devtypes = CFI_DEVICETYPE_X8, |
881 | .uaddr = MTD_UADDR_UNNECESSARY, | |
882 | .dev_size = SIZE_512KiB, | |
883 | .cmd_set = P_ID_INTEL_STD, | |
884 | .nr_regions = 2, | |
1da177e4 LT |
885 | .regions = { |
886 | ERASEINFO(0x02000, 8), | |
887 | ERASEINFO(0x10000, 7), | |
888 | } | |
889 | }, { | |
ae731822 | 890 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
891 | .dev_id = I28F004B3T, |
892 | .name = "Intel 28F004B3T", | |
5d3cce3b DW |
893 | .devtypes = CFI_DEVICETYPE_X8, |
894 | .uaddr = MTD_UADDR_UNNECESSARY, | |
895 | .dev_size = SIZE_512KiB, | |
896 | .cmd_set = P_ID_INTEL_STD, | |
897 | .nr_regions = 2, | |
1da177e4 LT |
898 | .regions = { |
899 | ERASEINFO(0x10000, 7), | |
900 | ERASEINFO(0x02000, 8), | |
901 | } | |
902 | }, { | |
ae731822 | 903 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
904 | .dev_id = I28F400B3B, |
905 | .name = "Intel 28F400B3B", | |
5d3cce3b DW |
906 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
907 | .uaddr = MTD_UADDR_UNNECESSARY, | |
5d3cce3b DW |
908 | .dev_size = SIZE_512KiB, |
909 | .cmd_set = P_ID_INTEL_STD, | |
910 | .nr_regions = 2, | |
1da177e4 LT |
911 | .regions = { |
912 | ERASEINFO(0x02000, 8), | |
913 | ERASEINFO(0x10000, 7), | |
914 | } | |
915 | }, { | |
ae731822 | 916 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
917 | .dev_id = I28F400B3T, |
918 | .name = "Intel 28F400B3T", | |
5d3cce3b DW |
919 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
920 | .uaddr = MTD_UADDR_UNNECESSARY, | |
5d3cce3b DW |
921 | .dev_size = SIZE_512KiB, |
922 | .cmd_set = P_ID_INTEL_STD, | |
923 | .nr_regions = 2, | |
1da177e4 LT |
924 | .regions = { |
925 | ERASEINFO(0x10000, 7), | |
926 | ERASEINFO(0x02000, 8), | |
927 | } | |
928 | }, { | |
ae731822 | 929 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
930 | .dev_id = I28F008B3B, |
931 | .name = "Intel 28F008B3B", | |
5d3cce3b DW |
932 | .devtypes = CFI_DEVICETYPE_X8, |
933 | .uaddr = MTD_UADDR_UNNECESSARY, | |
934 | .dev_size = SIZE_1MiB, | |
935 | .cmd_set = P_ID_INTEL_STD, | |
936 | .nr_regions = 2, | |
1da177e4 LT |
937 | .regions = { |
938 | ERASEINFO(0x02000, 8), | |
939 | ERASEINFO(0x10000, 15), | |
940 | } | |
941 | }, { | |
ae731822 | 942 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
943 | .dev_id = I28F008B3T, |
944 | .name = "Intel 28F008B3T", | |
5d3cce3b DW |
945 | .devtypes = CFI_DEVICETYPE_X8, |
946 | .uaddr = MTD_UADDR_UNNECESSARY, | |
947 | .dev_size = SIZE_1MiB, | |
948 | .cmd_set = P_ID_INTEL_STD, | |
949 | .nr_regions = 2, | |
1da177e4 LT |
950 | .regions = { |
951 | ERASEINFO(0x10000, 15), | |
952 | ERASEINFO(0x02000, 8), | |
953 | } | |
954 | }, { | |
ae731822 | 955 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
956 | .dev_id = I28F008S5, |
957 | .name = "Intel 28F008S5", | |
5d3cce3b DW |
958 | .devtypes = CFI_DEVICETYPE_X8, |
959 | .uaddr = MTD_UADDR_UNNECESSARY, | |
960 | .dev_size = SIZE_1MiB, | |
961 | .cmd_set = P_ID_INTEL_EXT, | |
962 | .nr_regions = 1, | |
1da177e4 LT |
963 | .regions = { |
964 | ERASEINFO(0x10000,16), | |
965 | } | |
966 | }, { | |
ae731822 | 967 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
968 | .dev_id = I28F016S5, |
969 | .name = "Intel 28F016S5", | |
5d3cce3b DW |
970 | .devtypes = CFI_DEVICETYPE_X8, |
971 | .uaddr = MTD_UADDR_UNNECESSARY, | |
972 | .dev_size = SIZE_2MiB, | |
973 | .cmd_set = P_ID_INTEL_EXT, | |
974 | .nr_regions = 1, | |
1da177e4 LT |
975 | .regions = { |
976 | ERASEINFO(0x10000,32), | |
977 | } | |
978 | }, { | |
ae731822 | 979 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
980 | .dev_id = I28F008SA, |
981 | .name = "Intel 28F008SA", | |
5d3cce3b DW |
982 | .devtypes = CFI_DEVICETYPE_X8, |
983 | .uaddr = MTD_UADDR_UNNECESSARY, | |
984 | .dev_size = SIZE_1MiB, | |
985 | .cmd_set = P_ID_INTEL_STD, | |
986 | .nr_regions = 1, | |
1da177e4 LT |
987 | .regions = { |
988 | ERASEINFO(0x10000, 16), | |
989 | } | |
990 | }, { | |
ae731822 | 991 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
992 | .dev_id = I28F800B3B, |
993 | .name = "Intel 28F800B3B", | |
5d3cce3b DW |
994 | .devtypes = CFI_DEVICETYPE_X16, |
995 | .uaddr = MTD_UADDR_UNNECESSARY, | |
996 | .dev_size = SIZE_1MiB, | |
997 | .cmd_set = P_ID_INTEL_STD, | |
998 | .nr_regions = 2, | |
1da177e4 LT |
999 | .regions = { |
1000 | ERASEINFO(0x02000, 8), | |
1001 | ERASEINFO(0x10000, 15), | |
1002 | } | |
1003 | }, { | |
ae731822 | 1004 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1005 | .dev_id = I28F800B3T, |
1006 | .name = "Intel 28F800B3T", | |
5d3cce3b DW |
1007 | .devtypes = CFI_DEVICETYPE_X16, |
1008 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1009 | .dev_size = SIZE_1MiB, | |
1010 | .cmd_set = P_ID_INTEL_STD, | |
1011 | .nr_regions = 2, | |
1da177e4 LT |
1012 | .regions = { |
1013 | ERASEINFO(0x10000, 15), | |
1014 | ERASEINFO(0x02000, 8), | |
1015 | } | |
1016 | }, { | |
ae731822 | 1017 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1018 | .dev_id = I28F016B3B, |
1019 | .name = "Intel 28F016B3B", | |
5d3cce3b DW |
1020 | .devtypes = CFI_DEVICETYPE_X8, |
1021 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1022 | .dev_size = SIZE_2MiB, | |
1023 | .cmd_set = P_ID_INTEL_STD, | |
1024 | .nr_regions = 2, | |
1da177e4 LT |
1025 | .regions = { |
1026 | ERASEINFO(0x02000, 8), | |
1027 | ERASEINFO(0x10000, 31), | |
1028 | } | |
1029 | }, { | |
ae731822 | 1030 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1031 | .dev_id = I28F016S3, |
1032 | .name = "Intel I28F016S3", | |
5d3cce3b DW |
1033 | .devtypes = CFI_DEVICETYPE_X8, |
1034 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1035 | .dev_size = SIZE_2MiB, | |
1036 | .cmd_set = P_ID_INTEL_STD, | |
1037 | .nr_regions = 1, | |
1da177e4 LT |
1038 | .regions = { |
1039 | ERASEINFO(0x10000, 32), | |
1040 | } | |
1041 | }, { | |
ae731822 | 1042 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1043 | .dev_id = I28F016B3T, |
1044 | .name = "Intel 28F016B3T", | |
5d3cce3b DW |
1045 | .devtypes = CFI_DEVICETYPE_X8, |
1046 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1047 | .dev_size = SIZE_2MiB, | |
1048 | .cmd_set = P_ID_INTEL_STD, | |
1049 | .nr_regions = 2, | |
1da177e4 LT |
1050 | .regions = { |
1051 | ERASEINFO(0x10000, 31), | |
1052 | ERASEINFO(0x02000, 8), | |
1053 | } | |
1054 | }, { | |
ae731822 | 1055 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1056 | .dev_id = I28F160B3B, |
1057 | .name = "Intel 28F160B3B", | |
5d3cce3b DW |
1058 | .devtypes = CFI_DEVICETYPE_X16, |
1059 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1060 | .dev_size = SIZE_2MiB, | |
1061 | .cmd_set = P_ID_INTEL_STD, | |
1062 | .nr_regions = 2, | |
1da177e4 LT |
1063 | .regions = { |
1064 | ERASEINFO(0x02000, 8), | |
1065 | ERASEINFO(0x10000, 31), | |
1066 | } | |
1067 | }, { | |
ae731822 | 1068 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1069 | .dev_id = I28F160B3T, |
1070 | .name = "Intel 28F160B3T", | |
5d3cce3b DW |
1071 | .devtypes = CFI_DEVICETYPE_X16, |
1072 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1073 | .dev_size = SIZE_2MiB, | |
1074 | .cmd_set = P_ID_INTEL_STD, | |
1075 | .nr_regions = 2, | |
1da177e4 LT |
1076 | .regions = { |
1077 | ERASEINFO(0x10000, 31), | |
1078 | ERASEINFO(0x02000, 8), | |
1079 | } | |
1080 | }, { | |
ae731822 | 1081 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1082 | .dev_id = I28F320B3B, |
1083 | .name = "Intel 28F320B3B", | |
5d3cce3b DW |
1084 | .devtypes = CFI_DEVICETYPE_X16, |
1085 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1086 | .dev_size = SIZE_4MiB, | |
1087 | .cmd_set = P_ID_INTEL_STD, | |
1088 | .nr_regions = 2, | |
1da177e4 LT |
1089 | .regions = { |
1090 | ERASEINFO(0x02000, 8), | |
1091 | ERASEINFO(0x10000, 63), | |
1092 | } | |
1093 | }, { | |
ae731822 | 1094 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1095 | .dev_id = I28F320B3T, |
1096 | .name = "Intel 28F320B3T", | |
5d3cce3b DW |
1097 | .devtypes = CFI_DEVICETYPE_X16, |
1098 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1099 | .dev_size = SIZE_4MiB, | |
1100 | .cmd_set = P_ID_INTEL_STD, | |
1101 | .nr_regions = 2, | |
1da177e4 LT |
1102 | .regions = { |
1103 | ERASEINFO(0x10000, 63), | |
1104 | ERASEINFO(0x02000, 8), | |
1105 | } | |
1106 | }, { | |
ae731822 | 1107 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1108 | .dev_id = I28F640B3B, |
1109 | .name = "Intel 28F640B3B", | |
5d3cce3b DW |
1110 | .devtypes = CFI_DEVICETYPE_X16, |
1111 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1112 | .dev_size = SIZE_8MiB, | |
1113 | .cmd_set = P_ID_INTEL_STD, | |
1114 | .nr_regions = 2, | |
1da177e4 LT |
1115 | .regions = { |
1116 | ERASEINFO(0x02000, 8), | |
1117 | ERASEINFO(0x10000, 127), | |
1118 | } | |
1119 | }, { | |
ae731822 | 1120 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1121 | .dev_id = I28F640B3T, |
1122 | .name = "Intel 28F640B3T", | |
5d3cce3b DW |
1123 | .devtypes = CFI_DEVICETYPE_X16, |
1124 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1125 | .dev_size = SIZE_8MiB, | |
1126 | .cmd_set = P_ID_INTEL_STD, | |
1127 | .nr_regions = 2, | |
1da177e4 LT |
1128 | .regions = { |
1129 | ERASEINFO(0x10000, 127), | |
1130 | ERASEINFO(0x02000, 8), | |
1131 | } | |
b4c8c8cf | 1132 | }, { |
ae731822 | 1133 | .mfr_id = CFI_MFR_INTEL, |
b4c8c8cf SR |
1134 | .dev_id = I28F640C3B, |
1135 | .name = "Intel 28F640C3B", | |
1136 | .devtypes = CFI_DEVICETYPE_X16, | |
1137 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1138 | .dev_size = SIZE_8MiB, | |
1139 | .cmd_set = P_ID_INTEL_STD, | |
1140 | .nr_regions = 2, | |
1141 | .regions = { | |
1142 | ERASEINFO(0x02000, 8), | |
1143 | ERASEINFO(0x10000, 127), | |
1144 | } | |
1da177e4 | 1145 | }, { |
ae731822 | 1146 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1147 | .dev_id = I82802AB, |
1148 | .name = "Intel 82802AB", | |
5d3cce3b DW |
1149 | .devtypes = CFI_DEVICETYPE_X8, |
1150 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1151 | .dev_size = SIZE_512KiB, | |
1152 | .cmd_set = P_ID_INTEL_EXT, | |
1153 | .nr_regions = 1, | |
1da177e4 LT |
1154 | .regions = { |
1155 | ERASEINFO(0x10000,8), | |
1156 | } | |
1157 | }, { | |
ae731822 | 1158 | .mfr_id = CFI_MFR_INTEL, |
1da177e4 LT |
1159 | .dev_id = I82802AC, |
1160 | .name = "Intel 82802AC", | |
5d3cce3b DW |
1161 | .devtypes = CFI_DEVICETYPE_X8, |
1162 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1163 | .dev_size = SIZE_1MiB, | |
1164 | .cmd_set = P_ID_INTEL_EXT, | |
1165 | .nr_regions = 1, | |
1da177e4 LT |
1166 | .regions = { |
1167 | ERASEINFO(0x10000,16), | |
1168 | } | |
1169 | }, { | |
ae731822 | 1170 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1171 | .dev_id = MX29LV040C, |
1172 | .name = "Macronix MX29LV040C", | |
5d3cce3b DW |
1173 | .devtypes = CFI_DEVICETYPE_X8, |
1174 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1175 | .dev_size = SIZE_512KiB, | |
1176 | .cmd_set = P_ID_AMD_STD, | |
1177 | .nr_regions = 1, | |
1da177e4 LT |
1178 | .regions = { |
1179 | ERASEINFO(0x10000,8), | |
1180 | } | |
1181 | }, { | |
ae731822 | 1182 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1183 | .dev_id = MX29LV160T, |
1184 | .name = "MXIC MX29LV160T", | |
5d3cce3b DW |
1185 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1186 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1187 | .dev_size = SIZE_2MiB, |
1188 | .cmd_set = P_ID_AMD_STD, | |
1189 | .nr_regions = 4, | |
1da177e4 LT |
1190 | .regions = { |
1191 | ERASEINFO(0x10000,31), | |
1192 | ERASEINFO(0x08000,1), | |
1193 | ERASEINFO(0x02000,2), | |
1194 | ERASEINFO(0x04000,1) | |
1195 | } | |
1196 | }, { | |
ae731822 | 1197 | .mfr_id = CFI_MFR_NEC, |
1da177e4 LT |
1198 | .dev_id = UPD29F064115, |
1199 | .name = "NEC uPD29F064115", | |
9aff1b1a HI |
1200 | .devtypes = CFI_DEVICETYPE_X16, |
1201 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
5d3cce3b DW |
1202 | .dev_size = SIZE_8MiB, |
1203 | .cmd_set = P_ID_AMD_STD, | |
1204 | .nr_regions = 3, | |
1da177e4 LT |
1205 | .regions = { |
1206 | ERASEINFO(0x2000,8), | |
1207 | ERASEINFO(0x10000,126), | |
1208 | ERASEINFO(0x2000,8), | |
1209 | } | |
1210 | }, { | |
ae731822 | 1211 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1212 | .dev_id = MX29LV160B, |
1213 | .name = "MXIC MX29LV160B", | |
5d3cce3b DW |
1214 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1215 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1216 | .dev_size = SIZE_2MiB, |
1217 | .cmd_set = P_ID_AMD_STD, | |
1218 | .nr_regions = 4, | |
1da177e4 LT |
1219 | .regions = { |
1220 | ERASEINFO(0x04000,1), | |
1221 | ERASEINFO(0x02000,2), | |
1222 | ERASEINFO(0x08000,1), | |
1223 | ERASEINFO(0x10000,31) | |
1224 | } | |
1225 | }, { | |
ae731822 | 1226 | .mfr_id = CFI_MFR_MACRONIX, |
c4e6952f TY |
1227 | .dev_id = MX29F040, |
1228 | .name = "Macronix MX29F040", | |
5d3cce3b DW |
1229 | .devtypes = CFI_DEVICETYPE_X8, |
1230 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1231 | .dev_size = SIZE_512KiB, | |
1232 | .cmd_set = P_ID_AMD_STD, | |
1233 | .nr_regions = 1, | |
c4e6952f TY |
1234 | .regions = { |
1235 | ERASEINFO(0x10000,8), | |
1236 | } | |
35d086b1 | 1237 | }, { |
ae731822 | 1238 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1239 | .dev_id = MX29F016, |
1240 | .name = "Macronix MX29F016", | |
5d3cce3b DW |
1241 | .devtypes = CFI_DEVICETYPE_X8, |
1242 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1243 | .dev_size = SIZE_2MiB, | |
1244 | .cmd_set = P_ID_AMD_STD, | |
1245 | .nr_regions = 1, | |
1da177e4 LT |
1246 | .regions = { |
1247 | ERASEINFO(0x10000,32), | |
1248 | } | |
35d086b1 | 1249 | }, { |
ae731822 | 1250 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1251 | .dev_id = MX29F004T, |
1252 | .name = "Macronix MX29F004T", | |
5d3cce3b DW |
1253 | .devtypes = CFI_DEVICETYPE_X8, |
1254 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1255 | .dev_size = SIZE_512KiB, | |
1256 | .cmd_set = P_ID_AMD_STD, | |
1257 | .nr_regions = 4, | |
1da177e4 LT |
1258 | .regions = { |
1259 | ERASEINFO(0x10000,7), | |
1260 | ERASEINFO(0x08000,1), | |
1261 | ERASEINFO(0x02000,2), | |
1262 | ERASEINFO(0x04000,1), | |
1263 | } | |
35d086b1 | 1264 | }, { |
ae731822 | 1265 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1266 | .dev_id = MX29F004B, |
1267 | .name = "Macronix MX29F004B", | |
5d3cce3b DW |
1268 | .devtypes = CFI_DEVICETYPE_X8, |
1269 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1270 | .dev_size = SIZE_512KiB, | |
1271 | .cmd_set = P_ID_AMD_STD, | |
1272 | .nr_regions = 4, | |
1da177e4 LT |
1273 | .regions = { |
1274 | ERASEINFO(0x04000,1), | |
1275 | ERASEINFO(0x02000,2), | |
1276 | ERASEINFO(0x08000,1), | |
1277 | ERASEINFO(0x10000,7), | |
1278 | } | |
1279 | }, { | |
ae731822 | 1280 | .mfr_id = CFI_MFR_MACRONIX, |
1da177e4 LT |
1281 | .dev_id = MX29F002T, |
1282 | .name = "Macronix MX29F002T", | |
5d3cce3b DW |
1283 | .devtypes = CFI_DEVICETYPE_X8, |
1284 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1285 | .dev_size = SIZE_256KiB, | |
1286 | .cmd_set = P_ID_AMD_STD, | |
1287 | .nr_regions = 4, | |
1da177e4 LT |
1288 | .regions = { |
1289 | ERASEINFO(0x10000,3), | |
1290 | ERASEINFO(0x08000,1), | |
1291 | ERASEINFO(0x02000,2), | |
1292 | ERASEINFO(0x04000,1), | |
1293 | } | |
1294 | }, { | |
ae731822 | 1295 | .mfr_id = CFI_MFR_PMC, |
1da177e4 LT |
1296 | .dev_id = PM49FL002, |
1297 | .name = "PMC Pm49FL002", | |
5d3cce3b DW |
1298 | .devtypes = CFI_DEVICETYPE_X8, |
1299 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1300 | .dev_size = SIZE_256KiB, | |
1301 | .cmd_set = P_ID_AMD_STD, | |
1302 | .nr_regions = 1, | |
1da177e4 LT |
1303 | .regions = { |
1304 | ERASEINFO( 0x01000, 64 ) | |
1305 | } | |
1306 | }, { | |
ae731822 | 1307 | .mfr_id = CFI_MFR_PMC, |
1da177e4 LT |
1308 | .dev_id = PM49FL004, |
1309 | .name = "PMC Pm49FL004", | |
5d3cce3b DW |
1310 | .devtypes = CFI_DEVICETYPE_X8, |
1311 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1312 | .dev_size = SIZE_512KiB, | |
1313 | .cmd_set = P_ID_AMD_STD, | |
1314 | .nr_regions = 1, | |
1da177e4 LT |
1315 | .regions = { |
1316 | ERASEINFO( 0x01000, 128 ) | |
1317 | } | |
1318 | }, { | |
ae731822 | 1319 | .mfr_id = CFI_MFR_PMC, |
1da177e4 LT |
1320 | .dev_id = PM49FL008, |
1321 | .name = "PMC Pm49FL008", | |
5d3cce3b DW |
1322 | .devtypes = CFI_DEVICETYPE_X8, |
1323 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1324 | .dev_size = SIZE_1MiB, | |
1325 | .cmd_set = P_ID_AMD_STD, | |
1326 | .nr_regions = 1, | |
1da177e4 LT |
1327 | .regions = { |
1328 | ERASEINFO( 0x01000, 256 ) | |
1329 | } | |
a63ec1b7 | 1330 | }, { |
ae731822 | 1331 | .mfr_id = CFI_MFR_SHARP, |
a63ec1b7 PM |
1332 | .dev_id = LH28F640BF, |
1333 | .name = "LH28F640BF", | |
fe2f4c8e | 1334 | .devtypes = CFI_DEVICETYPE_X16, |
5d3cce3b | 1335 | .uaddr = MTD_UADDR_UNNECESSARY, |
fe2f4c8e AA |
1336 | .dev_size = SIZE_8MiB, |
1337 | .cmd_set = P_ID_INTEL_EXT, | |
1338 | .nr_regions = 2, | |
5d3cce3b | 1339 | .regions = { |
fe2f4c8e AA |
1340 | ERASEINFO(0x10000, 127), |
1341 | ERASEINFO(0x02000, 8), | |
a63ec1b7 | 1342 | } |
35d086b1 | 1343 | }, { |
ae731822 | 1344 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1345 | .dev_id = SST39LF512, |
1346 | .name = "SST 39LF512", | |
5d3cce3b DW |
1347 | .devtypes = CFI_DEVICETYPE_X8, |
1348 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1349 | .dev_size = SIZE_64KiB, | |
1350 | .cmd_set = P_ID_AMD_STD, | |
1351 | .nr_regions = 1, | |
1da177e4 LT |
1352 | .regions = { |
1353 | ERASEINFO(0x01000,16), | |
1354 | } | |
35d086b1 | 1355 | }, { |
ae731822 | 1356 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1357 | .dev_id = SST39LF010, |
1358 | .name = "SST 39LF010", | |
5d3cce3b DW |
1359 | .devtypes = CFI_DEVICETYPE_X8, |
1360 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1361 | .dev_size = SIZE_128KiB, | |
1362 | .cmd_set = P_ID_AMD_STD, | |
1363 | .nr_regions = 1, | |
1da177e4 LT |
1364 | .regions = { |
1365 | ERASEINFO(0x01000,32), | |
1366 | } | |
35d086b1 | 1367 | }, { |
ae731822 | 1368 | .mfr_id = CFI_MFR_SST, |
7d84b627 | 1369 | .dev_id = SST29EE020, |
1da177e4 | 1370 | .name = "SST 29EE020", |
5d3cce3b DW |
1371 | .devtypes = CFI_DEVICETYPE_X8, |
1372 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1373 | .dev_size = SIZE_256KiB, | |
1374 | .cmd_set = P_ID_SST_PAGE, | |
1375 | .nr_regions = 1, | |
1376 | .regions = {ERASEINFO(0x01000,64), | |
1377 | } | |
1378 | }, { | |
7d84b627 | 1379 | .mfr_id = CFI_MFR_SST, |
1da177e4 | 1380 | .dev_id = SST29LE020, |
7d84b627 | 1381 | .name = "SST 29LE020", |
5d3cce3b DW |
1382 | .devtypes = CFI_DEVICETYPE_X8, |
1383 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1384 | .dev_size = SIZE_256KiB, | |
1385 | .cmd_set = P_ID_SST_PAGE, | |
1386 | .nr_regions = 1, | |
1387 | .regions = {ERASEINFO(0x01000,64), | |
1388 | } | |
1da177e4 | 1389 | }, { |
ae731822 | 1390 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1391 | .dev_id = SST39LF020, |
1392 | .name = "SST 39LF020", | |
5d3cce3b DW |
1393 | .devtypes = CFI_DEVICETYPE_X8, |
1394 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1395 | .dev_size = SIZE_256KiB, | |
1396 | .cmd_set = P_ID_AMD_STD, | |
1397 | .nr_regions = 1, | |
1da177e4 LT |
1398 | .regions = { |
1399 | ERASEINFO(0x01000,64), | |
1400 | } | |
35d086b1 | 1401 | }, { |
ae731822 | 1402 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1403 | .dev_id = SST39LF040, |
1404 | .name = "SST 39LF040", | |
5d3cce3b DW |
1405 | .devtypes = CFI_DEVICETYPE_X8, |
1406 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1407 | .dev_size = SIZE_512KiB, | |
1408 | .cmd_set = P_ID_AMD_STD, | |
1409 | .nr_regions = 1, | |
1da177e4 LT |
1410 | .regions = { |
1411 | ERASEINFO(0x01000,128), | |
1412 | } | |
35d086b1 | 1413 | }, { |
ae731822 | 1414 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1415 | .dev_id = SST39SF010A, |
1416 | .name = "SST 39SF010A", | |
5d3cce3b DW |
1417 | .devtypes = CFI_DEVICETYPE_X8, |
1418 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1419 | .dev_size = SIZE_128KiB, | |
1420 | .cmd_set = P_ID_AMD_STD, | |
1421 | .nr_regions = 1, | |
1da177e4 LT |
1422 | .regions = { |
1423 | ERASEINFO(0x01000,32), | |
1424 | } | |
35d086b1 | 1425 | }, { |
ae731822 | 1426 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1427 | .dev_id = SST39SF020A, |
1428 | .name = "SST 39SF020A", | |
5d3cce3b DW |
1429 | .devtypes = CFI_DEVICETYPE_X8, |
1430 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1431 | .dev_size = SIZE_256KiB, | |
1432 | .cmd_set = P_ID_AMD_STD, | |
1433 | .nr_regions = 1, | |
1da177e4 LT |
1434 | .regions = { |
1435 | ERASEINFO(0x01000,64), | |
1436 | } | |
a0645ce9 | 1437 | }, { |
ae731822 | 1438 | .mfr_id = CFI_MFR_SST, |
a0645ce9 MM |
1439 | .dev_id = SST39SF040, |
1440 | .name = "SST 39SF040", | |
1441 | .devtypes = CFI_DEVICETYPE_X8, | |
1442 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1443 | .dev_size = SIZE_512KiB, | |
1444 | .cmd_set = P_ID_AMD_STD, | |
1445 | .nr_regions = 1, | |
1446 | .regions = { | |
1447 | ERASEINFO(0x01000,128), | |
1448 | } | |
1da177e4 | 1449 | }, { |
ae731822 | 1450 | .mfr_id = CFI_MFR_SST, |
5d3cce3b DW |
1451 | .dev_id = SST49LF040B, |
1452 | .name = "SST 49LF040B", | |
1453 | .devtypes = CFI_DEVICETYPE_X8, | |
1454 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1455 | .dev_size = SIZE_512KiB, | |
1456 | .cmd_set = P_ID_AMD_STD, | |
1457 | .nr_regions = 1, | |
1458 | .regions = { | |
89072ef9 RJ |
1459 | ERASEINFO(0x01000,128), |
1460 | } | |
1461 | }, { | |
1462 | ||
ae731822 | 1463 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1464 | .dev_id = SST49LF004B, |
1465 | .name = "SST 49LF004B", | |
5d3cce3b DW |
1466 | .devtypes = CFI_DEVICETYPE_X8, |
1467 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1468 | .dev_size = SIZE_512KiB, | |
1469 | .cmd_set = P_ID_AMD_STD, | |
1470 | .nr_regions = 1, | |
1da177e4 LT |
1471 | .regions = { |
1472 | ERASEINFO(0x01000,128), | |
1473 | } | |
1474 | }, { | |
ae731822 | 1475 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1476 | .dev_id = SST49LF008A, |
1477 | .name = "SST 49LF008A", | |
5d3cce3b DW |
1478 | .devtypes = CFI_DEVICETYPE_X8, |
1479 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1480 | .dev_size = SIZE_1MiB, | |
1481 | .cmd_set = P_ID_AMD_STD, | |
1482 | .nr_regions = 1, | |
1da177e4 LT |
1483 | .regions = { |
1484 | ERASEINFO(0x01000,256), | |
1485 | } | |
1486 | }, { | |
ae731822 | 1487 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1488 | .dev_id = SST49LF030A, |
1489 | .name = "SST 49LF030A", | |
5d3cce3b DW |
1490 | .devtypes = CFI_DEVICETYPE_X8, |
1491 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1492 | .dev_size = SIZE_512KiB, | |
1493 | .cmd_set = P_ID_AMD_STD, | |
1494 | .nr_regions = 1, | |
1da177e4 LT |
1495 | .regions = { |
1496 | ERASEINFO(0x01000,96), | |
1497 | } | |
1498 | }, { | |
ae731822 | 1499 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1500 | .dev_id = SST49LF040A, |
1501 | .name = "SST 49LF040A", | |
5d3cce3b DW |
1502 | .devtypes = CFI_DEVICETYPE_X8, |
1503 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1504 | .dev_size = SIZE_512KiB, | |
1505 | .cmd_set = P_ID_AMD_STD, | |
1506 | .nr_regions = 1, | |
1da177e4 LT |
1507 | .regions = { |
1508 | ERASEINFO(0x01000,128), | |
1509 | } | |
1510 | }, { | |
ae731822 | 1511 | .mfr_id = CFI_MFR_SST, |
1da177e4 LT |
1512 | .dev_id = SST49LF080A, |
1513 | .name = "SST 49LF080A", | |
5d3cce3b DW |
1514 | .devtypes = CFI_DEVICETYPE_X8, |
1515 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1516 | .dev_size = SIZE_1MiB, | |
1517 | .cmd_set = P_ID_AMD_STD, | |
1518 | .nr_regions = 1, | |
1da177e4 LT |
1519 | .regions = { |
1520 | ERASEINFO(0x01000,256), | |
1521 | } | |
1522 | }, { | |
ae731822 | 1523 | .mfr_id = CFI_MFR_SST, /* should be CFI */ |
5d3cce3b DW |
1524 | .dev_id = SST39LF160, |
1525 | .name = "SST 39LF160", | |
ca6f12c6 AN |
1526 | .devtypes = CFI_DEVICETYPE_X16, |
1527 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
5d3cce3b DW |
1528 | .dev_size = SIZE_2MiB, |
1529 | .cmd_set = P_ID_AMD_STD, | |
1530 | .nr_regions = 2, | |
1531 | .regions = { | |
1532 | ERASEINFO(0x1000,256), | |
1533 | ERASEINFO(0x1000,256) | |
1534 | } | |
1535 | }, { | |
ae731822 | 1536 | .mfr_id = CFI_MFR_SST, /* should be CFI */ |
5d3cce3b DW |
1537 | .dev_id = SST39VF1601, |
1538 | .name = "SST 39VF1601", | |
ca6f12c6 AN |
1539 | .devtypes = CFI_DEVICETYPE_X16, |
1540 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
5d3cce3b DW |
1541 | .dev_size = SIZE_2MiB, |
1542 | .cmd_set = P_ID_AMD_STD, | |
1543 | .nr_regions = 2, | |
1544 | .regions = { | |
1545 | ERASEINFO(0x1000,256), | |
1546 | ERASEINFO(0x1000,256) | |
1547 | } | |
087acaf1 WS |
1548 | }, { |
1549 | /* CFI is broken: reports AMD_STD, but needs custom uaddr */ | |
1550 | .mfr_id = CFI_MFR_SST, | |
1551 | .dev_id = SST39WF1601, | |
1552 | .name = "SST 39WF1601", | |
1553 | .devtypes = CFI_DEVICETYPE_X16, | |
1554 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
1555 | .dev_size = SIZE_2MiB, | |
1556 | .cmd_set = P_ID_AMD_STD, | |
1557 | .nr_regions = 2, | |
1558 | .regions = { | |
1559 | ERASEINFO(0x1000,256), | |
1560 | ERASEINFO(0x1000,256) | |
1561 | } | |
1562 | }, { | |
1563 | /* CFI is broken: reports AMD_STD, but needs custom uaddr */ | |
1564 | .mfr_id = CFI_MFR_SST, | |
1565 | .dev_id = SST39WF1602, | |
1566 | .name = "SST 39WF1602", | |
1567 | .devtypes = CFI_DEVICETYPE_X16, | |
1568 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
1569 | .dev_size = SIZE_2MiB, | |
1570 | .cmd_set = P_ID_AMD_STD, | |
1571 | .nr_regions = 2, | |
1572 | .regions = { | |
1573 | ERASEINFO(0x1000,256), | |
1574 | ERASEINFO(0x1000,256) | |
1575 | } | |
bd50a0ff | 1576 | }, { |
ae731822 | 1577 | .mfr_id = CFI_MFR_SST, /* should be CFI */ |
bd50a0ff YY |
1578 | .dev_id = SST39VF3201, |
1579 | .name = "SST 39VF3201", | |
1580 | .devtypes = CFI_DEVICETYPE_X16, | |
1581 | .uaddr = MTD_UADDR_0xAAAA_0x5555, | |
1582 | .dev_size = SIZE_4MiB, | |
1583 | .cmd_set = P_ID_AMD_STD, | |
1584 | .nr_regions = 4, | |
1585 | .regions = { | |
1586 | ERASEINFO(0x1000,256), | |
1587 | ERASEINFO(0x1000,256), | |
1588 | ERASEINFO(0x1000,256), | |
1589 | ERASEINFO(0x1000,256) | |
1590 | } | |
1b0a062b | 1591 | }, { |
ae731822 | 1592 | .mfr_id = CFI_MFR_SST, |
1b0a062b AD |
1593 | .dev_id = SST36VF3203, |
1594 | .name = "SST 36VF3203", | |
1595 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
1596 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
1597 | .dev_size = SIZE_4MiB, | |
1598 | .cmd_set = P_ID_AMD_STD, | |
1599 | .nr_regions = 1, | |
1600 | .regions = { | |
1601 | ERASEINFO(0x10000,64), | |
1602 | } | |
c9856e39 | 1603 | }, { |
ae731822 | 1604 | .mfr_id = CFI_MFR_ST, |
c9856e39 PDM |
1605 | .dev_id = M29F800AB, |
1606 | .name = "ST M29F800AB", | |
5d3cce3b DW |
1607 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1608 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1609 | .dev_size = SIZE_1MiB, |
1610 | .cmd_set = P_ID_AMD_STD, | |
1611 | .nr_regions = 4, | |
c9856e39 PDM |
1612 | .regions = { |
1613 | ERASEINFO(0x04000,1), | |
1614 | ERASEINFO(0x02000,2), | |
1615 | ERASEINFO(0x08000,1), | |
1616 | ERASEINFO(0x10000,15), | |
1617 | } | |
35d086b1 | 1618 | }, { |
ae731822 | 1619 | .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */ |
1da177e4 LT |
1620 | .dev_id = M29W800DT, |
1621 | .name = "ST M29W800DT", | |
5d3cce3b | 1622 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
db5432db | 1623 | .uaddr = MTD_UADDR_0x0AAA_0x0555, |
5d3cce3b DW |
1624 | .dev_size = SIZE_1MiB, |
1625 | .cmd_set = P_ID_AMD_STD, | |
1626 | .nr_regions = 4, | |
1da177e4 LT |
1627 | .regions = { |
1628 | ERASEINFO(0x10000,15), | |
1629 | ERASEINFO(0x08000,1), | |
1630 | ERASEINFO(0x02000,2), | |
1631 | ERASEINFO(0x04000,1) | |
1632 | } | |
1633 | }, { | |
ae731822 | 1634 | .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */ |
1da177e4 LT |
1635 | .dev_id = M29W800DB, |
1636 | .name = "ST M29W800DB", | |
5d3cce3b | 1637 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
db5432db | 1638 | .uaddr = MTD_UADDR_0x0AAA_0x0555, |
5d3cce3b DW |
1639 | .dev_size = SIZE_1MiB, |
1640 | .cmd_set = P_ID_AMD_STD, | |
1641 | .nr_regions = 4, | |
1da177e4 LT |
1642 | .regions = { |
1643 | ERASEINFO(0x04000,1), | |
1644 | ERASEINFO(0x02000,2), | |
1645 | ERASEINFO(0x08000,1), | |
1646 | ERASEINFO(0x10000,15) | |
1647 | } | |
30d6a24e | 1648 | }, { |
ae731822 | 1649 | .mfr_id = CFI_MFR_ST, |
30d6a24e GF |
1650 | .dev_id = M29W400DT, |
1651 | .name = "ST M29W400DT", | |
1652 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
1653 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
1654 | .dev_size = SIZE_512KiB, | |
1655 | .cmd_set = P_ID_AMD_STD, | |
1656 | .nr_regions = 4, | |
1657 | .regions = { | |
1658 | ERASEINFO(0x04000,7), | |
1659 | ERASEINFO(0x02000,1), | |
1660 | ERASEINFO(0x08000,2), | |
1661 | ERASEINFO(0x10000,1) | |
1662 | } | |
1663 | }, { | |
ae731822 | 1664 | .mfr_id = CFI_MFR_ST, |
30d6a24e GF |
1665 | .dev_id = M29W400DB, |
1666 | .name = "ST M29W400DB", | |
1667 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, | |
1668 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
1669 | .dev_size = SIZE_512KiB, | |
1670 | .cmd_set = P_ID_AMD_STD, | |
1671 | .nr_regions = 4, | |
1672 | .regions = { | |
1673 | ERASEINFO(0x04000,1), | |
1674 | ERASEINFO(0x02000,2), | |
1675 | ERASEINFO(0x08000,1), | |
1676 | ERASEINFO(0x10000,7) | |
1677 | } | |
1da177e4 | 1678 | }, { |
ae731822 | 1679 | .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */ |
1da177e4 LT |
1680 | .dev_id = M29W160DT, |
1681 | .name = "ST M29W160DT", | |
5d3cce3b | 1682 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1683 | .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ |
5d3cce3b DW |
1684 | .dev_size = SIZE_2MiB, |
1685 | .cmd_set = P_ID_AMD_STD, | |
1686 | .nr_regions = 4, | |
1da177e4 LT |
1687 | .regions = { |
1688 | ERASEINFO(0x10000,31), | |
1689 | ERASEINFO(0x08000,1), | |
1690 | ERASEINFO(0x02000,2), | |
1691 | ERASEINFO(0x04000,1) | |
1692 | } | |
1693 | }, { | |
ae731822 | 1694 | .mfr_id = CFI_MFR_ST, /* FIXME - CFI device? */ |
1da177e4 LT |
1695 | .dev_id = M29W160DB, |
1696 | .name = "ST M29W160DB", | |
5d3cce3b | 1697 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
cec80bf2 | 1698 | .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ |
5d3cce3b DW |
1699 | .dev_size = SIZE_2MiB, |
1700 | .cmd_set = P_ID_AMD_STD, | |
1701 | .nr_regions = 4, | |
1da177e4 LT |
1702 | .regions = { |
1703 | ERASEINFO(0x04000,1), | |
1704 | ERASEINFO(0x02000,2), | |
1705 | ERASEINFO(0x08000,1), | |
1706 | ERASEINFO(0x10000,31) | |
1707 | } | |
35d086b1 | 1708 | }, { |
ae731822 | 1709 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1710 | .dev_id = M29W040B, |
1711 | .name = "ST M29W040B", | |
5d3cce3b DW |
1712 | .devtypes = CFI_DEVICETYPE_X8, |
1713 | .uaddr = MTD_UADDR_0x0555_0x02AA, | |
1714 | .dev_size = SIZE_512KiB, | |
1715 | .cmd_set = P_ID_AMD_STD, | |
1716 | .nr_regions = 1, | |
1da177e4 LT |
1717 | .regions = { |
1718 | ERASEINFO(0x10000,8), | |
1719 | } | |
35d086b1 | 1720 | }, { |
ae731822 | 1721 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1722 | .dev_id = M50FW040, |
1723 | .name = "ST M50FW040", | |
5d3cce3b DW |
1724 | .devtypes = CFI_DEVICETYPE_X8, |
1725 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1726 | .dev_size = SIZE_512KiB, | |
1727 | .cmd_set = P_ID_INTEL_EXT, | |
1728 | .nr_regions = 1, | |
1da177e4 LT |
1729 | .regions = { |
1730 | ERASEINFO(0x10000,8), | |
1731 | } | |
35d086b1 | 1732 | }, { |
ae731822 | 1733 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1734 | .dev_id = M50FW080, |
1735 | .name = "ST M50FW080", | |
5d3cce3b DW |
1736 | .devtypes = CFI_DEVICETYPE_X8, |
1737 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1738 | .dev_size = SIZE_1MiB, | |
1739 | .cmd_set = P_ID_INTEL_EXT, | |
1740 | .nr_regions = 1, | |
1da177e4 LT |
1741 | .regions = { |
1742 | ERASEINFO(0x10000,16), | |
1743 | } | |
35d086b1 | 1744 | }, { |
ae731822 | 1745 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1746 | .dev_id = M50FW016, |
1747 | .name = "ST M50FW016", | |
5d3cce3b DW |
1748 | .devtypes = CFI_DEVICETYPE_X8, |
1749 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1750 | .dev_size = SIZE_2MiB, | |
1751 | .cmd_set = P_ID_INTEL_EXT, | |
1752 | .nr_regions = 1, | |
1da177e4 LT |
1753 | .regions = { |
1754 | ERASEINFO(0x10000,32), | |
1755 | } | |
1756 | }, { | |
ae731822 | 1757 | .mfr_id = CFI_MFR_ST, |
1da177e4 LT |
1758 | .dev_id = M50LPW080, |
1759 | .name = "ST M50LPW080", | |
5d3cce3b DW |
1760 | .devtypes = CFI_DEVICETYPE_X8, |
1761 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1762 | .dev_size = SIZE_1MiB, | |
1763 | .cmd_set = P_ID_INTEL_EXT, | |
1764 | .nr_regions = 1, | |
1da177e4 LT |
1765 | .regions = { |
1766 | ERASEINFO(0x10000,16), | |
deb1a5f1 NC |
1767 | }, |
1768 | }, { | |
ae731822 | 1769 | .mfr_id = CFI_MFR_ST, |
deb1a5f1 NC |
1770 | .dev_id = M50FLW080A, |
1771 | .name = "ST M50FLW080A", | |
1772 | .devtypes = CFI_DEVICETYPE_X8, | |
1773 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1774 | .dev_size = SIZE_1MiB, | |
1775 | .cmd_set = P_ID_INTEL_EXT, | |
1776 | .nr_regions = 4, | |
1777 | .regions = { | |
1778 | ERASEINFO(0x1000,16), | |
1779 | ERASEINFO(0x10000,13), | |
1780 | ERASEINFO(0x1000,16), | |
1781 | ERASEINFO(0x1000,16), | |
1782 | } | |
1783 | }, { | |
ae731822 | 1784 | .mfr_id = CFI_MFR_ST, |
deb1a5f1 NC |
1785 | .dev_id = M50FLW080B, |
1786 | .name = "ST M50FLW080B", | |
1787 | .devtypes = CFI_DEVICETYPE_X8, | |
1788 | .uaddr = MTD_UADDR_UNNECESSARY, | |
1789 | .dev_size = SIZE_1MiB, | |
1790 | .cmd_set = P_ID_INTEL_EXT, | |
1791 | .nr_regions = 4, | |
1792 | .regions = { | |
1793 | ERASEINFO(0x1000,16), | |
1794 | ERASEINFO(0x1000,16), | |
1795 | ERASEINFO(0x10000,13), | |
1796 | ERASEINFO(0x1000,16), | |
1da177e4 | 1797 | } |
e1070211 | 1798 | }, { |
ae731822 | 1799 | .mfr_id = 0xff00 | CFI_MFR_ST, |
e1070211 MF |
1800 | .dev_id = 0xff00 | PSD4256G6V, |
1801 | .name = "ST PSD4256G6V", | |
1802 | .devtypes = CFI_DEVICETYPE_X16, | |
1803 | .uaddr = MTD_UADDR_0x0AAA_0x0554, | |
1804 | .dev_size = SIZE_1MiB, | |
1805 | .cmd_set = P_ID_AMD_STD, | |
1806 | .nr_regions = 1, | |
1807 | .regions = { | |
1808 | ERASEINFO(0x10000,16), | |
1809 | } | |
1da177e4 | 1810 | }, { |
ae731822 | 1811 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1812 | .dev_id = TC58FVT160, |
1813 | .name = "Toshiba TC58FVT160", | |
5d3cce3b DW |
1814 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1815 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1816 | .dev_size = SIZE_2MiB, |
1817 | .cmd_set = P_ID_AMD_STD, | |
1818 | .nr_regions = 4, | |
1da177e4 LT |
1819 | .regions = { |
1820 | ERASEINFO(0x10000,31), | |
1821 | ERASEINFO(0x08000,1), | |
1822 | ERASEINFO(0x02000,2), | |
1823 | ERASEINFO(0x04000,1) | |
1824 | } | |
1825 | }, { | |
ae731822 | 1826 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1827 | .dev_id = TC58FVB160, |
1828 | .name = "Toshiba TC58FVB160", | |
5d3cce3b DW |
1829 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1830 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1831 | .dev_size = SIZE_2MiB, |
1832 | .cmd_set = P_ID_AMD_STD, | |
1833 | .nr_regions = 4, | |
1da177e4 LT |
1834 | .regions = { |
1835 | ERASEINFO(0x04000,1), | |
1836 | ERASEINFO(0x02000,2), | |
1837 | ERASEINFO(0x08000,1), | |
1838 | ERASEINFO(0x10000,31) | |
1839 | } | |
1840 | }, { | |
ae731822 | 1841 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1842 | .dev_id = TC58FVB321, |
1843 | .name = "Toshiba TC58FVB321", | |
5d3cce3b DW |
1844 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1845 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1846 | .dev_size = SIZE_4MiB, |
1847 | .cmd_set = P_ID_AMD_STD, | |
1848 | .nr_regions = 2, | |
1da177e4 LT |
1849 | .regions = { |
1850 | ERASEINFO(0x02000,8), | |
1851 | ERASEINFO(0x10000,63) | |
1852 | } | |
1853 | }, { | |
ae731822 | 1854 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1855 | .dev_id = TC58FVT321, |
1856 | .name = "Toshiba TC58FVT321", | |
5d3cce3b DW |
1857 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1858 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1859 | .dev_size = SIZE_4MiB, |
1860 | .cmd_set = P_ID_AMD_STD, | |
1861 | .nr_regions = 2, | |
1da177e4 LT |
1862 | .regions = { |
1863 | ERASEINFO(0x10000,63), | |
1864 | ERASEINFO(0x02000,8) | |
1865 | } | |
1866 | }, { | |
ae731822 | 1867 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1868 | .dev_id = TC58FVB641, |
1869 | .name = "Toshiba TC58FVB641", | |
5d3cce3b DW |
1870 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1871 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1872 | .dev_size = SIZE_8MiB, |
1873 | .cmd_set = P_ID_AMD_STD, | |
1874 | .nr_regions = 2, | |
1da177e4 LT |
1875 | .regions = { |
1876 | ERASEINFO(0x02000,8), | |
1877 | ERASEINFO(0x10000,127) | |
1878 | } | |
1879 | }, { | |
ae731822 | 1880 | .mfr_id = CFI_MFR_TOSHIBA, |
1da177e4 LT |
1881 | .dev_id = TC58FVT641, |
1882 | .name = "Toshiba TC58FVT641", | |
5d3cce3b DW |
1883 | .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, |
1884 | .uaddr = MTD_UADDR_0x0AAA_0x0555, | |
5d3cce3b DW |
1885 | .dev_size = SIZE_8MiB, |
1886 | .cmd_set = P_ID_AMD_STD, | |
1887 | .nr_regions = 2, | |
1da177e4 LT |
1888 | .regions = { |
1889 | ERASEINFO(0x10000,127), | |
1890 | ERASEINFO(0x02000,8) | |
1891 | } | |
1892 | }, { | |
ae731822 | 1893 | .mfr_id = CFI_MFR_WINBOND, |
1da177e4 LT |
1894 | .dev_id = W49V002A, |
1895 | .name = "Winbond W49V002A", | |
5d3cce3b DW |
1896 | .devtypes = CFI_DEVICETYPE_X8, |
1897 | .uaddr = MTD_UADDR_0x5555_0x2AAA, | |
1898 | .dev_size = SIZE_256KiB, | |
1899 | .cmd_set = P_ID_AMD_STD, | |
1900 | .nr_regions = 4, | |
1da177e4 LT |
1901 | .regions = { |
1902 | ERASEINFO(0x10000, 3), | |
1903 | ERASEINFO(0x08000, 1), | |
1904 | ERASEINFO(0x02000, 2), | |
1905 | ERASEINFO(0x04000, 1), | |
1906 | } | |
1907 | } | |
1908 | }; | |
1909 | ||
5d3cce3b | 1910 | static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, |
1da177e4 LT |
1911 | struct cfi_private *cfi) |
1912 | { | |
1913 | map_word result; | |
1914 | unsigned long mask; | |
5c9c11e1 MR |
1915 | int bank = 0; |
1916 | ||
1917 | /* According to JEDEC "Standard Manufacturer's Identification Code" | |
1918 | * (http://www.jedec.org/download/search/jep106W.pdf) | |
1919 | * several first banks can contain 0x7f instead of actual ID | |
1920 | */ | |
1921 | do { | |
467622ef | 1922 | uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi); |
5c9c11e1 | 1923 | mask = (1 << (cfi->device_type * 8)) - 1; |
87a73eb5 LW |
1924 | if (ofs >= map->size) |
1925 | return 0; | |
5c9c11e1 MR |
1926 | result = map_read(map, base + ofs); |
1927 | bank++; | |
ae731822 | 1928 | } while ((result.x[0] & mask) == CFI_MFR_CONTINUATION); |
5c9c11e1 | 1929 | |
1da177e4 LT |
1930 | return result.x[0] & mask; |
1931 | } | |
1932 | ||
5d3cce3b | 1933 | static inline u32 jedec_read_id(struct map_info *map, uint32_t base, |
1da177e4 LT |
1934 | struct cfi_private *cfi) |
1935 | { | |
1936 | map_word result; | |
1937 | unsigned long mask; | |
467622ef | 1938 | u32 ofs = cfi_build_cmd_addr(1, map, cfi); |
1da177e4 LT |
1939 | mask = (1 << (cfi->device_type * 8)) -1; |
1940 | result = map_read(map, base + ofs); | |
1941 | return result.x[0] & mask; | |
1942 | } | |
1943 | ||
53d88553 | 1944 | static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) |
1da177e4 LT |
1945 | { |
1946 | /* Reset */ | |
1947 | ||
1948 | /* after checking the datasheets for SST, MACRONIX and ATMEL | |
1949 | * (oh and incidentaly the jedec spec - 3.5.3.3) the reset | |
1950 | * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at | |
1951 | * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips | |
7854d3f7 | 1952 | * as they will ignore the writes and don't care what address |
1da177e4 | 1953 | * the F0 is written to */ |
cec80bf2 | 1954 | if (cfi->addr_unlock1) { |
289c0522 | 1955 | pr_debug( "reset unlock called %x %x \n", |
1da177e4 LT |
1956 | cfi->addr_unlock1,cfi->addr_unlock2); |
1957 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
1958 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
1959 | } | |
1960 | ||
1961 | cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
cec80bf2 | 1962 | /* Some misdesigned Intel chips do not respond for 0xF0 for a reset, |
1da177e4 LT |
1963 | * so ensure we're in read mode. Send both the Intel and the AMD command |
1964 | * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so | |
1965 | * this should be safe. | |
1f948b43 | 1966 | */ |
1da177e4 LT |
1967 | cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); |
1968 | /* FIXME - should have reset delay before continuing */ | |
1969 | } | |
1970 | ||
1971 | ||
ceabebb2 | 1972 | static int cfi_jedec_setup(struct map_info *map, struct cfi_private *cfi, int index) |
1da177e4 LT |
1973 | { |
1974 | int i,num_erase_regions; | |
5d3cce3b DW |
1975 | uint8_t uaddr; |
1976 | ||
efba2e31 | 1977 | if (!(jedec_table[index].devtypes & cfi->device_type)) { |
289c0522 | 1978 | pr_debug("Rejecting potential %s with incompatible %d-bit device type\n", |
efba2e31 | 1979 | jedec_table[index].name, 4 * (1<<cfi->device_type)); |
5d3cce3b DW |
1980 | return 0; |
1981 | } | |
1da177e4 | 1982 | |
5d3cce3b | 1983 | printk(KERN_INFO "Found: %s\n",jedec_table[index].name); |
1da177e4 | 1984 | |
5d3cce3b | 1985 | num_erase_regions = jedec_table[index].nr_regions; |
1f948b43 | 1986 | |
efba2e31 AP |
1987 | cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); |
1988 | if (!cfi->cfiq) { | |
1da177e4 LT |
1989 | //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); |
1990 | return 0; | |
1991 | } | |
1992 | ||
efba2e31 | 1993 | memset(cfi->cfiq, 0, sizeof(struct cfi_ident)); |
1da177e4 | 1994 | |
efba2e31 AP |
1995 | cfi->cfiq->P_ID = jedec_table[index].cmd_set; |
1996 | cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions; | |
1997 | cfi->cfiq->DevSize = jedec_table[index].dev_size; | |
1998 | cfi->cfi_mode = CFI_MODE_JEDEC; | |
ceabebb2 | 1999 | cfi->sector_erase_cmd = CMD(0x30); |
1da177e4 LT |
2000 | |
2001 | for (i=0; i<num_erase_regions; i++){ | |
efba2e31 | 2002 | cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i]; |
1da177e4 | 2003 | } |
efba2e31 | 2004 | cfi->cmdset_priv = NULL; |
1da177e4 LT |
2005 | |
2006 | /* This may be redundant for some cases, but it doesn't hurt */ | |
efba2e31 AP |
2007 | cfi->mfr = jedec_table[index].mfr_id; |
2008 | cfi->id = jedec_table[index].dev_id; | |
1da177e4 | 2009 | |
5d3cce3b | 2010 | uaddr = jedec_table[index].uaddr; |
1da177e4 | 2011 | |
cec80bf2 DW |
2012 | /* The table has unlock addresses in _bytes_, and we try not to let |
2013 | our brains explode when we see the datasheets talking about address | |
2014 | lines numbered from A-1 to A18. The CFI table has unlock addresses | |
2015 | in device-words according to the mode the device is connected in */ | |
efba2e31 AP |
2016 | cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / cfi->device_type; |
2017 | cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / cfi->device_type; | |
1da177e4 | 2018 | |
7d84b627 | 2019 | return 1; /* ok */ |
1da177e4 LT |
2020 | } |
2021 | ||
2022 | ||
2023 | /* | |
f33686b5 | 2024 | * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing |
1da177e4 LT |
2025 | * the mapped address, unlock addresses, and proper chip ID. This function |
2026 | * attempts to minimize errors. It is doubtfull that this probe will ever | |
2027 | * be perfect - consequently there should be some module parameters that | |
2028 | * could be manually specified to force the chip info. | |
2029 | */ | |
5d3cce3b | 2030 | static inline int jedec_match( uint32_t base, |
1da177e4 LT |
2031 | struct map_info *map, |
2032 | struct cfi_private *cfi, | |
2033 | const struct amd_flash_info *finfo ) | |
2034 | { | |
2035 | int rc = 0; /* failure until all tests pass */ | |
2036 | u32 mfr, id; | |
5d3cce3b | 2037 | uint8_t uaddr; |
1da177e4 LT |
2038 | |
2039 | /* | |
2040 | * The IDs must match. For X16 and X32 devices operating in | |
2041 | * a lower width ( X8 or X16 ), the device ID's are usually just | |
2042 | * the lower byte(s) of the larger device ID for wider mode. If | |
2043 | * a part is found that doesn't fit this assumption (device id for | |
2044 | * smaller width mode is completely unrealated to full-width mode) | |
2045 | * then the jedec_table[] will have to be augmented with the IDs | |
2046 | * for different widths. | |
2047 | */ | |
2048 | switch (cfi->device_type) { | |
2049 | case CFI_DEVICETYPE_X8: | |
5d3cce3b DW |
2050 | mfr = (uint8_t)finfo->mfr_id; |
2051 | id = (uint8_t)finfo->dev_id; | |
011b2a36 BD |
2052 | |
2053 | /* bjd: it seems that if we do this, we can end up | |
2054 | * detecting 16bit flashes as an 8bit device, even though | |
2055 | * there aren't. | |
2056 | */ | |
2057 | if (finfo->dev_id > 0xff) { | |
289c0522 | 2058 | pr_debug("%s(): ID is not 8bit\n", |
011b2a36 BD |
2059 | __func__); |
2060 | goto match_done; | |
2061 | } | |
1da177e4 LT |
2062 | break; |
2063 | case CFI_DEVICETYPE_X16: | |
5d3cce3b DW |
2064 | mfr = (uint16_t)finfo->mfr_id; |
2065 | id = (uint16_t)finfo->dev_id; | |
1da177e4 LT |
2066 | break; |
2067 | case CFI_DEVICETYPE_X32: | |
5d3cce3b DW |
2068 | mfr = (uint16_t)finfo->mfr_id; |
2069 | id = (uint32_t)finfo->dev_id; | |
1da177e4 LT |
2070 | break; |
2071 | default: | |
2072 | printk(KERN_WARNING | |
2073 | "MTD %s(): Unsupported device type %d\n", | |
2074 | __func__, cfi->device_type); | |
2075 | goto match_done; | |
2076 | } | |
2077 | if ( cfi->mfr != mfr || cfi->id != id ) { | |
2078 | goto match_done; | |
2079 | } | |
2080 | ||
2081 | /* the part size must fit in the memory window */ | |
289c0522 | 2082 | pr_debug("MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", |
5d3cce3b DW |
2083 | __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); |
2084 | if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { | |
289c0522 | 2085 | pr_debug("MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", |
1da177e4 | 2086 | __func__, finfo->mfr_id, finfo->dev_id, |
5d3cce3b | 2087 | 1 << finfo->dev_size ); |
1da177e4 LT |
2088 | goto match_done; |
2089 | } | |
2090 | ||
5d3cce3b | 2091 | if (! (finfo->devtypes & cfi->device_type)) |
1da177e4 | 2092 | goto match_done; |
5d3cce3b DW |
2093 | |
2094 | uaddr = finfo->uaddr; | |
1da177e4 | 2095 | |
289c0522 | 2096 | pr_debug("MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", |
1da177e4 LT |
2097 | __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); |
2098 | if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr | |
cec80bf2 DW |
2099 | && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 || |
2100 | unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) { | |
289c0522 | 2101 | pr_debug("MTD %s(): 0x%.4x 0x%.4x did not match\n", |
1da177e4 LT |
2102 | __func__, |
2103 | unlock_addrs[uaddr].addr1, | |
2104 | unlock_addrs[uaddr].addr2); | |
2105 | goto match_done; | |
2106 | } | |
2107 | ||
2108 | /* | |
25985edc | 2109 | * Make sure the ID's disappear when the device is taken out of |
1da177e4 LT |
2110 | * ID mode. The only time this should fail when it should succeed |
2111 | * is when the ID's are written as data to the same | |
2112 | * addresses. For this rare and unfortunate case the chip | |
2113 | * cannot be probed correctly. | |
2114 | * FIXME - write a driver that takes all of the chip info as | |
2115 | * module parameters, doesn't probe but forces a load. | |
2116 | */ | |
289c0522 | 2117 | pr_debug("MTD %s(): check ID's disappear when not in ID mode\n", |
1da177e4 LT |
2118 | __func__ ); |
2119 | jedec_reset( base, map, cfi ); | |
2120 | mfr = jedec_read_mfr( map, base, cfi ); | |
2121 | id = jedec_read_id( map, base, cfi ); | |
2122 | if ( mfr == cfi->mfr && id == cfi->id ) { | |
289c0522 | 2123 | pr_debug("MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n" |
1da177e4 LT |
2124 | "You might need to manually specify JEDEC parameters.\n", |
2125 | __func__, cfi->mfr, cfi->id ); | |
2126 | goto match_done; | |
2127 | } | |
2128 | ||
2129 | /* all tests passed - mark as success */ | |
2130 | rc = 1; | |
2131 | ||
2132 | /* | |
2133 | * Put the device back in ID mode - only need to do this if we | |
2134 | * were truly frobbing a real device. | |
2135 | */ | |
289c0522 | 2136 | pr_debug("MTD %s(): return to ID mode\n", __func__ ); |
cec80bf2 | 2137 | if (cfi->addr_unlock1) { |
1da177e4 LT |
2138 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); |
2139 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
2140 | } | |
2141 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
2142 | /* FIXME - should have a delay before continuing */ | |
2143 | ||
1f948b43 | 2144 | match_done: |
1da177e4 LT |
2145 | return rc; |
2146 | } | |
2147 | ||
2148 | ||
2149 | static int jedec_probe_chip(struct map_info *map, __u32 base, | |
2150 | unsigned long *chip_map, struct cfi_private *cfi) | |
2151 | { | |
2152 | int i; | |
2153 | enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED; | |
2154 | u32 probe_offset1, probe_offset2; | |
2155 | ||
2156 | retry: | |
2157 | if (!cfi->numchips) { | |
2158 | uaddr_idx++; | |
2159 | ||
2160 | if (MTD_UADDR_UNNECESSARY == uaddr_idx) | |
2161 | return 0; | |
2162 | ||
cec80bf2 DW |
2163 | cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type; |
2164 | cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type; | |
1da177e4 LT |
2165 | } |
2166 | ||
2167 | /* Make certain we aren't probing past the end of map */ | |
2168 | if (base >= map->size) { | |
2169 | printk(KERN_NOTICE | |
2170 | "Probe at base(0x%08x) past the end of the map(0x%08lx)\n", | |
2171 | base, map->size -1); | |
2172 | return 0; | |
1f948b43 | 2173 | |
1da177e4 LT |
2174 | } |
2175 | /* Ensure the unlock addresses we try stay inside the map */ | |
467622ef EB |
2176 | probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi); |
2177 | probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi); | |
1da177e4 LT |
2178 | if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || |
2179 | ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) | |
1da177e4 | 2180 | goto retry; |
1f948b43 | 2181 | |
1da177e4 LT |
2182 | /* Reset */ |
2183 | jedec_reset(base, map, cfi); | |
2184 | ||
2185 | /* Autoselect Mode */ | |
2186 | if(cfi->addr_unlock1) { | |
2187 | cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
2188 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); | |
2189 | } | |
2190 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); | |
2191 | /* FIXME - should have a delay before continuing */ | |
2192 | ||
2193 | if (!cfi->numchips) { | |
1f948b43 | 2194 | /* This is the first time we're called. Set up the CFI |
1da177e4 | 2195 | stuff accordingly and return */ |
1f948b43 | 2196 | |
1da177e4 LT |
2197 | cfi->mfr = jedec_read_mfr(map, base, cfi); |
2198 | cfi->id = jedec_read_id(map, base, cfi); | |
289c0522 | 2199 | pr_debug("Search for id:(%02x %02x) interleave(%d) type(%d)\n", |
1da177e4 | 2200 | cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type); |
87d10f3c | 2201 | for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { |
1da177e4 | 2202 | if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { |
289c0522 | 2203 | pr_debug("MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n", |
1da177e4 LT |
2204 | __func__, cfi->mfr, cfi->id, |
2205 | cfi->addr_unlock1, cfi->addr_unlock2 ); | |
ceabebb2 | 2206 | if (!cfi_jedec_setup(map, cfi, i)) |
1da177e4 LT |
2207 | return 0; |
2208 | goto ok_out; | |
2209 | } | |
2210 | } | |
2211 | goto retry; | |
2212 | } else { | |
5d3cce3b DW |
2213 | uint16_t mfr; |
2214 | uint16_t id; | |
1da177e4 LT |
2215 | |
2216 | /* Make sure it is a chip of the same manufacturer and id */ | |
2217 | mfr = jedec_read_mfr(map, base, cfi); | |
2218 | id = jedec_read_id(map, base, cfi); | |
2219 | ||
2220 | if ((mfr != cfi->mfr) || (id != cfi->id)) { | |
2221 | printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n", | |
2222 | map->name, mfr, id, base); | |
2223 | jedec_reset(base, map, cfi); | |
2224 | return 0; | |
2225 | } | |
2226 | } | |
1f948b43 | 2227 | |
1da177e4 LT |
2228 | /* Check each previous chip locations to see if it's an alias */ |
2229 | for (i=0; i < (base >> cfi->chipshift); i++) { | |
2230 | unsigned long start; | |
2231 | if(!test_bit(i, chip_map)) { | |
2232 | continue; /* Skip location; no valid chip at this address */ | |
2233 | } | |
2234 | start = i << cfi->chipshift; | |
2235 | if (jedec_read_mfr(map, start, cfi) == cfi->mfr && | |
2236 | jedec_read_id(map, start, cfi) == cfi->id) { | |
2237 | /* Eep. This chip also looks like it's in autoselect mode. | |
2238 | Is it an alias for the new one? */ | |
2239 | jedec_reset(start, map, cfi); | |
2240 | ||
2241 | /* If the device IDs go away, it's an alias */ | |
2242 | if (jedec_read_mfr(map, base, cfi) != cfi->mfr || | |
2243 | jedec_read_id(map, base, cfi) != cfi->id) { | |
2244 | printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", | |
2245 | map->name, base, start); | |
2246 | return 0; | |
2247 | } | |
1f948b43 | 2248 | |
1da177e4 LT |
2249 | /* Yes, it's actually got the device IDs as data. Most |
2250 | * unfortunate. Stick the new chip in read mode | |
2251 | * too and if it's the same, assume it's an alias. */ | |
2252 | /* FIXME: Use other modes to do a proper check */ | |
2253 | jedec_reset(base, map, cfi); | |
2254 | if (jedec_read_mfr(map, base, cfi) == cfi->mfr && | |
2255 | jedec_read_id(map, base, cfi) == cfi->id) { | |
2256 | printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", | |
2257 | map->name, base, start); | |
2258 | return 0; | |
2259 | } | |
2260 | } | |
2261 | } | |
1f948b43 | 2262 | |
1da177e4 LT |
2263 | /* OK, if we got to here, then none of the previous chips appear to |
2264 | be aliases for the current one. */ | |
2265 | set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ | |
2266 | cfi->numchips++; | |
1f948b43 | 2267 | |
1da177e4 LT |
2268 | ok_out: |
2269 | /* Put it back into Read Mode */ | |
2270 | jedec_reset(base, map, cfi); | |
2271 | ||
2272 | printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", | |
1f948b43 | 2273 | map->name, cfi_interleave(cfi), cfi->device_type*8, base, |
1da177e4 | 2274 | map->bankwidth*8); |
1f948b43 | 2275 | |
1da177e4 LT |
2276 | return 1; |
2277 | } | |
2278 | ||
2279 | static struct chip_probe jedec_chip_probe = { | |
2280 | .name = "JEDEC", | |
2281 | .probe_chip = jedec_probe_chip | |
2282 | }; | |
2283 | ||
2284 | static struct mtd_info *jedec_probe(struct map_info *map) | |
2285 | { | |
2286 | /* | |
2287 | * Just use the generic probe stuff to call our CFI-specific | |
2288 | * chip_probe routine in all the possible permutations, etc. | |
2289 | */ | |
2290 | return mtd_do_chip_probe(map, &jedec_chip_probe); | |
2291 | } | |
2292 | ||
2293 | static struct mtd_chip_driver jedec_chipdrv = { | |
2294 | .probe = jedec_probe, | |
2295 | .name = "jedec_probe", | |
2296 | .module = THIS_MODULE | |
2297 | }; | |
2298 | ||
2299 | static int __init jedec_probe_init(void) | |
2300 | { | |
2301 | register_mtd_chip_driver(&jedec_chipdrv); | |
2302 | return 0; | |
2303 | } | |
2304 | ||
2305 | static void __exit jedec_probe_exit(void) | |
2306 | { | |
2307 | unregister_mtd_chip_driver(&jedec_chipdrv); | |
2308 | } | |
2309 | ||
2310 | module_init(jedec_probe_init); | |
2311 | module_exit(jedec_probe_exit); | |
2312 | ||
2313 | MODULE_LICENSE("GPL"); | |
2314 | MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al."); | |
2315 | MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips"); |