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nand: Embed mtd_info in struct nand_chip
[thirdparty/u-boot.git] / drivers / mtd / nand / atmel_nand.c
CommitLineData
1079432e
SL		 1/*
2 * (C) Copyright 2007-2008
c9e798d3 3 * Stelian Pop <stelian@popies.net>
1079432e
SL		 4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
7 *
bdfd59aa
WJ		 8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
10 *
1a459660 11 * SPDX-License-Identifier: GPL-2.0+
1079432e
SL		 12 */
13
14#include <common.h>
ac45bb16 15#include <asm/gpio.h>
1079432e 16#include <asm/arch/gpio.h>
1079432e 17
ddd85974 18#include <malloc.h>
1079432e 19#include <nand.h>
bdfd59aa 20#include <watchdog.h>
c1ec4062 21#include <linux/mtd/nand_ecc.h>
1079432e 22
7c27b7b1
NP		 23#ifdef CONFIG_ATMEL_NAND_HWECC
24
25/* Register access macros */
26#define ecc_readl(add, reg) \
27 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
28#define ecc_writel(add, reg, value) \
29 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
30
31#include "atmel_nand_ecc.h" /* Hardware ECC registers */
32
bdfd59aa
WJ		 33#ifdef CONFIG_ATMEL_NAND_HW_PMECC
34
0b0b4f59
BS		 35#ifdef CONFIG_SPL_BUILD
36#undef CONFIG_SYS_NAND_ONFI_DETECTION
37#endif
38
bdfd59aa
WJ		 39struct atmel_nand_host {
40 struct pmecc_regs __iomem *pmecc;
41 struct pmecc_errloc_regs __iomem *pmerrloc;
42 void __iomem *pmecc_rom_base;
43
44 u8 pmecc_corr_cap;
45 u16 pmecc_sector_size;
46 u32 pmecc_index_table_offset;
0e48dc5e 47 u32 pmecc_version;
bdfd59aa
WJ		 48
49 int pmecc_bytes_per_sector;
50 int pmecc_sector_number;
51 int pmecc_degree; /* Degree of remainders */
52 int pmecc_cw_len; /* Length of codeword */
53
54 /* lookup table for alpha_to and index_of */
55 void __iomem *pmecc_alpha_to;
56 void __iomem *pmecc_index_of;
57
58 /* data for pmecc computation */
ddd85974
WJ		 59 int16_t *pmecc_smu;
60 int16_t *pmecc_partial_syn;
61 int16_t *pmecc_si;
62 int16_t *pmecc_lmu; /* polynomal order */
63 int *pmecc_mu;
64 int *pmecc_dmu;
65 int *pmecc_delta;
bdfd59aa
WJ		 66};
67
68static struct atmel_nand_host pmecc_host;
69static struct nand_ecclayout atmel_pmecc_oobinfo;
70
71/*
72 * Return number of ecc bytes per sector according to sector size and
73 * correction capability
74 *
75 * Following table shows what at91 PMECC supported:
76 * Correction Capability Sector_512_bytes Sector_1024_bytes
77 * ===================== ================ =================
78 * 2-bits 4-bytes 4-bytes
79 * 4-bits 7-bytes 7-bytes
80 * 8-bits 13-bytes 14-bytes
81 * 12-bits 20-bytes 21-bytes
82 * 24-bits 39-bytes 42-bytes
258b21fc 83 * 32-bits 52-bytes 56-bytes
bdfd59aa
WJ		 84 */
85static int pmecc_get_ecc_bytes(int cap, int sector_size)
86{
87 int m = 12 + sector_size / 512;
88 return (m * cap + 7) / 8;
89}
90
91static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
92 int oobsize, int ecc_len)
93{
94 int i;
95
96 layout->eccbytes = ecc_len;
97
98 /* ECC will occupy the last ecc_len bytes continuously */
99 for (i = 0; i < ecc_len; i++)
100 layout->eccpos[i] = oobsize - ecc_len + i;
101
102 layout->oobfree[0].offset = 2;
103 layout->oobfree[0].length =
104 oobsize - ecc_len - layout->oobfree[0].offset;
105}
106
107static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
108{
109 int table_size;
110
111 table_size = host->pmecc_sector_size == 512 ?
112 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
113
114 /* the ALPHA lookup table is right behind the INDEX lookup table. */
115 return host->pmecc_rom_base + host->pmecc_index_table_offset +
116 table_size * sizeof(int16_t);
117}
118
ddd85974
WJ		 119static void pmecc_data_free(struct atmel_nand_host *host)
120{
121 free(host->pmecc_partial_syn);
122 free(host->pmecc_si);
123 free(host->pmecc_lmu);
124 free(host->pmecc_smu);
125 free(host->pmecc_mu);
126 free(host->pmecc_dmu);
127 free(host->pmecc_delta);
128}
129
130static int pmecc_data_alloc(struct atmel_nand_host *host)
131{
132 const int cap = host->pmecc_corr_cap;
133 int size;
134
135 size = (2 * cap + 1) * sizeof(int16_t);
136 host->pmecc_partial_syn = malloc(size);
137 host->pmecc_si = malloc(size);
138 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
139 host->pmecc_smu = malloc((cap + 2) * size);
140
141 size = (cap + 1) * sizeof(int);
142 host->pmecc_mu = malloc(size);
143 host->pmecc_dmu = malloc(size);
144 host->pmecc_delta = malloc(size);
145
146 if (host->pmecc_partial_syn &&
147 host->pmecc_si &&
148 host->pmecc_lmu &&
149 host->pmecc_smu &&
150 host->pmecc_mu &&
151 host->pmecc_dmu &&
152 host->pmecc_delta)
153 return 0;
154
155 /* error happened */
156 pmecc_data_free(host);
157 return -ENOMEM;
158
159}
160
bdfd59aa
WJ		 161static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
162{
163 struct nand_chip *nand_chip = mtd->priv;
164 struct atmel_nand_host *host = nand_chip->priv;
165 int i;
166 uint32_t value;
167
168 /* Fill odd syndromes */
169 for (i = 0; i < host->pmecc_corr_cap; i++) {
14b3b44e 170 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
bdfd59aa
WJ		 171 if (i & 1)
172 value >>= 16;
173 value &= 0xffff;
174 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
175 }
176}
177
178static void pmecc_substitute(struct mtd_info *mtd)
179{
180 struct nand_chip *nand_chip = mtd->priv;
181 struct atmel_nand_host *host = nand_chip->priv;
182 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
183 int16_t __iomem *index_of = host->pmecc_index_of;
184 int16_t *partial_syn = host->pmecc_partial_syn;
185 const int cap = host->pmecc_corr_cap;
186 int16_t *si;
187 int i, j;
188
189 /* si[] is a table that holds the current syndrome value,
190 * an element of that table belongs to the field
191 */
192 si = host->pmecc_si;
193
194 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
195
196 /* Computation 2t syndromes based on S(x) */
197 /* Odd syndromes */
198 for (i = 1; i < 2 * cap; i += 2) {
199 for (j = 0; j < host->pmecc_degree; j++) {
200 if (partial_syn[i] & (0x1 << j))
201 si[i] = readw(alpha_to + i * j) ^ si[i];
202 }
203 }
204 /* Even syndrome = (Odd syndrome) ** 2 */
205 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
206 if (si[j] == 0) {
207 si[i] = 0;
208 } else {
209 int16_t tmp;
210
211 tmp = readw(index_of + si[j]);
212 tmp = (tmp * 2) % host->pmecc_cw_len;
213 si[i] = readw(alpha_to + tmp);
214 }
215 }
216}
217
218/*
219 * This function defines a Berlekamp iterative procedure for
220 * finding the value of the error location polynomial.
221 * The input is si[], initialize by pmecc_substitute().
222 * The output is smu[][].
223 *
224 * This function is written according to chip datasheet Chapter:
225 * Find the Error Location Polynomial Sigma(x) of Section:
226 * Programmable Multibit ECC Control (PMECC).
227 */
228static void pmecc_get_sigma(struct mtd_info *mtd)
229{
230 struct nand_chip *nand_chip = mtd->priv;
231 struct atmel_nand_host *host = nand_chip->priv;
232
233 int16_t *lmu = host->pmecc_lmu;
234 int16_t *si = host->pmecc_si;
235 int *mu = host->pmecc_mu;
236 int *dmu = host->pmecc_dmu; /* Discrepancy */
237 int *delta = host->pmecc_delta; /* Delta order */
238 int cw_len = host->pmecc_cw_len;
239 const int16_t cap = host->pmecc_corr_cap;
240 const int num = 2 * cap + 1;
241 int16_t __iomem *index_of = host->pmecc_index_of;
242 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
243 int i, j, k;
244 uint32_t dmu_0_count, tmp;
245 int16_t *smu = host->pmecc_smu;
246
247 /* index of largest delta */
248 int ro;
249 int largest;
250 int diff;
251
252 /* Init the Sigma(x) */
253 memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
254
255 dmu_0_count = 0;
256
257 /* First Row */
258
259 /* Mu */
260 mu[0] = -1;
261
262 smu[0] = 1;
263
264 /* discrepancy set to 1 */
265 dmu[0] = 1;
266 /* polynom order set to 0 */
267 lmu[0] = 0;
268 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
269 delta[0] = -1;
270
271 /* Second Row */
272
273 /* Mu */
274 mu[1] = 0;
275 /* Sigma(x) set to 1 */
276 smu[num] = 1;
277
278 /* discrepancy set to S1 */
279 dmu[1] = si[1];
280
281 /* polynom order set to 0 */
282 lmu[1] = 0;
283
284 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
285 delta[1] = 0;
286
287 for (i = 1; i <= cap; i++) {
288 mu[i + 1] = i << 1;
289 /* Begin Computing Sigma (Mu+1) and L(mu) */
290 /* check if discrepancy is set to 0 */
291 if (dmu[i] == 0) {
292 dmu_0_count++;
293
294 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
295 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
296 tmp += 2;
297 else
298 tmp += 1;
299
300 if (dmu_0_count == tmp) {
301 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
302 smu[(cap + 1) * num + j] =
303 smu[i * num + j];
304
305 lmu[cap + 1] = lmu[i];
306 return;
307 }
308
309 /* copy polynom */
310 for (j = 0; j <= lmu[i] >> 1; j++)
311 smu[(i + 1) * num + j] = smu[i * num + j];
312
313 /* copy previous polynom order to the next */
314 lmu[i + 1] = lmu[i];
315 } else {
316 ro = 0;
317 largest = -1;
318 /* find largest delta with dmu != 0 */
319 for (j = 0; j < i; j++) {
320 if ((dmu[j]) && (delta[j] > largest)) {
321 largest = delta[j];
322 ro = j;
323 }
324 }
325
326 /* compute difference */
327 diff = (mu[i] - mu[ro]);
328
329 /* Compute degree of the new smu polynomial */
330 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
331 lmu[i + 1] = lmu[i];
332 else
333 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
334
335 /* Init smu[i+1] with 0 */
336 for (k = 0; k < num; k++)
337 smu[(i + 1) * num + k] = 0;
338
339 /* Compute smu[i+1] */
340 for (k = 0; k <= lmu[ro] >> 1; k++) {
341 int16_t a, b, c;
342
343 if (!(smu[ro * num + k] && dmu[i]))
344 continue;
345 a = readw(index_of + dmu[i]);
346 b = readw(index_of + dmu[ro]);
347 c = readw(index_of + smu[ro * num + k]);
348 tmp = a + (cw_len - b) + c;
349 a = readw(alpha_to + tmp % cw_len);
350 smu[(i + 1) * num + (k + diff)] = a;
351 }
352
353 for (k = 0; k <= lmu[i] >> 1; k++)
354 smu[(i + 1) * num + k] ^= smu[i * num + k];
355 }
356
357 /* End Computing Sigma (Mu+1) and L(mu) */
358 /* In either case compute delta */
359 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
360
361 /* Do not compute discrepancy for the last iteration */
362 if (i >= cap)
363 continue;
364
365 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
366 tmp = 2 * (i - 1);
367 if (k == 0) {
368 dmu[i + 1] = si[tmp + 3];
369 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
370 int16_t a, b, c;
371 a = readw(index_of +
372 smu[(i + 1) * num + k]);
373 b = si[2 * (i - 1) + 3 - k];
374 c = readw(index_of + b);
375 tmp = a + c;
376 tmp %= cw_len;
377 dmu[i + 1] = readw(alpha_to + tmp) ^
378 dmu[i + 1];
379 }
380 }
381 }
382}
383
384static int pmecc_err_location(struct mtd_info *mtd)
385{
386 struct nand_chip *nand_chip = mtd->priv;
387 struct atmel_nand_host *host = nand_chip->priv;
388 const int cap = host->pmecc_corr_cap;
389 const int num = 2 * cap + 1;
390 int sector_size = host->pmecc_sector_size;
391 int err_nbr = 0; /* number of error */
392 int roots_nbr; /* number of roots */
393 int i;
394 uint32_t val;
395 int16_t *smu = host->pmecc_smu;
396 int timeout = PMECC_MAX_TIMEOUT_US;
397
14b3b44e 398 pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
bdfd59aa
WJ		 399
400 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
14b3b44e
WJ		 401 pmecc_writel(host->pmerrloc, sigma[i],
402 smu[(cap + 1) * num + i]);
bdfd59aa
WJ		 403 err_nbr++;
404 }
405
406 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
407 if (sector_size == 1024)
408 val |= PMERRLOC_ELCFG_SECTOR_1024;
409
14b3b44e
WJ		 410 pmecc_writel(host->pmerrloc, elcfg, val);
411 pmecc_writel(host->pmerrloc, elen,
412 sector_size * 8 + host->pmecc_degree * cap);
bdfd59aa
WJ		 413
414 while (--timeout) {
14b3b44e 415 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
bdfd59aa
WJ		 416 break;
417 WATCHDOG_RESET();
418 udelay(1);
419 }
420
421 if (!timeout) {
c0dc3dec 422 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
bdfd59aa
WJ		 423 return -1;
424 }
425
14b3b44e 426 roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
bdfd59aa
WJ		 427 >> 8;
428 /* Number of roots == degree of smu hence <= cap */
429 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
430 return err_nbr - 1;
431
432 /* Number of roots does not match the degree of smu
433 * unable to correct error */
434 return -1;
435}
436
437static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
438 int sector_num, int extra_bytes, int err_nbr)
439{
440 struct nand_chip *nand_chip = mtd->priv;
441 struct atmel_nand_host *host = nand_chip->priv;
442 int i = 0;
443 int byte_pos, bit_pos, sector_size, pos;
444 uint32_t tmp;
445 uint8_t err_byte;
446
447 sector_size = host->pmecc_sector_size;
448
449 while (err_nbr) {
14b3b44e 450 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
bdfd59aa
WJ		 451 byte_pos = tmp / 8;
452 bit_pos = tmp % 8;
453
454 if (byte_pos >= (sector_size + extra_bytes))
455 BUG(); /* should never happen */
456
457 if (byte_pos < sector_size) {
458 err_byte = *(buf + byte_pos);
459 *(buf + byte_pos) ^= (1 << bit_pos);
460
461 pos = sector_num * host->pmecc_sector_size + byte_pos;
c55cc573 462 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
bdfd59aa
WJ		 463 pos, bit_pos, err_byte, *(buf + byte_pos));
464 } else {
465 /* Bit flip in OOB area */
466 tmp = sector_num * host->pmecc_bytes_per_sector
467 + (byte_pos - sector_size);
468 err_byte = ecc[tmp];
469 ecc[tmp] ^= (1 << bit_pos);
470
471 pos = tmp + nand_chip->ecc.layout->eccpos[0];
c55cc573 472 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
bdfd59aa
WJ		 473 pos, bit_pos, err_byte, ecc[tmp]);
474 }
475
476 i++;
477 err_nbr--;
478 }
479
480 return;
481}
482
483static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
484 u8 *ecc)
485{
486 struct nand_chip *nand_chip = mtd->priv;
487 struct atmel_nand_host *host = nand_chip->priv;
488 int i, err_nbr, eccbytes;
489 uint8_t *buf_pos;
490
0e48dc5e
WJ		 491 /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
492 if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
493 goto normal_check;
494
bdfd59aa
WJ		 495 eccbytes = nand_chip->ecc.bytes;
496 for (i = 0; i < eccbytes; i++)
497 if (ecc[i] != 0xff)
498 goto normal_check;
499 /* Erased page, return OK */
500 return 0;
501
502normal_check:
503 for (i = 0; i < host->pmecc_sector_number; i++) {
504 err_nbr = 0;
505 if (pmecc_stat & 0x1) {
506 buf_pos = buf + i * host->pmecc_sector_size;
507
508 pmecc_gen_syndrome(mtd, i);
509 pmecc_substitute(mtd);
510 pmecc_get_sigma(mtd);
511
512 err_nbr = pmecc_err_location(mtd);
513 if (err_nbr == -1) {
c0dc3dec 514 dev_err(host->dev, "PMECC: Too many errors\n");
bdfd59aa
WJ		 515 mtd->ecc_stats.failed++;
516 return -EIO;
517 } else {
518 pmecc_correct_data(mtd, buf_pos, ecc, i,
519 host->pmecc_bytes_per_sector, err_nbr);
520 mtd->ecc_stats.corrected += err_nbr;
521 }
522 }
523 pmecc_stat >>= 1;
524 }
525
526 return 0;
527}
528
529static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
dfe64e2c 530 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
bdfd59aa
WJ		 531{
532 struct atmel_nand_host *host = chip->priv;
533 int eccsize = chip->ecc.size;
534 uint8_t *oob = chip->oob_poi;
535 uint32_t *eccpos = chip->ecc.layout->eccpos;
536 uint32_t stat;
537 int timeout = PMECC_MAX_TIMEOUT_US;
538
539 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
540 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
541 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
542 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
543
544 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
545 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
546
547 chip->read_buf(mtd, buf, eccsize);
548 chip->read_buf(mtd, oob, mtd->oobsize);
549
550 while (--timeout) {
551 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
552 break;
553 WATCHDOG_RESET();
554 udelay(1);
555 }
556
557 if (!timeout) {
c0dc3dec 558 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
bdfd59aa
WJ		 559 return -1;
560 }
561
562 stat = pmecc_readl(host->pmecc, isr);
563 if (stat != 0)
564 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
565 return -EIO;
566
567 return 0;
568}
569
dfe64e2c
SL		 570static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
571 struct nand_chip *chip, const uint8_t *buf,
572 int oob_required)
bdfd59aa
WJ		 573{
574 struct atmel_nand_host *host = chip->priv;
575 uint32_t *eccpos = chip->ecc.layout->eccpos;
576 int i, j;
577 int timeout = PMECC_MAX_TIMEOUT_US;
578
579 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
580 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
581
582 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
583 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
584
585 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
586 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
587
588 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
589
590 while (--timeout) {
591 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
592 break;
593 WATCHDOG_RESET();
594 udelay(1);
595 }
596
597 if (!timeout) {
c0dc3dec 598 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
dfe64e2c 599 goto out;
bdfd59aa
WJ		 600 }
601
602 for (i = 0; i < host->pmecc_sector_number; i++) {
603 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
604 int pos;
605
606 pos = i * host->pmecc_bytes_per_sector + j;
607 chip->oob_poi[eccpos[pos]] =
14b3b44e 608 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
bdfd59aa
WJ		 609 }
610 }
611 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
dfe64e2c
SL		 612out:
613 return 0;
bdfd59aa
WJ		 614}
615
616static void atmel_pmecc_core_init(struct mtd_info *mtd)
617{
618 struct nand_chip *nand_chip = mtd->priv;
619 struct atmel_nand_host *host = nand_chip->priv;
620 uint32_t val = 0;
621 struct nand_ecclayout *ecc_layout;
622
623 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
624 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
625
626 switch (host->pmecc_corr_cap) {
627 case 2:
628 val = PMECC_CFG_BCH_ERR2;
629 break;
630 case 4:
631 val = PMECC_CFG_BCH_ERR4;
632 break;
633 case 8:
634 val = PMECC_CFG_BCH_ERR8;
635 break;
636 case 12:
637 val = PMECC_CFG_BCH_ERR12;
638 break;
639 case 24:
640 val = PMECC_CFG_BCH_ERR24;
641 break;
258b21fc
JW		 642 case 32:
643 val = PMECC_CFG_BCH_ERR32;
644 break;
bdfd59aa
WJ		 645 }
646
647 if (host->pmecc_sector_size == 512)
648 val |= PMECC_CFG_SECTOR512;
649 else if (host->pmecc_sector_size == 1024)
650 val |= PMECC_CFG_SECTOR1024;
651
652 switch (host->pmecc_sector_number) {
653 case 1:
654 val |= PMECC_CFG_PAGE_1SECTOR;
655 break;
656 case 2:
657 val |= PMECC_CFG_PAGE_2SECTORS;
658 break;
659 case 4:
660 val |= PMECC_CFG_PAGE_4SECTORS;
661 break;
662 case 8:
663 val |= PMECC_CFG_PAGE_8SECTORS;
664 break;
665 }
666
667 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
668 | PMECC_CFG_AUTO_DISABLE);
669 pmecc_writel(host->pmecc, cfg, val);
670
671 ecc_layout = nand_chip->ecc.layout;
672 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
673 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
674 pmecc_writel(host->pmecc, eaddr,
675 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
676 /* See datasheet about PMECC Clock Control Register */
677 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
678 pmecc_writel(host->pmecc, idr, 0xff);
679 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
680}
681
a07d2294 682#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
a07d2294
WJ		 683/*
684 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
685 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
686 * ONFI ECC parameters.
687 * @host: point to an atmel_nand_host structure.
688 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
689 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
690 * @chip: point to an nand_chip structure.
691 * @cap: store the ONFI ECC correct bits capbility
692 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
693 *
694 * Return 0 if success. otherwise return the error code.
695 */
696static int pmecc_choose_ecc(struct atmel_nand_host *host,
697 struct nand_chip *chip,
698 int *cap, int *sector_size)
699{
700 /* Get ECC requirement from ONFI parameters */
701 *cap = *sector_size = 0;
702 if (chip->onfi_version) {
3a205671
JW		 703 *cap = chip->ecc_strength_ds;
704 *sector_size = chip->ecc_step_ds;
705 MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
706 *cap, *sector_size);
a07d2294 707 }
3a205671 708
a07d2294 709 if (*cap == 0 && *sector_size == 0) {
3a205671
JW		 710 /* Non-ONFI compliant */
711 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
a07d2294
WJ		 712 *cap = 2;
713 *sector_size = 512;
714 }
715
716 /* If head file doesn't specify then use the one in ONFI parameters */
717 if (host->pmecc_corr_cap == 0) {
718 /* use the most fitable ecc bits (the near bigger one ) */
719 if (*cap <= 2)
720 host->pmecc_corr_cap = 2;
721 else if (*cap <= 4)
722 host->pmecc_corr_cap = 4;
723 else if (*cap <= 8)
724 host->pmecc_corr_cap = 8;
725 else if (*cap <= 12)
726 host->pmecc_corr_cap = 12;
727 else if (*cap <= 24)
728 host->pmecc_corr_cap = 24;
729 else
258b21fc
JW		 730#ifdef CONFIG_SAMA5D2
731 host->pmecc_corr_cap = 32;
732#else
733 host->pmecc_corr_cap = 24;
734#endif
a07d2294
WJ		 735 }
736 if (host->pmecc_sector_size == 0) {
737 /* use the most fitable sector size (the near smaller one ) */
738 if (*sector_size >= 1024)
739 host->pmecc_sector_size = 1024;
740 else if (*sector_size >= 512)
741 host->pmecc_sector_size = 512;
742 else
743 return -EINVAL;
744 }
745 return 0;
746}
747#endif
748
7df4486d
JW		 749#if defined(NO_GALOIS_TABLE_IN_ROM)
750static uint16_t *pmecc_galois_table;
751static inline int deg(unsigned int poly)
752{
753 /* polynomial degree is the most-significant bit index */
754 return fls(poly) - 1;
755}
756
757static int build_gf_tables(int mm, unsigned int poly,
758 int16_t *index_of, int16_t *alpha_to)
759{
760 unsigned int i, x = 1;
761 const unsigned int k = 1 << deg(poly);
762 unsigned int nn = (1 << mm) - 1;
763
764 /* primitive polynomial must be of degree m */
765 if (k != (1u << mm))
766 return -EINVAL;
767
768 for (i = 0; i < nn; i++) {
769 alpha_to[i] = x;
770 index_of[x] = i;
771 if (i && (x == 1))
772 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
773 return -EINVAL;
774 x <<= 1;
775 if (x & k)
776 x ^= poly;
777 }
778
779 alpha_to[nn] = 1;
780 index_of[0] = 0;
781
782 return 0;
783}
784
785static uint16_t *create_lookup_table(int sector_size)
786{
787 int degree = (sector_size == 512) ?
788 PMECC_GF_DIMENSION_13 :
789 PMECC_GF_DIMENSION_14;
790 unsigned int poly = (sector_size == 512) ?
791 PMECC_GF_13_PRIMITIVE_POLY :
792 PMECC_GF_14_PRIMITIVE_POLY;
793 int table_size = (sector_size == 512) ?
794 PMECC_INDEX_TABLE_SIZE_512 :
795 PMECC_INDEX_TABLE_SIZE_1024;
796
797 int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
798 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
799 return NULL;
800
801 return (uint16_t *)addr;
802}
803#endif
804
bdfd59aa
WJ		 805static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
806 struct mtd_info *mtd)
807{
808 struct atmel_nand_host *host;
809 int cap, sector_size;
810
811 host = nand->priv = &pmecc_host;
812
813 nand->ecc.mode = NAND_ECC_HW;
814 nand->ecc.calculate = NULL;
815 nand->ecc.correct = NULL;
816 nand->ecc.hwctl = NULL;
817
a07d2294
WJ		 818#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
819 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
820
821#ifdef CONFIG_PMECC_CAP
822 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
823#endif
824#ifdef CONFIG_PMECC_SECTOR_SIZE
825 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
826#endif
827 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
828 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
829 * from ONFI.
830 */
831 if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
4c6a6ea3
JW		 832 dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
833 cap, sector_size);
a07d2294
WJ		 834 return -EINVAL;
835 }
836
837 if (cap > host->pmecc_corr_cap)
838 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
839 host->pmecc_corr_cap, cap);
840 if (sector_size < host->pmecc_sector_size)
841 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
842 host->pmecc_sector_size, sector_size);
843#else /* CONFIG_SYS_NAND_ONFI_DETECTION */
844 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
845 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
846#endif
847
848 cap = host->pmecc_corr_cap;
849 sector_size = host->pmecc_sector_size;
850
851 /* TODO: need check whether cap & sector_size is validate */
7df4486d
JW		 852#if defined(NO_GALOIS_TABLE_IN_ROM)
853 /*
854 * As pmecc_rom_base is the begin of the gallois field table, So the
855 * index offset just set as 0.
856 */
857 host->pmecc_index_table_offset = 0;
858#else
b2d96dc2
WJ		 859 if (host->pmecc_sector_size == 512)
860 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
861 else
862 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
7df4486d 863#endif
bdfd59aa 864
b9c83c68
WJ		 865 MTDDEBUG(MTD_DEBUG_LEVEL1,
866 "Initialize PMECC params, cap: %d, sector: %d\n",
867 cap, sector_size);
bdfd59aa
WJ		 868
869 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
870 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
871 ATMEL_BASE_PMERRLOC;
7df4486d
JW		 872#if defined(NO_GALOIS_TABLE_IN_ROM)
873 pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
874 if (!pmecc_galois_table) {
875 dev_err(host->dev, "out of memory\n");
876 return -ENOMEM;
877 }
878
879 host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
880#else
bdfd59aa 881 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
7df4486d 882#endif
bdfd59aa
WJ		 883
884 /* ECC is calculated for the whole page (1 step) */
885 nand->ecc.size = mtd->writesize;
886
887 /* set ECC page size and oob layout */
888 switch (mtd->writesize) {
889 case 2048:
890 case 4096:
16dddef6 891 case 8192:
1bd3e2a8
WJ		 892 host->pmecc_degree = (sector_size == 512) ?
893 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
bdfd59aa
WJ		 894 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
895 host->pmecc_sector_number = mtd->writesize / sector_size;
896 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
897 cap, sector_size);
898 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
899 host->pmecc_index_of = host->pmecc_rom_base +
900 host->pmecc_index_table_offset;
901
902 nand->ecc.steps = 1;
903 nand->ecc.bytes = host->pmecc_bytes_per_sector *
904 host->pmecc_sector_number;
16dddef6
WJ		 905
906 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
907 dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
908 MTD_MAX_ECCPOS_ENTRIES_LARGE);
909 return -EINVAL;
910 }
911
422b49e2 912 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
c0dc3dec 913 dev_err(host->dev, "No room for ECC bytes\n");
bdfd59aa
WJ		 914 return -EINVAL;
915 }
916 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
917 mtd->oobsize,
918 nand->ecc.bytes);
919 nand->ecc.layout = &atmel_pmecc_oobinfo;
920 break;
921 case 512:
922 case 1024:
923 /* TODO */
c0dc3dec 924 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
bdfd59aa
WJ		 925 default:
926 /* page size not handled by HW ECC */
927 /* switching back to soft ECC */
928 nand->ecc.mode = NAND_ECC_SOFT;
929 nand->ecc.read_page = NULL;
930 nand->ecc.postpad = 0;
931 nand->ecc.prepad = 0;
932 nand->ecc.bytes = 0;
933 return 0;
934 }
935
ddd85974
WJ		 936 /* Allocate data for PMECC computation */
937 if (pmecc_data_alloc(host)) {
938 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
939 return -ENOMEM;
940 }
941
d357b940 942 nand->options |= NAND_NO_SUBPAGE_WRITE;
bdfd59aa
WJ		 943 nand->ecc.read_page = atmel_nand_pmecc_read_page;
944 nand->ecc.write_page = atmel_nand_pmecc_write_page;
dfe64e2c 945 nand->ecc.strength = cap;
bdfd59aa 946
0e48dc5e
WJ		 947 /* Check the PMECC ip version */
948 host->pmecc_version = pmecc_readl(host->pmerrloc, version);
949 dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
950
bdfd59aa
WJ		 951 atmel_pmecc_core_init(mtd);
952
953 return 0;
954}
955
956#else
957
7c27b7b1
NP		 958/* oob layout for large page size
959 * bad block info is on bytes 0 and 1
960 * the bytes have to be consecutives to avoid
961 * several NAND_CMD_RNDOUT during read
962 */
963static struct nand_ecclayout atmel_oobinfo_large = {
964 .eccbytes = 4,
965 .eccpos = {60, 61, 62, 63},
966 .oobfree = {
967 {2, 58}
968 },
969};
970
971/* oob layout for small page size
972 * bad block info is on bytes 4 and 5
973 * the bytes have to be consecutives to avoid
974 * several NAND_CMD_RNDOUT during read
975 */
976static struct nand_ecclayout atmel_oobinfo_small = {
977 .eccbytes = 4,
978 .eccpos = {0, 1, 2, 3},
979 .oobfree = {
980 {6, 10}
981 },
982};
983
984/*
985 * Calculate HW ECC
986 *
987 * function called after a write
988 *
989 * mtd: MTD block structure
990 * dat: raw data (unused)
991 * ecc_code: buffer for ECC
992 */
993static int atmel_nand_calculate(struct mtd_info *mtd,
994 const u_char *dat, unsigned char *ecc_code)
995{
7c27b7b1
NP		 996 unsigned int ecc_value;
997
998 /* get the first 2 ECC bytes */
999 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1000
1001 ecc_code[0] = ecc_value & 0xFF;
1002 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1003
1004 /* get the last 2 ECC bytes */
1005 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1006
1007 ecc_code[2] = ecc_value & 0xFF;
1008 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1009
1010 return 0;
1011}
1012
1013/*
1014 * HW ECC read page function
1015 *
1016 * mtd: mtd info structure
1017 * chip: nand chip info structure
1018 * buf: buffer to store read data
dfe64e2c 1019 * oob_required: caller expects OOB data read to chip->oob_poi
7c27b7b1 1020 */
dfe64e2c
SL		 1021static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1022 uint8_t *buf, int oob_required, int page)
7c27b7b1
NP		 1023{
1024 int eccsize = chip->ecc.size;
1025 int eccbytes = chip->ecc.bytes;
1026 uint32_t *eccpos = chip->ecc.layout->eccpos;
1027 uint8_t *p = buf;
1028 uint8_t *oob = chip->oob_poi;
1029 uint8_t *ecc_pos;
1030 int stat;
1031
1032 /* read the page */
1033 chip->read_buf(mtd, p, eccsize);
1034
1035 /* move to ECC position if needed */
1036 if (eccpos[0] != 0) {
1037 /* This only works on large pages
1038 * because the ECC controller waits for
1039 * NAND_CMD_RNDOUTSTART after the
1040 * NAND_CMD_RNDOUT.
1041 * anyway, for small pages, the eccpos[0] == 0
1042 */
1043 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1044 mtd->writesize + eccpos[0], -1);
1045 }
1046
1047 /* the ECC controller needs to read the ECC just after the data */
1048 ecc_pos = oob + eccpos[0];
1049 chip->read_buf(mtd, ecc_pos, eccbytes);
1050
1051 /* check if there's an error */
1052 stat = chip->ecc.correct(mtd, p, oob, NULL);
1053
1054 if (stat < 0)
1055 mtd->ecc_stats.failed++;
1056 else
1057 mtd->ecc_stats.corrected += stat;
1058
1059 /* get back to oob start (end of page) */
1060 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1061
1062 /* read the oob */
1063 chip->read_buf(mtd, oob, mtd->oobsize);
1064
1065 return 0;
1066}
1067
1068/*
1069 * HW ECC Correction
1070 *
1071 * function called after a read
1072 *
1073 * mtd: MTD block structure
1074 * dat: raw data read from the chip
1075 * read_ecc: ECC from the chip (unused)
1076 * isnull: unused
1077 *
1078 * Detect and correct a 1 bit error for a page
1079 */
1080static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1081 u_char *read_ecc, u_char *isnull)
1082{
1083 struct nand_chip *nand_chip = mtd->priv;
ae79794e 1084 unsigned int ecc_status;
7c27b7b1
NP		 1085 unsigned int ecc_word, ecc_bit;
1086
1087 /* get the status from the Status Register */
1088 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1089
1090 /* if there's no error */
1091 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1092 return 0;
1093
1094 /* get error bit offset (4 bits) */
1095 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1096 /* get word address (12 bits) */
1097 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1098 ecc_word >>= 4;
1099
1100 /* if there are multiple errors */
1101 if (ecc_status & ATMEL_ECC_MULERR) {
1102 /* check if it is a freshly erased block
1103 * (filled with 0xff) */
1104 if ((ecc_bit == ATMEL_ECC_BITADDR)
1105 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1106 /* the block has just been erased, return OK */
1107 return 0;
1108 }
1109 /* it doesn't seems to be a freshly
1110 * erased block.
1111 * We can't correct so many errors */
c0dc3dec 1112 dev_warn(host->dev, "atmel_nand : multiple errors detected."
7c27b7b1
NP		 1113 " Unable to correct.\n");
1114 return -EIO;
1115 }
1116
1117 /* if there's a single bit error : we can correct it */
1118 if (ecc_status & ATMEL_ECC_ECCERR) {
1119 /* there's nothing much to do here.
1120 * the bit error is on the ECC itself.
1121 */
c0dc3dec 1122 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
7c27b7b1
NP		 1123 " Nothing to correct\n");
1124 return 0;
1125 }
1126
c0dc3dec 1127 dev_warn(host->dev, "atmel_nand : one bit error on data."
7c27b7b1
NP		 1128 " (word offset in the page :"
1129 " 0x%x bit offset : 0x%x)\n",
1130 ecc_word, ecc_bit);
1131 /* correct the error */
1132 if (nand_chip->options & NAND_BUSWIDTH_16) {
1133 /* 16 bits words */
1134 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1135 } else {
1136 /* 8 bits words */
1137 dat[ecc_word] ^= (1 << ecc_bit);
1138 }
c0dc3dec 1139 dev_warn(host->dev, "atmel_nand : error corrected\n");
7c27b7b1
NP		 1140 return 1;
1141}
1142
1143/*
1144 * Enable HW ECC : unused on most chips
1145 */
1146static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1147{
1148}
fe2185ea
WJ		 1149
1150int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1151{
1152 nand->ecc.mode = NAND_ECC_HW;
1153 nand->ecc.calculate = atmel_nand_calculate;
1154 nand->ecc.correct = atmel_nand_correct;
1155 nand->ecc.hwctl = atmel_nand_hwctl;
1156 nand->ecc.read_page = atmel_nand_read_page;
1157 nand->ecc.bytes = 4;
1158
1159 if (nand->ecc.mode == NAND_ECC_HW) {
1160 /* ECC is calculated for the whole page (1 step) */
1161 nand->ecc.size = mtd->writesize;
1162
1163 /* set ECC page size and oob layout */
1164 switch (mtd->writesize) {
1165 case 512:
1166 nand->ecc.layout = &atmel_oobinfo_small;
1167 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1168 ATMEL_ECC_PAGESIZE_528);
1169 break;
1170 case 1024:
1171 nand->ecc.layout = &atmel_oobinfo_large;
1172 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1173 ATMEL_ECC_PAGESIZE_1056);
1174 break;
1175 case 2048:
1176 nand->ecc.layout = &atmel_oobinfo_large;
1177 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1178 ATMEL_ECC_PAGESIZE_2112);
1179 break;
1180 case 4096:
1181 nand->ecc.layout = &atmel_oobinfo_large;
1182 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1183 ATMEL_ECC_PAGESIZE_4224);
1184 break;
1185 default:
1186 /* page size not handled by HW ECC */
1187 /* switching back to soft ECC */
1188 nand->ecc.mode = NAND_ECC_SOFT;
1189 nand->ecc.calculate = NULL;
1190 nand->ecc.correct = NULL;
1191 nand->ecc.hwctl = NULL;
1192 nand->ecc.read_page = NULL;
1193 nand->ecc.postpad = 0;
1194 nand->ecc.prepad = 0;
1195 nand->ecc.bytes = 0;
1196 break;
1197 }
1198 }
1199
1200 return 0;
1201}
1202
bdfd59aa
WJ		 1203#endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1204
1205#endif /* CONFIG_ATMEL_NAND_HWECC */
7c27b7b1 1206
74c076d6 1207static void at91_nand_hwcontrol(struct mtd_info *mtd,
1079432e
SL		 1208 int cmd, unsigned int ctrl)
1209{
1210 struct nand_chip *this = mtd->priv;
1211
1212 if (ctrl & NAND_CTRL_CHANGE) {
1213 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
74c076d6
JCPV		 1214 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1215 | CONFIG_SYS_NAND_MASK_CLE);
1079432e
SL		 1216
1217 if (ctrl & NAND_CLE)
74c076d6 1218 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1079432e 1219 if (ctrl & NAND_ALE)
74c076d6 1220 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1079432e 1221
67a490d6 1222#ifdef CONFIG_SYS_NAND_ENABLE_PIN
ac45bb16 1223 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
67a490d6 1224#endif
1079432e
SL		 1225 this->IO_ADDR_W = (void *) IO_ADDR_W;
1226 }
1227
1228 if (cmd != NAND_CMD_NONE)
1229 writeb(cmd, this->IO_ADDR_W);
1230}
1231
74c076d6
JCPV		 1232#ifdef CONFIG_SYS_NAND_READY_PIN
1233static int at91_nand_ready(struct mtd_info *mtd)
1079432e 1234{
ac45bb16 1235 return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1079432e 1236}
74c076d6 1237#endif
1079432e 1238
0b0b4f59
BS		 1239#ifdef CONFIG_SPL_BUILD
1240/* The following code is for SPL */
b616d9b0 1241static struct mtd_info *mtd;
0b0b4f59
BS		 1242static struct nand_chip nand_chip;
1243
1244static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1245{
b616d9b0 1246 struct nand_chip *this = mtd->priv;
0b0b4f59
BS		 1247 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1248 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1249 unsigned int ctrl) = this->cmd_ctrl;
1250
b616d9b0 1251 while (!this->dev_ready(mtd))
0b0b4f59
BS		 1252 ;
1253
1254 if (cmd == NAND_CMD_READOOB) {
1255 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1256 cmd = NAND_CMD_READ0;
1257 }
1258
b616d9b0 1259 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
0b0b4f59 1260
27ce9e42 1261 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
0b0b4f59
BS		 1262 offs >>= 1;
1263
b616d9b0
SW		 1264 hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1265 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1266 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1267 hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
0b0b4f59 1268#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
b616d9b0 1269 hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
0b0b4f59 1270#endif
b616d9b0 1271 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
0b0b4f59 1272
b616d9b0
SW		 1273 hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1274 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
0b0b4f59 1275
b616d9b0 1276 while (!this->dev_ready(mtd))
0b0b4f59
BS		 1277 ;
1278
1279 return 0;
1280}
1281
1282static int nand_is_bad_block(int block)
1283{
b616d9b0 1284 struct nand_chip *this = mtd->priv;
0b0b4f59
BS		 1285
1286 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1287
1288 if (this->options & NAND_BUSWIDTH_16) {
1289 if (readw(this->IO_ADDR_R) != 0xffff)
1290 return 1;
1291 } else {
1292 if (readb(this->IO_ADDR_R) != 0xff)
1293 return 1;
1294 }
1295
1296 return 0;
1297}
1298
1299#ifdef CONFIG_SPL_NAND_ECC
1300static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1301#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1302 CONFIG_SYS_NAND_ECCSIZE)
1303#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1304
1305static int nand_read_page(int block, int page, void *dst)
1306{
b616d9b0 1307 struct nand_chip *this = mtd->priv;
0b0b4f59
BS		 1308 u_char ecc_calc[ECCTOTAL];
1309 u_char ecc_code[ECCTOTAL];
1310 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1311 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1312 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1313 int eccsteps = ECCSTEPS;
1314 int i;
1315 uint8_t *p = dst;
1316 nand_command(block, page, 0, NAND_CMD_READ0);
1317
1318 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1319 if (this->ecc.mode != NAND_ECC_SOFT)
b616d9b0
SW		 1320 this->ecc.hwctl(mtd, NAND_ECC_READ);
1321 this->read_buf(mtd, p, eccsize);
1322 this->ecc.calculate(mtd, p, &ecc_calc[i]);
0b0b4f59 1323 }
b616d9b0 1324 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
0b0b4f59
BS		 1325
1326 for (i = 0; i < ECCTOTAL; i++)
1327 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1328
1329 eccsteps = ECCSTEPS;
1330 p = dst;
1331
1332 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
b616d9b0 1333 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
0b0b4f59
BS		 1334
1335 return 0;
1336}
4dfd3605
HS		 1337
1338int spl_nand_erase_one(int block, int page)
1339{
b616d9b0 1340 struct nand_chip *this = mtd->priv;
4dfd3605
HS		 1341 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1342 unsigned int ctrl) = this->cmd_ctrl;
1343 int page_addr;
1344
1345 if (nand_chip.select_chip)
b616d9b0 1346 nand_chip.select_chip(mtd, 0);
4dfd3605
HS		 1347
1348 page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
b616d9b0 1349 hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
4dfd3605 1350 /* Row address */
b616d9b0
SW		 1351 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1352 hwctrl(mtd, ((page_addr >> 8) & 0xff),
4dfd3605
HS		 1353 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1354#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1355 /* One more address cycle for devices > 128MiB */
b616d9b0 1356 hwctrl(mtd, (page_addr >> 16) & 0x0f,
4dfd3605
HS		 1357 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1358#endif
b616d9b0 1359 hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
4dfd3605 1360
b616d9b0 1361 while (!this->dev_ready(mtd))
4dfd3605
HS		 1362 ;
1363
1364 nand_deselect();
1365
1366 return 0;
1367}
0b0b4f59
BS		 1368#else
1369static int nand_read_page(int block, int page, void *dst)
1370{
b616d9b0 1371 struct nand_chip *this = mtd->priv;
0b0b4f59
BS		 1372
1373 nand_command(block, page, 0, NAND_CMD_READ0);
b616d9b0 1374 atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
0b0b4f59
BS		 1375
1376 return 0;
1377}
1378#endif /* CONFIG_SPL_NAND_ECC */
1379
1380int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
1381{
1382 unsigned int block, lastblock;
1383 unsigned int page;
1384
1385 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
1386 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
1387 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
1388
1389 while (block <= lastblock) {
1390 if (!nand_is_bad_block(block)) {
1391 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
1392 nand_read_page(block, page, dst);
1393 dst += CONFIG_SYS_NAND_PAGE_SIZE;
1394 page++;
1395 }
1396
1397 page = 0;
1398 } else {
1399 lastblock++;
1400 }
1401
1402 block++;
1403 }
1404
1405 return 0;
1406}
1407
1408int at91_nand_wait_ready(struct mtd_info *mtd)
1409{
1410 struct nand_chip *this = mtd->priv;
1411
1412 udelay(this->chip_delay);
1413
667af369 1414 return 1;
0b0b4f59
BS		 1415}
1416
1417int board_nand_init(struct nand_chip *nand)
1418{
1419 int ret = 0;
1420
1421 nand->ecc.mode = NAND_ECC_SOFT;
1422#ifdef CONFIG_SYS_NAND_DBW_16
1423 nand->options = NAND_BUSWIDTH_16;
1424 nand->read_buf = nand_read_buf16;
1425#else
1426 nand->read_buf = nand_read_buf;
1427#endif
1428 nand->cmd_ctrl = at91_nand_hwcontrol;
1429#ifdef CONFIG_SYS_NAND_READY_PIN
1430 nand->dev_ready = at91_nand_ready;
1431#else
1432 nand->dev_ready = at91_nand_wait_ready;
1433#endif
1434 nand->chip_delay = 20;
da78fb54
DD		 1435#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1436 nand->bbt_options |= NAND_BBT_USE_FLASH;
1437#endif
0b0b4f59
BS		 1438
1439#ifdef CONFIG_ATMEL_NAND_HWECC
1440#ifdef CONFIG_ATMEL_NAND_HW_PMECC
b616d9b0 1441 ret = atmel_pmecc_nand_init_params(nand, mtd);
0b0b4f59
BS		 1442#endif
1443#endif
1444
1445 return ret;
1446}
1447
1448void nand_init(void)
1449{
b616d9b0
SW		 1450 mtd = &nand_chip.mtd;
1451 mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1452 mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1453 mtd->priv = &nand_chip;
0b0b4f59
BS		 1454 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1455 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1456 board_nand_init(&nand_chip);
1457
1458#ifdef CONFIG_SPL_NAND_ECC
1459 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1460 nand_chip.ecc.calculate = nand_calculate_ecc;
1461 nand_chip.ecc.correct = nand_correct_data;
1462 }
1463#endif
1464
1465 if (nand_chip.select_chip)
b616d9b0 1466 nand_chip.select_chip(mtd, 0);
0b0b4f59
BS		 1467}
1468
1469void nand_deselect(void)
1470{
1471 if (nand_chip.select_chip)
b616d9b0 1472 nand_chip.select_chip(mtd, -1);
0b0b4f59
BS		 1473}
1474
1475#else
1476
fe2185ea
WJ		 1477#ifndef CONFIG_SYS_NAND_BASE_LIST
1478#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
7c27b7b1 1479#endif
fe2185ea
WJ		 1480static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1481static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1482
1483int atmel_nand_chip_init(int devnum, ulong base_addr)
1484{
1485 int ret;
fe2185ea 1486 struct nand_chip *nand = &nand_chip[devnum];
b616d9b0 1487 struct mtd_info *mtd = &nand->mtd;
fe2185ea
WJ		 1488
1489 mtd->priv = nand;
1490 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
7c27b7b1 1491
7604a3f9
BS		 1492#ifdef CONFIG_NAND_ECC_BCH
1493 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1494#else
1079432e 1495 nand->ecc.mode = NAND_ECC_SOFT;
7604a3f9 1496#endif
1079432e
SL		 1497#ifdef CONFIG_SYS_NAND_DBW_16
1498 nand->options = NAND_BUSWIDTH_16;
1499#endif
74c076d6
JCPV		 1500 nand->cmd_ctrl = at91_nand_hwcontrol;
1501#ifdef CONFIG_SYS_NAND_READY_PIN
1502 nand->dev_ready = at91_nand_ready;
1503#endif
16dddef6 1504 nand->chip_delay = 75;
da78fb54
DD		 1505#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1506 nand->bbt_options |= NAND_BBT_USE_FLASH;
1507#endif
1079432e 1508
fe2185ea
WJ		 1509 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1510 if (ret)
1511 return ret;
7c27b7b1
NP		 1512
1513#ifdef CONFIG_ATMEL_NAND_HWECC
bdfd59aa
WJ		 1514#ifdef CONFIG_ATMEL_NAND_HW_PMECC
1515 ret = atmel_pmecc_nand_init_params(nand, mtd);
1516#else
fe2185ea 1517 ret = atmel_hwecc_nand_init_param(nand, mtd);
bdfd59aa 1518#endif
fe2185ea
WJ		 1519 if (ret)
1520 return ret;
1521#endif
7c27b7b1 1522
fe2185ea
WJ		 1523 ret = nand_scan_tail(mtd);
1524 if (!ret)
b616d9b0 1525 nand_register(devnum, mtd);
7c27b7b1 1526
fe2185ea
WJ		 1527 return ret;
1528}
7c27b7b1 1529
fe2185ea
WJ		 1530void board_nand_init(void)
1531{
1532 int i;
1533 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1534 if (atmel_nand_chip_init(i, base_addr[i]))
c0dc3dec 1535 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
fe2185ea 1536 i);
1079432e 1537}
0b0b4f59 1538#endif /* CONFIG_SPL_BUILD */
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