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3eb3e72a CLS |
1 | /* |
2 | * Copyright (C) 2014 Panasonic Corporation | |
3 | * Copyright (C) 2013-2014, Altera Corporation <www.altera.com> | |
4 | * Copyright (C) 2009-2010, Intel Corporation and its suppliers. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <malloc.h> | |
11 | #include <nand.h> | |
12 | #include <asm/errno.h> | |
13 | #include <asm/io.h> | |
14 | ||
15 | #include "denali.h" | |
16 | ||
17 | #define NAND_DEFAULT_TIMINGS -1 | |
18 | ||
19 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
20 | ||
d3963721 SW |
21 | /* |
22 | * We define a macro here that combines all interrupts this driver uses into | |
23 | * a single constant value, for convenience. | |
24 | */ | |
3eb3e72a CLS |
25 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
26 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
27 | INTR_STATUS__ECC_ERR | \ | |
28 | INTR_STATUS__PROGRAM_FAIL | \ | |
29 | INTR_STATUS__LOAD_COMP | \ | |
30 | INTR_STATUS__PROGRAM_COMP | \ | |
31 | INTR_STATUS__TIME_OUT | \ | |
32 | INTR_STATUS__ERASE_FAIL | \ | |
33 | INTR_STATUS__RST_COMP | \ | |
34 | INTR_STATUS__ERASE_COMP | \ | |
35 | INTR_STATUS__ECC_UNCOR_ERR | \ | |
36 | INTR_STATUS__INT_ACT | \ | |
37 | INTR_STATUS__LOCKED_BLK) | |
38 | ||
d3963721 SW |
39 | /* |
40 | * indicates whether or not the internal value for the flash bank is | |
41 | * valid or not | |
42 | */ | |
3eb3e72a CLS |
43 | #define CHIP_SELECT_INVALID -1 |
44 | ||
45 | #define SUPPORT_8BITECC 1 | |
46 | ||
47 | /* | |
48 | * this macro allows us to convert from an MTD structure to our own | |
49 | * device context (denali) structure. | |
50 | */ | |
65e4145a | 51 | #define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand) |
3eb3e72a | 52 | |
d3963721 SW |
53 | /* |
54 | * These constants are defined by the driver to enable common driver | |
55 | * configuration options. | |
56 | */ | |
3eb3e72a CLS |
57 | #define SPARE_ACCESS 0x41 |
58 | #define MAIN_ACCESS 0x42 | |
59 | #define MAIN_SPARE_ACCESS 0x43 | |
d3963721 | 60 | #define PIPELINE_ACCESS 0x2000 |
3eb3e72a CLS |
61 | |
62 | #define DENALI_UNLOCK_START 0x10 | |
63 | #define DENALI_UNLOCK_END 0x11 | |
64 | #define DENALI_LOCK 0x21 | |
65 | #define DENALI_LOCK_TIGHT 0x31 | |
66 | #define DENALI_BUFFER_LOAD 0x60 | |
67 | #define DENALI_BUFFER_WRITE 0x62 | |
68 | ||
69 | #define DENALI_READ 0 | |
70 | #define DENALI_WRITE 0x100 | |
71 | ||
72 | /* types of device accesses. We can issue commands and get status */ | |
73 | #define COMMAND_CYCLE 0 | |
74 | #define ADDR_CYCLE 1 | |
75 | #define STATUS_CYCLE 2 | |
76 | ||
d3963721 SW |
77 | /* |
78 | * this is a helper macro that allows us to | |
79 | * format the bank into the proper bits for the controller | |
80 | */ | |
3eb3e72a CLS |
81 | #define BANK(x) ((x) << 24) |
82 | ||
83 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
84 | static inline void clear_interrupt(struct denali_nand_info *denali, | |
85 | uint32_t irq_mask) | |
86 | { | |
87 | uint32_t intr_status_reg; | |
88 | ||
89 | intr_status_reg = INTR_STATUS(denali->flash_bank); | |
90 | ||
91 | writel(irq_mask, denali->flash_reg + intr_status_reg); | |
92 | } | |
93 | ||
94 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
95 | { | |
96 | uint32_t intr_status_reg; | |
97 | ||
98 | intr_status_reg = INTR_STATUS(denali->flash_bank); | |
99 | ||
100 | return readl(denali->flash_reg + intr_status_reg); | |
101 | } | |
102 | ||
103 | static void clear_interrupts(struct denali_nand_info *denali) | |
104 | { | |
105 | uint32_t status; | |
106 | ||
107 | status = read_interrupt_status(denali); | |
108 | clear_interrupt(denali, status); | |
109 | ||
110 | denali->irq_status = 0; | |
111 | } | |
112 | ||
113 | static void denali_irq_enable(struct denali_nand_info *denali, | |
114 | uint32_t int_mask) | |
115 | { | |
116 | int i; | |
117 | ||
118 | for (i = 0; i < denali->max_banks; ++i) | |
119 | writel(int_mask, denali->flash_reg + INTR_EN(i)); | |
120 | } | |
121 | ||
122 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
123 | { | |
124 | unsigned long timeout = 1000000; | |
125 | uint32_t intr_status; | |
126 | ||
127 | do { | |
128 | intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL; | |
129 | if (intr_status & irq_mask) { | |
130 | denali->irq_status &= ~irq_mask; | |
131 | /* our interrupt was detected */ | |
132 | break; | |
133 | } | |
134 | udelay(1); | |
135 | timeout--; | |
136 | } while (timeout != 0); | |
137 | ||
138 | if (timeout == 0) { | |
139 | /* timeout */ | |
140 | printf("Denali timeout with interrupt status %08x\n", | |
141 | read_interrupt_status(denali)); | |
142 | intr_status = 0; | |
143 | } | |
144 | return intr_status; | |
145 | } | |
146 | ||
147 | /* | |
148 | * Certain operations for the denali NAND controller use an indexed mode to | |
149 | * read/write data. The operation is performed by writing the address value | |
150 | * of the command to the device memory followed by the data. This function | |
151 | * abstracts this common operation. | |
d3963721 | 152 | */ |
3eb3e72a CLS |
153 | static void index_addr(struct denali_nand_info *denali, |
154 | uint32_t address, uint32_t data) | |
155 | { | |
156 | writel(address, denali->flash_mem + INDEX_CTRL_REG); | |
157 | writel(data, denali->flash_mem + INDEX_DATA_REG); | |
158 | } | |
159 | ||
160 | /* Perform an indexed read of the device */ | |
161 | static void index_addr_read_data(struct denali_nand_info *denali, | |
162 | uint32_t address, uint32_t *pdata) | |
163 | { | |
164 | writel(address, denali->flash_mem + INDEX_CTRL_REG); | |
165 | *pdata = readl(denali->flash_mem + INDEX_DATA_REG); | |
166 | } | |
167 | ||
d3963721 SW |
168 | /* |
169 | * We need to buffer some data for some of the NAND core routines. | |
170 | * The operations manage buffering that data. | |
171 | */ | |
3eb3e72a CLS |
172 | static void reset_buf(struct denali_nand_info *denali) |
173 | { | |
174 | denali->buf.head = 0; | |
175 | denali->buf.tail = 0; | |
176 | } | |
177 | ||
178 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
179 | { | |
180 | denali->buf.buf[denali->buf.tail++] = byte; | |
181 | } | |
182 | ||
183 | /* resets a specific device connected to the core */ | |
184 | static void reset_bank(struct denali_nand_info *denali) | |
185 | { | |
186 | uint32_t irq_status; | |
d3963721 | 187 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
3eb3e72a CLS |
188 | |
189 | clear_interrupts(denali); | |
190 | ||
191 | writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); | |
192 | ||
193 | irq_status = wait_for_irq(denali, irq_mask); | |
194 | if (irq_status & INTR_STATUS__TIME_OUT) | |
195 | debug("reset bank failed.\n"); | |
196 | } | |
197 | ||
198 | /* Reset the flash controller */ | |
199 | static uint32_t denali_nand_reset(struct denali_nand_info *denali) | |
200 | { | |
d3963721 | 201 | int i; |
3eb3e72a CLS |
202 | |
203 | for (i = 0; i < denali->max_banks; i++) | |
204 | writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, | |
205 | denali->flash_reg + INTR_STATUS(i)); | |
206 | ||
207 | for (i = 0; i < denali->max_banks; i++) { | |
208 | writel(1 << i, denali->flash_reg + DEVICE_RESET); | |
209 | while (!(readl(denali->flash_reg + INTR_STATUS(i)) & | |
210 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) | |
211 | if (readl(denali->flash_reg + INTR_STATUS(i)) & | |
212 | INTR_STATUS__TIME_OUT) | |
213 | debug("NAND Reset operation timed out on bank" | |
214 | " %d\n", i); | |
215 | } | |
216 | ||
217 | for (i = 0; i < denali->max_banks; i++) | |
218 | writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, | |
219 | denali->flash_reg + INTR_STATUS(i)); | |
220 | ||
221 | return 0; | |
222 | } | |
223 | ||
224 | /* | |
225 | * this routine calculates the ONFI timing values for a given mode and | |
226 | * programs the clocking register accordingly. The mode is determined by | |
227 | * the get_onfi_nand_para routine. | |
228 | */ | |
229 | static void nand_onfi_timing_set(struct denali_nand_info *denali, | |
230 | uint16_t mode) | |
231 | { | |
232 | uint32_t trea[6] = {40, 30, 25, 20, 20, 16}; | |
233 | uint32_t trp[6] = {50, 25, 17, 15, 12, 10}; | |
234 | uint32_t treh[6] = {30, 15, 15, 10, 10, 7}; | |
235 | uint32_t trc[6] = {100, 50, 35, 30, 25, 20}; | |
236 | uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
237 | uint32_t trloh[6] = {0, 0, 0, 0, 5, 5}; | |
238 | uint32_t tcea[6] = {100, 45, 30, 25, 25, 25}; | |
239 | uint32_t tadl[6] = {200, 100, 100, 100, 70, 70}; | |
240 | uint32_t trhw[6] = {200, 100, 100, 100, 100, 100}; | |
241 | uint32_t trhz[6] = {200, 100, 100, 100, 100, 100}; | |
242 | uint32_t twhr[6] = {120, 80, 80, 60, 60, 60}; | |
243 | uint32_t tcs[6] = {70, 35, 25, 25, 20, 15}; | |
244 | ||
3eb3e72a CLS |
245 | uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
246 | uint32_t dv_window = 0; | |
247 | uint32_t en_lo, en_hi; | |
248 | uint32_t acc_clks; | |
249 | uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
250 | ||
251 | en_lo = DIV_ROUND_UP(trp[mode], CLK_X); | |
252 | en_hi = DIV_ROUND_UP(treh[mode], CLK_X); | |
253 | if ((en_hi * CLK_X) < (treh[mode] + 2)) | |
254 | en_hi++; | |
255 | ||
256 | if ((en_lo + en_hi) * CLK_X < trc[mode]) | |
257 | en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X), | |
258 | CLK_X); | |
259 | ||
260 | if ((en_lo + en_hi) < CLK_MULTI) | |
261 | en_lo += CLK_MULTI - en_lo - en_hi; | |
262 | ||
263 | while (dv_window < 8) { | |
264 | data_invalid_rhoh = en_lo * CLK_X + trhoh[mode]; | |
265 | ||
266 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode]; | |
267 | ||
d3963721 SW |
268 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
269 | data_invalid_rhoh : data_invalid_rloh; | |
3eb3e72a CLS |
270 | |
271 | dv_window = data_invalid - trea[mode]; | |
272 | ||
273 | if (dv_window < 8) | |
274 | en_lo++; | |
275 | } | |
276 | ||
277 | acc_clks = DIV_ROUND_UP(trea[mode], CLK_X); | |
278 | ||
d3963721 | 279 | while (acc_clks * CLK_X - trea[mode] < 3) |
3eb3e72a CLS |
280 | acc_clks++; |
281 | ||
d3963721 | 282 | if (data_invalid - acc_clks * CLK_X < 2) |
3eb3e72a CLS |
283 | debug("%s, Line %d: Warning!\n", __FILE__, __LINE__); |
284 | ||
285 | addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X); | |
286 | re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X); | |
287 | re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X); | |
288 | we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X); | |
289 | cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X); | |
3eb3e72a CLS |
290 | if (cs_cnt == 0) |
291 | cs_cnt = 1; | |
292 | ||
293 | if (tcea[mode]) { | |
d3963721 | 294 | while (cs_cnt * CLK_X + trea[mode] < tcea[mode]) |
3eb3e72a CLS |
295 | cs_cnt++; |
296 | } | |
297 | ||
298 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
d3963721 SW |
299 | if (readl(denali->flash_reg + MANUFACTURER_ID) == 0 && |
300 | readl(denali->flash_reg + DEVICE_ID) == 0x88) | |
3eb3e72a CLS |
301 | acc_clks = 6; |
302 | ||
303 | writel(acc_clks, denali->flash_reg + ACC_CLKS); | |
304 | writel(re_2_we, denali->flash_reg + RE_2_WE); | |
305 | writel(re_2_re, denali->flash_reg + RE_2_RE); | |
306 | writel(we_2_re, denali->flash_reg + WE_2_RE); | |
307 | writel(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
308 | writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
309 | writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
310 | writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
311 | } | |
312 | ||
313 | /* queries the NAND device to see what ONFI modes it supports. */ | |
314 | static uint32_t get_onfi_nand_para(struct denali_nand_info *denali) | |
315 | { | |
316 | int i; | |
d3963721 | 317 | |
3eb3e72a CLS |
318 | /* |
319 | * we needn't to do a reset here because driver has already | |
320 | * reset all the banks before | |
321 | */ | |
322 | if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) & | |
323 | ONFI_TIMING_MODE__VALUE)) | |
324 | return -EIO; | |
325 | ||
326 | for (i = 5; i > 0; i--) { | |
327 | if (readl(denali->flash_reg + ONFI_TIMING_MODE) & | |
328 | (0x01 << i)) | |
329 | break; | |
330 | } | |
331 | ||
332 | nand_onfi_timing_set(denali, i); | |
333 | ||
d3963721 SW |
334 | /* |
335 | * By now, all the ONFI devices we know support the page cache | |
336 | * rw feature. So here we enable the pipeline_rw_ahead feature | |
337 | */ | |
338 | ||
3eb3e72a CLS |
339 | return 0; |
340 | } | |
341 | ||
342 | static void get_samsung_nand_para(struct denali_nand_info *denali, | |
343 | uint8_t device_id) | |
344 | { | |
345 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ | |
346 | /* Set timing register values according to datasheet */ | |
347 | writel(5, denali->flash_reg + ACC_CLKS); | |
348 | writel(20, denali->flash_reg + RE_2_WE); | |
349 | writel(12, denali->flash_reg + WE_2_RE); | |
350 | writel(14, denali->flash_reg + ADDR_2_DATA); | |
351 | writel(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
352 | writel(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
353 | writel(2, denali->flash_reg + CS_SETUP_CNT); | |
354 | } | |
355 | } | |
356 | ||
357 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
358 | { | |
359 | uint32_t tmp; | |
360 | ||
d3963721 SW |
361 | /* |
362 | * Workaround to fix a controller bug which reports a wrong | |
363 | * spare area size for some kind of Toshiba NAND device | |
364 | */ | |
3eb3e72a CLS |
365 | if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
366 | (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
367 | writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
368 | tmp = readl(denali->flash_reg + DEVICES_CONNECTED) * | |
369 | readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
370 | writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); | |
371 | } | |
372 | } | |
373 | ||
374 | static void get_hynix_nand_para(struct denali_nand_info *denali, | |
375 | uint8_t device_id) | |
376 | { | |
377 | uint32_t main_size, spare_size; | |
378 | ||
379 | switch (device_id) { | |
380 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ | |
381 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
382 | writel(128, denali->flash_reg + PAGES_PER_BLOCK); | |
383 | writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
384 | writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
385 | main_size = 4096 * | |
386 | readl(denali->flash_reg + DEVICES_CONNECTED); | |
387 | spare_size = 224 * | |
388 | readl(denali->flash_reg + DEVICES_CONNECTED); | |
389 | writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); | |
390 | writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); | |
391 | writel(0, denali->flash_reg + DEVICE_WIDTH); | |
392 | break; | |
393 | default: | |
d3963721 | 394 | debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n" |
3eb3e72a CLS |
395 | "Will use default parameter values instead.\n", |
396 | device_id); | |
397 | } | |
398 | } | |
399 | ||
400 | /* | |
401 | * determines how many NAND chips are connected to the controller. Note for | |
402 | * Intel CE4100 devices we don't support more than one device. | |
403 | */ | |
404 | static void find_valid_banks(struct denali_nand_info *denali) | |
405 | { | |
406 | uint32_t id[denali->max_banks]; | |
407 | int i; | |
408 | ||
409 | denali->total_used_banks = 1; | |
410 | for (i = 0; i < denali->max_banks; i++) { | |
d3963721 SW |
411 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
412 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); | |
413 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); | |
3eb3e72a CLS |
414 | |
415 | if (i == 0) { | |
416 | if (!(id[i] & 0x0ff)) | |
417 | break; | |
418 | } else { | |
419 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
420 | denali->total_used_banks++; | |
421 | else | |
422 | break; | |
423 | } | |
424 | } | |
425 | } | |
426 | ||
427 | /* | |
428 | * Use the configuration feature register to determine the maximum number of | |
429 | * banks that the hardware supports. | |
430 | */ | |
431 | static void detect_max_banks(struct denali_nand_info *denali) | |
432 | { | |
433 | uint32_t features = readl(denali->flash_reg + FEATURES); | |
15305c2f GM |
434 | /* |
435 | * Read the revision register, so we can calculate the max_banks | |
436 | * properly: the encoding changed from rev 5.0 to 5.1 | |
437 | */ | |
438 | u32 revision = MAKE_COMPARABLE_REVISION( | |
439 | readl(denali->flash_reg + REVISION)); | |
440 | if (revision < REVISION_5_1) | |
441 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); | |
442 | else | |
443 | denali->max_banks = 1 << (features & FEATURES__N_BANKS); | |
3eb3e72a CLS |
444 | } |
445 | ||
446 | static void detect_partition_feature(struct denali_nand_info *denali) | |
447 | { | |
448 | /* | |
449 | * For MRST platform, denali->fwblks represent the | |
450 | * number of blocks firmware is taken, | |
451 | * FW is in protect partition and MTD driver has no | |
452 | * permission to access it. So let driver know how many | |
453 | * blocks it can't touch. | |
454 | */ | |
455 | if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { | |
456 | if ((readl(denali->flash_reg + PERM_SRC_ID(1)) & | |
457 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { | |
458 | denali->fwblks = | |
459 | ((readl(denali->flash_reg + MIN_MAX_BANK(1)) & | |
460 | MIN_MAX_BANK__MIN_VALUE) * | |
461 | denali->blksperchip) | |
462 | + | |
463 | (readl(denali->flash_reg + MIN_BLK_ADDR(1)) & | |
464 | MIN_BLK_ADDR__VALUE); | |
465 | } else { | |
466 | denali->fwblks = SPECTRA_START_BLOCK; | |
467 | } | |
468 | } else { | |
469 | denali->fwblks = SPECTRA_START_BLOCK; | |
470 | } | |
471 | } | |
472 | ||
473 | static uint32_t denali_nand_timing_set(struct denali_nand_info *denali) | |
474 | { | |
d3963721 SW |
475 | uint32_t id_bytes[8], addr; |
476 | uint8_t maf_id, device_id; | |
477 | int i; | |
478 | ||
479 | /* | |
480 | * Use read id method to get device ID and other params. | |
481 | * For some NAND chips, controller can't report the correct | |
482 | * device ID by reading from DEVICE_ID register | |
483 | */ | |
484 | addr = MODE_11 | BANK(denali->flash_bank); | |
485 | index_addr(denali, addr | 0, 0x90); | |
486 | index_addr(denali, addr | 1, 0); | |
487 | for (i = 0; i < 8; i++) | |
3eb3e72a CLS |
488 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
489 | maf_id = id_bytes[0]; | |
490 | device_id = id_bytes[1]; | |
491 | ||
492 | if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
493 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
494 | if (get_onfi_nand_para(denali)) | |
495 | return -EIO; | |
496 | } else if (maf_id == 0xEC) { /* Samsung NAND */ | |
497 | get_samsung_nand_para(denali, device_id); | |
498 | } else if (maf_id == 0x98) { /* Toshiba NAND */ | |
499 | get_toshiba_nand_para(denali); | |
500 | } else if (maf_id == 0xAD) { /* Hynix NAND */ | |
501 | get_hynix_nand_para(denali, device_id); | |
502 | } | |
503 | ||
504 | find_valid_banks(denali); | |
505 | ||
506 | detect_partition_feature(denali); | |
507 | ||
d3963721 SW |
508 | /* |
509 | * If the user specified to override the default timings | |
3eb3e72a CLS |
510 | * with a specific ONFI mode, we apply those changes here. |
511 | */ | |
512 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
513 | nand_onfi_timing_set(denali, onfi_timing_mode); | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
d3963721 SW |
518 | /* |
519 | * validation function to verify that the controlling software is making | |
3eb3e72a CLS |
520 | * a valid request |
521 | */ | |
522 | static inline bool is_flash_bank_valid(int flash_bank) | |
523 | { | |
524 | return flash_bank >= 0 && flash_bank < 4; | |
525 | } | |
526 | ||
527 | static void denali_irq_init(struct denali_nand_info *denali) | |
528 | { | |
d3963721 | 529 | uint32_t int_mask; |
3eb3e72a CLS |
530 | int i; |
531 | ||
532 | /* Disable global interrupts */ | |
533 | writel(0, denali->flash_reg + GLOBAL_INT_ENABLE); | |
534 | ||
535 | int_mask = DENALI_IRQ_ALL; | |
536 | ||
537 | /* Clear all status bits */ | |
538 | for (i = 0; i < denali->max_banks; ++i) | |
539 | writel(0xFFFF, denali->flash_reg + INTR_STATUS(i)); | |
540 | ||
541 | denali_irq_enable(denali, int_mask); | |
542 | } | |
543 | ||
d3963721 SW |
544 | /* |
545 | * This helper function setups the registers for ECC and whether or not | |
546 | * the spare area will be transferred. | |
547 | */ | |
3eb3e72a CLS |
548 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
549 | bool transfer_spare) | |
550 | { | |
d3963721 | 551 | int ecc_en_flag, transfer_spare_flag; |
3eb3e72a CLS |
552 | |
553 | /* set ECC, transfer spare bits if needed */ | |
554 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
555 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
556 | ||
557 | /* Enable spare area/ECC per user's request. */ | |
558 | writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE); | |
559 | /* applicable for MAP01 only */ | |
560 | writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); | |
561 | } | |
562 | ||
d3963721 SW |
563 | /* |
564 | * sends a pipeline command operation to the controller. See the Denali NAND | |
3eb3e72a CLS |
565 | * controller's user guide for more information (section 4.2.3.6). |
566 | */ | |
567 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |
d3963721 SW |
568 | bool ecc_en, bool transfer_spare, |
569 | int access_type, int op) | |
3eb3e72a CLS |
570 | { |
571 | uint32_t addr, cmd, irq_status; | |
572 | static uint32_t page_count = 1; | |
573 | ||
574 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
575 | ||
3eb3e72a CLS |
576 | clear_interrupts(denali); |
577 | ||
578 | addr = BANK(denali->flash_bank) | denali->page; | |
579 | ||
580 | /* setup the acccess type */ | |
581 | cmd = MODE_10 | addr; | |
582 | index_addr(denali, cmd, access_type); | |
583 | ||
584 | /* setup the pipeline command */ | |
585 | index_addr(denali, cmd, 0x2000 | op | page_count); | |
586 | ||
587 | cmd = MODE_01 | addr; | |
588 | writel(cmd, denali->flash_mem + INDEX_CTRL_REG); | |
589 | ||
590 | if (op == DENALI_READ) { | |
591 | /* wait for command to be accepted */ | |
592 | irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP); | |
593 | ||
594 | if (irq_status == 0) | |
595 | return -EIO; | |
596 | } | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | /* helper function that simply writes a buffer to the flash */ | |
602 | static int write_data_to_flash_mem(struct denali_nand_info *denali, | |
d3963721 | 603 | const uint8_t *buf, int len) |
3eb3e72a | 604 | { |
d3963721 SW |
605 | uint32_t *buf32; |
606 | int i; | |
3eb3e72a | 607 | |
d3963721 SW |
608 | /* |
609 | * verify that the len is a multiple of 4. | |
610 | * see comment in read_data_from_flash_mem() | |
611 | */ | |
3eb3e72a CLS |
612 | BUG_ON((len % 4) != 0); |
613 | ||
614 | /* write the data to the flash memory */ | |
615 | buf32 = (uint32_t *)buf; | |
616 | for (i = 0; i < len / 4; i++) | |
617 | writel(*buf32++, denali->flash_mem + INDEX_DATA_REG); | |
618 | return i * 4; /* intent is to return the number of bytes read */ | |
619 | } | |
620 | ||
621 | /* helper function that simply reads a buffer from the flash */ | |
622 | static int read_data_from_flash_mem(struct denali_nand_info *denali, | |
d3963721 | 623 | uint8_t *buf, int len) |
3eb3e72a | 624 | { |
d3963721 SW |
625 | uint32_t *buf32; |
626 | int i; | |
3eb3e72a CLS |
627 | |
628 | /* | |
d3963721 SW |
629 | * we assume that len will be a multiple of 4, if not it would be nice |
630 | * to know about it ASAP rather than have random failures... | |
631 | * This assumption is based on the fact that this function is designed | |
632 | * to be used to read flash pages, which are typically multiples of 4. | |
3eb3e72a | 633 | */ |
3eb3e72a CLS |
634 | BUG_ON((len % 4) != 0); |
635 | ||
636 | /* transfer the data from the flash */ | |
637 | buf32 = (uint32_t *)buf; | |
638 | for (i = 0; i < len / 4; i++) | |
639 | *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG); | |
640 | ||
641 | return i * 4; /* intent is to return the number of bytes read */ | |
642 | } | |
643 | ||
644 | static void denali_mode_main_access(struct denali_nand_info *denali) | |
645 | { | |
646 | uint32_t addr, cmd; | |
647 | ||
648 | addr = BANK(denali->flash_bank) | denali->page; | |
649 | cmd = MODE_10 | addr; | |
650 | index_addr(denali, cmd, MAIN_ACCESS); | |
651 | } | |
652 | ||
653 | static void denali_mode_main_spare_access(struct denali_nand_info *denali) | |
654 | { | |
655 | uint32_t addr, cmd; | |
656 | ||
657 | addr = BANK(denali->flash_bank) | denali->page; | |
658 | cmd = MODE_10 | addr; | |
659 | index_addr(denali, cmd, MAIN_SPARE_ACCESS); | |
660 | } | |
661 | ||
662 | /* writes OOB data to the device */ | |
663 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
664 | { | |
665 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
666 | uint32_t irq_status; | |
667 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | | |
668 | INTR_STATUS__PROGRAM_FAIL; | |
669 | int status = 0; | |
670 | ||
671 | denali->page = page; | |
672 | ||
673 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, | |
674 | DENALI_WRITE) == 0) { | |
675 | write_data_to_flash_mem(denali, buf, mtd->oobsize); | |
676 | ||
677 | /* wait for operation to complete */ | |
678 | irq_status = wait_for_irq(denali, irq_mask); | |
679 | ||
680 | if (irq_status == 0) { | |
681 | dev_err(denali->dev, "OOB write failed\n"); | |
682 | status = -EIO; | |
683 | } | |
684 | } else { | |
685 | printf("unable to send pipeline command\n"); | |
686 | status = -EIO; | |
687 | } | |
688 | return status; | |
689 | } | |
690 | ||
691 | /* reads OOB data from the device */ | |
692 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
693 | { | |
694 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
d3963721 SW |
695 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
696 | uint32_t irq_status, addr, cmd; | |
3eb3e72a CLS |
697 | |
698 | denali->page = page; | |
699 | ||
700 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, | |
701 | DENALI_READ) == 0) { | |
702 | read_data_from_flash_mem(denali, buf, mtd->oobsize); | |
703 | ||
d3963721 SW |
704 | /* |
705 | * wait for command to be accepted | |
706 | * can always use status0 bit as the | |
707 | * mask is identical for each bank. | |
708 | */ | |
3eb3e72a CLS |
709 | irq_status = wait_for_irq(denali, irq_mask); |
710 | ||
711 | if (irq_status == 0) | |
712 | printf("page on OOB timeout %d\n", denali->page); | |
713 | ||
d3963721 SW |
714 | /* |
715 | * We set the device back to MAIN_ACCESS here as I observed | |
3eb3e72a CLS |
716 | * instability with the controller if you do a block erase |
717 | * and the last transaction was a SPARE_ACCESS. Block erase | |
718 | * is reliable (according to the MTD test infrastructure) | |
719 | * if you are in MAIN_ACCESS. | |
720 | */ | |
721 | addr = BANK(denali->flash_bank) | denali->page; | |
722 | cmd = MODE_10 | addr; | |
723 | index_addr(denali, cmd, MAIN_ACCESS); | |
724 | } | |
725 | } | |
726 | ||
d3963721 SW |
727 | /* |
728 | * this function examines buffers to see if they contain data that | |
3eb3e72a CLS |
729 | * indicate that the buffer is part of an erased region of flash. |
730 | */ | |
731 | static bool is_erased(uint8_t *buf, int len) | |
732 | { | |
d3963721 SW |
733 | int i; |
734 | ||
3eb3e72a CLS |
735 | for (i = 0; i < len; i++) |
736 | if (buf[i] != 0xFF) | |
737 | return false; | |
738 | return true; | |
739 | } | |
740 | ||
741 | /* programs the controller to either enable/disable DMA transfers */ | |
742 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) | |
743 | { | |
d3963721 | 744 | writel(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
3eb3e72a CLS |
745 | readl(denali->flash_reg + DMA_ENABLE); |
746 | } | |
747 | ||
748 | /* setups the HW to perform the data DMA */ | |
749 | static void denali_setup_dma(struct denali_nand_info *denali, int op) | |
750 | { | |
751 | uint32_t mode; | |
752 | const int page_count = 1; | |
73b5b27b | 753 | uint64_t addr = (unsigned long)denali->buf.dma_buf; |
3eb3e72a CLS |
754 | |
755 | flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf)); | |
756 | ||
757 | /* For Denali controller that is 64 bit bus IP core */ | |
758 | #ifdef CONFIG_SYS_NAND_DENALI_64BIT | |
759 | mode = MODE_10 | BANK(denali->flash_bank) | denali->page; | |
760 | ||
761 | /* DMA is a three step process */ | |
762 | ||
763 | /* 1. setup transfer type, interrupt when complete, | |
764 | burst len = 64 bytes, the number of pages */ | |
765 | index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); | |
766 | ||
767 | /* 2. set memory low address bits 31:0 */ | |
768 | index_addr(denali, mode, addr); | |
769 | ||
770 | /* 3. set memory high address bits 64:32 */ | |
73b5b27b | 771 | index_addr(denali, mode, addr >> 32); |
3eb3e72a CLS |
772 | #else |
773 | mode = MODE_10 | BANK(denali->flash_bank); | |
774 | ||
775 | /* DMA is a four step process */ | |
776 | ||
777 | /* 1. setup transfer type and # of pages */ | |
778 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
779 | ||
780 | /* 2. set memory high address bits 23:8 */ | |
73b5b27b | 781 | index_addr(denali, mode | (((addr >> 16) & 0xffff) << 8), 0x2200); |
3eb3e72a CLS |
782 | |
783 | /* 3. set memory low address bits 23:8 */ | |
d3963721 | 784 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
3eb3e72a | 785 | |
d3963721 | 786 | /* 4. interrupt when complete, burst len = 64 bytes */ |
3eb3e72a CLS |
787 | index_addr(denali, mode | 0x14000, 0x2400); |
788 | #endif | |
789 | } | |
790 | ||
791 | /* Common DMA function */ | |
792 | static uint32_t denali_dma_configuration(struct denali_nand_info *denali, | |
793 | uint32_t ops, bool raw_xfer, | |
794 | uint32_t irq_mask, int oob_required) | |
795 | { | |
796 | uint32_t irq_status = 0; | |
797 | /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */ | |
798 | setup_ecc_for_xfer(denali, !raw_xfer, oob_required); | |
799 | ||
800 | /* clear any previous interrupt flags */ | |
801 | clear_interrupts(denali); | |
802 | ||
803 | /* enable the DMA */ | |
804 | denali_enable_dma(denali, true); | |
805 | ||
806 | /* setup the DMA */ | |
807 | denali_setup_dma(denali, ops); | |
808 | ||
809 | /* wait for operation to complete */ | |
810 | irq_status = wait_for_irq(denali, irq_mask); | |
811 | ||
812 | /* if ECC fault happen, seems we need delay before turning off DMA. | |
813 | * If not, the controller will go into non responsive condition */ | |
814 | if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) | |
815 | udelay(100); | |
816 | ||
817 | /* disable the DMA */ | |
818 | denali_enable_dma(denali, false); | |
819 | ||
820 | return irq_status; | |
821 | } | |
822 | ||
823 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
824 | const uint8_t *buf, bool raw_xfer, int oob_required) | |
825 | { | |
826 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
827 | ||
828 | uint32_t irq_status = 0; | |
829 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; | |
830 | ||
831 | denali->status = 0; | |
832 | ||
833 | /* copy buffer into DMA buffer */ | |
834 | memcpy(denali->buf.dma_buf, buf, mtd->writesize); | |
835 | ||
836 | /* need extra memcpy for raw transfer */ | |
837 | if (raw_xfer) | |
838 | memcpy(denali->buf.dma_buf + mtd->writesize, | |
839 | chip->oob_poi, mtd->oobsize); | |
840 | ||
841 | /* setting up DMA */ | |
842 | irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer, | |
843 | irq_mask, oob_required); | |
844 | ||
845 | /* if timeout happen, error out */ | |
846 | if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) { | |
847 | debug("DMA timeout for denali write_page\n"); | |
848 | denali->status = NAND_STATUS_FAIL; | |
849 | return -EIO; | |
850 | } | |
851 | ||
852 | if (irq_status & INTR_STATUS__LOCKED_BLK) { | |
853 | debug("Failed as write to locked block\n"); | |
854 | denali->status = NAND_STATUS_FAIL; | |
855 | return -EIO; | |
856 | } | |
857 | return 0; | |
858 | } | |
859 | ||
860 | /* NAND core entry points */ | |
861 | ||
862 | /* | |
863 | * this is the callback that the NAND core calls to write a page. Since | |
864 | * writing a page with ECC or without is similar, all the work is done | |
865 | * by write_page above. | |
866 | */ | |
867 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
868 | const uint8_t *buf, int oob_required) | |
869 | { | |
870 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
871 | ||
872 | /* | |
873 | * for regular page writes, we let HW handle all the ECC | |
874 | * data written to the device. | |
875 | */ | |
876 | if (oob_required) | |
877 | /* switch to main + spare access */ | |
878 | denali_mode_main_spare_access(denali); | |
879 | else | |
880 | /* switch to main access only */ | |
881 | denali_mode_main_access(denali); | |
882 | ||
883 | return write_page(mtd, chip, buf, false, oob_required); | |
884 | } | |
885 | ||
886 | /* | |
887 | * This is the callback that the NAND core calls to write a page without ECC. | |
888 | * raw access is similar to ECC page writes, so all the work is done in the | |
889 | * write_page() function above. | |
890 | */ | |
891 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
892 | const uint8_t *buf, int oob_required) | |
893 | { | |
894 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
895 | ||
896 | /* | |
897 | * for raw page writes, we want to disable ECC and simply write | |
898 | * whatever data is in the buffer. | |
899 | */ | |
900 | ||
901 | if (oob_required) | |
902 | /* switch to main + spare access */ | |
903 | denali_mode_main_spare_access(denali); | |
904 | else | |
905 | /* switch to main access only */ | |
906 | denali_mode_main_access(denali); | |
907 | ||
908 | return write_page(mtd, chip, buf, true, oob_required); | |
909 | } | |
910 | ||
911 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
912 | int page) | |
913 | { | |
914 | return write_oob_data(mtd, chip->oob_poi, page); | |
915 | } | |
916 | ||
917 | /* raw include ECC value and all the spare area */ | |
918 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
919 | uint8_t *buf, int oob_required, int page) | |
920 | { | |
921 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
922 | ||
923 | uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP; | |
924 | ||
925 | if (denali->page != page) { | |
926 | debug("Missing NAND_CMD_READ0 command\n"); | |
927 | return -EIO; | |
928 | } | |
929 | ||
930 | if (oob_required) | |
931 | /* switch to main + spare access */ | |
932 | denali_mode_main_spare_access(denali); | |
933 | else | |
934 | /* switch to main access only */ | |
935 | denali_mode_main_access(denali); | |
936 | ||
937 | /* setting up the DMA where ecc_enable is false */ | |
938 | irq_status = denali_dma_configuration(denali, DENALI_READ, true, | |
939 | irq_mask, oob_required); | |
940 | ||
941 | /* if timeout happen, error out */ | |
942 | if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) { | |
943 | debug("DMA timeout for denali_read_page_raw\n"); | |
944 | return -EIO; | |
945 | } | |
946 | ||
947 | /* splitting the content to destination buffer holder */ | |
948 | memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize), | |
949 | mtd->oobsize); | |
950 | memcpy(buf, denali->buf.dma_buf, mtd->writesize); | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956 | uint8_t *buf, int oob_required, int page) | |
957 | { | |
958 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
959 | uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP; | |
960 | ||
961 | if (denali->page != page) { | |
962 | debug("Missing NAND_CMD_READ0 command\n"); | |
963 | return -EIO; | |
964 | } | |
965 | ||
966 | if (oob_required) | |
967 | /* switch to main + spare access */ | |
968 | denali_mode_main_spare_access(denali); | |
969 | else | |
970 | /* switch to main access only */ | |
971 | denali_mode_main_access(denali); | |
972 | ||
973 | /* setting up the DMA where ecc_enable is true */ | |
974 | irq_status = denali_dma_configuration(denali, DENALI_READ, false, | |
975 | irq_mask, oob_required); | |
976 | ||
977 | memcpy(buf, denali->buf.dma_buf, mtd->writesize); | |
978 | ||
979 | /* check whether any ECC error */ | |
980 | if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) { | |
981 | /* is the ECC cause by erase page, check using read_page_raw */ | |
982 | debug(" Uncorrected ECC detected\n"); | |
983 | denali_read_page_raw(mtd, chip, buf, oob_required, | |
984 | denali->page); | |
985 | ||
986 | if (is_erased(buf, mtd->writesize) == true && | |
987 | is_erased(chip->oob_poi, mtd->oobsize) == true) { | |
988 | debug(" ECC error cause by erased block\n"); | |
989 | /* false alarm, return the 0xFF */ | |
990 | } else { | |
991 | return -EIO; | |
992 | } | |
993 | } | |
994 | memcpy(buf, denali->buf.dma_buf, mtd->writesize); | |
995 | return 0; | |
996 | } | |
997 | ||
998 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
999 | int page) | |
1000 | { | |
1001 | read_oob_data(mtd, chip->oob_poi, page); | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1007 | { | |
1008 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1009 | uint32_t addr, result; | |
1010 | ||
1011 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
1012 | index_addr_read_data(denali, addr | 2, &result); | |
1013 | return (uint8_t)result & 0xFF; | |
1014 | } | |
1015 | ||
1016 | static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
1017 | { | |
1018 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1019 | uint32_t i, addr, result; | |
1020 | ||
1021 | /* delay for tR (data transfer from Flash array to data register) */ | |
1022 | udelay(25); | |
1023 | ||
1024 | /* ensure device completed else additional delay and polling */ | |
1025 | wait_for_irq(denali, INTR_STATUS__INT_ACT); | |
1026 | ||
1027 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
1028 | for (i = 0; i < len; i++) { | |
1029 | index_addr_read_data(denali, (uint32_t)addr | 2, &result); | |
1030 | write_byte_to_buf(denali, result); | |
1031 | } | |
1032 | memcpy(buf, denali->buf.buf, len); | |
1033 | } | |
1034 | ||
1035 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1036 | { | |
1037 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1038 | ||
1039 | denali->flash_bank = chip; | |
1040 | } | |
1041 | ||
1042 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1043 | { | |
1044 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1045 | int status = denali->status; | |
d3963721 | 1046 | |
3eb3e72a CLS |
1047 | denali->status = 0; |
1048 | ||
1049 | return status; | |
1050 | } | |
1051 | ||
d3963721 | 1052 | static int denali_erase(struct mtd_info *mtd, int page) |
3eb3e72a CLS |
1053 | { |
1054 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
d3963721 | 1055 | |
3eb3e72a CLS |
1056 | uint32_t cmd, irq_status; |
1057 | ||
3eb3e72a CLS |
1058 | clear_interrupts(denali); |
1059 | ||
1060 | /* setup page read request for access type */ | |
1061 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
1062 | index_addr(denali, cmd, 0x1); | |
1063 | ||
1064 | /* wait for erase to complete or failure to occur */ | |
1065 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | | |
1066 | INTR_STATUS__ERASE_FAIL); | |
1067 | ||
1068 | if (irq_status & INTR_STATUS__ERASE_FAIL || | |
1069 | irq_status & INTR_STATUS__LOCKED_BLK) | |
d3963721 SW |
1070 | return NAND_STATUS_FAIL; |
1071 | ||
1072 | return 0; | |
3eb3e72a CLS |
1073 | } |
1074 | ||
1075 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, | |
1076 | int page) | |
1077 | { | |
1078 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1079 | uint32_t addr; | |
1080 | ||
1081 | switch (cmd) { | |
1082 | case NAND_CMD_PAGEPROG: | |
1083 | break; | |
1084 | case NAND_CMD_STATUS: | |
1085 | addr = MODE_11 | BANK(denali->flash_bank); | |
1086 | index_addr(denali, addr | 0, cmd); | |
1087 | break; | |
3eb3e72a | 1088 | case NAND_CMD_READID: |
05968e7c | 1089 | case NAND_CMD_PARAM: |
3eb3e72a | 1090 | reset_buf(denali); |
d3963721 SW |
1091 | /* |
1092 | * sometimes ManufactureId read from register is not right | |
3eb3e72a CLS |
1093 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
1094 | * So here we send READID cmd to NAND insteand | |
d3963721 | 1095 | */ |
3eb3e72a CLS |
1096 | addr = MODE_11 | BANK(denali->flash_bank); |
1097 | index_addr(denali, addr | 0, cmd); | |
1098 | index_addr(denali, addr | 1, col & 0xFF); | |
05968e7c MY |
1099 | if (cmd == NAND_CMD_PARAM) |
1100 | udelay(50); | |
3eb3e72a | 1101 | break; |
ed3c980b MY |
1102 | case NAND_CMD_RNDOUT: |
1103 | addr = MODE_11 | BANK(denali->flash_bank); | |
1104 | index_addr(denali, addr | 0, cmd); | |
1105 | index_addr(denali, addr | 1, col & 0xFF); | |
1106 | index_addr(denali, addr | 1, col >> 8); | |
1107 | index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART); | |
1108 | break; | |
3eb3e72a CLS |
1109 | case NAND_CMD_READ0: |
1110 | case NAND_CMD_SEQIN: | |
1111 | denali->page = page; | |
1112 | break; | |
1113 | case NAND_CMD_RESET: | |
1114 | reset_bank(denali); | |
1115 | break; | |
1116 | case NAND_CMD_READOOB: | |
1117 | /* TODO: Read OOB data */ | |
1118 | break; | |
1119 | case NAND_CMD_ERASE1: | |
1120 | /* | |
1121 | * supporting block erase only, not multiblock erase as | |
1122 | * it will cross plane and software need complex calculation | |
1123 | * to identify the block count for the cross plane | |
1124 | */ | |
1125 | denali_erase(mtd, page); | |
1126 | break; | |
1127 | case NAND_CMD_ERASE2: | |
1128 | /* nothing to do here as it was done during NAND_CMD_ERASE1 */ | |
1129 | break; | |
1130 | case NAND_CMD_UNLOCK1: | |
1131 | addr = MODE_10 | BANK(denali->flash_bank) | page; | |
1132 | index_addr(denali, addr | 0, DENALI_UNLOCK_START); | |
1133 | break; | |
1134 | case NAND_CMD_UNLOCK2: | |
1135 | addr = MODE_10 | BANK(denali->flash_bank) | page; | |
1136 | index_addr(denali, addr | 0, DENALI_UNLOCK_END); | |
1137 | break; | |
1138 | case NAND_CMD_LOCK: | |
1139 | addr = MODE_10 | BANK(denali->flash_bank); | |
1140 | index_addr(denali, addr | 0, DENALI_LOCK); | |
1141 | break; | |
1142 | default: | |
1143 | printf(": unsupported command received 0x%x\n", cmd); | |
1144 | break; | |
1145 | } | |
1146 | } | |
1147 | /* end NAND core entry points */ | |
1148 | ||
1149 | /* Initialization code to bring the device up to a known good state */ | |
1150 | static void denali_hw_init(struct denali_nand_info *denali) | |
1151 | { | |
1152 | /* | |
1153 | * tell driver how many bit controller will skip before writing | |
1154 | * ECC code in OOB. This is normally used for bad block marker | |
1155 | */ | |
1156 | writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, | |
1157 | denali->flash_reg + SPARE_AREA_SKIP_BYTES); | |
1158 | detect_max_banks(denali); | |
1159 | denali_nand_reset(denali); | |
1160 | writel(0x0F, denali->flash_reg + RB_PIN_ENABLED); | |
1161 | writel(CHIP_EN_DONT_CARE__FLAG, | |
1162 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); | |
1163 | writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER); | |
1164 | ||
1165 | /* Should set value for these registers when init */ | |
1166 | writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); | |
1167 | writel(1, denali->flash_reg + ECC_ENABLE); | |
1168 | denali_nand_timing_set(denali); | |
1169 | denali_irq_init(denali); | |
1170 | } | |
1171 | ||
1172 | static struct nand_ecclayout nand_oob; | |
1173 | ||
65e4145a | 1174 | static int denali_init(struct denali_nand_info *denali) |
3eb3e72a | 1175 | { |
65e4145a | 1176 | int ret; |
3eb3e72a | 1177 | |
65e4145a | 1178 | denali_hw_init(denali); |
3eb3e72a | 1179 | |
65e4145a MY |
1180 | denali->mtd->name = "denali-nand"; |
1181 | denali->mtd->owner = THIS_MODULE; | |
1182 | denali->mtd->priv = &denali->nand; | |
3eb3e72a | 1183 | |
65e4145a MY |
1184 | /* register the driver with the NAND core subsystem */ |
1185 | denali->nand.select_chip = denali_select_chip; | |
1186 | denali->nand.cmdfunc = denali_cmdfunc; | |
1187 | denali->nand.read_byte = denali_read_byte; | |
1188 | denali->nand.read_buf = denali_read_buf; | |
1189 | denali->nand.waitfunc = denali_waitfunc; | |
1190 | ||
1191 | /* | |
1192 | * scan for NAND devices attached to the controller | |
1193 | * this is the first stage in a two step process to register | |
1194 | * with the nand subsystem | |
1195 | */ | |
1196 | if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) { | |
1197 | ret = -ENXIO; | |
1198 | goto fail; | |
1199 | } | |
3eb3e72a CLS |
1200 | |
1201 | #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT | |
1202 | /* check whether flash got BBT table (located at end of flash). As we | |
1203 | * use NAND_BBT_NO_OOB, the BBT page will start with | |
1204 | * bbt_pattern. We will have mirror pattern too */ | |
65e4145a | 1205 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
3eb3e72a CLS |
1206 | /* |
1207 | * We are using main + spare with ECC support. As BBT need ECC support, | |
1208 | * we need to ensure BBT code don't write to OOB for the BBT pattern. | |
1209 | * All BBT info will be stored into data area with ECC support. | |
1210 | */ | |
65e4145a | 1211 | denali->nand.bbt_options |= NAND_BBT_NO_OOB; |
3eb3e72a CLS |
1212 | #endif |
1213 | ||
65e4145a MY |
1214 | denali->nand.ecc.mode = NAND_ECC_HW; |
1215 | denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE; | |
1216 | ||
d3963721 SW |
1217 | /* no subpage writes on denali */ |
1218 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; | |
1219 | ||
3eb3e72a CLS |
1220 | /* |
1221 | * Tell driver the ecc strength. This register may be already set | |
1222 | * correctly. So we read this value out. | |
1223 | */ | |
65e4145a MY |
1224 | denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION); |
1225 | switch (denali->nand.ecc.size) { | |
3eb3e72a | 1226 | case 512: |
65e4145a MY |
1227 | denali->nand.ecc.bytes = |
1228 | (denali->nand.ecc.strength * 13 + 15) / 16 * 2; | |
3eb3e72a CLS |
1229 | break; |
1230 | case 1024: | |
65e4145a MY |
1231 | denali->nand.ecc.bytes = |
1232 | (denali->nand.ecc.strength * 14 + 15) / 16 * 2; | |
3eb3e72a CLS |
1233 | break; |
1234 | default: | |
1235 | pr_err("Unsupported ECC size\n"); | |
65e4145a MY |
1236 | ret = -EINVAL; |
1237 | goto fail; | |
3eb3e72a | 1238 | } |
65e4145a MY |
1239 | nand_oob.eccbytes = denali->nand.ecc.bytes; |
1240 | denali->nand.ecc.layout = &nand_oob; | |
1241 | ||
f09eb52b MY |
1242 | writel(denali->mtd->erasesize / denali->mtd->writesize, |
1243 | denali->flash_reg + PAGES_PER_BLOCK); | |
1244 | writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0, | |
1245 | denali->flash_reg + DEVICE_WIDTH); | |
1246 | writel(denali->mtd->writesize, | |
1247 | denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
1248 | writel(denali->mtd->oobsize, | |
1249 | denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
1250 | if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0) | |
1251 | writel(1, denali->flash_reg + DEVICES_CONNECTED); | |
1252 | ||
65e4145a MY |
1253 | /* override the default operations */ |
1254 | denali->nand.ecc.read_page = denali_read_page; | |
1255 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1256 | denali->nand.ecc.write_page = denali_write_page; | |
1257 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1258 | denali->nand.ecc.read_oob = denali_read_oob; | |
1259 | denali->nand.ecc.write_oob = denali_write_oob; | |
1260 | ||
1261 | if (nand_scan_tail(denali->mtd)) { | |
1262 | ret = -ENXIO; | |
1263 | goto fail; | |
1264 | } | |
1265 | ||
b616d9b0 | 1266 | ret = nand_register(0, denali->mtd); |
65e4145a MY |
1267 | |
1268 | fail: | |
1269 | return ret; | |
1270 | } | |
1271 | ||
1272 | static int __board_nand_init(void) | |
1273 | { | |
1274 | struct denali_nand_info *denali; | |
1275 | ||
1276 | denali = kzalloc(sizeof(*denali), GFP_KERNEL); | |
1277 | if (!denali) | |
1278 | return -ENOMEM; | |
1279 | ||
1280 | /* | |
1281 | * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible | |
1282 | * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c | |
1283 | * still provides a "struct mtd_info nand_info" instance. | |
1284 | */ | |
b616d9b0 | 1285 | denali->mtd = &denali->nand.mtd; |
65e4145a MY |
1286 | |
1287 | /* | |
1288 | * In the future, these base addresses should be taken from | |
1289 | * Device Tree or platform data. | |
1290 | */ | |
1291 | denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; | |
1292 | denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; | |
1293 | ||
1294 | return denali_init(denali); | |
3eb3e72a CLS |
1295 | } |
1296 | ||
65e4145a | 1297 | void board_nand_init(void) |
3eb3e72a | 1298 | { |
65e4145a MY |
1299 | if (__board_nand_init() < 0) |
1300 | pr_warn("Failed to initialize Denali NAND controller.\n"); | |
3eb3e72a | 1301 | } |