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9fd020d6 SW |
1 | /* Freescale Enhanced Local Bus Controller FCM NAND driver |
2 | * | |
3 | * Copyright (c) 2006-2008 Freescale Semiconductor | |
4 | * | |
5 | * Authors: Nick Spence <nick.spence@freescale.com>, | |
6 | * Scott Wood <scottwood@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <malloc.h> | |
25 | ||
26 | #include <linux/mtd/mtd.h> | |
27 | #include <linux/mtd/nand.h> | |
28 | #include <linux/mtd/nand_ecc.h> | |
29 | ||
30 | #include <asm/io.h> | |
31 | #include <asm/errno.h> | |
32 | ||
33 | #ifdef VERBOSE_DEBUG | |
34 | #define DEBUG_ELBC | |
35 | #define vdbg(format, arg...) printf("DEBUG: " format, ##arg) | |
36 | #else | |
37 | #define vdbg(format, arg...) do {} while (0) | |
38 | #endif | |
39 | ||
40 | /* Can't use plain old DEBUG because the linux mtd | |
41 | * headers define it as a macro. | |
42 | */ | |
43 | #ifdef DEBUG_ELBC | |
44 | #define dbg(format, arg...) printf("DEBUG: " format, ##arg) | |
45 | #else | |
46 | #define dbg(format, arg...) do {} while (0) | |
47 | #endif | |
48 | ||
49 | #define MAX_BANKS 8 | |
50 | #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ | |
51 | #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */ | |
52 | ||
53 | #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) | |
54 | ||
55 | struct fsl_elbc_ctrl; | |
56 | ||
57 | /* mtd information per set */ | |
58 | ||
59 | struct fsl_elbc_mtd { | |
60 | struct mtd_info mtd; | |
61 | struct nand_chip chip; | |
62 | struct fsl_elbc_ctrl *ctrl; | |
63 | ||
64 | struct device *dev; | |
65 | int bank; /* Chip select bank number */ | |
66 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
67 | int page_size; /* NAND page size (0=512, 1=2048) */ | |
68 | unsigned int fmr; /* FCM Flash Mode Register value */ | |
69 | }; | |
70 | ||
71 | /* overview of the fsl elbc controller */ | |
72 | ||
73 | struct fsl_elbc_ctrl { | |
74 | struct nand_hw_control controller; | |
75 | struct fsl_elbc_mtd *chips[MAX_BANKS]; | |
76 | ||
77 | /* device info */ | |
4e190b03 | 78 | fsl_lbus_t *regs; |
9fd020d6 SW |
79 | u8 __iomem *addr; /* Address of assigned FCM buffer */ |
80 | unsigned int page; /* Last page written to / read from */ | |
81 | unsigned int read_bytes; /* Number of bytes read during command */ | |
82 | unsigned int column; /* Saved column from SEQIN */ | |
83 | unsigned int index; /* Pointer to next byte to 'read' */ | |
84 | unsigned int status; /* status read from LTESR after last op */ | |
85 | unsigned int mdr; /* UPM/FCM Data Register value */ | |
86 | unsigned int use_mdr; /* Non zero if the MDR is to be set */ | |
87 | unsigned int oob; /* Non zero if operating on OOB data */ | |
88 | uint8_t *oob_poi; /* Place to write ECC after read back */ | |
89 | }; | |
90 | ||
91 | /* These map to the positions used by the FCM hardware ECC generator */ | |
92 | ||
93 | /* Small Page FLASH with FMR[ECCM] = 0 */ | |
94 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { | |
95 | .eccbytes = 3, | |
96 | .eccpos = {6, 7, 8}, | |
97 | .oobfree = { {0, 5}, {9, 7} }, | |
9fd020d6 SW |
98 | }; |
99 | ||
100 | /* Small Page FLASH with FMR[ECCM] = 1 */ | |
101 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { | |
102 | .eccbytes = 3, | |
103 | .eccpos = {8, 9, 10}, | |
104 | .oobfree = { {0, 5}, {6, 2}, {11, 5} }, | |
9fd020d6 SW |
105 | }; |
106 | ||
107 | /* Large Page FLASH with FMR[ECCM] = 0 */ | |
108 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { | |
109 | .eccbytes = 12, | |
110 | .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, | |
111 | .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, | |
9fd020d6 SW |
112 | }; |
113 | ||
114 | /* Large Page FLASH with FMR[ECCM] = 1 */ | |
115 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { | |
116 | .eccbytes = 12, | |
117 | .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, | |
118 | .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, | |
9fd020d6 SW |
119 | }; |
120 | ||
97ae0236 AV |
121 | /* |
122 | * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset | |
123 | * 1, so we have to adjust bad block pattern. This pattern should be used for | |
124 | * x8 chips only. So far hardware does not support x16 chips anyway. | |
125 | */ | |
126 | static u8 scan_ff_pattern[] = { 0xff, }; | |
127 | ||
128 | static struct nand_bbt_descr largepage_memorybased = { | |
129 | .options = 0, | |
130 | .offs = 0, | |
131 | .len = 1, | |
132 | .pattern = scan_ff_pattern, | |
133 | }; | |
134 | ||
8f42bf1c AV |
135 | /* |
136 | * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, | |
137 | * interfere with ECC positions, that's why we implement our own descriptors. | |
138 | * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. | |
139 | */ | |
140 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
141 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
142 | ||
143 | static struct nand_bbt_descr bbt_main_descr = { | |
144 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
145 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
146 | .offs = 11, | |
147 | .len = 4, | |
148 | .veroffs = 15, | |
149 | .maxblocks = 4, | |
150 | .pattern = bbt_pattern, | |
151 | }; | |
152 | ||
153 | static struct nand_bbt_descr bbt_mirror_descr = { | |
154 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
155 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
156 | .offs = 11, | |
157 | .len = 4, | |
158 | .veroffs = 15, | |
159 | .maxblocks = 4, | |
160 | .pattern = mirror_pattern, | |
161 | }; | |
162 | ||
9fd020d6 SW |
163 | /*=================================*/ |
164 | ||
165 | /* | |
166 | * Set up the FCM hardware block and page address fields, and the fcm | |
167 | * structure addr field to point to the correct FCM buffer in memory | |
168 | */ | |
169 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
170 | { | |
171 | struct nand_chip *chip = mtd->priv; | |
172 | struct fsl_elbc_mtd *priv = chip->priv; | |
173 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
4e190b03 | 174 | fsl_lbus_t *lbc = ctrl->regs; |
9fd020d6 SW |
175 | int buf_num; |
176 | ||
177 | ctrl->page = page_addr; | |
178 | ||
9fd020d6 | 179 | if (priv->page_size) { |
30025330 | 180 | out_be32(&lbc->fbar, page_addr >> 6); |
9fd020d6 | 181 | out_be32(&lbc->fpar, |
4b070809 WD |
182 | ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | |
183 | (oob ? FPAR_LP_MS : 0) | column); | |
9fd020d6 SW |
184 | buf_num = (page_addr & 1) << 2; |
185 | } else { | |
30025330 | 186 | out_be32(&lbc->fbar, page_addr >> 5); |
9fd020d6 | 187 | out_be32(&lbc->fpar, |
4b070809 WD |
188 | ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | |
189 | (oob ? FPAR_SP_MS : 0) | column); | |
9fd020d6 SW |
190 | buf_num = page_addr & 7; |
191 | } | |
192 | ||
193 | ctrl->addr = priv->vbase + buf_num * 1024; | |
194 | ctrl->index = column; | |
195 | ||
196 | /* for OOB data point to the second half of the buffer */ | |
197 | if (oob) | |
198 | ctrl->index += priv->page_size ? 2048 : 512; | |
199 | ||
200 | vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), " | |
201 | "index %x, pes %d ps %d\n", | |
202 | buf_num, ctrl->addr, priv->vbase, ctrl->index, | |
203 | chip->phys_erase_shift, chip->page_shift); | |
204 | } | |
205 | ||
206 | /* | |
207 | * execute FCM command and wait for it to complete | |
208 | */ | |
209 | static int fsl_elbc_run_command(struct mtd_info *mtd) | |
210 | { | |
211 | struct nand_chip *chip = mtd->priv; | |
212 | struct fsl_elbc_mtd *priv = chip->priv; | |
213 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
4e190b03 | 214 | fsl_lbus_t *lbc = ctrl->regs; |
9fd020d6 SW |
215 | long long end_tick; |
216 | u32 ltesr; | |
217 | ||
218 | /* Setup the FMR[OP] to execute without write protection */ | |
219 | out_be32(&lbc->fmr, priv->fmr | 3); | |
220 | if (ctrl->use_mdr) | |
221 | out_be32(&lbc->mdr, ctrl->mdr); | |
222 | ||
223 | vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", | |
224 | in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); | |
225 | vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x " | |
226 | "fbcr=%08x bank=%d\n", | |
227 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), | |
228 | in_be32(&lbc->fbcr), priv->bank); | |
229 | ||
230 | /* execute special operation */ | |
231 | out_be32(&lbc->lsor, priv->bank); | |
232 | ||
233 | /* wait for FCM complete flag or timeout */ | |
234 | end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks(); | |
235 | ||
236 | ltesr = 0; | |
237 | while (end_tick > get_ticks()) { | |
238 | ltesr = in_be32(&lbc->ltesr); | |
239 | if (ltesr & LTESR_CC) | |
240 | break; | |
241 | } | |
242 | ||
243 | ctrl->status = ltesr & LTESR_NAND_MASK; | |
244 | out_be32(&lbc->ltesr, ctrl->status); | |
245 | out_be32(&lbc->lteatr, 0); | |
246 | ||
247 | /* store mdr value in case it was needed */ | |
248 | if (ctrl->use_mdr) | |
249 | ctrl->mdr = in_be32(&lbc->mdr); | |
250 | ||
251 | ctrl->use_mdr = 0; | |
252 | ||
253 | vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n", | |
254 | ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); | |
255 | ||
256 | /* returns 0 on success otherwise non-zero) */ | |
257 | return ctrl->status == LTESR_CC ? 0 : -EIO; | |
258 | } | |
259 | ||
260 | static void fsl_elbc_do_read(struct nand_chip *chip, int oob) | |
261 | { | |
262 | struct fsl_elbc_mtd *priv = chip->priv; | |
263 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
4e190b03 | 264 | fsl_lbus_t *lbc = ctrl->regs; |
9fd020d6 SW |
265 | |
266 | if (priv->page_size) { | |
267 | out_be32(&lbc->fir, | |
4b070809 WD |
268 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | |
269 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
270 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
271 | (FIR_OP_CW1 << FIR_OP3_SHIFT) | | |
272 | (FIR_OP_RBW << FIR_OP4_SHIFT)); | |
9fd020d6 SW |
273 | |
274 | out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | | |
4b070809 | 275 | (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); |
9fd020d6 SW |
276 | } else { |
277 | out_be32(&lbc->fir, | |
4b070809 WD |
278 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | |
279 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
280 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
281 | (FIR_OP_RBW << FIR_OP3_SHIFT)); | |
9fd020d6 SW |
282 | |
283 | if (oob) | |
284 | out_be32(&lbc->fcr, | |
4b070809 | 285 | NAND_CMD_READOOB << FCR_CMD0_SHIFT); |
9fd020d6 SW |
286 | else |
287 | out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); | |
288 | } | |
289 | } | |
290 | ||
291 | /* cmdfunc send commands to the FCM */ | |
292 | static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
4b070809 | 293 | int column, int page_addr) |
9fd020d6 SW |
294 | { |
295 | struct nand_chip *chip = mtd->priv; | |
296 | struct fsl_elbc_mtd *priv = chip->priv; | |
297 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
4e190b03 | 298 | fsl_lbus_t *lbc = ctrl->regs; |
9fd020d6 SW |
299 | |
300 | ctrl->use_mdr = 0; | |
301 | ||
302 | /* clear the read buffer */ | |
303 | ctrl->read_bytes = 0; | |
304 | if (command != NAND_CMD_PAGEPROG) | |
305 | ctrl->index = 0; | |
306 | ||
307 | switch (command) { | |
308 | /* READ0 and READ1 read the entire buffer to use hardware ECC. */ | |
309 | case NAND_CMD_READ1: | |
310 | column += 256; | |
311 | ||
312 | /* fall-through */ | |
313 | case NAND_CMD_READ0: | |
314 | vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" | |
315 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
316 | ||
317 | out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ | |
318 | set_addr(mtd, 0, page_addr, 0); | |
319 | ||
320 | ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
321 | ctrl->index += column; | |
322 | ||
323 | fsl_elbc_do_read(chip, 0); | |
324 | fsl_elbc_run_command(mtd); | |
325 | return; | |
326 | ||
327 | /* READOOB reads only the OOB because no ECC is performed. */ | |
328 | case NAND_CMD_READOOB: | |
329 | vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" | |
330 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
331 | ||
332 | out_be32(&lbc->fbcr, mtd->oobsize - column); | |
333 | set_addr(mtd, column, page_addr, 1); | |
334 | ||
335 | ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
336 | ||
337 | fsl_elbc_do_read(chip, 1); | |
338 | fsl_elbc_run_command(mtd); | |
339 | ||
340 | return; | |
341 | ||
342 | /* READID must read all 5 possible bytes while CEB is active */ | |
343 | case NAND_CMD_READID: | |
344 | vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); | |
345 | ||
346 | out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
4b070809 WD |
347 | (FIR_OP_UA << FIR_OP1_SHIFT) | |
348 | (FIR_OP_RBW << FIR_OP2_SHIFT)); | |
9fd020d6 SW |
349 | out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); |
350 | /* 5 bytes for manuf, device and exts */ | |
351 | out_be32(&lbc->fbcr, 5); | |
352 | ctrl->read_bytes = 5; | |
353 | ctrl->use_mdr = 1; | |
354 | ctrl->mdr = 0; | |
355 | ||
356 | set_addr(mtd, 0, 0, 0); | |
357 | fsl_elbc_run_command(mtd); | |
358 | return; | |
359 | ||
360 | /* ERASE1 stores the block and page address */ | |
361 | case NAND_CMD_ERASE1: | |
362 | vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " | |
363 | "page_addr: 0x%x.\n", page_addr); | |
364 | set_addr(mtd, 0, page_addr, 0); | |
365 | return; | |
366 | ||
367 | /* ERASE2 uses the block and page address from ERASE1 */ | |
368 | case NAND_CMD_ERASE2: | |
369 | vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); | |
370 | ||
371 | out_be32(&lbc->fir, | |
4b070809 WD |
372 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | |
373 | (FIR_OP_PA << FIR_OP1_SHIFT) | | |
374 | (FIR_OP_CM1 << FIR_OP2_SHIFT)); | |
9fd020d6 SW |
375 | |
376 | out_be32(&lbc->fcr, | |
4b070809 WD |
377 | (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | |
378 | (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT)); | |
9fd020d6 SW |
379 | |
380 | out_be32(&lbc->fbcr, 0); | |
381 | ctrl->read_bytes = 0; | |
382 | ||
383 | fsl_elbc_run_command(mtd); | |
384 | return; | |
385 | ||
386 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
387 | case NAND_CMD_SEQIN: { | |
388 | u32 fcr; | |
389 | vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " | |
390 | "page_addr: 0x%x, column: 0x%x.\n", | |
391 | page_addr, column); | |
392 | ||
393 | ctrl->column = column; | |
394 | ctrl->oob = 0; | |
395 | ||
396 | if (priv->page_size) { | |
397 | fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | | |
398 | (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); | |
399 | ||
400 | out_be32(&lbc->fir, | |
4b070809 WD |
401 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | |
402 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
403 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
404 | (FIR_OP_WB << FIR_OP3_SHIFT) | | |
405 | (FIR_OP_CW1 << FIR_OP4_SHIFT)); | |
9fd020d6 SW |
406 | } else { |
407 | fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) | | |
408 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); | |
409 | ||
410 | out_be32(&lbc->fir, | |
4b070809 WD |
411 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | |
412 | (FIR_OP_CM2 << FIR_OP1_SHIFT) | | |
413 | (FIR_OP_CA << FIR_OP2_SHIFT) | | |
414 | (FIR_OP_PA << FIR_OP3_SHIFT) | | |
415 | (FIR_OP_WB << FIR_OP4_SHIFT) | | |
416 | (FIR_OP_CW1 << FIR_OP5_SHIFT)); | |
9fd020d6 SW |
417 | |
418 | if (column >= mtd->writesize) { | |
419 | /* OOB area --> READOOB */ | |
420 | column -= mtd->writesize; | |
421 | fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; | |
422 | ctrl->oob = 1; | |
423 | } else if (column < 256) { | |
424 | /* First 256 bytes --> READ0 */ | |
425 | fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; | |
426 | } else { | |
427 | /* Second 256 bytes --> READ1 */ | |
428 | fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT; | |
429 | } | |
430 | } | |
431 | ||
432 | out_be32(&lbc->fcr, fcr); | |
433 | set_addr(mtd, column, page_addr, ctrl->oob); | |
434 | return; | |
435 | } | |
436 | ||
437 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
438 | case NAND_CMD_PAGEPROG: { | |
439 | int full_page; | |
440 | vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " | |
441 | "writing %d bytes.\n", ctrl->index); | |
442 | ||
443 | /* if the write did not start at 0 or is not a full page | |
444 | * then set the exact length, otherwise use a full page | |
445 | * write so the HW generates the ECC. | |
446 | */ | |
447 | if (ctrl->oob || ctrl->column != 0 || | |
448 | ctrl->index != mtd->writesize + mtd->oobsize) { | |
449 | out_be32(&lbc->fbcr, ctrl->index); | |
450 | full_page = 0; | |
451 | } else { | |
452 | out_be32(&lbc->fbcr, 0); | |
453 | full_page = 1; | |
454 | } | |
455 | ||
456 | fsl_elbc_run_command(mtd); | |
457 | ||
458 | /* Read back the page in order to fill in the ECC for the | |
459 | * caller. Is this really needed? | |
460 | */ | |
461 | if (full_page && ctrl->oob_poi) { | |
462 | out_be32(&lbc->fbcr, 3); | |
463 | set_addr(mtd, 6, page_addr, 1); | |
464 | ||
465 | ctrl->read_bytes = mtd->writesize + 9; | |
466 | ||
467 | fsl_elbc_do_read(chip, 1); | |
468 | fsl_elbc_run_command(mtd); | |
469 | ||
470 | memcpy_fromio(ctrl->oob_poi + 6, | |
4b070809 | 471 | &ctrl->addr[ctrl->index], 3); |
9fd020d6 SW |
472 | ctrl->index += 3; |
473 | } | |
474 | ||
475 | ctrl->oob_poi = NULL; | |
476 | return; | |
477 | } | |
478 | ||
479 | /* CMD_STATUS must read the status byte while CEB is active */ | |
480 | /* Note - it does not wait for the ready line */ | |
481 | case NAND_CMD_STATUS: | |
482 | out_be32(&lbc->fir, | |
4b070809 WD |
483 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
484 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
9fd020d6 SW |
485 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); |
486 | out_be32(&lbc->fbcr, 1); | |
487 | set_addr(mtd, 0, 0, 0); | |
488 | ctrl->read_bytes = 1; | |
489 | ||
490 | fsl_elbc_run_command(mtd); | |
491 | ||
492 | /* The chip always seems to report that it is | |
493 | * write-protected, even when it is not. | |
494 | */ | |
495 | out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); | |
496 | return; | |
497 | ||
498 | /* RESET without waiting for the ready line */ | |
499 | case NAND_CMD_RESET: | |
500 | dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); | |
501 | out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); | |
502 | out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); | |
503 | fsl_elbc_run_command(mtd); | |
504 | return; | |
505 | ||
506 | default: | |
507 | printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", | |
4b070809 | 508 | command); |
9fd020d6 SW |
509 | } |
510 | } | |
511 | ||
512 | static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) | |
513 | { | |
514 | /* The hardware does not seem to support multiple | |
515 | * chips per bank. | |
516 | */ | |
517 | } | |
518 | ||
519 | /* | |
520 | * Write buf to the FCM Controller Data Buffer | |
521 | */ | |
522 | static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
523 | { | |
524 | struct nand_chip *chip = mtd->priv; | |
525 | struct fsl_elbc_mtd *priv = chip->priv; | |
526 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
527 | unsigned int bufsize = mtd->writesize + mtd->oobsize; | |
528 | ||
9c814b0a | 529 | if (len <= 0) { |
9fd020d6 SW |
530 | printf("write_buf of %d bytes", len); |
531 | ctrl->status = 0; | |
532 | return; | |
533 | } | |
534 | ||
535 | if ((unsigned int)len > bufsize - ctrl->index) { | |
536 | printf("write_buf beyond end of buffer " | |
537 | "(%d requested, %u available)\n", | |
538 | len, bufsize - ctrl->index); | |
539 | len = bufsize - ctrl->index; | |
540 | } | |
541 | ||
542 | memcpy_toio(&ctrl->addr[ctrl->index], buf, len); | |
9c814b0a AV |
543 | /* |
544 | * This is workaround for the weird elbc hangs during nand write, | |
545 | * Scott Wood says: "...perhaps difference in how long it takes a | |
546 | * write to make it through the localbus compared to a write to IMMR | |
547 | * is causing problems, and sync isn't helping for some reason." | |
548 | * Reading back the last byte helps though. | |
549 | */ | |
550 | in_8(&ctrl->addr[ctrl->index] + len - 1); | |
551 | ||
9fd020d6 SW |
552 | ctrl->index += len; |
553 | } | |
554 | ||
555 | /* | |
556 | * read a byte from either the FCM hardware buffer if it has any data left | |
557 | * otherwise issue a command to read a single byte. | |
558 | */ | |
559 | static u8 fsl_elbc_read_byte(struct mtd_info *mtd) | |
560 | { | |
561 | struct nand_chip *chip = mtd->priv; | |
562 | struct fsl_elbc_mtd *priv = chip->priv; | |
563 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
564 | ||
565 | /* If there are still bytes in the FCM, then use the next byte. */ | |
566 | if (ctrl->index < ctrl->read_bytes) | |
567 | return in_8(&ctrl->addr[ctrl->index++]); | |
568 | ||
569 | printf("read_byte beyond end of buffer\n"); | |
570 | return ERR_BYTE; | |
571 | } | |
572 | ||
573 | /* | |
574 | * Read from the FCM Controller Data Buffer | |
575 | */ | |
576 | static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
577 | { | |
578 | struct nand_chip *chip = mtd->priv; | |
579 | struct fsl_elbc_mtd *priv = chip->priv; | |
580 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
581 | int avail; | |
582 | ||
583 | if (len < 0) | |
584 | return; | |
585 | ||
586 | avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index); | |
587 | memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail); | |
588 | ctrl->index += avail; | |
589 | ||
590 | if (len > avail) | |
591 | printf("read_buf beyond end of buffer " | |
592 | "(%d requested, %d available)\n", | |
593 | len, avail); | |
594 | } | |
595 | ||
596 | /* | |
597 | * Verify buffer against the FCM Controller Data Buffer | |
598 | */ | |
599 | static int fsl_elbc_verify_buf(struct mtd_info *mtd, | |
4b070809 | 600 | const u_char *buf, int len) |
9fd020d6 SW |
601 | { |
602 | struct nand_chip *chip = mtd->priv; | |
603 | struct fsl_elbc_mtd *priv = chip->priv; | |
604 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
605 | int i; | |
606 | ||
607 | if (len < 0) { | |
608 | printf("write_buf of %d bytes", len); | |
609 | return -EINVAL; | |
610 | } | |
611 | ||
612 | if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { | |
613 | printf("verify_buf beyond end of buffer " | |
614 | "(%d requested, %u available)\n", | |
615 | len, ctrl->read_bytes - ctrl->index); | |
616 | ||
617 | ctrl->index = ctrl->read_bytes; | |
618 | return -EINVAL; | |
619 | } | |
620 | ||
621 | for (i = 0; i < len; i++) | |
622 | if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) | |
623 | break; | |
624 | ||
625 | ctrl->index += len; | |
626 | return i == len && ctrl->status == LTESR_CC ? 0 : -EIO; | |
627 | } | |
628 | ||
629 | /* This function is called after Program and Erase Operations to | |
630 | * check for success or failure. | |
631 | */ | |
632 | static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
633 | { | |
634 | struct fsl_elbc_mtd *priv = chip->priv; | |
635 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
4e190b03 | 636 | fsl_lbus_t *lbc = ctrl->regs; |
9fd020d6 SW |
637 | |
638 | if (ctrl->status != LTESR_CC) | |
639 | return NAND_STATUS_FAIL; | |
640 | ||
641 | /* Use READ_STATUS command, but wait for the device to be ready */ | |
642 | ctrl->use_mdr = 0; | |
643 | out_be32(&lbc->fir, | |
4b070809 WD |
644 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | |
645 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
9fd020d6 SW |
646 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); |
647 | out_be32(&lbc->fbcr, 1); | |
648 | set_addr(mtd, 0, 0, 0); | |
649 | ctrl->read_bytes = 1; | |
650 | ||
651 | fsl_elbc_run_command(mtd); | |
652 | ||
653 | if (ctrl->status != LTESR_CC) | |
654 | return NAND_STATUS_FAIL; | |
655 | ||
656 | /* The chip always seems to report that it is | |
657 | * write-protected, even when it is not. | |
658 | */ | |
659 | out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); | |
660 | return fsl_elbc_read_byte(mtd); | |
661 | } | |
662 | ||
663 | static int fsl_elbc_read_page(struct mtd_info *mtd, | |
4b070809 | 664 | struct nand_chip *chip, |
a2c65b47 | 665 | uint8_t *buf, int page) |
9fd020d6 SW |
666 | { |
667 | fsl_elbc_read_buf(mtd, buf, mtd->writesize); | |
668 | fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
669 | ||
670 | if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) | |
671 | mtd->ecc_stats.failed++; | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | /* ECC will be calculated automatically, and errors will be detected in | |
677 | * waitfunc. | |
678 | */ | |
679 | static void fsl_elbc_write_page(struct mtd_info *mtd, | |
4b070809 WD |
680 | struct nand_chip *chip, |
681 | const uint8_t *buf) | |
9fd020d6 SW |
682 | { |
683 | struct fsl_elbc_mtd *priv = chip->priv; | |
684 | struct fsl_elbc_ctrl *ctrl = priv->ctrl; | |
685 | ||
686 | fsl_elbc_write_buf(mtd, buf, mtd->writesize); | |
687 | fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
688 | ||
689 | ctrl->oob_poi = chip->oob_poi; | |
690 | } | |
691 | ||
692 | static struct fsl_elbc_ctrl *elbc_ctrl; | |
693 | ||
694 | static void fsl_elbc_ctrl_init(void) | |
695 | { | |
9fd020d6 SW |
696 | elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL); |
697 | if (!elbc_ctrl) | |
698 | return; | |
699 | ||
4e190b03 HW |
700 | #ifdef CONFIG_MPC85xx |
701 | elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR; | |
702 | #else | |
703 | elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus; | |
704 | #endif | |
9fd020d6 SW |
705 | |
706 | /* clear event registers */ | |
707 | out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK); | |
708 | out_be32(&elbc_ctrl->regs->lteatr, 0); | |
709 | ||
710 | /* Enable interrupts for any detected events */ | |
711 | out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK); | |
712 | ||
713 | elbc_ctrl->read_bytes = 0; | |
714 | elbc_ctrl->index = 0; | |
715 | elbc_ctrl->addr = NULL; | |
716 | } | |
717 | ||
718 | int board_nand_init(struct nand_chip *nand) | |
719 | { | |
720 | struct fsl_elbc_mtd *priv; | |
9d94aff6 | 721 | uint32_t br = 0, or = 0; |
9fd020d6 SW |
722 | |
723 | if (!elbc_ctrl) { | |
724 | fsl_elbc_ctrl_init(); | |
725 | if (!elbc_ctrl) | |
726 | return -1; | |
727 | } | |
728 | ||
729 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
730 | if (!priv) | |
731 | return -ENOMEM; | |
732 | ||
733 | priv->ctrl = elbc_ctrl; | |
734 | priv->vbase = nand->IO_ADDR_R; | |
735 | ||
736 | /* Find which chip select it is connected to. It'd be nice | |
737 | * if we could pass more than one datum to the NAND driver... | |
738 | */ | |
739 | for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { | |
9d94aff6 KG |
740 | phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R); |
741 | ||
9fd020d6 SW |
742 | br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br); |
743 | or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or); | |
744 | ||
745 | if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM && | |
9d94aff6 | 746 | (br & or & BR_BA) == BR_PHYS_ADDR(base_addr)) |
9fd020d6 SW |
747 | break; |
748 | } | |
749 | ||
750 | if (priv->bank >= MAX_BANKS) { | |
751 | printf("fsl_elbc_nand: address did not match any " | |
752 | "chip selects\n"); | |
753 | return -ENODEV; | |
754 | } | |
755 | ||
756 | elbc_ctrl->chips[priv->bank] = priv; | |
757 | ||
758 | /* fill in nand_chip structure */ | |
759 | /* set up function call table */ | |
760 | nand->read_byte = fsl_elbc_read_byte; | |
761 | nand->write_buf = fsl_elbc_write_buf; | |
762 | nand->read_buf = fsl_elbc_read_buf; | |
763 | nand->verify_buf = fsl_elbc_verify_buf; | |
764 | nand->select_chip = fsl_elbc_select_chip; | |
765 | nand->cmdfunc = fsl_elbc_cmdfunc; | |
766 | nand->waitfunc = fsl_elbc_wait; | |
767 | ||
768 | /* set up nand options */ | |
8f42bf1c AV |
769 | nand->bbt_td = &bbt_main_descr; |
770 | nand->bbt_md = &bbt_mirror_descr; | |
771 | ||
772 | /* set up nand options */ | |
773 | nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR | | |
774 | NAND_USE_FLASH_BBT; | |
9fd020d6 SW |
775 | |
776 | nand->controller = &elbc_ctrl->controller; | |
777 | nand->priv = priv; | |
778 | ||
779 | nand->ecc.read_page = fsl_elbc_read_page; | |
780 | nand->ecc.write_page = fsl_elbc_write_page; | |
781 | ||
f7fe57c0 SW |
782 | #ifdef CONFIG_FSL_ELBC_FMR |
783 | priv->fmr = CONFIG_FSL_ELBC_FMR; | |
784 | #else | |
785 | priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT); | |
786 | ||
787 | /* | |
788 | * Hardware expects small page has ECCM0, large page has ECCM1 | |
789 | * when booting from NAND. Board config can override if not | |
790 | * booting from NAND. | |
791 | */ | |
792 | if (or & OR_FCM_PGS) | |
793 | priv->fmr |= FMR_ECCM; | |
794 | #endif | |
795 | ||
9fd020d6 SW |
796 | /* If CS Base Register selects full hardware ECC then use it */ |
797 | if ((br & BR_DECC) == BR_DECC_CHK_GEN) { | |
798 | nand->ecc.mode = NAND_ECC_HW; | |
799 | ||
800 | nand->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
4b070809 WD |
801 | &fsl_elbc_oob_sp_eccm1 : |
802 | &fsl_elbc_oob_sp_eccm0; | |
9fd020d6 SW |
803 | |
804 | nand->ecc.size = 512; | |
805 | nand->ecc.bytes = 3; | |
806 | nand->ecc.steps = 1; | |
807 | } else { | |
808 | /* otherwise fall back to default software ECC */ | |
809 | nand->ecc.mode = NAND_ECC_SOFT; | |
810 | } | |
811 | ||
97ae0236 | 812 | /* Large-page-specific setup */ |
9fd020d6 SW |
813 | if (or & OR_FCM_PGS) { |
814 | priv->page_size = 1; | |
97ae0236 | 815 | nand->badblock_pattern = &largepage_memorybased; |
9fd020d6 SW |
816 | |
817 | /* adjust ecc setup if needed */ | |
818 | if ((br & BR_DECC) == BR_DECC_CHK_GEN) { | |
819 | nand->ecc.steps = 4; | |
820 | nand->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
4b070809 WD |
821 | &fsl_elbc_oob_lp_eccm1 : |
822 | &fsl_elbc_oob_lp_eccm0; | |
9fd020d6 SW |
823 | } |
824 | } | |
825 | ||
826 | return 0; | |
827 | } |