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fsl_elbc_nand: workaround for hangs during nand write
[people/ms/u-boot.git] / drivers / mtd / nand / fsl_elbc_nand.c
CommitLineData
9fd020d6
SW		 1/* Freescale Enhanced Local Bus Controller FCM NAND driver
2 *
3 * Copyright (c) 2006-2008 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <malloc.h>
25
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29
30#include <asm/io.h>
31#include <asm/errno.h>
32
33#ifdef VERBOSE_DEBUG
34#define DEBUG_ELBC
35#define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
36#else
37#define vdbg(format, arg...) do {} while (0)
38#endif
39
40/* Can't use plain old DEBUG because the linux mtd
41 * headers define it as a macro.
42 */
43#ifdef DEBUG_ELBC
44#define dbg(format, arg...) printf("DEBUG: " format, ##arg)
45#else
46#define dbg(format, arg...) do {} while (0)
47#endif
48
49#define MAX_BANKS 8
50#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
51#define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
52
53#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
54
55struct fsl_elbc_ctrl;
56
57/* mtd information per set */
58
59struct fsl_elbc_mtd {
60 struct mtd_info mtd;
61 struct nand_chip chip;
62 struct fsl_elbc_ctrl *ctrl;
63
64 struct device *dev;
65 int bank; /* Chip select bank number */
66 u8 __iomem *vbase; /* Chip select base virtual address */
67 int page_size; /* NAND page size (0=512, 1=2048) */
68 unsigned int fmr; /* FCM Flash Mode Register value */
69};
70
71/* overview of the fsl elbc controller */
72
73struct fsl_elbc_ctrl {
74 struct nand_hw_control controller;
75 struct fsl_elbc_mtd *chips[MAX_BANKS];
76
77 /* device info */
78 lbus83xx_t *regs;
79 u8 __iomem *addr; /* Address of assigned FCM buffer */
80 unsigned int page; /* Last page written to / read from */
81 unsigned int read_bytes; /* Number of bytes read during command */
82 unsigned int column; /* Saved column from SEQIN */
83 unsigned int index; /* Pointer to next byte to 'read' */
84 unsigned int status; /* status read from LTESR after last op */
85 unsigned int mdr; /* UPM/FCM Data Register value */
86 unsigned int use_mdr; /* Non zero if the MDR is to be set */
87 unsigned int oob; /* Non zero if operating on OOB data */
88 uint8_t *oob_poi; /* Place to write ECC after read back */
89};
90
91/* These map to the positions used by the FCM hardware ECC generator */
92
93/* Small Page FLASH with FMR[ECCM] = 0 */
94static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
95 .eccbytes = 3,
96 .eccpos = {6, 7, 8},
97 .oobfree = { {0, 5}, {9, 7} },
98 .oobavail = 12,
99};
100
101/* Small Page FLASH with FMR[ECCM] = 1 */
102static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
103 .eccbytes = 3,
104 .eccpos = {8, 9, 10},
105 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
106 .oobavail = 12,
107};
108
109/* Large Page FLASH with FMR[ECCM] = 0 */
110static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
111 .eccbytes = 12,
112 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
113 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
114 .oobavail = 48,
115};
116
117/* Large Page FLASH with FMR[ECCM] = 1 */
118static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
119 .eccbytes = 12,
120 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
121 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
122 .oobavail = 48,
123};
124
125/*=================================*/
126
127/*
128 * Set up the FCM hardware block and page address fields, and the fcm
129 * structure addr field to point to the correct FCM buffer in memory
130 */
131static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
132{
133 struct nand_chip *chip = mtd->priv;
134 struct fsl_elbc_mtd *priv = chip->priv;
135 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
136 lbus83xx_t *lbc = ctrl->regs;
137 int buf_num;
138
139 ctrl->page = page_addr;
140
141 out_be32(&lbc->fbar,
142 page_addr >> (chip->phys_erase_shift - chip->page_shift));
143
144 if (priv->page_size) {
145 out_be32(&lbc->fpar,
146 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
147 (oob ? FPAR_LP_MS : 0) | column);
148 buf_num = (page_addr & 1) << 2;
149 } else {
150 out_be32(&lbc->fpar,
151 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
152 (oob ? FPAR_SP_MS : 0) | column);
153 buf_num = page_addr & 7;
154 }
155
156 ctrl->addr = priv->vbase + buf_num * 1024;
157 ctrl->index = column;
158
159 /* for OOB data point to the second half of the buffer */
160 if (oob)
161 ctrl->index += priv->page_size ? 2048 : 512;
162
163 vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
164 "index %x, pes %d ps %d\n",
165 buf_num, ctrl->addr, priv->vbase, ctrl->index,
166 chip->phys_erase_shift, chip->page_shift);
167}
168
169/*
170 * execute FCM command and wait for it to complete
171 */
172static int fsl_elbc_run_command(struct mtd_info *mtd)
173{
174 struct nand_chip *chip = mtd->priv;
175 struct fsl_elbc_mtd *priv = chip->priv;
176 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
177 lbus83xx_t *lbc = ctrl->regs;
178 long long end_tick;
179 u32 ltesr;
180
181 /* Setup the FMR[OP] to execute without write protection */
182 out_be32(&lbc->fmr, priv->fmr | 3);
183 if (ctrl->use_mdr)
184 out_be32(&lbc->mdr, ctrl->mdr);
185
186 vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
187 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
188 vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
189 "fbcr=%08x bank=%d\n",
190 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
191 in_be32(&lbc->fbcr), priv->bank);
192
193 /* execute special operation */
194 out_be32(&lbc->lsor, priv->bank);
195
196 /* wait for FCM complete flag or timeout */
197 end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
198
199 ltesr = 0;
200 while (end_tick > get_ticks()) {
201 ltesr = in_be32(&lbc->ltesr);
202 if (ltesr & LTESR_CC)
203 break;
204 }
205
206 ctrl->status = ltesr & LTESR_NAND_MASK;
207 out_be32(&lbc->ltesr, ctrl->status);
208 out_be32(&lbc->lteatr, 0);
209
210 /* store mdr value in case it was needed */
211 if (ctrl->use_mdr)
212 ctrl->mdr = in_be32(&lbc->mdr);
213
214 ctrl->use_mdr = 0;
215
216 vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
217 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
218
219 /* returns 0 on success otherwise non-zero) */
220 return ctrl->status == LTESR_CC ? 0 : -EIO;
221}
222
223static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
224{
225 struct fsl_elbc_mtd *priv = chip->priv;
226 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
227 lbus83xx_t *lbc = ctrl->regs;
228
229 if (priv->page_size) {
230 out_be32(&lbc->fir,
231 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
232 (FIR_OP_CA << FIR_OP1_SHIFT) |
233 (FIR_OP_PA << FIR_OP2_SHIFT) |
234 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
235 (FIR_OP_RBW << FIR_OP4_SHIFT));
236
237 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
238 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
239 } else {
240 out_be32(&lbc->fir,
241 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
242 (FIR_OP_CA << FIR_OP1_SHIFT) |
243 (FIR_OP_PA << FIR_OP2_SHIFT) |
244 (FIR_OP_RBW << FIR_OP3_SHIFT));
245
246 if (oob)
247 out_be32(&lbc->fcr,
248 NAND_CMD_READOOB << FCR_CMD0_SHIFT);
249 else
250 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
251 }
252}
253
254/* cmdfunc send commands to the FCM */
255static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
256 int column, int page_addr)
257{
258 struct nand_chip *chip = mtd->priv;
259 struct fsl_elbc_mtd *priv = chip->priv;
260 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
261 lbus83xx_t *lbc = ctrl->regs;
262
263 ctrl->use_mdr = 0;
264
265 /* clear the read buffer */
266 ctrl->read_bytes = 0;
267 if (command != NAND_CMD_PAGEPROG)
268 ctrl->index = 0;
269
270 switch (command) {
271 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
272 case NAND_CMD_READ1:
273 column += 256;
274
275 /* fall-through */
276 case NAND_CMD_READ0:
277 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
278 " 0x%x, column: 0x%x.\n", page_addr, column);
279
280 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
281 set_addr(mtd, 0, page_addr, 0);
282
283 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
284 ctrl->index += column;
285
286 fsl_elbc_do_read(chip, 0);
287 fsl_elbc_run_command(mtd);
288 return;
289
290 /* READOOB reads only the OOB because no ECC is performed. */
291 case NAND_CMD_READOOB:
292 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
293 " 0x%x, column: 0x%x.\n", page_addr, column);
294
295 out_be32(&lbc->fbcr, mtd->oobsize - column);
296 set_addr(mtd, column, page_addr, 1);
297
298 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
299
300 fsl_elbc_do_read(chip, 1);
301 fsl_elbc_run_command(mtd);
302
303 return;
304
305 /* READID must read all 5 possible bytes while CEB is active */
306 case NAND_CMD_READID:
307 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
308
309 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
310 (FIR_OP_UA << FIR_OP1_SHIFT) |
311 (FIR_OP_RBW << FIR_OP2_SHIFT));
312 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
313 /* 5 bytes for manuf, device and exts */
314 out_be32(&lbc->fbcr, 5);
315 ctrl->read_bytes = 5;
316 ctrl->use_mdr = 1;
317 ctrl->mdr = 0;
318
319 set_addr(mtd, 0, 0, 0);
320 fsl_elbc_run_command(mtd);
321 return;
322
323 /* ERASE1 stores the block and page address */
324 case NAND_CMD_ERASE1:
325 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
326 "page_addr: 0x%x.\n", page_addr);
327 set_addr(mtd, 0, page_addr, 0);
328 return;
329
330 /* ERASE2 uses the block and page address from ERASE1 */
331 case NAND_CMD_ERASE2:
332 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
333
334 out_be32(&lbc->fir,
335 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
336 (FIR_OP_PA << FIR_OP1_SHIFT) |
337 (FIR_OP_CM1 << FIR_OP2_SHIFT));
338
339 out_be32(&lbc->fcr,
340 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
341 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
342
343 out_be32(&lbc->fbcr, 0);
344 ctrl->read_bytes = 0;
345
346 fsl_elbc_run_command(mtd);
347 return;
348
349 /* SEQIN sets up the addr buffer and all registers except the length */
350 case NAND_CMD_SEQIN: {
351 u32 fcr;
352 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
353 "page_addr: 0x%x, column: 0x%x.\n",
354 page_addr, column);
355
356 ctrl->column = column;
357 ctrl->oob = 0;
358
359 if (priv->page_size) {
360 fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
361 (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
362
363 out_be32(&lbc->fir,
364 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
365 (FIR_OP_CA << FIR_OP1_SHIFT) |
366 (FIR_OP_PA << FIR_OP2_SHIFT) |
367 (FIR_OP_WB << FIR_OP3_SHIFT) |
368 (FIR_OP_CW1 << FIR_OP4_SHIFT));
369 } else {
370 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
371 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
372
373 out_be32(&lbc->fir,
374 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
375 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
376 (FIR_OP_CA << FIR_OP2_SHIFT) |
377 (FIR_OP_PA << FIR_OP3_SHIFT) |
378 (FIR_OP_WB << FIR_OP4_SHIFT) |
379 (FIR_OP_CW1 << FIR_OP5_SHIFT));
380
381 if (column >= mtd->writesize) {
382 /* OOB area --> READOOB */
383 column -= mtd->writesize;
384 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
385 ctrl->oob = 1;
386 } else if (column < 256) {
387 /* First 256 bytes --> READ0 */
388 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
389 } else {
390 /* Second 256 bytes --> READ1 */
391 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
392 }
393 }
394
395 out_be32(&lbc->fcr, fcr);
396 set_addr(mtd, column, page_addr, ctrl->oob);
397 return;
398 }
399
400 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
401 case NAND_CMD_PAGEPROG: {
402 int full_page;
403 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
404 "writing %d bytes.\n", ctrl->index);
405
406 /* if the write did not start at 0 or is not a full page
407 * then set the exact length, otherwise use a full page
408 * write so the HW generates the ECC.
409 */
410 if (ctrl->oob || ctrl->column != 0 ||
411 ctrl->index != mtd->writesize + mtd->oobsize) {
412 out_be32(&lbc->fbcr, ctrl->index);
413 full_page = 0;
414 } else {
415 out_be32(&lbc->fbcr, 0);
416 full_page = 1;
417 }
418
419 fsl_elbc_run_command(mtd);
420
421 /* Read back the page in order to fill in the ECC for the
422 * caller. Is this really needed?
423 */
424 if (full_page && ctrl->oob_poi) {
425 out_be32(&lbc->fbcr, 3);
426 set_addr(mtd, 6, page_addr, 1);
427
428 ctrl->read_bytes = mtd->writesize + 9;
429
430 fsl_elbc_do_read(chip, 1);
431 fsl_elbc_run_command(mtd);
432
433 memcpy_fromio(ctrl->oob_poi + 6,
434 &ctrl->addr[ctrl->index], 3);
435 ctrl->index += 3;
436 }
437
438 ctrl->oob_poi = NULL;
439 return;
440 }
441
442 /* CMD_STATUS must read the status byte while CEB is active */
443 /* Note - it does not wait for the ready line */
444 case NAND_CMD_STATUS:
445 out_be32(&lbc->fir,
446 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
447 (FIR_OP_RBW << FIR_OP1_SHIFT));
448 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
449 out_be32(&lbc->fbcr, 1);
450 set_addr(mtd, 0, 0, 0);
451 ctrl->read_bytes = 1;
452
453 fsl_elbc_run_command(mtd);
454
455 /* The chip always seems to report that it is
456 * write-protected, even when it is not.
457 */
458 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
459 return;
460
461 /* RESET without waiting for the ready line */
462 case NAND_CMD_RESET:
463 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
464 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
465 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
466 fsl_elbc_run_command(mtd);
467 return;
468
469 default:
470 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
471 command);
472 }
473}
474
475static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
476{
477 /* The hardware does not seem to support multiple
478 * chips per bank.
479 */
480}
481
482/*
483 * Write buf to the FCM Controller Data Buffer
484 */
485static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
486{
487 struct nand_chip *chip = mtd->priv;
488 struct fsl_elbc_mtd *priv = chip->priv;
489 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
490 unsigned int bufsize = mtd->writesize + mtd->oobsize;
491
9c814b0a 492 if (len <= 0) {
9fd020d6
SW		 493 printf("write_buf of %d bytes", len);
494 ctrl->status = 0;
495 return;
496 }
497
498 if ((unsigned int)len > bufsize - ctrl->index) {
499 printf("write_buf beyond end of buffer "
500 "(%d requested, %u available)\n",
501 len, bufsize - ctrl->index);
502 len = bufsize - ctrl->index;
503 }
504
505 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
9c814b0a
AV		 506 /*
507 * This is workaround for the weird elbc hangs during nand write,
508 * Scott Wood says: "...perhaps difference in how long it takes a
509 * write to make it through the localbus compared to a write to IMMR
510 * is causing problems, and sync isn't helping for some reason."
511 * Reading back the last byte helps though.
512 */
513 in_8(&ctrl->addr[ctrl->index] + len - 1);
514
9fd020d6
SW		 515 ctrl->index += len;
516}
517
518/*
519 * read a byte from either the FCM hardware buffer if it has any data left
520 * otherwise issue a command to read a single byte.
521 */
522static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
523{
524 struct nand_chip *chip = mtd->priv;
525 struct fsl_elbc_mtd *priv = chip->priv;
526 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
527
528 /* If there are still bytes in the FCM, then use the next byte. */
529 if (ctrl->index < ctrl->read_bytes)
530 return in_8(&ctrl->addr[ctrl->index++]);
531
532 printf("read_byte beyond end of buffer\n");
533 return ERR_BYTE;
534}
535
536/*
537 * Read from the FCM Controller Data Buffer
538 */
539static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
540{
541 struct nand_chip *chip = mtd->priv;
542 struct fsl_elbc_mtd *priv = chip->priv;
543 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
544 int avail;
545
546 if (len < 0)
547 return;
548
549 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
550 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
551 ctrl->index += avail;
552
553 if (len > avail)
554 printf("read_buf beyond end of buffer "
555 "(%d requested, %d available)\n",
556 len, avail);
557}
558
559/*
560 * Verify buffer against the FCM Controller Data Buffer
561 */
562static int fsl_elbc_verify_buf(struct mtd_info *mtd,
563 const u_char *buf, int len)
564{
565 struct nand_chip *chip = mtd->priv;
566 struct fsl_elbc_mtd *priv = chip->priv;
567 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
568 int i;
569
570 if (len < 0) {
571 printf("write_buf of %d bytes", len);
572 return -EINVAL;
573 }
574
575 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
576 printf("verify_buf beyond end of buffer "
577 "(%d requested, %u available)\n",
578 len, ctrl->read_bytes - ctrl->index);
579
580 ctrl->index = ctrl->read_bytes;
581 return -EINVAL;
582 }
583
584 for (i = 0; i < len; i++)
585 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
586 break;
587
588 ctrl->index += len;
589 return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
590}
591
592/* This function is called after Program and Erase Operations to
593 * check for success or failure.
594 */
595static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
596{
597 struct fsl_elbc_mtd *priv = chip->priv;
598 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
599 lbus83xx_t *lbc = ctrl->regs;
600
601 if (ctrl->status != LTESR_CC)
602 return NAND_STATUS_FAIL;
603
604 /* Use READ_STATUS command, but wait for the device to be ready */
605 ctrl->use_mdr = 0;
606 out_be32(&lbc->fir,
607 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
608 (FIR_OP_RBW << FIR_OP1_SHIFT));
609 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
610 out_be32(&lbc->fbcr, 1);
611 set_addr(mtd, 0, 0, 0);
612 ctrl->read_bytes = 1;
613
614 fsl_elbc_run_command(mtd);
615
616 if (ctrl->status != LTESR_CC)
617 return NAND_STATUS_FAIL;
618
619 /* The chip always seems to report that it is
620 * write-protected, even when it is not.
621 */
622 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
623 return fsl_elbc_read_byte(mtd);
624}
625
626static int fsl_elbc_read_page(struct mtd_info *mtd,
627 struct nand_chip *chip,
628 uint8_t *buf)
629{
630 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
631 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
632
633 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
634 mtd->ecc_stats.failed++;
635
636 return 0;
637}
638
639/* ECC will be calculated automatically, and errors will be detected in
640 * waitfunc.
641 */
642static void fsl_elbc_write_page(struct mtd_info *mtd,
643 struct nand_chip *chip,
644 const uint8_t *buf)
645{
646 struct fsl_elbc_mtd *priv = chip->priv;
647 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
648
649 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
650 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
651
652 ctrl->oob_poi = chip->oob_poi;
653}
654
655static struct fsl_elbc_ctrl *elbc_ctrl;
656
657static void fsl_elbc_ctrl_init(void)
658{
659 immap_t *im = (immap_t *)CFG_IMMR;
660
661 elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
662 if (!elbc_ctrl)
663 return;
664
665 elbc_ctrl->regs = &im->lbus;
666
667 /* clear event registers */
668 out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
669 out_be32(&elbc_ctrl->regs->lteatr, 0);
670
671 /* Enable interrupts for any detected events */
672 out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
673
674 elbc_ctrl->read_bytes = 0;
675 elbc_ctrl->index = 0;
676 elbc_ctrl->addr = NULL;
677}
678
679int board_nand_init(struct nand_chip *nand)
680{
681 struct fsl_elbc_mtd *priv;
682 uint32_t br, or;
683
684 if (!elbc_ctrl) {
685 fsl_elbc_ctrl_init();
686 if (!elbc_ctrl)
687 return -1;
688 }
689
690 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
691 if (!priv)
692 return -ENOMEM;
693
694 priv->ctrl = elbc_ctrl;
695 priv->vbase = nand->IO_ADDR_R;
696
697 /* Find which chip select it is connected to. It'd be nice
698 * if we could pass more than one datum to the NAND driver...
699 */
700 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
701 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
702 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
703
704 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
705 (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R)
706 break;
707 }
708
709 if (priv->bank >= MAX_BANKS) {
710 printf("fsl_elbc_nand: address did not match any "
711 "chip selects\n");
712 return -ENODEV;
713 }
714
715 elbc_ctrl->chips[priv->bank] = priv;
716
717 /* fill in nand_chip structure */
718 /* set up function call table */
719 nand->read_byte = fsl_elbc_read_byte;
720 nand->write_buf = fsl_elbc_write_buf;
721 nand->read_buf = fsl_elbc_read_buf;
722 nand->verify_buf = fsl_elbc_verify_buf;
723 nand->select_chip = fsl_elbc_select_chip;
724 nand->cmdfunc = fsl_elbc_cmdfunc;
725 nand->waitfunc = fsl_elbc_wait;
726
727 /* set up nand options */
728 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
729
730 nand->controller = &elbc_ctrl->controller;
731 nand->priv = priv;
732
733 nand->ecc.read_page = fsl_elbc_read_page;
734 nand->ecc.write_page = fsl_elbc_write_page;
735
736 /* If CS Base Register selects full hardware ECC then use it */
737 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
738 nand->ecc.mode = NAND_ECC_HW;
739
740 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
741 &fsl_elbc_oob_sp_eccm1 :
742 &fsl_elbc_oob_sp_eccm0;
743
744 nand->ecc.size = 512;
745 nand->ecc.bytes = 3;
746 nand->ecc.steps = 1;
747 } else {
748 /* otherwise fall back to default software ECC */
749 nand->ecc.mode = NAND_ECC_SOFT;
750 }
751
752 priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
753
754 /* adjust Option Register and ECC to match Flash page size */
755 if (or & OR_FCM_PGS) {
756 priv->page_size = 1;
757
758 /* adjust ecc setup if needed */
759 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
760 nand->ecc.steps = 4;
761 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
762 &fsl_elbc_oob_lp_eccm1 :
763 &fsl_elbc_oob_lp_eccm0;
764 }
765 }
766
767 return 0;
768}
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