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[thirdparty/u-boot.git] / drivers / mtd / nand / fsl_ifc_nand.c
CommitLineData
52f90dad
DD		 1/* Integrated Flash Controller NAND Machine Driver
2 *
5f720b85 3 * Copyright (c) 2012 Freescale Semiconductor, Inc
52f90dad
DD		 4 *
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
52f90dad
DD		 8 */
9
10#include <common.h>
11#include <malloc.h>
a1b81ab2 12#include <nand.h>
52f90dad
DD		 13
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/nand.h>
16#include <linux/mtd/nand_ecc.h>
17
18#include <asm/io.h>
19#include <asm/errno.h>
20#include <asm/fsl_ifc.h>
21
79da5e3d 22#define FSL_IFC_V1_1_0 0x01010000
52f90dad
DD		 23#define MAX_BANKS 4
24#define ERR_BYTE 0xFF /* Value returned for read bytes
25 when read failed */
26#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
27 NAND Machine */
28
29struct fsl_ifc_ctrl;
30
31/* mtd information per set */
32struct fsl_ifc_mtd {
52f90dad
DD		 33 struct nand_chip chip;
34 struct fsl_ifc_ctrl *ctrl;
35
36 struct device *dev;
37 int bank; /* Chip select bank number */
38 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
39 u8 __iomem *vbase; /* Chip select base virtual address */
40};
41
42/* overview of the fsl ifc controller */
43struct fsl_ifc_ctrl {
44 struct nand_hw_control controller;
45 struct fsl_ifc_mtd *chips[MAX_BANKS];
46
47 /* device info */
48 struct fsl_ifc *regs;
49 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
50 unsigned int cs_nand; /* On which chipsel NAND is connected */
51 unsigned int page; /* Last page written to / read from */
52 unsigned int read_bytes; /* Number of bytes read during command */
53 unsigned int column; /* Saved column from SEQIN */
54 unsigned int index; /* Pointer to next byte to 'read' */
55 unsigned int status; /* status read from NEESR after last op */
56 unsigned int oob; /* Non zero if operating on OOB data */
57 unsigned int eccread; /* Non zero for a full-page ECC read */
58};
59
60static struct fsl_ifc_ctrl *ifc_ctrl;
61
62/* 512-byte page with 4-bit ECC, 8-bit */
63static struct nand_ecclayout oob_512_8bit_ecc4 = {
64 .eccbytes = 8,
65 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
66 .oobfree = { {0, 5}, {6, 2} },
67};
68
69/* 512-byte page with 4-bit ECC, 16-bit */
70static struct nand_ecclayout oob_512_16bit_ecc4 = {
71 .eccbytes = 8,
72 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
73 .oobfree = { {2, 6}, },
74};
75
76/* 2048-byte page size with 4-bit ECC */
77static struct nand_ecclayout oob_2048_ecc4 = {
78 .eccbytes = 32,
79 .eccpos = {
80 8, 9, 10, 11, 12, 13, 14, 15,
81 16, 17, 18, 19, 20, 21, 22, 23,
82 24, 25, 26, 27, 28, 29, 30, 31,
83 32, 33, 34, 35, 36, 37, 38, 39,
84 },
85 .oobfree = { {2, 6}, {40, 24} },
86};
87
88/* 4096-byte page size with 4-bit ECC */
89static struct nand_ecclayout oob_4096_ecc4 = {
90 .eccbytes = 64,
91 .eccpos = {
92 8, 9, 10, 11, 12, 13, 14, 15,
93 16, 17, 18, 19, 20, 21, 22, 23,
94 24, 25, 26, 27, 28, 29, 30, 31,
95 32, 33, 34, 35, 36, 37, 38, 39,
96 40, 41, 42, 43, 44, 45, 46, 47,
97 48, 49, 50, 51, 52, 53, 54, 55,
98 56, 57, 58, 59, 60, 61, 62, 63,
99 64, 65, 66, 67, 68, 69, 70, 71,
100 },
101 .oobfree = { {2, 6}, {72, 56} },
102};
103
104/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
105static struct nand_ecclayout oob_4096_ecc8 = {
106 .eccbytes = 128,
107 .eccpos = {
108 8, 9, 10, 11, 12, 13, 14, 15,
109 16, 17, 18, 19, 20, 21, 22, 23,
110 24, 25, 26, 27, 28, 29, 30, 31,
111 32, 33, 34, 35, 36, 37, 38, 39,
112 40, 41, 42, 43, 44, 45, 46, 47,
113 48, 49, 50, 51, 52, 53, 54, 55,
114 56, 57, 58, 59, 60, 61, 62, 63,
115 64, 65, 66, 67, 68, 69, 70, 71,
116 72, 73, 74, 75, 76, 77, 78, 79,
117 80, 81, 82, 83, 84, 85, 86, 87,
118 88, 89, 90, 91, 92, 93, 94, 95,
119 96, 97, 98, 99, 100, 101, 102, 103,
120 104, 105, 106, 107, 108, 109, 110, 111,
121 112, 113, 114, 115, 116, 117, 118, 119,
122 120, 121, 122, 123, 124, 125, 126, 127,
123 128, 129, 130, 131, 132, 133, 134, 135,
124 },
125 .oobfree = { {2, 6}, {136, 82} },
126};
127
128
129/*
130 * Generic flash bbt descriptors
131 */
132static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
133static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
134
135static struct nand_bbt_descr bbt_main_descr = {
136 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
137 NAND_BBT_2BIT | NAND_BBT_VERSION,
138 .offs = 2, /* 0 on 8-bit small page */
139 .len = 4,
140 .veroffs = 6,
141 .maxblocks = 4,
142 .pattern = bbt_pattern,
143};
144
145static struct nand_bbt_descr bbt_mirror_descr = {
146 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
147 NAND_BBT_2BIT | NAND_BBT_VERSION,
148 .offs = 2, /* 0 on 8-bit small page */
149 .len = 4,
150 .veroffs = 6,
151 .maxblocks = 4,
152 .pattern = mirror_pattern,
153};
154
155/*
156 * Set up the IFC hardware block and page address fields, and the ifc nand
157 * structure addr field to point to the correct IFC buffer in memory
158 */
159static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
160{
161 struct nand_chip *chip = mtd->priv;
162 struct fsl_ifc_mtd *priv = chip->priv;
163 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
164 struct fsl_ifc *ifc = ctrl->regs;
165 int buf_num;
166
167 ctrl->page = page_addr;
168
169 /* Program ROW0/COL0 */
170 out_be32(&ifc->ifc_nand.row0, page_addr);
171 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
172
173 buf_num = page_addr & priv->bufnum_mask;
174
175 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
176 ctrl->index = column;
177
178 /* for OOB data point to the second half of the buffer */
179 if (oob)
180 ctrl->index += mtd->writesize;
181}
182
183static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
184 unsigned int bufnum)
185{
186 struct nand_chip *chip = mtd->priv;
187 struct fsl_ifc_mtd *priv = chip->priv;
188 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
189 u32 __iomem *main = (u32 *)addr;
190 u8 __iomem *oob = addr + mtd->writesize;
191 int i;
192
193 for (i = 0; i < mtd->writesize / 4; i++) {
194 if (__raw_readl(&main[i]) != 0xffffffff)
195 return 0;
196 }
197
198 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
199 int pos = chip->ecc.layout->eccpos[i];
200
201 if (__raw_readb(&oob[pos]) != 0xff)
202 return 0;
203 }
204
205 return 1;
206}
207
208/* returns nonzero if entire page is blank */
209static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
210 u32 *eccstat, unsigned int bufnum)
211{
212 u32 reg = eccstat[bufnum / 4];
5f720b85
PK		 213 int errors;
214
215 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
52f90dad 216
5f720b85 217 return errors;
52f90dad
DD		 218}
219
220/*
221 * execute IFC NAND command and wait for it to complete
222 */
223static int fsl_ifc_run_command(struct mtd_info *mtd)
224{
225 struct nand_chip *chip = mtd->priv;
226 struct fsl_ifc_mtd *priv = chip->priv;
227 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
228 struct fsl_ifc *ifc = ctrl->regs;
229 long long end_tick;
230 u32 eccstat[4];
231 int i;
232
233 /* set the chip select for NAND Transaction */
234 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
235
236 /* start read/write seq */
237 out_be32(&ifc->ifc_nand.nandseq_strt,
238 IFC_NAND_SEQ_STRT_FIR_STRT);
239
240 /* wait for NAND Machine complete flag or timeout */
241 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
242
243 while (end_tick > get_ticks()) {
244 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
245
246 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
247 break;
248 }
249
250 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
251
252 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
253 printf("%s: Flash Time Out Error\n", __func__);
254 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
255 printf("%s: Write Protect Error\n", __func__);
256
257 if (ctrl->eccread) {
5f720b85
PK		 258 int errors;
259 int bufnum = ctrl->page & priv->bufnum_mask;
260 int sector = bufnum * chip->ecc.steps;
261 int sector_end = sector + chip->ecc.steps - 1;
52f90dad 262
5f720b85 263 for (i = sector / 4; i <= sector_end / 4; i++)
52f90dad
DD		 264 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
265
5f720b85
PK		 266 for (i = sector; i <= sector_end; i++) {
267 errors = check_read_ecc(mtd, ctrl, eccstat, i);
268
269 if (errors == 15) {
270 /*
271 * Uncorrectable error.
272 * OK only if the whole page is blank.
273 *
274 * We disable ECCER reporting due to erratum
275 * IFC-A002770 -- so report it now if we
276 * see an uncorrectable error in ECCSTAT.
277 */
278 if (!is_blank(mtd, ctrl, bufnum))
279 ctrl->status |=
280 IFC_NAND_EVTER_STAT_ECCER;
52f90dad 281 break;
5f720b85
PK		 282 }
283
284 mtd->ecc_stats.corrected += errors;
52f90dad
DD		 285 }
286
287 ctrl->eccread = 0;
288 }
289
290 /* returns 0 on success otherwise non-zero) */
291 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
292}
293
294static void fsl_ifc_do_read(struct nand_chip *chip,
295 int oob,
296 struct mtd_info *mtd)
297{
298 struct fsl_ifc_mtd *priv = chip->priv;
299 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
300 struct fsl_ifc *ifc = ctrl->regs;
301
302 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
303 if (mtd->writesize > 512) {
304 out_be32(&ifc->ifc_nand.nand_fir0,
305 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
306 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
307 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
308 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
309 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
310 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
311
312 out_be32(&ifc->ifc_nand.nand_fcr0,
313 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
314 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
315 } else {
316 out_be32(&ifc->ifc_nand.nand_fir0,
317 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
318 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
319 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
320 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
321
322 if (oob)
323 out_be32(&ifc->ifc_nand.nand_fcr0,
324 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
325 else
326 out_be32(&ifc->ifc_nand.nand_fcr0,
327 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
328 }
329}
330
331/* cmdfunc send commands to the IFC NAND Machine */
332static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
333 int column, int page_addr)
334{
335 struct nand_chip *chip = mtd->priv;
336 struct fsl_ifc_mtd *priv = chip->priv;
337 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
338 struct fsl_ifc *ifc = ctrl->regs;
339
340 /* clear the read buffer */
341 ctrl->read_bytes = 0;
342 if (command != NAND_CMD_PAGEPROG)
343 ctrl->index = 0;
344
345 switch (command) {
346 /* READ0 read the entire buffer to use hardware ECC. */
347 case NAND_CMD_READ0: {
348 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
349 set_addr(mtd, 0, page_addr, 0);
350
351 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
352 ctrl->index += column;
353
354 if (chip->ecc.mode == NAND_ECC_HW)
355 ctrl->eccread = 1;
356
357 fsl_ifc_do_read(chip, 0, mtd);
358 fsl_ifc_run_command(mtd);
359 return;
360 }
361
362 /* READOOB reads only the OOB because no ECC is performed. */
363 case NAND_CMD_READOOB:
364 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
365 set_addr(mtd, column, page_addr, 1);
366
367 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
368
369 fsl_ifc_do_read(chip, 1, mtd);
370 fsl_ifc_run_command(mtd);
371
372 return;
373
374 /* READID must read all possible bytes while CEB is active */
375 case NAND_CMD_READID:
807fc702
PK		 376 case NAND_CMD_PARAM: {
377 int timing = IFC_FIR_OP_RB;
378 if (command == NAND_CMD_PARAM)
379 timing = IFC_FIR_OP_RBCD;
380
52f90dad 381 out_be32(&ifc->ifc_nand.nand_fir0,
ba427678 382 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
52f90dad 383 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
807fc702 384 (timing << IFC_NAND_FIR0_OP2_SHIFT));
52f90dad 385 out_be32(&ifc->ifc_nand.nand_fcr0,
807fc702
PK		 386 command << IFC_NAND_FCR0_CMD0_SHIFT);
387 out_be32(&ifc->ifc_nand.row3, column);
388
389 /*
390 * although currently it's 8 bytes for READID, we always read
391 * the maximum 256 bytes(for PARAM)
392 */
393 out_be32(&ifc->ifc_nand.nand_fbcr, 256);
394 ctrl->read_bytes = 256;
52f90dad
DD		 395
396 set_addr(mtd, 0, 0, 0);
397 fsl_ifc_run_command(mtd);
398 return;
807fc702 399 }
52f90dad
DD		 400
401 /* ERASE1 stores the block and page address */
402 case NAND_CMD_ERASE1:
403 set_addr(mtd, 0, page_addr, 0);
404 return;
405
406 /* ERASE2 uses the block and page address from ERASE1 */
407 case NAND_CMD_ERASE2:
408 out_be32(&ifc->ifc_nand.nand_fir0,
409 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
410 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
411 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
412
413 out_be32(&ifc->ifc_nand.nand_fcr0,
414 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
415 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
416
417 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
418 ctrl->read_bytes = 0;
419 fsl_ifc_run_command(mtd);
420 return;
421
422 /* SEQIN sets up the addr buffer and all registers except the length */
423 case NAND_CMD_SEQIN: {
424 u32 nand_fcr0;
425 ctrl->column = column;
426 ctrl->oob = 0;
427
428 if (mtd->writesize > 512) {
429 nand_fcr0 =
430 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
431 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
432
433 out_be32(&ifc->ifc_nand.nand_fir0,
434 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
435 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
436 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
437 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
438 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
439 out_be32(&ifc->ifc_nand.nand_fir1, 0);
440 } else {
441 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
442 IFC_NAND_FCR0_CMD1_SHIFT) |
443 (NAND_CMD_SEQIN <<
444 IFC_NAND_FCR0_CMD2_SHIFT));
445
446 out_be32(&ifc->ifc_nand.nand_fir0,
447 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
448 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
449 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
450 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
451 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
452 out_be32(&ifc->ifc_nand.nand_fir1,
453 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
454
d9036128
PK		 455 if (column >= mtd->writesize)
456 nand_fcr0 |=
457 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
458 else
459 nand_fcr0 |=
460 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
52f90dad
DD		 461 }
462
d9036128
PK		 463 if (column >= mtd->writesize) {
464 /* OOB area --> READOOB */
465 column -= mtd->writesize;
466 ctrl->oob = 1;
467 }
52f90dad
DD		 468 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
469 set_addr(mtd, column, page_addr, ctrl->oob);
470 return;
471 }
472
473 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
474 case NAND_CMD_PAGEPROG:
475 if (ctrl->oob)
d9036128
PK		 476 out_be32(&ifc->ifc_nand.nand_fbcr,
477 ctrl->index - ctrl->column);
52f90dad
DD		 478 else
479 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
480
481 fsl_ifc_run_command(mtd);
482 return;
483
484 case NAND_CMD_STATUS:
485 out_be32(&ifc->ifc_nand.nand_fir0,
486 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
487 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
488 out_be32(&ifc->ifc_nand.nand_fcr0,
489 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
490 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
491 set_addr(mtd, 0, 0, 0);
492 ctrl->read_bytes = 1;
493
494 fsl_ifc_run_command(mtd);
495
496 /* Chip sometimes reporting write protect even when it's not */
497 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
498 return;
499
500 case NAND_CMD_RESET:
501 out_be32(&ifc->ifc_nand.nand_fir0,
502 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
503 out_be32(&ifc->ifc_nand.nand_fcr0,
504 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
505 fsl_ifc_run_command(mtd);
506 return;
507
508 default:
509 printf("%s: error, unsupported command 0x%x.\n",
510 __func__, command);
511 }
512}
513
514/*
515 * Write buf to the IFC NAND Controller Data Buffer
516 */
517static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
518{
519 struct nand_chip *chip = mtd->priv;
520 struct fsl_ifc_mtd *priv = chip->priv;
521 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
522 unsigned int bufsize = mtd->writesize + mtd->oobsize;
523
524 if (len <= 0) {
525 printf("%s of %d bytes", __func__, len);
526 ctrl->status = 0;
527 return;
528 }
529
530 if ((unsigned int)len > bufsize - ctrl->index) {
531 printf("%s beyond end of buffer "
532 "(%d requested, %u available)\n",
533 __func__, len, bufsize - ctrl->index);
534 len = bufsize - ctrl->index;
535 }
536
537 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
538 ctrl->index += len;
539}
540
541/*
542 * read a byte from either the IFC hardware buffer if it has any data left
543 * otherwise issue a command to read a single byte.
544 */
545static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
546{
547 struct nand_chip *chip = mtd->priv;
548 struct fsl_ifc_mtd *priv = chip->priv;
549 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
550
551 /* If there are still bytes in the IFC buffer, then use the
552 * next byte. */
553 if (ctrl->index < ctrl->read_bytes)
554 return in_8(&ctrl->addr[ctrl->index++]);
555
556 printf("%s beyond end of buffer\n", __func__);
557 return ERR_BYTE;
558}
559
560/*
561 * Read two bytes from the IFC hardware buffer
562 * read function for 16-bit buswith
563 */
564static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
565{
566 struct nand_chip *chip = mtd->priv;
567 struct fsl_ifc_mtd *priv = chip->priv;
568 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
569 uint16_t data;
570
571 /*
572 * If there are still bytes in the IFC buffer, then use the
573 * next byte.
574 */
575 if (ctrl->index < ctrl->read_bytes) {
576 data = in_be16((uint16_t *)&ctrl->
577 addr[ctrl->index]);
578 ctrl->index += 2;
579 return (uint8_t)data;
580 }
581
582 printf("%s beyond end of buffer\n", __func__);
583 return ERR_BYTE;
584}
585
586/*
587 * Read from the IFC Controller Data Buffer
588 */
589static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
590{
591 struct nand_chip *chip = mtd->priv;
592 struct fsl_ifc_mtd *priv = chip->priv;
593 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
594 int avail;
595
596 if (len < 0)
597 return;
598
599 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
600 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
601 ctrl->index += avail;
602
603 if (len > avail)
604 printf("%s beyond end of buffer "
605 "(%d requested, %d available)\n",
606 __func__, len, avail);
607}
608
609/*
610 * Verify buffer against the IFC Controller Data Buffer
611 */
612static int fsl_ifc_verify_buf(struct mtd_info *mtd,
613 const u_char *buf, int len)
614{
615 struct nand_chip *chip = mtd->priv;
616 struct fsl_ifc_mtd *priv = chip->priv;
617 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
618 int i;
619
620 if (len < 0) {
621 printf("%s of %d bytes", __func__, len);
622 return -EINVAL;
623 }
624
625 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
626 printf("%s beyond end of buffer "
627 "(%d requested, %u available)\n",
628 __func__, len, ctrl->read_bytes - ctrl->index);
629
630 ctrl->index = ctrl->read_bytes;
631 return -EINVAL;
632 }
633
634 for (i = 0; i < len; i++)
635 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
636 break;
637
638 ctrl->index += len;
639 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
640}
641
642/* This function is called after Program and Erase Operations to
643 * check for success or failure.
644 */
645static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
646{
647 struct fsl_ifc_mtd *priv = chip->priv;
648 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
649 struct fsl_ifc *ifc = ctrl->regs;
650 u32 nand_fsr;
651
652 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
653 return NAND_STATUS_FAIL;
654
655 /* Use READ_STATUS command, but wait for the device to be ready */
656 out_be32(&ifc->ifc_nand.nand_fir0,
657 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
658 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
659 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
660 IFC_NAND_FCR0_CMD0_SHIFT);
661 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
662 set_addr(mtd, 0, 0, 0);
663 ctrl->read_bytes = 1;
664
665 fsl_ifc_run_command(mtd);
666
667 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
668 return NAND_STATUS_FAIL;
669
670 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
671
672 /* Chip sometimes reporting write protect even when it's not */
673 nand_fsr = nand_fsr | NAND_STATUS_WP;
674 return nand_fsr;
675}
676
dfe64e2c
SL		 677static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
678 uint8_t *buf, int oob_required, int page)
52f90dad
DD		 679{
680 struct fsl_ifc_mtd *priv = chip->priv;
681 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
682
683 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
684 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
685
686 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
687 mtd->ecc_stats.failed++;
688
689 return 0;
690}
691
692/* ECC will be calculated automatically, and errors will be detected in
693 * waitfunc.
694 */
dfe64e2c
SL		 695static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
696 const uint8_t *buf, int oob_required)
52f90dad
DD		 697{
698 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
699 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
dfe64e2c
SL		 700
701 return 0;
52f90dad
DD		 702}
703
704static void fsl_ifc_ctrl_init(void)
705{
706 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
707 if (!ifc_ctrl)
708 return;
709
710 ifc_ctrl->regs = IFC_BASE_ADDR;
711
712 /* clear event registers */
713 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
714 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
715
716 /* Enable error and event for any detected errors */
717 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
718 IFC_NAND_EVTER_EN_OPC_EN |
719 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
720 IFC_NAND_EVTER_EN_FTOER_EN |
721 IFC_NAND_EVTER_EN_WPER_EN);
722
723 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
724}
725
726static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
727{
728}
729
79da5e3d
PK		 730static void fsl_ifc_sram_init(void)
731{
732 struct fsl_ifc *ifc = ifc_ctrl->regs;
733 uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
734 long long end_tick;
735
736 cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
737
738 /* Save CSOR and CSOR_ext */
739 csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
740 csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
741
742 /* chage PageSize 8K and SpareSize 1K*/
743 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
744 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
745 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
746
747 /* READID */
748 out_be32(&ifc->ifc_nand.nand_fir0,
ba427678 749 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
79da5e3d
PK		 750 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
751 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
752 out_be32(&ifc->ifc_nand.nand_fcr0,
753 NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
754 out_be32(&ifc->ifc_nand.row3, 0x0);
755
756 out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
757
758 /* Program ROW0/COL0 */
759 out_be32(&ifc->ifc_nand.row0, 0x0);
760 out_be32(&ifc->ifc_nand.col0, 0x0);
761
762 /* set the chip select for NAND Transaction */
763 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
764
765 /* start read seq */
766 out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
767
768 /* wait for NAND Machine complete flag or timeout */
769 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
770
771 while (end_tick > get_ticks()) {
772 ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
773
774 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
775 break;
776 }
777
778 out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
779
780 /* Restore CSOR and CSOR_ext */
781 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
782 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
783}
784
a1b81ab2 785static int fsl_ifc_chip_init(int devnum, u8 *addr)
52f90dad 786{
a1b81ab2
PK		 787 struct mtd_info *mtd = &nand_info[devnum];
788 struct nand_chip *nand;
52f90dad
DD		 789 struct fsl_ifc_mtd *priv;
790 struct nand_ecclayout *layout;
79da5e3d 791 uint32_t cspr = 0, csor = 0, ver = 0;
a1b81ab2 792 int ret;
52f90dad
DD		 793
794 if (!ifc_ctrl) {
795 fsl_ifc_ctrl_init();
796 if (!ifc_ctrl)
797 return -1;
798 }
799
800 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
801 if (!priv)
802 return -ENOMEM;
803
804 priv->ctrl = ifc_ctrl;
a1b81ab2 805 priv->vbase = addr;
52f90dad
DD		 806
807 /* Find which chip select it is connected to.
808 */
809 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
a1b81ab2 810 phys_addr_t phys_addr = virt_to_phys(addr);
52f90dad
DD		 811
812 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
813 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
814
815 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
a1b81ab2 816 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
52f90dad
DD		 817 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
818 break;
819 }
820 }
821
822 if (priv->bank >= MAX_BANKS) {
823 printf("%s: address did not match any "
824 "chip selects\n", __func__);
76d067ac 825 kfree(priv);
52f90dad
DD		 826 return -ENODEV;
827 }
828
a1b81ab2
PK		 829 nand = &priv->chip;
830 mtd->priv = nand;
831
52f90dad
DD		 832 ifc_ctrl->chips[priv->bank] = priv;
833
834 /* fill in nand_chip structure */
835 /* set up function call table */
836
837 nand->write_buf = fsl_ifc_write_buf;
838 nand->read_buf = fsl_ifc_read_buf;
839 nand->verify_buf = fsl_ifc_verify_buf;
840 nand->select_chip = fsl_ifc_select_chip;
841 nand->cmdfunc = fsl_ifc_cmdfunc;
842 nand->waitfunc = fsl_ifc_wait;
843
844 /* set up nand options */
845 nand->bbt_td = &bbt_main_descr;
846 nand->bbt_md = &bbt_mirror_descr;
847
848 /* set up nand options */
dfe64e2c
SL		 849 nand->options = NAND_NO_SUBPAGE_WRITE;
850 nand->bbt_options = NAND_BBT_USE_FLASH;
52f90dad
DD		 851
852 if (cspr & CSPR_PORT_SIZE_16) {
853 nand->read_byte = fsl_ifc_read_byte16;
854 nand->options |= NAND_BUSWIDTH_16;
855 } else {
856 nand->read_byte = fsl_ifc_read_byte;
857 }
858
859 nand->controller = &ifc_ctrl->controller;
860 nand->priv = priv;
861
862 nand->ecc.read_page = fsl_ifc_read_page;
863 nand->ecc.write_page = fsl_ifc_write_page;
864
865 /* Hardware generates ECC per 512 Bytes */
866 nand->ecc.size = 512;
867 nand->ecc.bytes = 8;
868
869 switch (csor & CSOR_NAND_PGS_MASK) {
870 case CSOR_NAND_PGS_512:
871 if (nand->options & NAND_BUSWIDTH_16) {
872 layout = &oob_512_16bit_ecc4;
873 } else {
874 layout = &oob_512_8bit_ecc4;
875
876 /* Avoid conflict with bad block marker */
877 bbt_main_descr.offs = 0;
878 bbt_mirror_descr.offs = 0;
879 }
880
dfe64e2c 881 nand->ecc.strength = 4;
52f90dad
DD		 882 priv->bufnum_mask = 15;
883 break;
884
885 case CSOR_NAND_PGS_2K:
886 layout = &oob_2048_ecc4;
dfe64e2c 887 nand->ecc.strength = 4;
52f90dad
DD		 888 priv->bufnum_mask = 3;
889 break;
890
891 case CSOR_NAND_PGS_4K:
892 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
893 CSOR_NAND_ECC_MODE_4) {
894 layout = &oob_4096_ecc4;
dfe64e2c 895 nand->ecc.strength = 4;
52f90dad
DD		 896 } else {
897 layout = &oob_4096_ecc8;
dfe64e2c 898 nand->ecc.strength = 8;
52f90dad
DD		 899 nand->ecc.bytes = 16;
900 }
901
902 priv->bufnum_mask = 1;
903 break;
904
905 default:
906 printf("ifc nand: bad csor %#x: bad page size\n", csor);
907 return -ENODEV;
908 }
909
910 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
911 if (csor & CSOR_NAND_ECC_DEC_EN) {
912 nand->ecc.mode = NAND_ECC_HW;
913 nand->ecc.layout = layout;
914 } else {
915 nand->ecc.mode = NAND_ECC_SOFT;
916 }
917
79da5e3d
PK		 918 ver = in_be32(&ifc_ctrl->regs->ifc_rev);
919 if (ver == FSL_IFC_V1_1_0)
920 fsl_ifc_sram_init();
921
a1b81ab2
PK		 922 ret = nand_scan_ident(mtd, 1, NULL);
923 if (ret)
924 return ret;
925
926 ret = nand_scan_tail(mtd);
927 if (ret)
928 return ret;
929
930 ret = nand_register(devnum);
931 if (ret)
932 return ret;
52f90dad
DD		 933 return 0;
934}
a1b81ab2
PK		 935
936#ifndef CONFIG_SYS_NAND_BASE_LIST
937#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
938#endif
939
940static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
941 CONFIG_SYS_NAND_BASE_LIST;
942
943void board_nand_init(void)
944{
945 int i;
946
947 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
948 fsl_ifc_chip_init(i, (u8 *)base_address[i]);
949}
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