[people/ms/u-boot.git] / drivers / mtd / nand / mxc_nand_spl.c

/*
 * (C) Copyright 2009
 * Magnus Lilja <lilja.magnus@gmail.com>
 *
 * (C) Copyright 2008
 * Maxim Artamonov, <scn1874 at yandex.ru>
 *
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr at denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <nand.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include "mxc_nand.h"

#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR;
#elif defined(MXC_NFC_V3_2)
static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR_AXI;
static struct mxc_nand_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR;
#endif

static void nfc_wait_ready(void)
{
	uint32_t tmp;

#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
	while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
		;

	/* Reset interrupt flag */
	tmp = readnfc(&nfc->config2);
	tmp &= ~NFC_V1_V2_CONFIG2_INT;
	writenfc(tmp, &nfc->config2);
#elif defined(MXC_NFC_V3_2)
	while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT))
		;

	/* Reset interrupt flag */
	tmp = readnfc(&nfc_ip->ipc);
	tmp &= ~NFC_V3_IPC_INT;
	writenfc(tmp, &nfc_ip->ipc);
#endif
}

static void nfc_nand_init(void)
{
#if defined(MXC_NFC_V3_2)
	int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
	int tmp;

	tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK |
			NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) |
		NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) |
		NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN |
		NFC_V3_CONFIG2_ONE_CYCLE;
	if (CONFIG_SYS_NAND_PAGE_SIZE == 4096)
		tmp |= NFC_V3_CONFIG2_PS_4096;
	else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048)
		tmp |= NFC_V3_CONFIG2_PS_2048;
	else if (CONFIG_SYS_NAND_PAGE_SIZE == 512)
		tmp |= NFC_V3_CONFIG2_PS_512;
	/*
	 * if spare size is larger that 16 bytes per 512 byte hunk
	 * then use 8 symbol correction instead of 4
	 */
	if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
		tmp |= NFC_V3_CONFIG2_ECC_MODE_8;
	else
		tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8;
	writenfc(tmp, &nfc_ip->config2);

	tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
			NFC_V3_CONFIG3_NO_SDMA |
			NFC_V3_CONFIG3_RBB_MODE |
			NFC_V3_CONFIG3_SBB(6) | /* Reset default */
			NFC_V3_CONFIG3_ADD_OP(0);
#ifndef CONFIG_SYS_NAND_BUSWIDTH_16
	tmp |= NFC_V3_CONFIG3_FW8;
#endif
	writenfc(tmp, &nfc_ip->config3);

	writenfc(0, &nfc_ip->delay_line);
#elif defined(MXC_NFC_V2_1)
	int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
	int config1;

	writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size);

	/* unlocking RAM Buff */
	writenfc(0x2, &nfc->config);

	/* hardware ECC checking and correct */
	config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN |
			NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE |
			NFC_V2_CONFIG1_FP_INT;
	/*
	 * if spare size is larger that 16 bytes per 512 byte hunk
	 * then use 8 symbol correction instead of 4
	 */
	if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
		config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
	else
		config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
	writenfc(config1, &nfc->config1);
#elif defined(MXC_NFC_V1)
	/* unlocking RAM Buff */
	writenfc(0x2, &nfc->config);

	/* hardware ECC checking and correct */
	writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK,
			&nfc->config1);
#endif
}

static void nfc_nand_command(unsigned short command)
{
	writenfc(command, &nfc->flash_cmd);
	writenfc(NFC_CMD, &nfc->operation);
	nfc_wait_ready();
}

static void nfc_nand_address(unsigned short address)
{
	writenfc(address, &nfc->flash_addr);
	writenfc(NFC_ADDR, &nfc->operation);
	nfc_wait_ready();
}

static void nfc_nand_page_address(unsigned int page_address)
{
	unsigned int page_count;

	nfc_nand_address(0x00);

	/* code only for large page flash */
	if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
		nfc_nand_address(0x00);

	page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;

	if (page_address <= page_count) {
		page_count--; /* transform 0x01000000 to 0x00ffffff */
		do {
			nfc_nand_address(page_address & 0xff);
			page_address = page_address >> 8;
			page_count = page_count >> 8;
		} while (page_count);
	}

	nfc_nand_address(0x00);
}

static void nfc_nand_data_output(void)
{
#ifdef NAND_MXC_2K_MULTI_CYCLE
	int i;
#endif

#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
	writenfc(0, &nfc->buf_addr);
#elif defined(MXC_NFC_V3_2)
	int config1 = readnfc(&nfc->config1);
	config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
	writenfc(config1, &nfc->config1);
#endif
	writenfc(NFC_OUTPUT, &nfc->operation);
	nfc_wait_ready();
#ifdef NAND_MXC_2K_MULTI_CYCLE
	/*
	 * This NAND controller requires multiple input commands
	 * for pages larger than 512 bytes.
	 */
	for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
		writenfc(i, &nfc->buf_addr);
		writenfc(NFC_OUTPUT, &nfc->operation);
		nfc_wait_ready();
	}
#endif
}

static int nfc_nand_check_ecc(void)
{
#if defined(MXC_NFC_V1)
	u16 ecc_status = readw(&nfc->ecc_status_result);
	return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
	u32 ecc_status = readl(&nfc->ecc_status_result);
	int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
	int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4;
	int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;

	do {
		if ((ecc_status & 0xf) > err_limit)
			return 1;
		ecc_status >>= 4;
	} while (--subpages);

	return 0;
#endif
}

static void nfc_nand_read_page(unsigned int page_address)
{
	/* read in first 0 buffer */
#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
	writenfc(0, &nfc->buf_addr);
#elif defined(MXC_NFC_V3_2)
	int config1 = readnfc(&nfc->config1);
	config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
	writenfc(config1, &nfc->config1);
#endif
	nfc_nand_command(NAND_CMD_READ0);
	nfc_nand_page_address(page_address);

	if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
		nfc_nand_command(NAND_CMD_READSTART);

	nfc_nand_data_output(); /* fill the main buffer 0 */
}

static int nfc_read_page(unsigned int page_address, unsigned char *buf)
{
	int i;
	u32 *src;
	u32 *dst;

	nfc_nand_read_page(page_address);

	if (nfc_nand_check_ecc())
		return -1;

	src = (u32 *)&nfc->main_area[0][0];
	dst = (u32 *)buf;

	/* main copy loop from NAND-buffer to SDRAM memory */
	for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) {
		writel(readl(src), dst);
		src++;
		dst++;
	}

	return 0;
}

static int is_badblock(int pagenumber)
{
	int page = pagenumber;
	u32 badblock;
	u32 *src;

	/* Check the first two pages for bad block markers */
	for (page = pagenumber; page < pagenumber + 2; page++) {
		nfc_nand_read_page(page);

		src = (u32 *)&nfc->spare_area[0][0];

		/*
		 * IMPORTANT NOTE: The nand flash controller uses a non-
		 * standard layout for large page devices. This can
		 * affect the position of the bad block marker.
		 */
		/* Get the bad block marker */
		badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
		badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
		badblock &= 0xff;

		/* bad block marker verify */
		if (badblock != 0xff)
			return 1; /* potential bad block */
	}

	return 0;
}

int nand_spl_load_image(uint32_t from, unsigned int size, void *buf)
{
	int i;
	unsigned int page;
	unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
				CONFIG_SYS_NAND_PAGE_SIZE;

	nfc_nand_init();

	/* Convert to page number */
	page = from / CONFIG_SYS_NAND_PAGE_SIZE;
	i = 0;

	size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE);
	while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
		if (nfc_read_page(page, buf) < 0)
			return -1;

		page++;
		i++;
		buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;

		/*
		 * Check if we have crossed a block boundary, and if so
		 * check for bad block.
		 */
		if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
			/*
			 * Yes, new block. See if this block is good. If not,
			 * loop until we find a good block.
			 */
			while (is_badblock(page)) {
				page = page + CONFIG_SYS_NAND_PAGE_COUNT;
				/* Check i we've reached the end of flash. */
				if (page >= maxpages)
					return -1;
			}
		}
	}

	return 0;
}

#ifndef CONFIG_SPL_FRAMEWORK
/*
 * The main entry for NAND booting. It's necessary that SDRAM is already
 * configured and available since this code loads the main U-Boot image
 * from NAND into SDRAM and starts it from there.
 */
void nand_boot(void)
{
	__attribute__((noreturn)) void (*uboot)(void);

	/*
	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
	 * be aligned to full pages
	 */
	if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
			CONFIG_SYS_NAND_U_BOOT_SIZE,
			(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
		/* Copy from NAND successful, start U-Boot */
		uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
		uboot();
	} else {
		/* Unrecoverable error when copying from NAND */
		hang();
	}
}
#endif

void nand_init(void) {}
void nand_deselect(void) {}
Commit	Line	Data
40c642bc ML	1	/*
	2	* (C) Copyright 2009
	3	* Magnus Lilja <lilja.magnus@gmail.com>
	4	*
	5	* (C) Copyright 2008
	6	* Maxim Artamonov, <scn1874 at yandex.ru>
	7	*
	8	* (C) Copyright 2006-2008
	9	* Stefan Roese, DENX Software Engineering, sr at denx.de.
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
40c642bc ML	12	*/
	13
	14	#include <common.h>
	15	#include <nand.h>
61f2b38a	16	#include <asm/arch/imx-regs.h>
40c642bc	17	#include <asm/io.h>
da962b71	18	#include "mxc_nand.h"
40c642bc	19
35537bc7	20	#if defined(MXC_NFC_V1) \|\| defined(MXC_NFC_V2_1)
da962b71	21	static struct mxc_nand_regs const nfc = (void )NFC_BASE_ADDR;
35537bc7	22	#elif defined(MXC_NFC_V3_2)
da962b71 BT	23	static struct mxc_nand_regs const nfc = (void )NFC_BASE_ADDR_AXI;
da962b71 BT	24	static struct mxc_nand_ip_regs const nfc_ip = (void )NFC_BASE_ADDR;
35537bc7	25	#endif
40c642bc ML	26
	27	static void nfc_wait_ready(void)
	28	{
	29	uint32_t tmp;
	30
35537bc7	31	#if defined(MXC_NFC_V1) \|\| defined(MXC_NFC_V2_1)
2dc0aa02	32	while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
40c642bc ML	33	;
	34
	35	/* Reset interrupt flag */
2dc0aa02 BT	36	tmp = readnfc(&nfc->config2);
	37	tmp &= ~NFC_V1_V2_CONFIG2_INT;
	38	writenfc(tmp, &nfc->config2);
35537bc7 BT	39	#elif defined(MXC_NFC_V3_2)
	40	while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT))
	41	;
	42
	43	/* Reset interrupt flag */
	44	tmp = readnfc(&nfc_ip->ipc);
	45	tmp &= ~NFC_V3_IPC_INT;
	46	writenfc(tmp, &nfc_ip->ipc);
	47	#endif
40c642bc ML	48	}
40c642bc ML	49
365b2c07	50	static void nfc_nand_init(void)
40c642bc	51	{
35537bc7 BT	52	#if defined(MXC_NFC_V3_2)
	53	int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
	54	int tmp;
	55
	56	tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK \|
	57	NFC_V3_CONFIG2_EDC_MASK \| NFC_V3_CONFIG2_PS_MASK)) \|
da962b71	58	NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) \|
35537bc7 BT	59	NFC_V3_CONFIG2_INT_MSK \| NFC_V3_CONFIG2_ECC_EN \|
	60	NFC_V3_CONFIG2_ONE_CYCLE;
	61	if (CONFIG_SYS_NAND_PAGE_SIZE == 4096)
	62	tmp \|= NFC_V3_CONFIG2_PS_4096;
	63	else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048)
	64	tmp \|= NFC_V3_CONFIG2_PS_2048;
	65	else if (CONFIG_SYS_NAND_PAGE_SIZE == 512)
	66	tmp \|= NFC_V3_CONFIG2_PS_512;
	67	/*
	68	* if spare size is larger that 16 bytes per 512 byte hunk
	69	* then use 8 symbol correction instead of 4
	70	*/
da962b71	71	if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
35537bc7 BT	72	tmp \|= NFC_V3_CONFIG2_ECC_MODE_8;
	73	else
	74	tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8;
	75	writenfc(tmp, &nfc_ip->config2);
	76
	77	tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) \|
	78	NFC_V3_CONFIG3_NO_SDMA \|
	79	NFC_V3_CONFIG3_RBB_MODE \|
	80	NFC_V3_CONFIG3_SBB(6) \| /* Reset default */
	81	NFC_V3_CONFIG3_ADD_OP(0);
	82	#ifndef CONFIG_SYS_NAND_BUSWIDTH_16
	83	tmp \|= NFC_V3_CONFIG3_FW8;
	84	#endif
	85	writenfc(tmp, &nfc_ip->config3);
	86
	87	writenfc(0, &nfc_ip->delay_line);
	88	#elif defined(MXC_NFC_V2_1)
365b2c07	89	int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
f3bb63a3 JR	90	int config1;
f3bb63a3 JR	91
da962b71	92	writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size);
f3bb63a3 JR	93
f3bb63a3 JR	94	/* unlocking RAM Buff */
2dc0aa02	95	writenfc(0x2, &nfc->config);
f3bb63a3 JR	96
f3bb63a3 JR	97	/* hardware ECC checking and correct */
2dc0aa02 BT	98	config1 = readnfc(&nfc->config1) \| NFC_V1_V2_CONFIG1_ECC_EN \|
	99	NFC_V1_V2_CONFIG1_INT_MSK \| NFC_V2_CONFIG1_ONE_CYCLE \|
	100	NFC_V2_CONFIG1_FP_INT;
f3bb63a3 JR	101	/*
	102	* if spare size is larger that 16 bytes per 512 byte hunk
	103	* then use 8 symbol correction instead of 4
	104	*/
da962b71	105	if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
2dc0aa02	106	config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
f3bb63a3	107	else
2dc0aa02 BT	108	config1 \|= NFC_V2_CONFIG1_ECC_MODE_4;
2dc0aa02 BT	109	writenfc(config1, &nfc->config1);
f3bb63a3	110	#elif defined(MXC_NFC_V1)
40c642bc	111	/* unlocking RAM Buff */
2dc0aa02	112	writenfc(0x2, &nfc->config);
40c642bc ML	113
40c642bc ML	114	/* hardware ECC checking and correct */
2dc0aa02 BT	115	writenfc(NFC_V1_V2_CONFIG1_ECC_EN \| NFC_V1_V2_CONFIG1_INT_MSK,
2dc0aa02 BT	116	&nfc->config1);
f3bb63a3	117	#endif
40c642bc ML	118	}
	119
	120	static void nfc_nand_command(unsigned short command)
	121	{
2dc0aa02 BT	122	writenfc(command, &nfc->flash_cmd);
2dc0aa02 BT	123	writenfc(NFC_CMD, &nfc->operation);
40c642bc ML	124	nfc_wait_ready();
	125	}
	126
5d818a28 BT	127	static void nfc_nand_address(unsigned short address)
5d818a28 BT	128	{
2dc0aa02 BT	129	writenfc(address, &nfc->flash_addr);
2dc0aa02 BT	130	writenfc(NFC_ADDR, &nfc->operation);
5d818a28 BT	131	nfc_wait_ready();
	132	}
	133
40c642bc ML	134	static void nfc_nand_page_address(unsigned int page_address)
	135	{
	136	unsigned int page_count;
	137
5d818a28	138	nfc_nand_address(0x00);
40c642bc	139
f3bb63a3	140	/* code only for large page flash */
5d818a28 BT	141	if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
5d818a28 BT	142	nfc_nand_address(0x00);
40c642bc ML	143
	144	page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
	145
	146	if (page_address <= page_count) {
	147	page_count--; /* transform 0x01000000 to 0x00ffffff */
	148	do {
5d818a28	149	nfc_nand_address(page_address & 0xff);
40c642bc ML	150	page_address = page_address >> 8;
	151	page_count = page_count >> 8;
	152	} while (page_count);
	153	}
f3bb63a3	154
5d818a28	155	nfc_nand_address(0x00);
40c642bc ML	156	}
	157
	158	static void nfc_nand_data_output(void)
	159	{
f3bb63a3	160	#ifdef NAND_MXC_2K_MULTI_CYCLE
40c642bc	161	int i;
f3bb63a3	162	#endif
40c642bc	163
35537bc7	164	#if defined(MXC_NFC_V1) \|\| defined(MXC_NFC_V2_1)
2dc0aa02	165	writenfc(0, &nfc->buf_addr);
35537bc7 BT	166	#elif defined(MXC_NFC_V3_2)
	167	int config1 = readnfc(&nfc->config1);
	168	config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
	169	writenfc(config1, &nfc->config1);
	170	#endif
2dc0aa02	171	writenfc(NFC_OUTPUT, &nfc->operation);
f3bb63a3 JR	172	nfc_wait_ready();
f3bb63a3 JR	173	#ifdef NAND_MXC_2K_MULTI_CYCLE
40c642bc	174	/*
f3bb63a3 JR	175	* This NAND controller requires multiple input commands
f3bb63a3 JR	176	* for pages larger than 512 bytes.
40c642bc	177	*/
365b2c07	178	for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
2dc0aa02 BT	179	writenfc(i, &nfc->buf_addr);
2dc0aa02 BT	180	writenfc(NFC_OUTPUT, &nfc->operation);
40c642bc ML	181	nfc_wait_ready();
40c642bc ML	182	}
f3bb63a3	183	#endif
40c642bc ML	184	}
	185
	186	static int nfc_nand_check_ecc(void)
	187	{
c1db8dd6	188	#if defined(MXC_NFC_V1)
b8fea2b2 BT	189	u16 ecc_status = readw(&nfc->ecc_status_result);
b8fea2b2 BT	190	return (ecc_status & 0x3) == 2 \|\| (ecc_status >> 2) == 2;
35537bc7	191	#elif defined(MXC_NFC_V2_1) \|\| defined(MXC_NFC_V3_2)
b8fea2b2 BT	192	u32 ecc_status = readl(&nfc->ecc_status_result);
b8fea2b2 BT	193	int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
da962b71	194	int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4;
b8fea2b2 BT	195	int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
	196
	197	do {
	198	if ((ecc_status & 0xf) > err_limit)
	199	return 1;
	200	ecc_status >>= 4;
	201	} while (--subpages);
	202
	203	return 0;
c1db8dd6	204	#endif
40c642bc ML	205	}
40c642bc ML	206
5d818a28	207	static void nfc_nand_read_page(unsigned int page_address)
40c642bc	208	{
2dc0aa02	209	/* read in first 0 buffer */
35537bc7	210	#if defined(MXC_NFC_V1) \|\| defined(MXC_NFC_V2_1)
2dc0aa02	211	writenfc(0, &nfc->buf_addr);
35537bc7 BT	212	#elif defined(MXC_NFC_V3_2)
	213	int config1 = readnfc(&nfc->config1);
	214	config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
	215	writenfc(config1, &nfc->config1);
	216	#endif
40c642bc ML	217	nfc_nand_command(NAND_CMD_READ0);
	218	nfc_nand_page_address(page_address);
	219
f3bb63a3	220	if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
40c642bc ML	221	nfc_nand_command(NAND_CMD_READSTART);
	222
	223	nfc_nand_data_output(); /* fill the main buffer 0 */
5d818a28 BT	224	}
	225
	226	static int nfc_read_page(unsigned int page_address, unsigned char *buf)
	227	{
	228	int i;
	229	u32 *src;
	230	u32 *dst;
	231
	232	nfc_nand_read_page(page_address);
40c642bc ML	233
	234	if (nfc_nand_check_ecc())
	235	return -1;
	236
80c8ab7b	237	src = (u32 *)&nfc->main_area[0][0];
40c642bc ML	238	dst = (u32 *)buf;
	239
	240	/* main copy loop from NAND-buffer to SDRAM memory */
365b2c07	241	for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) {
40c642bc ML	242	writel(readl(src), dst);
	243	src++;
	244	dst++;
	245	}
	246
	247	return 0;
	248	}
	249
	250	static int is_badblock(int pagenumber)
	251	{
	252	int page = pagenumber;
	253	u32 badblock;
	254	u32 *src;
	255
	256	/* Check the first two pages for bad block markers */
	257	for (page = pagenumber; page < pagenumber + 2; page++) {
5d818a28	258	nfc_nand_read_page(page);
40c642bc	259
80c8ab7b	260	src = (u32 *)&nfc->spare_area[0][0];
40c642bc ML	261
	262	/*
	263	* IMPORTANT NOTE: The nand flash controller uses a non-
	264	* standard layout for large page devices. This can
	265	* affect the position of the bad block marker.
	266	*/
	267	/* Get the bad block marker */
	268	badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
	269	badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
	270	badblock &= 0xff;
	271
	272	/* bad block marker verify */
	273	if (badblock != 0xff)
	274	return 1; /* potential bad block */
	275	}
	276
	277	return 0;
	278	}
	279
5c651e86	280	int nand_spl_load_image(uint32_t from, unsigned int size, void *buf)
40c642bc ML	281	{
	282	int i;
	283	unsigned int page;
	284	unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
	285	CONFIG_SYS_NAND_PAGE_SIZE;
	286
40c642bc ML	287	nfc_nand_init();
	288
	289	/* Convert to page number */
	290	page = from / CONFIG_SYS_NAND_PAGE_SIZE;
	291	i = 0;
	292
5c651e86	293	size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE);
365b2c07	294	while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
40c642bc ML	295	if (nfc_read_page(page, buf) < 0)
	296	return -1;
	297
	298	page++;
	299	i++;
	300	buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
	301
	302	/*
	303	* Check if we have crossed a block boundary, and if so
	304	* check for bad block.
	305	*/
	306	if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
	307	/*
	308	* Yes, new block. See if this block is good. If not,
f3bb63a3	309	* loop until we find a good block.
40c642bc ML	310	*/
	311	while (is_badblock(page)) {
	312	page = page + CONFIG_SYS_NAND_PAGE_COUNT;
	313	/* Check i we've reached the end of flash. */
	314	if (page >= maxpages)
	315	return -1;
	316	}
	317	}
	318	}
	319
	320	return 0;
	321	}
	322
5c651e86	323	#ifndef CONFIG_SPL_FRAMEWORK
40c642bc ML	324	/*
	325	* The main entry for NAND booting. It's necessary that SDRAM is already
	326	* configured and available since this code loads the main U-Boot image
	327	* from NAND into SDRAM and starts it from there.
	328	*/
	329	void nand_boot(void)
	330	{
	331	__attribute__((noreturn)) void (*uboot)(void);
	332
40c642bc ML	333	/*
	334	* CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
	335	* be aligned to full pages
	336	*/
5c651e86 MV	337	if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
	338	CONFIG_SYS_NAND_U_BOOT_SIZE,
	339	(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
a187559e	340	/* Copy from NAND successful, start U-Boot */
40c642bc ML	341	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
	342	uboot();
	343	} else {
	344	/* Unrecoverable error when copying from NAND */
	345	hang();
	346	}
	347	}
5c651e86	348	#endif
c1b43ac7 AA	349
	350	void nand_init(void) {}
	351	void nand_deselect(void) {}