[people/ms/u-boot.git] / drivers / mtd / nand / nand_spl_simple.c

/*
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include <linux/mtd/nand_ecc.h>

static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
static nand_info_t mtd;
static struct nand_chip nand_chip;

#define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
					CONFIG_SYS_NAND_ECCSIZE)
#define ECCTOTAL	(ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)


#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
/*
 * NAND command for small page NAND devices (512)
 */
static int nand_command(int block, int page, uint32_t offs,
	u8 cmd)
{
	struct nand_chip *this = mtd.priv;
	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;

	while (!this->dev_ready(&mtd))
		;

	/* Begin command latch cycle */
	this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	/* Set ALE and clear CLE to start address cycle */
	/* Column address */
	this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
	this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
	this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
		       NAND_CTRL_ALE); /* A[24:17] */
#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
	/* One more address cycle for devices > 32MiB */
	this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
		       NAND_CTRL_ALE); /* A[28:25] */
#endif
	/* Latch in address */
	this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	while (!this->dev_ready(&mtd))
		;

	return 0;
}
#else
/*
 * NAND command for large page NAND devices (2k)
 */
static int nand_command(int block, int page, uint32_t offs,
	u8 cmd)
{
	struct nand_chip *this = mtd.priv;
	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
	void (*hwctrl)(struct mtd_info *mtd, int cmd,
			unsigned int ctrl) = this->cmd_ctrl;

	while (!this->dev_ready(&mtd))
		;

	/* Emulate NAND_CMD_READOOB */
	if (cmd == NAND_CMD_READOOB) {
		offs += CONFIG_SYS_NAND_PAGE_SIZE;
		cmd = NAND_CMD_READ0;
	}

	/* Shift the offset from byte addressing to word addressing. */
	if (this->options & NAND_BUSWIDTH_16)
		offs >>= 1;

	/* Begin command latch cycle */
	hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	/* Set ALE and clear CLE to start address cycle */
	/* Column address */
	hwctrl(&mtd, offs & 0xff,
		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
	/* Row address */
	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
		       NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
	/* One more address cycle for devices > 128MiB */
	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
		       NAND_CTRL_ALE); /* A[31:28] */
#endif
	/* Latch in address */
	hwctrl(&mtd, NAND_CMD_READSTART,
		       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	while (!this->dev_ready(&mtd))
		;

	return 0;
}
#endif

static int nand_is_bad_block(int block)
{
	struct nand_chip *this = mtd.priv;

	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
		NAND_CMD_READOOB);

	/*
	 * Read one byte (or two if it's a 16 bit chip).
	 */
	if (this->options & NAND_BUSWIDTH_16) {
		if (readw(this->IO_ADDR_R) != 0xffff)
			return 1;
	} else {
		if (readb(this->IO_ADDR_R) != 0xff)
			return 1;
	}

	return 0;
}

#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
static int nand_read_page(int block, int page, uchar *dst)
{
	struct nand_chip *this = mtd.priv;
	u_char ecc_calc[ECCTOTAL];
	u_char ecc_code[ECCTOTAL];
	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
	int i;
	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
	int eccsteps = ECCSTEPS;
	uint8_t *p = dst;

	nand_command(block, page, 0, NAND_CMD_READOOB);
	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
	nand_command(block, page, 0, NAND_CMD_READ0);

	/* Pick the ECC bytes out of the oob data */
	for (i = 0; i < ECCTOTAL; i++)
		ecc_code[i] = oob_data[nand_ecc_pos[i]];


	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		this->ecc.hwctl(&mtd, NAND_ECC_READ);
		this->read_buf(&mtd, p, eccsize);
		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
	}

	return 0;
}
#else
static int nand_read_page(int block, int page, void *dst)
{
	struct nand_chip *this = mtd.priv;
	u_char ecc_calc[ECCTOTAL];
	u_char ecc_code[ECCTOTAL];
	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
	int i;
	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
	int eccsteps = ECCSTEPS;
	uint8_t *p = dst;

	nand_command(block, page, 0, NAND_CMD_READ0);

	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		if (this->ecc.mode != NAND_ECC_SOFT)
			this->ecc.hwctl(&mtd, NAND_ECC_READ);
		this->read_buf(&mtd, p, eccsize);
		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
	}
	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);

	/* Pick the ECC bytes out of the oob data */
	for (i = 0; i < ECCTOTAL; i++)
		ecc_code[i] = oob_data[nand_ecc_pos[i]];

	eccsteps = ECCSTEPS;
	p = dst;

	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		/* No chance to do something with the possible error message
		 * from correct_data(). We just hope that all possible errors
		 * are corrected by this routine.
		 */
		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
	}

	return 0;
}
#endif

int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
	unsigned int block, lastblock;
	unsigned int page;

	/*
	 * offs has to be aligned to a page address!
	 */
	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
	lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;

	while (block <= lastblock) {
		if (!nand_is_bad_block(block)) {
			/*
			 * Skip bad blocks
			 */
			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
				nand_read_page(block, page, dst);
				dst += CONFIG_SYS_NAND_PAGE_SIZE;
				page++;
			}

			page = 0;
		} else {
			lastblock++;
		}

		block++;
	}

	return 0;
}

/* nand_init() - initialize data to make nand usable by SPL */
void nand_init(void)
{
	/*
	 * Init board specific nand support
	 */
	mtd.priv = &nand_chip;
	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
		(void  __iomem *)CONFIG_SYS_NAND_BASE;
	board_nand_init(&nand_chip);

#ifdef CONFIG_SPL_NAND_SOFTECC
	if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
		nand_chip.ecc.calculate = nand_calculate_ecc;
		nand_chip.ecc.correct = nand_correct_data;
	}
#endif

	if (nand_chip.select_chip)
		nand_chip.select_chip(&mtd, 0);
}

/* Unselect after operation */
void nand_deselect(void)
{
	if (nand_chip.select_chip)
		nand_chip.select_chip(&mtd, -1);
}
Commit	Line	Data
12c2f1ee SS	1	/*
	2	* (C) Copyright 2006-2008
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#include <common.h>
	22	#include <nand.h>
	23	#include <asm/io.h>
1df308e5	24	#include <linux/mtd/nand_ecc.h>
12c2f1ee SS	25
	26	static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
	27	static nand_info_t mtd;
	28	static struct nand_chip nand_chip;
	29
d3022c5f SB	30	#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
	31	CONFIG_SYS_NAND_ECCSIZE)
	32	#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
	33
	34
12c2f1ee SS	35	#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
	36	/*
	37	* NAND command for small page NAND devices (512)
	38	*/
	39	static int nand_command(int block, int page, uint32_t offs,
	40	u8 cmd)
	41	{
	42	struct nand_chip *this = mtd.priv;
	43	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
	44
	45	while (!this->dev_ready(&mtd))
	46	;
	47
	48	/* Begin command latch cycle */
	49	this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
	50	/* Set ALE and clear CLE to start address cycle */
	51	/* Column address */
	52	this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE \| NAND_CTRL_CHANGE);
	53	this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
	54	this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
	55	NAND_CTRL_ALE); /* A[24:17] */
	56	#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
	57	/* One more address cycle for devices > 32MiB */
	58	this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
	59	NAND_CTRL_ALE); /* A[28:25] */
	60	#endif
	61	/* Latch in address */
	62	this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
	63
	64	/*
	65	* Wait a while for the data to be ready
	66	*/
	67	while (!this->dev_ready(&mtd))
	68	;
	69
	70	return 0;
	71	}
	72	#else
	73	/*
	74	* NAND command for large page NAND devices (2k)
	75	*/
	76	static int nand_command(int block, int page, uint32_t offs,
	77	u8 cmd)
	78	{
	79	struct nand_chip *this = mtd.priv;
	80	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
	81	void (hwctrl)(struct mtd_info mtd, int cmd,
	82	unsigned int ctrl) = this->cmd_ctrl;
	83
	84	while (!this->dev_ready(&mtd))
	85	;
	86
	87	/* Emulate NAND_CMD_READOOB */
	88	if (cmd == NAND_CMD_READOOB) {
	89	offs += CONFIG_SYS_NAND_PAGE_SIZE;
	90	cmd = NAND_CMD_READ0;
	91	}
	92
	93	/* Shift the offset from byte addressing to word addressing. */
	94	if (this->options & NAND_BUSWIDTH_16)
	95	offs >>= 1;
	96
	97	/* Begin command latch cycle */
	98	hwctrl(&mtd, cmd, NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
99	/* Set ALE and clear CLE to start address cycle */
100	/* Column address */
101	hwctrl(&mtd, offs & 0xff,
102	NAND_CTRL_ALE \| NAND_CTRL_CHANGE); /* A[7:0] */
103	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
104	/* Row address */
105	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
106	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
107	NAND_CTRL_ALE); /* A[27:20] */
108	#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
109	/* One more address cycle for devices > 128MiB */
110	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
111	NAND_CTRL_ALE); /* A[31:28] */
112	#endif
113	/* Latch in address */
114	hwctrl(&mtd, NAND_CMD_READSTART,
115	NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
116	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
117
118	/*
119	* Wait a while for the data to be ready
120	*/
121	while (!this->dev_ready(&mtd))
122	;
123
124	return 0;
125	}
126	#endif
127
128	static int nand_is_bad_block(int block)
129	{
130	struct nand_chip *this = mtd.priv;
131
132	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
133	NAND_CMD_READOOB);
134
135	/*
136	* Read one byte (or two if it's a 16 bit chip).
137	*/
138	if (this->options & NAND_BUSWIDTH_16) {
139	if (readw(this->IO_ADDR_R) != 0xffff)
140	return 1;
141	} else {
142	if (readb(this->IO_ADDR_R) != 0xff)
143	return 1;
144	}
145
146	return 0;
147	}
148
68bb8295 HS	149	#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
	150	static int nand_read_page(int block, int page, uchar *dst)
	151	{
	152	struct nand_chip *this = mtd.priv;
d3022c5f SB	153	u_char ecc_calc[ECCTOTAL];
	154	u_char ecc_code[ECCTOTAL];
	155	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
68bb8295 HS	156	int i;
	157	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	158	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
d3022c5f	159	int eccsteps = ECCSTEPS;
68bb8295	160	uint8_t *p = dst;
68bb8295	161
68bb8295 HS	162	nand_command(block, page, 0, NAND_CMD_READOOB);
	163	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
	164	nand_command(block, page, 0, NAND_CMD_READ0);
	165
	166	/* Pick the ECC bytes out of the oob data */
d3022c5f	167	for (i = 0; i < ECCTOTAL; i++)
68bb8295 HS	168	ecc_code[i] = oob_data[nand_ecc_pos[i]];
	169
	170
	171	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
	172	this->ecc.hwctl(&mtd, NAND_ECC_READ);
	173	this->read_buf(&mtd, p, eccsize);
	174	this->ecc.calculate(&mtd, p, &ecc_calc[i]);
18b89072	175	this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
68bb8295 HS	176	}
	177
	178	return 0;
	179	}
	180	#else
12c2f1ee SS	181	static int nand_read_page(int block, int page, void *dst)
	182	{
	183	struct nand_chip *this = mtd.priv;
d3022c5f SB	184	u_char ecc_calc[ECCTOTAL];
	185	u_char ecc_code[ECCTOTAL];
	186	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
12c2f1ee SS	187	int i;
	188	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	189	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
d3022c5f	190	int eccsteps = ECCSTEPS;
12c2f1ee	191	uint8_t *p = dst;
12c2f1ee SS	192
	193	nand_command(block, page, 0, NAND_CMD_READ0);
	194
12c2f1ee	195	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1df308e5 IY	196	if (this->ecc.mode != NAND_ECC_SOFT)
1df308e5 IY	197	this->ecc.hwctl(&mtd, NAND_ECC_READ);
12c2f1ee SS	198	this->read_buf(&mtd, p, eccsize);
	199	this->ecc.calculate(&mtd, p, &ecc_calc[i]);
	200	}
	201	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
	202
	203	/* Pick the ECC bytes out of the oob data */
d3022c5f	204	for (i = 0; i < ECCTOTAL; i++)
12c2f1ee SS	205	ecc_code[i] = oob_data[nand_ecc_pos[i]];
12c2f1ee SS	206
d3022c5f	207	eccsteps = ECCSTEPS;
12c2f1ee SS	208	p = dst;
	209
	210	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
	211	/* No chance to do something with the possible error message
	212	* from correct_data(). We just hope that all possible errors
	213	* are corrected by this routine.
	214	*/
18b89072	215	this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
12c2f1ee SS	216	}
	217
	218	return 0;
	219	}
68bb8295	220	#endif
12c2f1ee SS	221
	222	int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
	223	{
	224	unsigned int block, lastblock;
	225	unsigned int page;
	226
	227	/*
	228	* offs has to be aligned to a page address!
	229	*/
	230	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
	231	lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
	232	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
	233
	234	while (block <= lastblock) {
	235	if (!nand_is_bad_block(block)) {
	236	/*
	237	* Skip bad blocks
	238	*/
	239	while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
	240	nand_read_page(block, page, dst);
	241	dst += CONFIG_SYS_NAND_PAGE_SIZE;
	242	page++;
	243	}
	244
	245	page = 0;
	246	} else {
	247	lastblock++;
	248	}
	249
	250	block++;
	251	}
	252
	253	return 0;
	254	}
	255
	256	/* nand_init() - initialize data to make nand usable by SPL */
	257	void nand_init(void)
	258	{
	259	/*
	260	* Init board specific nand support
	261	*/
	262	mtd.priv = &nand_chip;
	263	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
	264	(void __iomem *)CONFIG_SYS_NAND_BASE;
12c2f1ee SS	265	board_nand_init(&nand_chip);
12c2f1ee SS	266
1df308e5 IY	267	#ifdef CONFIG_SPL_NAND_SOFTECC
	268	if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
	269	nand_chip.ecc.calculate = nand_calculate_ecc;
	270	nand_chip.ecc.correct = nand_correct_data;
	271	}
	272	#endif
	273
12c2f1ee SS	274	if (nand_chip.select_chip)
	275	nand_chip.select_chip(&mtd, 0);
	276	}
	277
	278	/* Unselect after operation */
	279	void nand_deselect(void)
	280	{
	281	if (nand_chip.select_chip)
	282	nand_chip.select_chip(&mtd, -1);
	283	}