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12201a13 DB |
1 | /* |
2 | * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> | |
3 | * Rohit Choraria <rohitkc@ti.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
12201a13 DB |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/io.h> | |
10 | #include <asm/errno.h> | |
11 | #include <asm/arch/mem.h> | |
6aff0509 | 12 | #include <linux/mtd/omap_gpmc.h> |
12201a13 | 13 | #include <linux/mtd/nand_ecc.h> |
4a093006 | 14 | #include <linux/bch.h> |
f7dad8f1 | 15 | #include <linux/compiler.h> |
12201a13 | 16 | #include <nand.h> |
2eda892f | 17 | #include <linux/mtd/omap_elm.h> |
d016dc42 | 18 | |
19 | #define BADBLOCK_MARKER_LENGTH 2 | |
20 | #define SECTOR_BYTES 512 | |
f5f1f614 | 21 | #define ECCCLEAR (0x1 << 8) |
22 | #define ECCRESULTREG1 (0x1 << 0) | |
6e562b11 | 23 | /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ |
24 | #define BCH4_BIT_PAD 4 | |
25 | ||
71a7f956 | 26 | #ifdef CONFIG_BCH |
27 | static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, | |
28 | 0x97, 0x79, 0xe5, 0x24, 0xb5}; | |
29 | #endif | |
5c3f7e0e | 30 | static uint8_t cs_next; |
d016dc42 | 31 | static __maybe_unused struct nand_ecclayout omap_ecclayout; |
12201a13 | 32 | |
5c3f7e0e RL |
33 | /* |
34 | * Driver configurations | |
35 | */ | |
36 | struct omap_nand_info { | |
37 | struct bch_control *control; | |
38 | enum omap_ecc ecc_scheme; | |
39 | int cs; | |
40 | }; | |
41 | ||
42 | /* We are wasting a bit of memory but al least we are safe */ | |
43 | static struct omap_nand_info omap_nand_info[GPMC_MAX_CS]; | |
44 | ||
12201a13 DB |
45 | /* |
46 | * omap_nand_hwcontrol - Set the address pointers corretly for the | |
47 | * following address/data/command operation | |
48 | */ | |
49 | static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, | |
50 | uint32_t ctrl) | |
51 | { | |
52 | register struct nand_chip *this = mtd->priv; | |
5c3f7e0e RL |
53 | struct omap_nand_info *info = this->priv; |
54 | int cs = info->cs; | |
12201a13 DB |
55 | |
56 | /* | |
57 | * Point the IO_ADDR to DATA and ADDRESS registers instead | |
58 | * of chip address | |
59 | */ | |
60 | switch (ctrl) { | |
61 | case NAND_CTRL_CHANGE | NAND_CTRL_CLE: | |
89411352 | 62 | this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; |
12201a13 DB |
63 | break; |
64 | case NAND_CTRL_CHANGE | NAND_CTRL_ALE: | |
89411352 | 65 | this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; |
12201a13 DB |
66 | break; |
67 | case NAND_CTRL_CHANGE | NAND_NCE: | |
89411352 | 68 | this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; |
12201a13 DB |
69 | break; |
70 | } | |
71 | ||
72 | if (cmd != NAND_CMD_NONE) | |
73 | writeb(cmd, this->IO_ADDR_W); | |
74 | } | |
75 | ||
12c2f1ee SS |
76 | #ifdef CONFIG_SPL_BUILD |
77 | /* Check wait pin as dev ready indicator */ | |
78 | int omap_spl_dev_ready(struct mtd_info *mtd) | |
79 | { | |
80 | return gpmc_cfg->status & (1 << 8); | |
81 | } | |
82 | #endif | |
83 | ||
12201a13 DB |
84 | |
85 | /* | |
86 | * gen_true_ecc - This function will generate true ECC value, which | |
87 | * can be used when correcting data read from NAND flash memory core | |
88 | * | |
89 | * @ecc_buf: buffer to store ecc code | |
90 | * | |
91 | * @return: re-formatted ECC value | |
92 | */ | |
93 | static uint32_t gen_true_ecc(uint8_t *ecc_buf) | |
94 | { | |
95 | return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) | | |
96 | ((ecc_buf[2] & 0x0F) << 8); | |
97 | } | |
98 | ||
99 | /* | |
100 | * omap_correct_data - Compares the ecc read from nand spare area with ECC | |
101 | * registers values and corrects one bit error if it has occured | |
102 | * Further details can be had from OMAP TRM and the following selected links: | |
103 | * http://en.wikipedia.org/wiki/Hamming_code | |
104 | * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf | |
105 | * | |
106 | * @mtd: MTD device structure | |
107 | * @dat: page data | |
108 | * @read_ecc: ecc read from nand flash | |
109 | * @calc_ecc: ecc read from ECC registers | |
110 | * | |
111 | * @return 0 if data is OK or corrected, else returns -1 | |
112 | */ | |
f7dad8f1 | 113 | static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, |
12201a13 DB |
114 | uint8_t *read_ecc, uint8_t *calc_ecc) |
115 | { | |
116 | uint32_t orig_ecc, new_ecc, res, hm; | |
117 | uint16_t parity_bits, byte; | |
118 | uint8_t bit; | |
119 | ||
120 | /* Regenerate the orginal ECC */ | |
121 | orig_ecc = gen_true_ecc(read_ecc); | |
122 | new_ecc = gen_true_ecc(calc_ecc); | |
123 | /* Get the XOR of real ecc */ | |
124 | res = orig_ecc ^ new_ecc; | |
125 | if (res) { | |
126 | /* Get the hamming width */ | |
127 | hm = hweight32(res); | |
128 | /* Single bit errors can be corrected! */ | |
129 | if (hm == 12) { | |
130 | /* Correctable data! */ | |
131 | parity_bits = res >> 16; | |
132 | bit = (parity_bits & 0x7); | |
133 | byte = (parity_bits >> 3) & 0x1FF; | |
134 | /* Flip the bit to correct */ | |
135 | dat[byte] ^= (0x1 << bit); | |
136 | } else if (hm == 1) { | |
137 | printf("Error: Ecc is wrong\n"); | |
138 | /* ECC itself is corrupted */ | |
139 | return 2; | |
140 | } else { | |
141 | /* | |
142 | * hm distance != parity pairs OR one, could mean 2 bit | |
143 | * error OR potentially be on a blank page.. | |
144 | * orig_ecc: contains spare area data from nand flash. | |
145 | * new_ecc: generated ecc while reading data area. | |
146 | * Note: if the ecc = 0, all data bits from which it was | |
147 | * generated are 0xFF. | |
148 | * The 3 byte(24 bits) ecc is generated per 512byte | |
149 | * chunk of a page. If orig_ecc(from spare area) | |
150 | * is 0xFF && new_ecc(computed now from data area)=0x0, | |
151 | * this means that data area is 0xFF and spare area is | |
152 | * 0xFF. A sure sign of a erased page! | |
153 | */ | |
154 | if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000)) | |
155 | return 0; | |
156 | printf("Error: Bad compare! failed\n"); | |
157 | /* detected 2 bit error */ | |
158 | return -1; | |
159 | } | |
160 | } | |
161 | return 0; | |
162 | } | |
163 | ||
6e562b11 | 164 | /* |
165 | * omap_reverse_list - re-orders list elements in reverse order [internal] | |
166 | * @list: pointer to start of list | |
167 | * @length: length of list | |
168 | */ | |
169 | void omap_reverse_list(u8 *list, unsigned int length) | |
170 | { | |
171 | unsigned int i, j; | |
172 | unsigned int half_length = length / 2; | |
173 | u8 tmp; | |
174 | for (i = 0, j = length - 1; i < half_length; i++, j--) { | |
175 | tmp = list[i]; | |
176 | list[i] = list[j]; | |
177 | list[j] = tmp; | |
178 | } | |
179 | } | |
180 | ||
4a093006 | 181 | /* |
f5f1f614 | 182 | * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write |
4a093006 AB |
183 | * @mtd: MTD device structure |
184 | * @mode: Read/Write mode | |
185 | */ | |
186 | __maybe_unused | |
f5f1f614 | 187 | static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) |
4a093006 | 188 | { |
f5f1f614 | 189 | struct nand_chip *nand = mtd->priv; |
9233279f | 190 | struct omap_nand_info *info = nand->priv; |
f5f1f614 | 191 | unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; |
192 | unsigned int ecc_algo = 0; | |
193 | unsigned int bch_type = 0; | |
194 | unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00; | |
195 | u32 ecc_size_config_val = 0; | |
196 | u32 ecc_config_val = 0; | |
5c3f7e0e | 197 | int cs = info->cs; |
f5f1f614 | 198 | |
199 | /* configure GPMC for specific ecc-scheme */ | |
9233279f | 200 | switch (info->ecc_scheme) { |
f5f1f614 | 201 | case OMAP_ECC_HAM1_CODE_SW: |
202 | return; | |
203 | case OMAP_ECC_HAM1_CODE_HW: | |
204 | ecc_algo = 0x0; | |
205 | bch_type = 0x0; | |
206 | bch_wrapmode = 0x00; | |
207 | eccsize0 = 0xFF; | |
208 | eccsize1 = 0xFF; | |
209 | break; | |
210 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
211 | case OMAP_ECC_BCH8_CODE_HW: | |
212 | ecc_algo = 0x1; | |
213 | bch_type = 0x1; | |
214 | if (mode == NAND_ECC_WRITE) { | |
215 | bch_wrapmode = 0x01; | |
216 | eccsize0 = 0; /* extra bits in nibbles per sector */ | |
217 | eccsize1 = 28; /* OOB bits in nibbles per sector */ | |
218 | } else { | |
219 | bch_wrapmode = 0x01; | |
220 | eccsize0 = 26; /* ECC bits in nibbles per sector */ | |
221 | eccsize1 = 2; /* non-ECC bits in nibbles per sector */ | |
5d7a49b9 | 222 | } |
f5f1f614 | 223 | break; |
46840f66 | 224 | case OMAP_ECC_BCH16_CODE_HW: |
225 | ecc_algo = 0x1; | |
226 | bch_type = 0x2; | |
227 | if (mode == NAND_ECC_WRITE) { | |
228 | bch_wrapmode = 0x01; | |
229 | eccsize0 = 0; /* extra bits in nibbles per sector */ | |
230 | eccsize1 = 52; /* OOB bits in nibbles per sector */ | |
231 | } else { | |
232 | bch_wrapmode = 0x01; | |
233 | eccsize0 = 52; /* ECC bits in nibbles per sector */ | |
234 | eccsize1 = 0; /* non-ECC bits in nibbles per sector */ | |
235 | } | |
236 | break; | |
f5f1f614 | 237 | default: |
238 | return; | |
d016dc42 | 239 | } |
f5f1f614 | 240 | /* Clear ecc and enable bits */ |
241 | writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); | |
242 | /* Configure ecc size for BCH */ | |
243 | ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12); | |
244 | writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config); | |
245 | ||
246 | /* Configure device details for BCH engine */ | |
247 | ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */ | |
248 | (bch_type << 12) | /* BCH4/BCH8/BCH16 */ | |
249 | (bch_wrapmode << 8) | /* wrap mode */ | |
250 | (dev_width << 7) | /* bus width */ | |
251 | (0x0 << 4) | /* number of sectors */ | |
252 | (cs << 1) | /* ECC CS */ | |
253 | (0x1)); /* enable ECC */ | |
254 | writel(ecc_config_val, &gpmc_cfg->ecc_config); | |
4a093006 AB |
255 | } |
256 | ||
257 | /* | |
71a7f956 | 258 | * omap_calculate_ecc - Read ECC result |
259 | * @mtd: MTD structure | |
260 | * @dat: unused | |
261 | * @ecc_code: ecc_code buffer | |
262 | * Using noninverted ECC can be considered ugly since writing a blank | |
263 | * page ie. padding will clear the ECC bytes. This is no problem as | |
264 | * long nobody is trying to write data on the seemingly unused page. | |
265 | * Reading an erased page will produce an ECC mismatch between | |
266 | * generated and read ECC bytes that has to be dealt with separately. | |
267 | * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC | |
268 | * is used, the result of read will be 0x0 while the ECC offsets of the | |
269 | * spare area will be 0xFF which will result in an ECC mismatch. | |
c3754e9c | 270 | */ |
71a7f956 | 271 | static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, |
c3754e9c MA |
272 | uint8_t *ecc_code) |
273 | { | |
71a7f956 | 274 | struct nand_chip *chip = mtd->priv; |
9233279f | 275 | struct omap_nand_info *info = chip->priv; |
71a7f956 | 276 | uint32_t *ptr, val = 0; |
c3754e9c MA |
277 | int8_t i = 0, j; |
278 | ||
9233279f | 279 | switch (info->ecc_scheme) { |
71a7f956 | 280 | case OMAP_ECC_HAM1_CODE_HW: |
281 | val = readl(&gpmc_cfg->ecc1_result); | |
282 | ecc_code[0] = val & 0xFF; | |
283 | ecc_code[1] = (val >> 16) & 0xFF; | |
284 | ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); | |
285 | break; | |
286 | #ifdef CONFIG_BCH | |
287 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
288 | #endif | |
289 | case OMAP_ECC_BCH8_CODE_HW: | |
c3754e9c | 290 | ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; |
71a7f956 | 291 | val = readl(ptr); |
292 | ecc_code[i++] = (val >> 0) & 0xFF; | |
c3754e9c MA |
293 | ptr--; |
294 | for (j = 0; j < 3; j++) { | |
71a7f956 | 295 | val = readl(ptr); |
296 | ecc_code[i++] = (val >> 24) & 0xFF; | |
297 | ecc_code[i++] = (val >> 16) & 0xFF; | |
298 | ecc_code[i++] = (val >> 8) & 0xFF; | |
299 | ecc_code[i++] = (val >> 0) & 0xFF; | |
c3754e9c MA |
300 | ptr--; |
301 | } | |
71a7f956 | 302 | break; |
46840f66 | 303 | case OMAP_ECC_BCH16_CODE_HW: |
304 | val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]); | |
305 | ecc_code[i++] = (val >> 8) & 0xFF; | |
306 | ecc_code[i++] = (val >> 0) & 0xFF; | |
307 | val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]); | |
308 | ecc_code[i++] = (val >> 24) & 0xFF; | |
309 | ecc_code[i++] = (val >> 16) & 0xFF; | |
310 | ecc_code[i++] = (val >> 8) & 0xFF; | |
311 | ecc_code[i++] = (val >> 0) & 0xFF; | |
312 | val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]); | |
313 | ecc_code[i++] = (val >> 24) & 0xFF; | |
314 | ecc_code[i++] = (val >> 16) & 0xFF; | |
315 | ecc_code[i++] = (val >> 8) & 0xFF; | |
316 | ecc_code[i++] = (val >> 0) & 0xFF; | |
317 | for (j = 3; j >= 0; j--) { | |
318 | val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j] | |
319 | ); | |
320 | ecc_code[i++] = (val >> 24) & 0xFF; | |
321 | ecc_code[i++] = (val >> 16) & 0xFF; | |
322 | ecc_code[i++] = (val >> 8) & 0xFF; | |
323 | ecc_code[i++] = (val >> 0) & 0xFF; | |
324 | } | |
325 | break; | |
71a7f956 | 326 | default: |
327 | return -EINVAL; | |
328 | } | |
329 | /* ECC scheme specific syndrome customizations */ | |
9233279f | 330 | switch (info->ecc_scheme) { |
71a7f956 | 331 | case OMAP_ECC_HAM1_CODE_HW: |
332 | break; | |
333 | #ifdef CONFIG_BCH | |
334 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
335 | ||
336 | for (i = 0; i < chip->ecc.bytes; i++) | |
337 | *(ecc_code + i) = *(ecc_code + i) ^ | |
338 | bch8_polynomial[i]; | |
339 | break; | |
340 | #endif | |
341 | case OMAP_ECC_BCH8_CODE_HW: | |
342 | ecc_code[chip->ecc.bytes - 1] = 0x00; | |
343 | break; | |
46840f66 | 344 | case OMAP_ECC_BCH16_CODE_HW: |
345 | break; | |
71a7f956 | 346 | default: |
347 | return -EINVAL; | |
c3754e9c | 348 | } |
71a7f956 | 349 | return 0; |
c3754e9c MA |
350 | } |
351 | ||
71a7f956 | 352 | #ifdef CONFIG_NAND_OMAP_ELM |
c3754e9c MA |
353 | /* |
354 | * omap_correct_data_bch - Compares the ecc read from nand spare area | |
355 | * with ECC registers values and corrects one bit error if it has occured | |
356 | * | |
357 | * @mtd: MTD device structure | |
358 | * @dat: page data | |
359 | * @read_ecc: ecc read from nand flash (ignored) | |
360 | * @calc_ecc: ecc read from ECC registers | |
361 | * | |
362 | * @return 0 if data is OK or corrected, else returns -1 | |
363 | */ | |
364 | static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, | |
365 | uint8_t *read_ecc, uint8_t *calc_ecc) | |
366 | { | |
367 | struct nand_chip *chip = mtd->priv; | |
9233279f | 368 | struct omap_nand_info *info = chip->priv; |
a09431da | 369 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
6e562b11 | 370 | uint32_t error_count = 0, error_max; |
46840f66 | 371 | uint32_t error_loc[ELM_MAX_ERROR_COUNT]; |
d21e77ff | 372 | enum bch_level bch_type; |
6e562b11 | 373 | uint32_t i, ecc_flag = 0; |
374 | uint8_t count, err = 0; | |
375 | uint32_t byte_pos, bit_pos; | |
376 | ||
377 | /* check calculated ecc */ | |
a09431da | 378 | for (i = 0; i < ecc->bytes && !ecc_flag; i++) { |
6e562b11 | 379 | if (calc_ecc[i] != 0x00) |
380 | ecc_flag = 1; | |
381 | } | |
382 | if (!ecc_flag) | |
383 | return 0; | |
c3754e9c | 384 | |
6e562b11 | 385 | /* check for whether its a erased-page */ |
c3754e9c | 386 | ecc_flag = 0; |
a09431da | 387 | for (i = 0; i < ecc->bytes && !ecc_flag; i++) { |
c3754e9c MA |
388 | if (read_ecc[i] != 0xff) |
389 | ecc_flag = 1; | |
6e562b11 | 390 | } |
c3754e9c MA |
391 | if (!ecc_flag) |
392 | return 0; | |
393 | ||
c3754e9c MA |
394 | /* |
395 | * while reading ECC result we read it in big endian. | |
396 | * Hence while loading to ELM we have rotate to get the right endian. | |
397 | */ | |
9233279f | 398 | switch (info->ecc_scheme) { |
6e562b11 | 399 | case OMAP_ECC_BCH8_CODE_HW: |
d21e77ff | 400 | bch_type = BCH_8_BIT; |
a09431da | 401 | omap_reverse_list(calc_ecc, ecc->bytes - 1); |
6e562b11 | 402 | break; |
46840f66 | 403 | case OMAP_ECC_BCH16_CODE_HW: |
404 | bch_type = BCH_16_BIT; | |
405 | omap_reverse_list(calc_ecc, ecc->bytes); | |
406 | break; | |
6e562b11 | 407 | default: |
408 | return -EINVAL; | |
409 | } | |
c3754e9c | 410 | /* use elm module to check for errors */ |
d21e77ff | 411 | elm_config(bch_type); |
3f990dc8 | 412 | err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc); |
413 | if (err) | |
414 | return err; | |
415 | ||
c3754e9c | 416 | /* correct bch error */ |
6e562b11 | 417 | for (count = 0; count < error_count; count++) { |
9233279f | 418 | switch (info->ecc_scheme) { |
d21e77ff | 419 | case OMAP_ECC_BCH8_CODE_HW: |
6e562b11 | 420 | /* 14th byte in ECC is reserved to match ROM layout */ |
a09431da | 421 | error_max = SECTOR_BYTES + (ecc->bytes - 1); |
6e562b11 | 422 | break; |
46840f66 | 423 | case OMAP_ECC_BCH16_CODE_HW: |
424 | error_max = SECTOR_BYTES + ecc->bytes; | |
425 | break; | |
6e562b11 | 426 | default: |
427 | return -EINVAL; | |
428 | } | |
429 | byte_pos = error_max - (error_loc[count] / 8) - 1; | |
430 | bit_pos = error_loc[count] % 8; | |
431 | if (byte_pos < SECTOR_BYTES) { | |
432 | dat[byte_pos] ^= 1 << bit_pos; | |
433 | printf("nand: bit-flip corrected @data=%d\n", byte_pos); | |
434 | } else if (byte_pos < error_max) { | |
97eeae1a | 435 | read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos; |
6e562b11 | 436 | printf("nand: bit-flip corrected @oob=%d\n", byte_pos - |
437 | SECTOR_BYTES); | |
438 | } else { | |
439 | err = -EBADMSG; | |
440 | printf("nand: error: invalid bit-flip location\n"); | |
441 | } | |
442 | } | |
443 | return (err) ? err : error_count; | |
c3754e9c | 444 | } |
c3754e9c MA |
445 | |
446 | /** | |
447 | * omap_read_page_bch - hardware ecc based page read function | |
448 | * @mtd: mtd info structure | |
449 | * @chip: nand chip info structure | |
450 | * @buf: buffer to store read data | |
dfe64e2c | 451 | * @oob_required: caller expects OOB data read to chip->oob_poi |
c3754e9c MA |
452 | * @page: page number to read |
453 | * | |
454 | */ | |
455 | static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
dfe64e2c | 456 | uint8_t *buf, int oob_required, int page) |
c3754e9c MA |
457 | { |
458 | int i, eccsize = chip->ecc.size; | |
459 | int eccbytes = chip->ecc.bytes; | |
460 | int eccsteps = chip->ecc.steps; | |
461 | uint8_t *p = buf; | |
462 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
463 | uint8_t *ecc_code = chip->buffers->ecccode; | |
464 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
465 | uint8_t *oob = chip->oob_poi; | |
466 | uint32_t data_pos; | |
467 | uint32_t oob_pos; | |
468 | ||
469 | data_pos = 0; | |
470 | /* oob area start */ | |
471 | oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; | |
472 | oob += chip->ecc.layout->eccpos[0]; | |
473 | ||
474 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, | |
475 | oob += eccbytes) { | |
476 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
477 | /* read data */ | |
478 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page); | |
479 | chip->read_buf(mtd, p, eccsize); | |
480 | ||
481 | /* read respective ecc from oob area */ | |
482 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page); | |
483 | chip->read_buf(mtd, oob, eccbytes); | |
484 | /* read syndrome */ | |
485 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
486 | ||
487 | data_pos += eccsize; | |
488 | oob_pos += eccbytes; | |
489 | } | |
490 | ||
491 | for (i = 0; i < chip->ecc.total; i++) | |
492 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
493 | ||
494 | eccsteps = chip->ecc.steps; | |
495 | p = buf; | |
496 | ||
497 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
498 | int stat; | |
499 | ||
500 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
501 | if (stat < 0) | |
502 | mtd->ecc_stats.failed++; | |
503 | else | |
504 | mtd->ecc_stats.corrected += stat; | |
505 | } | |
506 | return 0; | |
507 | } | |
d016dc42 | 508 | #endif /* CONFIG_NAND_OMAP_ELM */ |
c3754e9c | 509 | |
4a093006 AB |
510 | /* |
511 | * OMAP3 BCH8 support (with BCH library) | |
512 | */ | |
d016dc42 | 513 | #ifdef CONFIG_BCH |
4a093006 | 514 | /** |
d016dc42 | 515 | * omap_correct_data_bch_sw - Decode received data and correct errors |
4a093006 AB |
516 | * @mtd: MTD device structure |
517 | * @data: page data | |
518 | * @read_ecc: ecc read from nand flash | |
519 | * @calc_ecc: ecc read from HW ECC registers | |
520 | */ | |
d016dc42 | 521 | static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, |
4a093006 AB |
522 | u_char *read_ecc, u_char *calc_ecc) |
523 | { | |
524 | int i, count; | |
525 | /* cannot correct more than 8 errors */ | |
526 | unsigned int errloc[8]; | |
527 | struct nand_chip *chip = mtd->priv; | |
9233279f | 528 | struct omap_nand_info *info = chip->priv; |
4a093006 | 529 | |
9233279f | 530 | count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc, |
531 | NULL, errloc); | |
4a093006 AB |
532 | if (count > 0) { |
533 | /* correct errors */ | |
534 | for (i = 0; i < count; i++) { | |
535 | /* correct data only, not ecc bytes */ | |
536 | if (errloc[i] < 8*512) | |
537 | data[errloc[i]/8] ^= 1 << (errloc[i] & 7); | |
538 | printf("corrected bitflip %u\n", errloc[i]); | |
539 | #ifdef DEBUG | |
540 | puts("read_ecc: "); | |
541 | /* | |
542 | * BCH8 have 13 bytes of ECC; BCH4 needs adoption | |
543 | * here! | |
544 | */ | |
545 | for (i = 0; i < 13; i++) | |
546 | printf("%02x ", read_ecc[i]); | |
547 | puts("\n"); | |
548 | puts("calc_ecc: "); | |
549 | for (i = 0; i < 13; i++) | |
550 | printf("%02x ", calc_ecc[i]); | |
551 | puts("\n"); | |
552 | #endif | |
553 | } | |
554 | } else if (count < 0) { | |
555 | puts("ecc unrecoverable error\n"); | |
556 | } | |
557 | return count; | |
558 | } | |
559 | ||
560 | /** | |
561 | * omap_free_bch - Release BCH ecc resources | |
562 | * @mtd: MTD device structure | |
563 | */ | |
564 | static void __maybe_unused omap_free_bch(struct mtd_info *mtd) | |
565 | { | |
566 | struct nand_chip *chip = mtd->priv; | |
9233279f | 567 | struct omap_nand_info *info = chip->priv; |
4a093006 | 568 | |
9233279f | 569 | if (info->control) { |
570 | free_bch(info->control); | |
571 | info->control = NULL; | |
4a093006 AB |
572 | } |
573 | } | |
d016dc42 | 574 | #endif /* CONFIG_BCH */ |
575 | ||
576 | /** | |
577 | * omap_select_ecc_scheme - configures driver for particular ecc-scheme | |
578 | * @nand: NAND chip device structure | |
579 | * @ecc_scheme: ecc scheme to configure | |
580 | * @pagesize: number of main-area bytes per page of NAND device | |
581 | * @oobsize: number of OOB/spare bytes per page of NAND device | |
582 | */ | |
583 | static int omap_select_ecc_scheme(struct nand_chip *nand, | |
584 | enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { | |
9233279f | 585 | struct omap_nand_info *info = nand->priv; |
eb237a15 | 586 | struct nand_ecclayout *ecclayout = &omap_ecclayout; |
d016dc42 | 587 | int eccsteps = pagesize / SECTOR_BYTES; |
588 | int i; | |
589 | ||
590 | switch (ecc_scheme) { | |
591 | case OMAP_ECC_HAM1_CODE_SW: | |
592 | debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); | |
593 | /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are | |
594 | * initialized in nand_scan_tail(), so just set ecc.mode */ | |
9233279f | 595 | info->control = NULL; |
d016dc42 | 596 | nand->ecc.mode = NAND_ECC_SOFT; |
597 | nand->ecc.layout = NULL; | |
2528460c | 598 | nand->ecc.size = 0; |
d016dc42 | 599 | break; |
600 | ||
601 | case OMAP_ECC_HAM1_CODE_HW: | |
602 | debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n"); | |
603 | /* check ecc-scheme requirements before updating ecc info */ | |
604 | if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { | |
605 | printf("nand: error: insufficient OOB: require=%d\n", ( | |
606 | (3 * eccsteps) + BADBLOCK_MARKER_LENGTH)); | |
607 | return -EINVAL; | |
608 | } | |
9233279f | 609 | info->control = NULL; |
d016dc42 | 610 | /* populate ecc specific fields */ |
fcd05245 | 611 | memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); |
d016dc42 | 612 | nand->ecc.mode = NAND_ECC_HW; |
613 | nand->ecc.strength = 1; | |
614 | nand->ecc.size = SECTOR_BYTES; | |
615 | nand->ecc.bytes = 3; | |
616 | nand->ecc.hwctl = omap_enable_hwecc; | |
617 | nand->ecc.correct = omap_correct_data; | |
618 | nand->ecc.calculate = omap_calculate_ecc; | |
619 | /* define ecc-layout */ | |
620 | ecclayout->eccbytes = nand->ecc.bytes * eccsteps; | |
69cc97f8 | 621 | for (i = 0; i < ecclayout->eccbytes; i++) { |
622 | if (nand->options & NAND_BUSWIDTH_16) | |
623 | ecclayout->eccpos[i] = i + 2; | |
624 | else | |
625 | ecclayout->eccpos[i] = i + 1; | |
626 | } | |
d016dc42 | 627 | ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; |
628 | ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - | |
629 | BADBLOCK_MARKER_LENGTH; | |
d016dc42 | 630 | break; |
631 | ||
632 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
633 | #ifdef CONFIG_BCH | |
634 | debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); | |
635 | /* check ecc-scheme requirements before updating ecc info */ | |
636 | if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { | |
637 | printf("nand: error: insufficient OOB: require=%d\n", ( | |
638 | (13 * eccsteps) + BADBLOCK_MARKER_LENGTH)); | |
639 | return -EINVAL; | |
640 | } | |
641 | /* check if BCH S/W library can be used for error detection */ | |
9233279f | 642 | info->control = init_bch(13, 8, 0x201b); |
643 | if (!info->control) { | |
d016dc42 | 644 | printf("nand: error: could not init_bch()\n"); |
645 | return -ENODEV; | |
646 | } | |
d016dc42 | 647 | /* populate ecc specific fields */ |
fcd05245 | 648 | memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); |
d016dc42 | 649 | nand->ecc.mode = NAND_ECC_HW; |
650 | nand->ecc.strength = 8; | |
651 | nand->ecc.size = SECTOR_BYTES; | |
652 | nand->ecc.bytes = 13; | |
f5f1f614 | 653 | nand->ecc.hwctl = omap_enable_hwecc; |
d016dc42 | 654 | nand->ecc.correct = omap_correct_data_bch_sw; |
71a7f956 | 655 | nand->ecc.calculate = omap_calculate_ecc; |
d016dc42 | 656 | /* define ecc-layout */ |
657 | ecclayout->eccbytes = nand->ecc.bytes * eccsteps; | |
658 | ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; | |
659 | for (i = 1; i < ecclayout->eccbytes; i++) { | |
660 | if (i % nand->ecc.bytes) | |
661 | ecclayout->eccpos[i] = | |
662 | ecclayout->eccpos[i - 1] + 1; | |
663 | else | |
664 | ecclayout->eccpos[i] = | |
665 | ecclayout->eccpos[i - 1] + 2; | |
666 | } | |
667 | ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; | |
668 | ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - | |
669 | BADBLOCK_MARKER_LENGTH; | |
d016dc42 | 670 | break; |
671 | #else | |
672 | printf("nand: error: CONFIG_BCH required for ECC\n"); | |
673 | return -EINVAL; | |
674 | #endif | |
675 | ||
676 | case OMAP_ECC_BCH8_CODE_HW: | |
677 | #ifdef CONFIG_NAND_OMAP_ELM | |
678 | debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n"); | |
679 | /* check ecc-scheme requirements before updating ecc info */ | |
680 | if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { | |
681 | printf("nand: error: insufficient OOB: require=%d\n", ( | |
682 | (14 * eccsteps) + BADBLOCK_MARKER_LENGTH)); | |
683 | return -EINVAL; | |
684 | } | |
685 | /* intialize ELM for ECC error detection */ | |
686 | elm_init(); | |
9233279f | 687 | info->control = NULL; |
d016dc42 | 688 | /* populate ecc specific fields */ |
fcd05245 | 689 | memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); |
d016dc42 | 690 | nand->ecc.mode = NAND_ECC_HW; |
691 | nand->ecc.strength = 8; | |
692 | nand->ecc.size = SECTOR_BYTES; | |
693 | nand->ecc.bytes = 14; | |
f5f1f614 | 694 | nand->ecc.hwctl = omap_enable_hwecc; |
d016dc42 | 695 | nand->ecc.correct = omap_correct_data_bch; |
71a7f956 | 696 | nand->ecc.calculate = omap_calculate_ecc; |
d016dc42 | 697 | nand->ecc.read_page = omap_read_page_bch; |
698 | /* define ecc-layout */ | |
699 | ecclayout->eccbytes = nand->ecc.bytes * eccsteps; | |
700 | for (i = 0; i < ecclayout->eccbytes; i++) | |
701 | ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; | |
702 | ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; | |
703 | ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - | |
704 | BADBLOCK_MARKER_LENGTH; | |
d016dc42 | 705 | break; |
706 | #else | |
707 | printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); | |
708 | return -EINVAL; | |
709 | #endif | |
710 | ||
46840f66 | 711 | case OMAP_ECC_BCH16_CODE_HW: |
712 | #ifdef CONFIG_NAND_OMAP_ELM | |
713 | debug("nand: using OMAP_ECC_BCH16_CODE_HW\n"); | |
714 | /* check ecc-scheme requirements before updating ecc info */ | |
715 | if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { | |
716 | printf("nand: error: insufficient OOB: require=%d\n", ( | |
717 | (26 * eccsteps) + BADBLOCK_MARKER_LENGTH)); | |
718 | return -EINVAL; | |
719 | } | |
720 | /* intialize ELM for ECC error detection */ | |
721 | elm_init(); | |
722 | /* populate ecc specific fields */ | |
723 | nand->ecc.mode = NAND_ECC_HW; | |
724 | nand->ecc.size = SECTOR_BYTES; | |
725 | nand->ecc.bytes = 26; | |
726 | nand->ecc.strength = 16; | |
727 | nand->ecc.hwctl = omap_enable_hwecc; | |
728 | nand->ecc.correct = omap_correct_data_bch; | |
729 | nand->ecc.calculate = omap_calculate_ecc; | |
730 | nand->ecc.read_page = omap_read_page_bch; | |
731 | /* define ecc-layout */ | |
732 | ecclayout->eccbytes = nand->ecc.bytes * eccsteps; | |
733 | for (i = 0; i < ecclayout->eccbytes; i++) | |
734 | ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; | |
735 | ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; | |
736 | ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes - | |
737 | BADBLOCK_MARKER_LENGTH; | |
738 | break; | |
739 | #else | |
740 | printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); | |
741 | return -EINVAL; | |
742 | #endif | |
d016dc42 | 743 | default: |
744 | debug("nand: error: ecc scheme not enabled or supported\n"); | |
745 | return -EINVAL; | |
746 | } | |
eb237a15 NK |
747 | |
748 | /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */ | |
749 | if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW) | |
750 | nand->ecc.layout = ecclayout; | |
751 | ||
9233279f | 752 | info->ecc_scheme = ecc_scheme; |
d016dc42 | 753 | return 0; |
754 | } | |
4a093006 | 755 | |
12c2f1ee | 756 | #ifndef CONFIG_SPL_BUILD |
12201a13 | 757 | /* |
da634ae3 AB |
758 | * omap_nand_switch_ecc - switch the ECC operation between different engines |
759 | * (h/w and s/w) and different algorithms (hamming and BCHx) | |
12201a13 | 760 | * |
da634ae3 AB |
761 | * @hardware - true if one of the HW engines should be used |
762 | * @eccstrength - the number of bits that could be corrected | |
763 | * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16) | |
12201a13 | 764 | */ |
d016dc42 | 765 | int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) |
12201a13 DB |
766 | { |
767 | struct nand_chip *nand; | |
768 | struct mtd_info *mtd; | |
d016dc42 | 769 | int err = 0; |
12201a13 DB |
770 | |
771 | if (nand_curr_device < 0 || | |
772 | nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || | |
773 | !nand_info[nand_curr_device].name) { | |
d016dc42 | 774 | printf("nand: error: no NAND devices found\n"); |
775 | return -ENODEV; | |
12201a13 DB |
776 | } |
777 | ||
778 | mtd = &nand_info[nand_curr_device]; | |
779 | nand = mtd->priv; | |
12201a13 | 780 | nand->options |= NAND_OWN_BUFFERS; |
13fbde6e | 781 | nand->options &= ~NAND_SUBPAGE_READ; |
12201a13 | 782 | /* Setup the ecc configurations again */ |
da634ae3 AB |
783 | if (hardware) { |
784 | if (eccstrength == 1) { | |
d016dc42 | 785 | err = omap_select_ecc_scheme(nand, |
786 | OMAP_ECC_HAM1_CODE_HW, | |
787 | mtd->writesize, mtd->oobsize); | |
788 | } else if (eccstrength == 8) { | |
789 | err = omap_select_ecc_scheme(nand, | |
790 | OMAP_ECC_BCH8_CODE_HW, | |
791 | mtd->writesize, mtd->oobsize); | |
792 | } else { | |
793 | printf("nand: error: unsupported ECC scheme\n"); | |
794 | return -EINVAL; | |
da634ae3 | 795 | } |
12201a13 | 796 | } else { |
d016dc42 | 797 | err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, |
798 | mtd->writesize, mtd->oobsize); | |
12201a13 DB |
799 | } |
800 | ||
801 | /* Update NAND handling after ECC mode switch */ | |
d016dc42 | 802 | if (!err) |
803 | err = nand_scan_tail(mtd); | |
804 | return err; | |
12201a13 | 805 | } |
12c2f1ee | 806 | #endif /* CONFIG_SPL_BUILD */ |
12201a13 DB |
807 | |
808 | /* | |
809 | * Board-specific NAND initialization. The following members of the | |
810 | * argument are board-specific: | |
811 | * - IO_ADDR_R: address to read the 8 I/O lines of the flash device | |
812 | * - IO_ADDR_W: address to write the 8 I/O lines of the flash device | |
813 | * - cmd_ctrl: hardwarespecific function for accesing control-lines | |
814 | * - waitfunc: hardwarespecific function for accesing device ready/busy line | |
815 | * - ecc.hwctl: function to enable (reset) hardware ecc generator | |
816 | * - ecc.mode: mode of ecc, see defines | |
817 | * - chip_delay: chip dependent delay for transfering data from array to | |
818 | * read regs (tR) | |
819 | * - options: various chip options. They can partly be set to inform | |
820 | * nand_scan about special functionality. See the defines for further | |
821 | * explanation | |
822 | */ | |
823 | int board_nand_init(struct nand_chip *nand) | |
824 | { | |
825 | int32_t gpmc_config = 0; | |
5c3f7e0e | 826 | int cs = cs_next++; |
d016dc42 | 827 | int err = 0; |
12201a13 DB |
828 | /* |
829 | * xloader/Uboot's gpmc configuration would have configured GPMC for | |
830 | * nand type of memory. The following logic scans and latches on to the | |
831 | * first CS with NAND type memory. | |
832 | * TBD: need to make this logic generic to handle multiple CS NAND | |
833 | * devices. | |
834 | */ | |
835 | while (cs < GPMC_MAX_CS) { | |
12201a13 | 836 | /* Check if NAND type is set */ |
89411352 | 837 | if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) { |
12201a13 DB |
838 | /* Found it!! */ |
839 | break; | |
840 | } | |
841 | cs++; | |
842 | } | |
843 | if (cs >= GPMC_MAX_CS) { | |
d016dc42 | 844 | printf("nand: error: Unable to find NAND settings in " |
12201a13 DB |
845 | "GPMC Configuration - quitting\n"); |
846 | return -ENODEV; | |
847 | } | |
848 | ||
89411352 | 849 | gpmc_config = readl(&gpmc_cfg->config); |
12201a13 DB |
850 | /* Disable Write protect */ |
851 | gpmc_config |= 0x10; | |
89411352 | 852 | writel(gpmc_config, &gpmc_cfg->config); |
12201a13 | 853 | |
89411352 DB |
854 | nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; |
855 | nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; | |
5c3f7e0e RL |
856 | omap_nand_info[cs].control = NULL; |
857 | omap_nand_info[cs].cs = cs; | |
858 | nand->priv = &omap_nand_info[cs]; | |
d016dc42 | 859 | nand->cmd_ctrl = omap_nand_hwcontrol; |
860 | nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; | |
12201a13 | 861 | nand->chip_delay = 100; |
d016dc42 | 862 | nand->ecc.layout = &omap_ecclayout; |
863 | ||
b80a6603 | 864 | /* configure driver and controller based on NAND device bus-width */ |
865 | gpmc_config = readl(&gpmc_cfg->cs[cs].config1); | |
866 | #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT) | |
867 | nand->options |= NAND_BUSWIDTH_16; | |
868 | writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1); | |
869 | #else | |
870 | nand->options &= ~NAND_BUSWIDTH_16; | |
871 | writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1); | |
872 | #endif | |
d016dc42 | 873 | /* select ECC scheme */ |
3f719069 | 874 | #if defined(CONFIG_NAND_OMAP_ECCSCHEME) |
875 | err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, | |
d016dc42 | 876 | CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); |
3f719069 | 877 | #else |
878 | /* pagesize and oobsize are not required to configure sw ecc-scheme */ | |
d016dc42 | 879 | err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, |
880 | 0, 0); | |
c3754e9c | 881 | #endif |
d016dc42 | 882 | if (err) |
883 | return err; | |
12c2f1ee | 884 | |
ff62fb4c | 885 | #ifdef CONFIG_SPL_BUILD |
12c2f1ee SS |
886 | if (nand->options & NAND_BUSWIDTH_16) |
887 | nand->read_buf = nand_read_buf16; | |
888 | else | |
889 | nand->read_buf = nand_read_buf; | |
890 | nand->dev_ready = omap_spl_dev_ready; | |
891 | #endif | |
12201a13 DB |
892 | return 0; |
893 | } |