[people/ms/u-boot.git] / drivers / mtd / spi / sf_ops.c

/*
 * SPI flash operations
 *
 * Copyright (C) 2008 Atmel Corporation
 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <spi_flash.h>
#include <watchdog.h>

#include "sf_internal.h"

static void spi_flash_addr(u32 addr, u8 *cmd)
{
	/* cmd[0] is actual command */
	cmd[1] = addr >> 16;
	cmd[2] = addr >> 8;
	cmd[3] = addr >> 0;
}

int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
{
	u8 cmd;
	int ret;

	cmd = CMD_WRITE_STATUS;
	ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
	if (ret < 0) {
		debug("SF: fail to write status register\n");
		return ret;
	}

	return 0;
}

#ifdef CONFIG_SPI_FLASH_MACRONIX
int spi_flash_set_qeb_mxic(struct spi_flash *flash)
{
	u8 qeb_status;
	u8 cmd;
	int ret;

	cmd = CMD_READ_STATUS;
	ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
	if (ret < 0) {
		debug("SF: fail to read status register\n");
		return ret;
	}

	if (qeb_status & STATUS_QEB_MXIC) {
		debug("SF: Quad enable bit is already set\n");
	} else {
		ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
		if (ret < 0)
			return ret;
	}

	return ret;
}
#endif

#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
{
	u8 data[2];
	u8 cmd;
	int ret;

	cmd = CMD_READ_STATUS;
	ret = spi_flash_read_common(flash, &cmd, 1, &data[0], 1);
	if (ret < 0) {
		debug("SF: fail to read status register\n");
		return ret;
	}

	cmd = CMD_WRITE_STATUS;
	data[1] = cr;
	ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
	if (ret) {
		debug("SF: fail to write config register\n");
		return ret;
	}

	return 0;
}

int spi_flash_set_qeb_winspan(struct spi_flash *flash)
{
	u8 qeb_status;
	u8 cmd;
	int ret;

	cmd = CMD_READ_CONFIG;
	ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
	if (ret < 0) {
		debug("SF: fail to read config register\n");
		return ret;
	}

	if (qeb_status & STATUS_QEB_WINSPAN) {
		debug("SF: Quad enable bit is already set\n");
	} else {
		ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
		if (ret < 0)
			return ret;
	}

	return ret;
}
#endif

#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
	u8 cmd;
	int ret;

	if (flash->bank_curr == bank_sel) {
		debug("SF: not require to enable bank%d\n", bank_sel);
		return 0;
	}

	cmd = flash->bank_write_cmd;
	ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
	if (ret < 0) {
		debug("SF: fail to write bank register\n");
		return ret;
	}
	flash->bank_curr = bank_sel;

	return 0;
}

static int spi_flash_bank(struct spi_flash *flash, u32 offset)
{
	u8 bank_sel;
	int ret;

	bank_sel = offset / SPI_FLASH_16MB_BOUN;

	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
	if (ret) {
		debug("SF: fail to set bank%d\n", bank_sel);
		return ret;
	}

	return 0;
}
#endif

int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
	struct spi_slave *spi = flash->spi;
	unsigned long timebase;
	int ret;
	u8 status;
	u8 check_status = 0x0;
	u8 poll_bit = STATUS_WIP;
	u8 cmd = flash->poll_cmd;

	if (cmd == CMD_FLAG_STATUS) {
		poll_bit = STATUS_PEC;
		check_status = poll_bit;
	}

	ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
	if (ret) {
		debug("SF: fail to read %s status register\n",
		      cmd == CMD_READ_STATUS ? "read" : "flag");
		return ret;
	}

	timebase = get_timer(0);
	do {
		WATCHDOG_RESET();

		ret = spi_xfer(spi, 8, NULL, &status, 0);
		if (ret)
			return -1;

		if ((status & poll_bit) == check_status)
			break;

	} while (get_timer(timebase) < timeout);

	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);

	if ((status & poll_bit) == check_status)
		return 0;

	/* Timed out */
	debug("SF: time out!\n");
	return -1;
}

int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
		size_t cmd_len, const void *buf, size_t buf_len)
{
	struct spi_slave *spi = flash->spi;
	unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
	int ret;

	if (buf == NULL)
		timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;

	ret = spi_claim_bus(flash->spi);
	if (ret) {
		debug("SF: unable to claim SPI bus\n");
		return ret;
	}

	ret = spi_flash_cmd_write_enable(flash);
	if (ret < 0) {
		debug("SF: enabling write failed\n");
		return ret;
	}

	ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
	if (ret < 0) {
		debug("SF: write cmd failed\n");
		return ret;
	}

	ret = spi_flash_cmd_wait_ready(flash, timeout);
	if (ret < 0) {
		debug("SF: write %s timed out\n",
		      timeout == SPI_FLASH_PROG_TIMEOUT ?
			"program" : "page erase");
		return ret;
	}

	spi_release_bus(spi);

	return ret;
}

int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
	u32 erase_size;
	u8 cmd[SPI_FLASH_CMD_LEN];
	int ret = -1;

	erase_size = flash->erase_size;
	if (offset % erase_size || len % erase_size) {
		debug("SF: Erase offset/length not multiple of erase size\n");
		return -1;
	}

	cmd[0] = flash->erase_cmd;
	while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
		ret = spi_flash_bank(flash, offset);
		if (ret < 0)
			return ret;
#endif
		spi_flash_addr(offset, cmd);

		debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
		      cmd[2], cmd[3], offset);

		ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
		if (ret < 0) {
			debug("SF: erase failed\n");
			break;
		}

		offset += erase_size;
		len -= erase_size;
	}

	return ret;
}

int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
		size_t len, const void *buf)
{
	unsigned long byte_addr, page_size;
	size_t chunk_len, actual;
	u8 cmd[SPI_FLASH_CMD_LEN];
	int ret = -1;

	page_size = flash->page_size;

	cmd[0] = flash->write_cmd;
	for (actual = 0; actual < len; actual += chunk_len) {
#ifdef CONFIG_SPI_FLASH_BAR
		ret = spi_flash_bank(flash, offset);
		if (ret < 0)
			return ret;
#endif
		byte_addr = offset % page_size;
		chunk_len = min(len - actual, page_size - byte_addr);

		if (flash->spi->max_write_size)
			chunk_len = min(chunk_len, flash->spi->max_write_size);

		spi_flash_addr(offset, cmd);

		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);

		ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
					buf + actual, chunk_len);
		if (ret < 0) {
			debug("SF: write failed\n");
			break;
		}

		offset += chunk_len;
	}

	return ret;
}

int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
		size_t cmd_len, void *data, size_t data_len)
{
	struct spi_slave *spi = flash->spi;
	int ret;

	ret = spi_claim_bus(flash->spi);
	if (ret) {
		debug("SF: unable to claim SPI bus\n");
		return ret;
	}

	ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
	if (ret < 0) {
		debug("SF: read cmd failed\n");
		return ret;
	}

	spi_release_bus(spi);

	return ret;
}

int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
		size_t len, void *data)
{
	u8 *cmd, cmdsz, bank_sel = 0;
	u32 remain_len, read_len;
	int ret = -1;

	/* Handle memory-mapped SPI */
	if (flash->memory_map) {
		ret = spi_claim_bus(flash->spi);
		if (ret) {
			debug("SF: unable to claim SPI bus\n");
			return ret;
		}
		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
		memcpy(data, flash->memory_map + offset, len);
		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
		spi_release_bus(flash->spi);
		return 0;
	}

	cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
	cmd = malloc(cmdsz);
	memset(cmd, 0, cmdsz);

	cmd[0] = flash->read_cmd;
	while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
		bank_sel = offset / SPI_FLASH_16MB_BOUN;

		ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
		if (ret) {
			debug("SF: fail to set bank%d\n", bank_sel);
			return ret;
		}
#endif
		remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
		if (len < remain_len)
			read_len = len;
		else
			read_len = remain_len;

		spi_flash_addr(offset, cmd);

		ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
		if (ret < 0) {
			debug("SF: read failed\n");
			break;
		}

		offset += read_len;
		len -= read_len;
		data += read_len;
	}

	return ret;
}

#ifdef CONFIG_SPI_FLASH_SST
static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
{
	int ret;
	u8 cmd[4] = {
		CMD_SST_BP,
		offset >> 16,
		offset >> 8,
		offset,
	};

	debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
	      spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);

	ret = spi_flash_cmd_write_enable(flash);
	if (ret)
		return ret;

	ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
	if (ret)
		return ret;

	return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
}

int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
		const void *buf)
{
	size_t actual, cmd_len;
	int ret;
	u8 cmd[4];

	ret = spi_claim_bus(flash->spi);
	if (ret) {
		debug("SF: Unable to claim SPI bus\n");
		return ret;
	}

	/* If the data is not word aligned, write out leading single byte */
	actual = offset % 2;
	if (actual) {
		ret = sst_byte_write(flash, offset, buf);
		if (ret)
			goto done;
	}
	offset += actual;

	ret = spi_flash_cmd_write_enable(flash);
	if (ret)
		goto done;

	cmd_len = 4;
	cmd[0] = CMD_SST_AAI_WP;
	cmd[1] = offset >> 16;
	cmd[2] = offset >> 8;
	cmd[3] = offset;

	for (; actual < len - 1; actual += 2) {
		debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
		      spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
		      cmd[0], offset);

		ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
					buf + actual, 2);
		if (ret) {
			debug("SF: sst word program failed\n");
			break;
		}

		ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
		if (ret)
			break;

		cmd_len = 1;
		offset += 2;
	}

	if (!ret)
		ret = spi_flash_cmd_write_disable(flash);

	/* If there is a single trailing byte, write it out */
	if (!ret && actual != len)
		ret = sst_byte_write(flash, offset, buf + actual);

 done:
	debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
	      ret ? "failure" : "success", len, offset - actual);

	spi_release_bus(flash->spi);
	return ret;
}
#endif
Commit	Line	Data
4d5e29a6 JT	1	/*
	2	* SPI flash operations
	3	*
	4	* Copyright (C) 2008 Atmel Corporation
	5	* Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
	6	* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
	7	*
0c88a84a	8	* SPDX-License-Identifier: GPL-2.0+
4d5e29a6 JT	9	*/
	10
	11	#include <common.h>
ff063ed4	12	#include <malloc.h>
4d5e29a6 JT	13	#include <spi.h>
	14	#include <spi_flash.h>
	15	#include <watchdog.h>
	16
898e76c9	17	#include "sf_internal.h"
4d5e29a6 JT	18
	19	static void spi_flash_addr(u32 addr, u8 *cmd)
	20	{
	21	/* cmd[0] is actual command */
	22	cmd[1] = addr >> 16;
	23	cmd[2] = addr >> 8;
	24	cmd[3] = addr >> 0;
	25	}
	26
	27	int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
	28	{
	29	u8 cmd;
	30	int ret;
	31
	32	cmd = CMD_WRITE_STATUS;
	33	ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
	34	if (ret < 0) {
	35	debug("SF: fail to write status register\n");
	36	return ret;
	37	}
	38
	39	return 0;
	40	}
	41
06795122 JT	42	#ifdef CONFIG_SPI_FLASH_MACRONIX
	43	int spi_flash_set_qeb_mxic(struct spi_flash *flash)
	44	{
	45	u8 qeb_status;
	46	u8 cmd;
	47	int ret;
	48
	49	cmd = CMD_READ_STATUS;
	50	ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
	51	if (ret < 0) {
	52	debug("SF: fail to read status register\n");
	53	return ret;
	54	}
	55
	56	if (qeb_status & STATUS_QEB_MXIC) {
	57	debug("SF: Quad enable bit is already set\n");
	58	} else {
	59	ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
	60	if (ret < 0)
	61	return ret;
	62	}
	63
	64	return ret;
	65	}
	66	#endif
	67
d08a1baf	68	#if defined(CONFIG_SPI_FLASH_SPANSION) \|\| defined(CONFIG_SPI_FLASH_WINBOND)
6cba6fdf JT	69	static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
	70	{
	71	u8 data[2];
	72	u8 cmd;
	73	int ret;
	74
	75	cmd = CMD_READ_STATUS;
	76	ret = spi_flash_read_common(flash, &cmd, 1, &data[0], 1);
	77	if (ret < 0) {
	78	debug("SF: fail to read status register\n");
	79	return ret;
	80	}
	81
	82	cmd = CMD_WRITE_STATUS;
	83	data[1] = cr;
	84	ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
	85	if (ret) {
	86	debug("SF: fail to write config register\n");
	87	return ret;
	88	}
	89
	90	return 0;
	91	}
	92
d08a1baf JT	93	int spi_flash_set_qeb_winspan(struct spi_flash *flash)
	94	{
	95	u8 qeb_status;
	96	u8 cmd;
	97	int ret;
	98
	99	cmd = CMD_READ_CONFIG;
	100	ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
	101	if (ret < 0) {
	102	debug("SF: fail to read config register\n");
	103	return ret;
	104	}
	105
	106	if (qeb_status & STATUS_QEB_WINSPAN) {
	107	debug("SF: Quad enable bit is already set\n");
	108	} else {
	109	ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
	110	if (ret < 0)
	111	return ret;
	112	}
	113
	114	return ret;
	115	}
	116	#endif
	117
4d5e29a6	118	#ifdef CONFIG_SPI_FLASH_BAR
532f2f11	119	static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
4d5e29a6 JT	120	{
	121	u8 cmd;
	122	int ret;
	123
	124	if (flash->bank_curr == bank_sel) {
	125	debug("SF: not require to enable bank%d\n", bank_sel);
	126	return 0;
	127	}
	128
	129	cmd = flash->bank_write_cmd;
	130	ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
	131	if (ret < 0) {
	132	debug("SF: fail to write bank register\n");
	133	return ret;
	134	}
	135	flash->bank_curr = bank_sel;
	136
	137	return 0;
	138	}
6152dd15 JT	139
	140	static int spi_flash_bank(struct spi_flash *flash, u32 offset)
	141	{
	142	u8 bank_sel;
	143	int ret;
	144
	145	bank_sel = offset / SPI_FLASH_16MB_BOUN;
	146
	147	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
	148	if (ret) {
	149	debug("SF: fail to set bank%d\n", bank_sel);
	150	return ret;
	151	}
	152
	153	return 0;
	154	}
4d5e29a6 JT	155	#endif
	156
	157	int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
	158	{
	159	struct spi_slave *spi = flash->spi;
	160	unsigned long timebase;
	161	int ret;
	162	u8 status;
	163	u8 check_status = 0x0;
	164	u8 poll_bit = STATUS_WIP;
	165	u8 cmd = flash->poll_cmd;
	166
	167	if (cmd == CMD_FLAG_STATUS) {
	168	poll_bit = STATUS_PEC;
	169	check_status = poll_bit;
	170	}
	171
	172	ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
	173	if (ret) {
	174	debug("SF: fail to read %s status register\n",
	175	cmd == CMD_READ_STATUS ? "read" : "flag");
	176	return ret;
	177	}
	178
	179	timebase = get_timer(0);
	180	do {
	181	WATCHDOG_RESET();
	182
	183	ret = spi_xfer(spi, 8, NULL, &status, 0);
	184	if (ret)
	185	return -1;
	186
	187	if ((status & poll_bit) == check_status)
	188	break;
	189
	190	} while (get_timer(timebase) < timeout);
	191
	192	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
	193
	194	if ((status & poll_bit) == check_status)
	195	return 0;
	196
	197	/* Timed out */
	198	debug("SF: time out!\n");
	199	return -1;
	200	}
	201
	202	int spi_flash_write_common(struct spi_flash flash, const u8 cmd,
	203	size_t cmd_len, const void *buf, size_t buf_len)
	204	{
	205	struct spi_slave *spi = flash->spi;
	206	unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
	207	int ret;
	208
	209	if (buf == NULL)
	210	timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
	211
	212	ret = spi_claim_bus(flash->spi);
	213	if (ret) {
	214	debug("SF: unable to claim SPI bus\n");
	215	return ret;
	216	}
	217
	218	ret = spi_flash_cmd_write_enable(flash);
219	if (ret < 0) {
220	debug("SF: enabling write failed\n");
221	return ret;
222	}
223
224	ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
225	if (ret < 0) {
226	debug("SF: write cmd failed\n");
227	return ret;
228	}
229
230	ret = spi_flash_cmd_wait_ready(flash, timeout);
231	if (ret < 0) {
232	debug("SF: write %s timed out\n",
233	timeout == SPI_FLASH_PROG_TIMEOUT ?
234	"program" : "page erase");
235	return ret;
236	}
237
238	spi_release_bus(spi);
239
240	return ret;
241	}
242
a5e8199a	243	int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
4d5e29a6 JT	244	{
4d5e29a6 JT	245	u32 erase_size;
ff063ed4	246	u8 cmd[SPI_FLASH_CMD_LEN];
4d5e29a6 JT	247	int ret = -1;
4d5e29a6 JT	248
f4f51a8f	249	erase_size = flash->erase_size;
4d5e29a6 JT	250	if (offset % erase_size \|\| len % erase_size) {
	251	debug("SF: Erase offset/length not multiple of erase size\n");
	252	return -1;
	253	}
	254
f4f51a8f	255	cmd[0] = flash->erase_cmd;
4d5e29a6 JT	256	while (len) {
4d5e29a6 JT	257	#ifdef CONFIG_SPI_FLASH_BAR
6152dd15 JT	258	ret = spi_flash_bank(flash, offset);
6152dd15 JT	259	if (ret < 0)
4d5e29a6	260	return ret;
4d5e29a6 JT	261	#endif
	262	spi_flash_addr(offset, cmd);
	263
	264	debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
	265	cmd[2], cmd[3], offset);
	266
	267	ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
	268	if (ret < 0) {
	269	debug("SF: erase failed\n");
	270	break;
	271	}
	272
	273	offset += erase_size;
	274	len -= erase_size;
	275	}
	276
	277	return ret;
	278	}
	279
a5e8199a	280	int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
4d5e29a6 JT	281	size_t len, const void *buf)
	282	{
	283	unsigned long byte_addr, page_size;
	284	size_t chunk_len, actual;
ff063ed4	285	u8 cmd[SPI_FLASH_CMD_LEN];
4d5e29a6 JT	286	int ret = -1;
	287
	288	page_size = flash->page_size;
	289
3163aaa6	290	cmd[0] = flash->write_cmd;
4d5e29a6 JT	291	for (actual = 0; actual < len; actual += chunk_len) {
4d5e29a6 JT	292	#ifdef CONFIG_SPI_FLASH_BAR
6152dd15 JT	293	ret = spi_flash_bank(flash, offset);
6152dd15 JT	294	if (ret < 0)
4d5e29a6	295	return ret;
4d5e29a6 JT	296	#endif
	297	byte_addr = offset % page_size;
	298	chunk_len = min(len - actual, page_size - byte_addr);
	299
	300	if (flash->spi->max_write_size)
	301	chunk_len = min(chunk_len, flash->spi->max_write_size);
	302
	303	spi_flash_addr(offset, cmd);
	304
	305	debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
	306	buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
	307
	308	ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
	309	buf + actual, chunk_len);
	310	if (ret < 0) {
	311	debug("SF: write failed\n");
	312	break;
	313	}
	314
	315	offset += chunk_len;
	316	}
	317
	318	return ret;
	319	}
	320
	321	int spi_flash_read_common(struct spi_flash flash, const u8 cmd,
	322	size_t cmd_len, void *data, size_t data_len)
	323	{
	324	struct spi_slave *spi = flash->spi;
	325	int ret;
	326
	327	ret = spi_claim_bus(flash->spi);
	328	if (ret) {
	329	debug("SF: unable to claim SPI bus\n");
	330	return ret;
	331	}
	332
	333	ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
	334	if (ret < 0) {
	335	debug("SF: read cmd failed\n");
	336	return ret;
	337	}
	338
	339	spi_release_bus(spi);
	340
	341	return ret;
	342	}
	343
a5e8199a	344	int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
4d5e29a6 JT	345	size_t len, void *data)
4d5e29a6 JT	346	{
ff063ed4	347	u8 *cmd, cmdsz, bank_sel = 0;
4d5e29a6 JT	348	u32 remain_len, read_len;
	349	int ret = -1;
	350
	351	/* Handle memory-mapped SPI */
	352	if (flash->memory_map) {
ac5cce38 PS	353	ret = spi_claim_bus(flash->spi);
	354	if (ret) {
	355	debug("SF: unable to claim SPI bus\n");
	356	return ret;
	357	}
004f15b6	358	spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
4d5e29a6	359	memcpy(data, flash->memory_map + offset, len);
004f15b6	360	spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
ac5cce38	361	spi_release_bus(flash->spi);
4d5e29a6 JT	362	return 0;
	363	}
	364
ff063ed4 JT	365	cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
	366	cmd = malloc(cmdsz);
	367	memset(cmd, 0, cmdsz);
4d5e29a6	368
ff063ed4	369	cmd[0] = flash->read_cmd;
4d5e29a6 JT	370	while (len) {
	371	#ifdef CONFIG_SPI_FLASH_BAR
	372	bank_sel = offset / SPI_FLASH_16MB_BOUN;
	373
	374	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
	375	if (ret) {
	376	debug("SF: fail to set bank%d\n", bank_sel);
	377	return ret;
	378	}
	379	#endif
469146c0	380	remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
4d5e29a6 JT	381	if (len < remain_len)
	382	read_len = len;
	383	else
	384	read_len = remain_len;
	385
	386	spi_flash_addr(offset, cmd);
	387
ff063ed4	388	ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
4d5e29a6 JT	389	if (ret < 0) {
	390	debug("SF: read failed\n");
	391	break;
	392	}
	393
	394	offset += read_len;
	395	len -= read_len;
	396	data += read_len;
	397	}
	398
	399	return ret;
	400	}
10ca45d0 JT	401
	402	#ifdef CONFIG_SPI_FLASH_SST
	403	static int sst_byte_write(struct spi_flash flash, u32 offset, const void buf)
	404	{
	405	int ret;
	406	u8 cmd[4] = {
	407	CMD_SST_BP,
	408	offset >> 16,
	409	offset >> 8,
	410	offset,
	411	};
	412
	413	debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
	414	spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
	415
	416	ret = spi_flash_cmd_write_enable(flash);
	417	if (ret)
	418	return ret;
	419
	420	ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
	421	if (ret)
	422	return ret;
	423
	424	return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
	425	}
	426
	427	int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
	428	const void *buf)
	429	{
	430	size_t actual, cmd_len;
	431	int ret;
	432	u8 cmd[4];
	433
	434	ret = spi_claim_bus(flash->spi);
	435	if (ret) {
	436	debug("SF: Unable to claim SPI bus\n");
	437	return ret;
	438	}
	439
	440	/* If the data is not word aligned, write out leading single byte */
	441	actual = offset % 2;
	442	if (actual) {
	443	ret = sst_byte_write(flash, offset, buf);
	444	if (ret)
	445	goto done;
	446	}
	447	offset += actual;
	448
	449	ret = spi_flash_cmd_write_enable(flash);
	450	if (ret)
	451	goto done;
	452
	453	cmd_len = 4;
	454	cmd[0] = CMD_SST_AAI_WP;
	455	cmd[1] = offset >> 16;
	456	cmd[2] = offset >> 8;
	457	cmd[3] = offset;
	458
	459	for (; actual < len - 1; actual += 2) {
	460	debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
	461	spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
	462	cmd[0], offset);
	463
	464	ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
465	buf + actual, 2);
466	if (ret) {
467	debug("SF: sst word program failed\n");
468	break;
469	}
470
471	ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
472	if (ret)
473	break;
474
475	cmd_len = 1;
476	offset += 2;
477	}
478
479	if (!ret)
480	ret = spi_flash_cmd_write_disable(flash);
481
482	/* If there is a single trailing byte, write it out */
483	if (!ret && actual != len)
484	ret = sst_byte_write(flash, offset, buf + actual);
485
486	done:
487	debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
488	ret ? "failure" : "success", len, offset - actual);
489
490	spi_release_bus(flash->spi);
491	return ret;
492	}
493	#endif