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mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80B
[thirdparty/u-boot.git] / drivers / mtd / spi / spi-nor-ids.c
CommitLineData
778572d7
V		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 *
4 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
5 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com>
a94a4071 6 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
778572d7
V		 7 */
8
9#include <common.h>
10#include <spi.h>
11#include <spi_flash.h>
12
13#include "sf_internal.h"
14
15/* Exclude chip names for SPL to save space */
16#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
17#define INFO_NAME(_name) .name = _name,
18#else
19#define INFO_NAME(_name)
20#endif
21
22/* Used when the "_ext_id" is two bytes at most */
23#define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
24 INFO_NAME(_name) \
25 .id = { \
26 ((_jedec_id) >> 16) & 0xff, \
27 ((_jedec_id) >> 8) & 0xff, \
28 (_jedec_id) & 0xff, \
29 ((_ext_id) >> 8) & 0xff, \
30 (_ext_id) & 0xff, \
31 }, \
32 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
33 .sector_size = (_sector_size), \
34 .n_sectors = (_n_sectors), \
35 .page_size = 256, \
36 .flags = (_flags),
37
38#define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
39 INFO_NAME(_name) \
40 .id = { \
41 ((_jedec_id) >> 16) & 0xff, \
42 ((_jedec_id) >> 8) & 0xff, \
43 (_jedec_id) & 0xff, \
44 ((_ext_id) >> 16) & 0xff, \
45 ((_ext_id) >> 8) & 0xff, \
46 (_ext_id) & 0xff, \
47 }, \
48 .id_len = 6, \
49 .sector_size = (_sector_size), \
50 .n_sectors = (_n_sectors), \
51 .page_size = 256, \
52 .flags = (_flags),
53
54/* NOTE: double check command sets and memory organization when you add
55 * more nor chips. This current list focusses on newer chips, which
56 * have been converging on command sets which including JEDEC ID.
57 *
58 * All newly added entries should describe *hardware* and should use SECT_4K
59 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
60 * scenarios excluding small sectors there is config option that can be
2a2174d3 61 * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS.
778572d7
V		 62 * For historical (and compatibility) reasons (before we got above config) some
63 * old entries may be missing 4K flag.
64 */
65const struct flash_info spi_nor_ids[] = {
66#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
67 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
68 { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
69 { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
70
71 { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
72 { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
73 { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
74 { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
75 { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
76 { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
77 { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
395ec741 78 { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) },
0cf207ec 79 { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
778572d7
V		 80#endif
81#ifdef CONFIG_SPI_FLASH_EON /* EON */
82 /* EON -- en25xxx */
d4091971 83 { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) },
778572d7
V		 84 { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
85 { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
baef13ec 86 { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
778572d7
V		 87 { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
88 { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
89#endif
90#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
91 /* GigaDevice */
92 {
93 INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32,
94 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
95 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
96 },
97 {
98 INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64,
99 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
100 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
101 },
102 {
103 INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64,
104 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
105 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
106 },
107 {
108 INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128,
109 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
110 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
111 },
eb69d797
ANY		 112 {
113 INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128,
114 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
115 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
116 },
864d6643
PR		 117 {
118 INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
119 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
120 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
121 },
e72023c4
VL		 122 /* adding these 3V QSPI flash parts */
123 {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K |
124 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) },
125 {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K |
126 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
127 {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K |
128 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
129 {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K |
130 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
131 {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K |
132 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
133 {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K |
134 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
135 {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K |
136 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
137 {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K |
138 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
139 {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K |
140 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
141 {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K |
142 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
143 {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K |
144 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
145 /* adding these 3V OSPI flash parts */
146 {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K |
147 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
148 {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K |
149 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
150 {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
151 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
30b9a28a
NA		 152 {
153 INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
228173d8 154 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
30b9a28a
NA		 155 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
156 },
e4f97f12
YW		 157 {
158 INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512,
159 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
160 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
161 },
e72023c4
VL		 162 /* adding these 1.8V QSPI flash parts */
163 {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K |
164 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
165 {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K |
166 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
167 {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K |
168 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
169 {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K |
170 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
171 {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K |
172 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
173 {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K |
174 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
175 {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K |
176 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
177 {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K |
178 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
179 {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K |
180 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
181 {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K |
182 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
183 {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K |
184 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
185 {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K |
186 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
187 {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K |
188 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
189 {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K |
190 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
191 {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K |
192 SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
baef13ec
ARS		 193 {
194 INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
195 SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
196 },
e72023c4
VL		 197 /* adding these 1.8V OSPI flash parts */
198 {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K |
199 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
200 {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K |
201 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
202 {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K |
203 SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
77f3b5e4
THC		 204 {
205 INFO("gd55lb02ge", 0xc8671c, 0, 64 * 1024, 4096,
206 SECT_4K | SPI_NOR_QUAD_READ |
207 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
208 },
778572d7
V		 209#endif
210#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
211 /* ISSI */
212 { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
213 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
baef13ec
ARS		 214 { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
215 { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
778572d7
V		 216 { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
217 { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
218 { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
219 SECT_4K | SPI_NOR_DUAL_READ) },
220 { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
221 SECT_4K | SPI_NOR_DUAL_READ) },
b7a772a3
KC		 222 { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
223 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
baef13ec
ARS		 224 { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
225 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
226 { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
227 { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
778572d7
V		 228 { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
229 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
230 { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
231 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
232 { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
233 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
97009d54 234 { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
a976238d
JT		 235 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
236 SPI_NOR_4B_OPCODES) },
b7a772a3
KC		 237 { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
238 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
baef13ec
ARS		 239 { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
240 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
241 { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
242 SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
18e61f23
TB		 243 { INFO("is25lx512", 0x9d5a1a, 0, 64 * 1024, 1024,
244 SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) },
778572d7
V		 245#endif
246#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
247 /* Macronix */
248 { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) },
249 { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) },
250 { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) },
251 { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) },
252 { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) },
253 { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
254 { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
255 { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
808e1936 256 { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
778572d7 257 { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
d1b6b942 258 { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
2781c718 259 { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
f0084f1d 260 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K) },
f9b96413
TFC		 261 { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
262 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
778572d7
V		 263 { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
264 { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
265 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
2a797750
FS		 266 { INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
267 { INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
778572d7
V		 268 { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
269 { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
270 { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
baef13ec
ARS		 271 { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
272 { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
3d2f12c4 273 { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
778572d7 274 { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
baef13ec 275 { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
778572d7 276 { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
8af1caa2 277 { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
4290ed78
J		 278 { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
279 { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
280 { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
281 { INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
282 { INFO("mx25lm25645g", 0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
283 { INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
284 { INFO("mx66um1g45g", 0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
285 { INFO("mx66uw1g45g", 0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
286 { INFO("mx25uw51245g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
287 { INFO("mx25uw51345g", 0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
288 { INFO("mx25um25645g", 0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
289 { INFO("mx25uw25645g", 0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
290 { INFO("mx25um25345g", 0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
291 { INFO("mx25uw25345g", 0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
292 { INFO("mx25uw12845g", 0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
293 { INFO("mx25uw12345g", 0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
294 { INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
295 { INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
778572d7
V		 296#endif
297
791e2bf9
JK		 298#ifdef CONFIG_SPI_FLASH_SILICONKAISER
299 { INFO("sk25lp128", 0x257018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
300#endif
301
778572d7
V		 302#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
303 /* Micron */
304 { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
305 { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
306 { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
307 { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
308 { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
309 { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
310 { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
73d74b58
VR		 311 { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
312 { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
313 { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
314 { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
a08f7de3 315 { INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
8385520f 316 { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
85886161 317 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
73d74b58 318 USE_FSR) },
d66e07cd 319 { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
8651593a 320 { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
d66e07cd 321 { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
778572d7
V		 322 { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
323 { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
936a6456 324 { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
bf41cb3d 325 { INFO6("mt25qu01g", 0x20bb21, 0x104400, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
778572d7 326 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
e8966138 327 { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
f6adec1a 328#ifdef CONFIG_SPI_FLASH_MT35XU
baef13ec 329 { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
f6adec1a
PY		 330 { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
331#endif /* CONFIG_SPI_FLASH_MT35XU */
baef13ec 332 { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
cae3c7cc 333 { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
778572d7
V		 334#endif
335#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
336 /* Spansion/Cypress -- single (large) sector size only, at least
337 * for the chips listed here (without boot sectors).
338 */
339 { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
340 { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
6f3b1f4a 341 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
778572d7 342 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
685465fb
KS		 343 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
344 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
778572d7
V		 345 { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
346 { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
347 { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
baef13ec 348 { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
778572d7
V		 349 { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) },
350 { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) },
351 { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
352 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
353 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
354 { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) },
355 { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) },
356 { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) },
357 { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) },
358 { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
359 { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) },
360 { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
a2dc8b18 361 { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
778572d7 362 { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
e66c6f10 363 { INFO("s25fl256l", 0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
c95a914a
TK		 364 { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256,
365 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
366 USE_CLSR) },
367 { INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512,
368 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
369 USE_CLSR) },
370 { INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024,
371 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
372 { INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256,
373 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
374 USE_CLSR) },
375 { INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512,
376 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
377 USE_CLSR) },
378 { INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024,
379 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
87a6d865
TK		 380 { INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256,
381 SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
f422c4be 382#ifdef CONFIG_SPI_FLASH_S28HX_T
de9e8378
TK		 383 { INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
384 { INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
ea9a22f7 385 { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
de9e8378 386 { INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
16dd1095 387 { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ) },
ea9a22f7 388#endif
778572d7
V		 389#endif
390#ifdef CONFIG_SPI_FLASH_SST /* SST */
391 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
392 { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
393 { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
394 { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
395 { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
396 { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
397 { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
398 { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
399 { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
400 { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) },
401 { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) },
402 { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
403 { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
718fd834 404 { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
baef13ec 405 { INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) },
718fd834
EP		 406 { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
407 { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
408 { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
778572d7
V		 409#endif
410#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
eae488b7 411 /* STMicroelectronics -- newer production may have feature updates */
778572d7
V		 412 { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) },
413 { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) },
414 { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) },
415 { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) },
416 { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) },
417 { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) },
418 { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) },
419 { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) },
420 { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) },
421 { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
422 { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) },
423#endif
424#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
425 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
426 { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) },
427 { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) },
428 { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) },
429 { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) },
430 { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) },
431 { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) },
432 {
433 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
434 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
435 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
436 },
437 { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) },
438 { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },
439 { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
440 { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },
441 { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
baef13ec
ARS		 442 {
443 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
444 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
445 },
778572d7
V		 446 {
447 INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
448 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
449 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
450 },
baef13ec
ARS		 451 {
452 INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32,
453 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
454 },
778572d7
V		 455 {
456 INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64,
457 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
458 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
459 },
38298567
MW		 460 {
461 INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64,
462 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
463 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
464 },
4a31e145
VYA		 465 {
466 INFO("w25q256jwm", 0xef8019, 0, 64 * 1024, 512,
467 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
468 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
469 },
778572d7
V		 470 { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },
471 {
472 INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
473 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
474 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
475 },
476 {
477 INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128,
478 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
479 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
480 },
481 {
482 INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256,
483 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
484 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
485 },
486 {
487 INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256,
488 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
489 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
490 },
1aa60f0c
MV		 491 {
492 INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
493 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
494 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
495 },
778572d7
V		 496 {
497 INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512,
498 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
499 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
500 },
501 {
502 INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512,
503 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
504 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
505 },
baef13ec
ARS		 506 {
507 INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512,
508 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
509 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
510 },
47ed8b22
JHY		 511 {
512 INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024,
513 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
514 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
515 },
516 {
517 INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024,
518 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
519 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
520 },
c184aca7
CTK		 521 {
522 INFO("w25q512jvq", 0xef4020, 0, 64 * 1024, 1024,
523 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
524 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
525 },
d7b1d825
RN		 526 {
527 INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
528 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
529 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
530 },
b2906f5b
JL		 531 {
532 INFO("w25q01jvfim", 0xef7021, 0, 64 * 1024, 2048,
533 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
534 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
535 },
536 {
537 INFO("w25q02jv", 0xef7022, 0, 64 * 1024, 4096,
538 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
539 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
540 },
778572d7
V		 541 { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
542 { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
543 { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
baef13ec 544 { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
778572d7 545 { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
de76ae36
SB		 546 { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256,
547 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
548 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
549 },
778572d7 550 { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
9dddead7 551 { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1910aca0 552 { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
baef13ec 553 { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
778572d7
V		 554#endif
555#ifdef CONFIG_SPI_FLASH_XMC
556 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
557 { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
9102cce7 558 { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
778572d7 559 { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
7b4544f1 560 { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
f07ca790
S		 561 { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
562 { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
563 { INFO("XM25QH512C", 0x204020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
564 { INFO("XM25QU512C", 0x204120, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
674a9483
CM		 565#endif
566#ifdef CONFIG_SPI_FLASH_XTX
3a4da23c 567 /* XTX Technology Limited */
41b5c79e
BS		 568 /* adding these 3V QSPI flash parts */
569 { INFO("xt25f08", 0x0b4014, 0, 64 * 1024, 16,
570 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
571 { INFO("xt25f16", 0x0b4015, 0, 64 * 1024, 32,
572 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
573 { INFO("xt25f32", 0x0b4016, 0, 64 * 1024, 64,
574 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
575 { INFO("xt25f64", 0x0b4017, 0, 64 * 1024, 128,
576 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
577 { INFO("xt25f128", 0x0b4018, 0, 64 * 1024, 256,
578 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
579 { INFO("xt25f256", 0x0b4019, 0, 64 * 1024, 512,
580 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
581 /* adding these 1.8V QSPI flash parts */
582 { INFO("xt25q08", 0x0b6014, 0, 64 * 1024, 16,
583 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
584 { INFO("xt25q16", 0x0b6015, 0, 64 * 1024, 32,
585 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
586 { INFO("xt25q32", 0x0b6016, 0, 64 * 1024, 64,
587 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
588 { INFO("xt25q64", 0x0b6017, 0, 64 * 1024, 128,
589 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
590 { INFO("xt25q128", 0x0b6018, 0, 64 * 1024, 256,
591 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
592 { INFO("xt25q256", 0x0b6019, 0, 64 * 1024, 512,
593 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
594 { INFO("xt25q512", 0x0b601A, 0, 64 * 1024, 1024,
595 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
596 { INFO("xt25q01g", 0x0b601B, 0, 64 * 1024, 2048,
597 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
fd9851e0
BS		 598 { INFO("xt55q02g", 0x0b601C, 0, 64 * 1024, 4096,
599 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
41b5c79e
BS		 600 /* adding these wide voltage QSPI flash parts */
601 { INFO("xt25w512", 0x0b651A, 0, 64 * 1024, 1024,
602 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
603 { INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048,
604 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
9ac57fb3
AP		 605#endif
606#ifdef CONFIG_SPI_FLASH_ZBIT
607 /* Zbit Semiconductor Inc. */
608 { INFO("zb25vq128", 0x5e4018, 0, 64 * 1024, 256,
609 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
778572d7
V		 610#endif
611 { },
612};
"Das U-Boot" Source Tree