[people/ms/u-boot.git] / drivers / mtd / stm32_flash.h

struct stm32_flash_regs {
	u32 acr;
	u32 key;
	u32 optkeyr;
	u32 sr;
	u32 cr;
	u32 optcr;
	u32 optcr1;
};

#define STM32_FLASH_KEY1	0x45670123
#define STM32_FLASH_KEY2	0xCDEF89AB

#define STM32_FLASH_SR_BSY		(1 << 16)

#define STM32_FLASH_CR_PG		(1 << 0)
#define STM32_FLASH_CR_SER		(1 << 1)
#define STM32_FLASH_CR_STRT		(1 << 16)
#define STM32_FLASH_CR_LOCK		(1 << 31)
#define STM32_FLASH_CR_SNB_OFFSET	3
#define STM32_FLASH_CR_SNB_MASK		(15 << STM32_FLASH_CR_SNB_OFFSET)

/* Flash ACR: Access control register */
#define FLASH_ACR_WS(n)		n
#define FLASH_ACR_PRFTEN	(1 << 8)
#define FLASH_ACR_ICEN		(1 << 9)
#define FLASH_ACR_DCEN		(1 << 10)
Commit	Line	Data
9ecb0c41 VM	1	struct stm32_flash_regs {
	2	u32 acr;
	3	u32 key;
	4	u32 optkeyr;
	5	u32 sr;
	6	u32 cr;
	7	u32 optcr;
	8	u32 optcr1;
	9	};
	10
	11	#define STM32_FLASH_KEY1 0x45670123
	12	#define STM32_FLASH_KEY2 0xCDEF89AB
	13
	14	#define STM32_FLASH_SR_BSY (1 << 16)
	15
	16	#define STM32_FLASH_CR_PG (1 << 0)
	17	#define STM32_FLASH_CR_SER (1 << 1)
	18	#define STM32_FLASH_CR_STRT (1 << 16)
	19	#define STM32_FLASH_CR_LOCK (1 << 31)
	20	#define STM32_FLASH_CR_SNB_OFFSET 3
	21	#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET)
	22
	23	/* Flash ACR: Access control register */
	24	#define FLASH_ACR_WS(n) n
	25	#define FLASH_ACR_PRFTEN (1 << 8)
	26	#define FLASH_ACR_ICEN (1 << 9)
	27	#define FLASH_ACR_DCEN (1 << 10)