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Commit | Line | Data |
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e40095f6 MV |
1 | /* |
2 | * Atheros AR71xx / AR9xxx GMAC driver | |
3 | * | |
4 | * Copyright (C) 2016 Marek Vasut <marex@denx.de> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <dm.h> | |
11 | #include <errno.h> | |
12 | #include <miiphy.h> | |
13 | #include <malloc.h> | |
14 | #include <linux/compiler.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/mii.h> | |
17 | #include <wait_bit.h> | |
18 | #include <asm/io.h> | |
19 | ||
20 | #include <mach/ath79.h> | |
21 | ||
22 | DECLARE_GLOBAL_DATA_PTR; | |
23 | ||
24 | enum ag7xxx_model { | |
25 | AG7XXX_MODEL_AG933X, | |
26 | AG7XXX_MODEL_AG934X, | |
27 | }; | |
28 | ||
9240a2f5 | 29 | /* MAC Configuration 1 */ |
e40095f6 MV |
30 | #define AG7XXX_ETH_CFG1 0x00 |
31 | #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31) | |
32 | #define AG7XXX_ETH_CFG1_RX_RST BIT(19) | |
33 | #define AG7XXX_ETH_CFG1_TX_RST BIT(18) | |
34 | #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8) | |
35 | #define AG7XXX_ETH_CFG1_RX_EN BIT(2) | |
36 | #define AG7XXX_ETH_CFG1_TX_EN BIT(0) | |
37 | ||
9240a2f5 | 38 | /* MAC Configuration 2 */ |
e40095f6 MV |
39 | #define AG7XXX_ETH_CFG2 0x04 |
40 | #define AG7XXX_ETH_CFG2_IF_1000 BIT(9) | |
41 | #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8) | |
42 | #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8) | |
43 | #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5) | |
44 | #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4) | |
45 | #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2) | |
46 | #define AG7XXX_ETH_CFG2_FDX BIT(0) | |
47 | ||
9240a2f5 | 48 | /* MII Configuration */ |
e40095f6 MV |
49 | #define AG7XXX_ETH_MII_MGMT_CFG 0x20 |
50 | #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31) | |
51 | ||
9240a2f5 | 52 | /* MII Command */ |
e40095f6 MV |
53 | #define AG7XXX_ETH_MII_MGMT_CMD 0x24 |
54 | #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1 | |
55 | ||
9240a2f5 | 56 | /* MII Address */ |
e40095f6 MV |
57 | #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28 |
58 | #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8 | |
59 | ||
9240a2f5 | 60 | /* MII Control */ |
e40095f6 MV |
61 | #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c |
62 | ||
9240a2f5 | 63 | /* MII Status */ |
e40095f6 MV |
64 | #define AG7XXX_ETH_MII_MGMT_STATUS 0x30 |
65 | ||
9240a2f5 | 66 | /* MII Indicators */ |
e40095f6 MV |
67 | #define AG7XXX_ETH_MII_MGMT_IND 0x34 |
68 | #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2) | |
69 | #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0) | |
70 | ||
9240a2f5 | 71 | /* STA Address 1 & 2 */ |
e40095f6 MV |
72 | #define AG7XXX_ETH_ADDR1 0x40 |
73 | #define AG7XXX_ETH_ADDR2 0x44 | |
74 | ||
9240a2f5 | 75 | /* ETH Configuration 0 - 5 */ |
e40095f6 MV |
76 | #define AG7XXX_ETH_FIFO_CFG_0 0x48 |
77 | #define AG7XXX_ETH_FIFO_CFG_1 0x4c | |
78 | #define AG7XXX_ETH_FIFO_CFG_2 0x50 | |
79 | #define AG7XXX_ETH_FIFO_CFG_3 0x54 | |
80 | #define AG7XXX_ETH_FIFO_CFG_4 0x58 | |
81 | #define AG7XXX_ETH_FIFO_CFG_5 0x5c | |
82 | ||
9240a2f5 | 83 | /* DMA Transfer Control for Queue 0 */ |
e40095f6 MV |
84 | #define AG7XXX_ETH_DMA_TX_CTRL 0x180 |
85 | #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0) | |
86 | ||
9240a2f5 | 87 | /* Descriptor Address for Queue 0 Tx */ |
e40095f6 MV |
88 | #define AG7XXX_ETH_DMA_TX_DESC 0x184 |
89 | ||
9240a2f5 | 90 | /* DMA Tx Status */ |
e40095f6 MV |
91 | #define AG7XXX_ETH_DMA_TX_STATUS 0x188 |
92 | ||
9240a2f5 | 93 | /* Rx Control */ |
e40095f6 MV |
94 | #define AG7XXX_ETH_DMA_RX_CTRL 0x18c |
95 | #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0) | |
96 | ||
9240a2f5 | 97 | /* Pointer to Rx Descriptor */ |
e40095f6 MV |
98 | #define AG7XXX_ETH_DMA_RX_DESC 0x190 |
99 | ||
9240a2f5 | 100 | /* Rx Status */ |
e40095f6 MV |
101 | #define AG7XXX_ETH_DMA_RX_STATUS 0x194 |
102 | ||
103 | /* Custom register at 0x18070000 */ | |
104 | #define AG7XXX_GMAC_ETH_CFG 0x00 | |
105 | #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) | |
106 | #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7) | |
107 | #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6) | |
108 | #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5) | |
109 | #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4) | |
110 | #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3) | |
111 | #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2) | |
112 | #define AG7XXX_ETH_CFG_MII_GE0 BIT(1) | |
113 | #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0) | |
114 | ||
115 | #define CONFIG_TX_DESCR_NUM 8 | |
116 | #define CONFIG_RX_DESCR_NUM 8 | |
117 | #define CONFIG_ETH_BUFSIZE 2048 | |
118 | #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) | |
119 | #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) | |
120 | ||
121 | /* DMA descriptor. */ | |
122 | struct ag7xxx_dma_desc { | |
123 | u32 data_addr; | |
124 | #define AG7XXX_DMADESC_IS_EMPTY BIT(31) | |
125 | #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16 | |
126 | #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0 | |
127 | #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff | |
128 | u32 config; | |
129 | u32 next_desc; | |
130 | u32 _pad[5]; | |
131 | }; | |
132 | ||
133 | struct ar7xxx_eth_priv { | |
134 | struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; | |
135 | struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; | |
136 | char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); | |
137 | char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); | |
138 | ||
139 | void __iomem *regs; | |
140 | void __iomem *phyregs; | |
141 | ||
142 | struct eth_device *dev; | |
143 | struct phy_device *phydev; | |
144 | struct mii_dev *bus; | |
145 | ||
146 | u32 interface; | |
147 | u32 tx_currdescnum; | |
148 | u32 rx_currdescnum; | |
149 | enum ag7xxx_model model; | |
150 | }; | |
151 | ||
152 | /* | |
153 | * Switch and MDIO access | |
154 | */ | |
155 | static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val) | |
156 | { | |
157 | struct ar7xxx_eth_priv *priv = bus->priv; | |
158 | void __iomem *regs = priv->phyregs; | |
159 | int ret; | |
160 | ||
161 | writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD); | |
162 | writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg, | |
163 | regs + AG7XXX_ETH_MII_MGMT_ADDRESS); | |
164 | writel(AG7XXX_ETH_MII_MGMT_CMD_READ, | |
165 | regs + AG7XXX_ETH_MII_MGMT_CMD); | |
166 | ||
167 | ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND, | |
168 | AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0); | |
169 | if (ret) | |
170 | return ret; | |
171 | ||
172 | *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff; | |
173 | writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
178 | static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val) | |
179 | { | |
180 | struct ar7xxx_eth_priv *priv = bus->priv; | |
181 | void __iomem *regs = priv->phyregs; | |
182 | int ret; | |
183 | ||
184 | writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg, | |
185 | regs + AG7XXX_ETH_MII_MGMT_ADDRESS); | |
186 | writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL); | |
187 | ||
188 | ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND, | |
189 | AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0); | |
190 | ||
191 | return ret; | |
192 | } | |
193 | ||
194 | static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) | |
195 | { | |
196 | struct ar7xxx_eth_priv *priv = bus->priv; | |
197 | u32 phy_addr; | |
198 | u32 reg_addr; | |
199 | u32 phy_temp; | |
200 | u32 reg_temp; | |
201 | u16 rv = 0; | |
202 | int ret; | |
203 | ||
204 | if (priv->model == AG7XXX_MODEL_AG933X) { | |
205 | phy_addr = 0x1f; | |
206 | reg_addr = 0x10; | |
207 | } else if (priv->model == AG7XXX_MODEL_AG934X) { | |
208 | phy_addr = 0x18; | |
209 | reg_addr = 0x00; | |
210 | } else | |
211 | return -EINVAL; | |
212 | ||
213 | ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); | |
214 | if (ret) | |
215 | return ret; | |
216 | ||
217 | phy_temp = ((reg >> 6) & 0x7) | 0x10; | |
218 | reg_temp = (reg >> 1) & 0x1e; | |
219 | *val = 0; | |
220 | ||
221 | ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv); | |
222 | if (ret < 0) | |
223 | return ret; | |
224 | *val |= rv; | |
225 | ||
226 | ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv); | |
227 | if (ret < 0) | |
228 | return ret; | |
229 | *val |= (rv << 16); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val) | |
235 | { | |
236 | struct ar7xxx_eth_priv *priv = bus->priv; | |
237 | u32 phy_addr; | |
238 | u32 reg_addr; | |
239 | u32 phy_temp; | |
240 | u32 reg_temp; | |
241 | int ret; | |
242 | ||
243 | if (priv->model == AG7XXX_MODEL_AG933X) { | |
244 | phy_addr = 0x1f; | |
245 | reg_addr = 0x10; | |
246 | } else if (priv->model == AG7XXX_MODEL_AG934X) { | |
247 | phy_addr = 0x18; | |
248 | reg_addr = 0x00; | |
249 | } else | |
250 | return -EINVAL; | |
251 | ||
252 | ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); | |
253 | if (ret) | |
254 | return ret; | |
255 | ||
256 | phy_temp = ((reg >> 6) & 0x7) | 0x10; | |
257 | reg_temp = (reg >> 1) & 0x1e; | |
258 | ||
259 | /* | |
260 | * The switch on AR933x has some special register behavior, which | |
261 | * expects particular write order of their nibbles: | |
262 | * 0x40 ..... MSB first, LSB second | |
263 | * 0x50 ..... MSB first, LSB second | |
264 | * 0x98 ..... LSB first, MSB second | |
265 | * others ... don't care | |
266 | */ | |
267 | if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) { | |
268 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); | |
269 | if (ret < 0) | |
270 | return ret; | |
271 | ||
272 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); | |
273 | if (ret < 0) | |
274 | return ret; | |
275 | } else { | |
276 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); | |
277 | if (ret < 0) | |
278 | return ret; | |
279 | ||
280 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); | |
281 | if (ret < 0) | |
282 | return ret; | |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
2fd519f7 | 288 | static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val) |
e40095f6 MV |
289 | { |
290 | u32 data; | |
2fd519f7 JH |
291 | unsigned long start; |
292 | int ret; | |
293 | /* No idea if this is long enough or too long */ | |
294 | int timeout_ms = 1000; | |
e40095f6 MV |
295 | |
296 | /* Dummy read followed by PHY read/write command. */ | |
2fd519f7 JH |
297 | ret = ag7xxx_switch_reg_read(bus, 0x98, &data); |
298 | if (ret < 0) | |
299 | return ret; | |
e40095f6 | 300 | data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31); |
2fd519f7 JH |
301 | ret = ag7xxx_switch_reg_write(bus, 0x98, data); |
302 | if (ret < 0) | |
303 | return ret; | |
304 | ||
305 | start = get_timer(0); | |
e40095f6 MV |
306 | |
307 | /* Wait for operation to finish */ | |
308 | do { | |
2fd519f7 JH |
309 | ret = ag7xxx_switch_reg_read(bus, 0x98, &data); |
310 | if (ret < 0) | |
311 | return ret; | |
312 | ||
313 | if (get_timer(start) > timeout_ms) | |
314 | return -ETIMEDOUT; | |
e40095f6 MV |
315 | } while (data & BIT(31)); |
316 | ||
317 | return data & 0xffff; | |
318 | } | |
319 | ||
320 | static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) | |
321 | { | |
322 | return ag7xxx_mdio_rw(bus, addr, reg, BIT(27)); | |
323 | } | |
324 | ||
325 | static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, | |
326 | u16 val) | |
327 | { | |
2fd519f7 JH |
328 | int ret; |
329 | ||
330 | ret = ag7xxx_mdio_rw(bus, addr, reg, val); | |
331 | if (ret < 0) | |
332 | return ret; | |
e40095f6 MV |
333 | return 0; |
334 | } | |
335 | ||
336 | /* | |
337 | * DMA ring handlers | |
338 | */ | |
339 | static void ag7xxx_dma_clean_tx(struct udevice *dev) | |
340 | { | |
341 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
342 | struct ag7xxx_dma_desc *curr, *next; | |
343 | u32 start, end; | |
344 | int i; | |
345 | ||
346 | for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) { | |
347 | curr = &priv->tx_mac_descrtable[i]; | |
348 | next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM]; | |
349 | ||
350 | curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]); | |
351 | curr->config = AG7XXX_DMADESC_IS_EMPTY; | |
352 | curr->next_desc = virt_to_phys(next); | |
353 | } | |
354 | ||
355 | priv->tx_currdescnum = 0; | |
356 | ||
357 | /* Cache: Flush descriptors, don't care about buffers. */ | |
358 | start = (u32)(&priv->tx_mac_descrtable[0]); | |
359 | end = start + sizeof(priv->tx_mac_descrtable); | |
360 | flush_dcache_range(start, end); | |
361 | } | |
362 | ||
363 | static void ag7xxx_dma_clean_rx(struct udevice *dev) | |
364 | { | |
365 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
366 | struct ag7xxx_dma_desc *curr, *next; | |
367 | u32 start, end; | |
368 | int i; | |
369 | ||
370 | for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) { | |
371 | curr = &priv->rx_mac_descrtable[i]; | |
372 | next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM]; | |
373 | ||
374 | curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]); | |
375 | curr->config = AG7XXX_DMADESC_IS_EMPTY; | |
376 | curr->next_desc = virt_to_phys(next); | |
377 | } | |
378 | ||
379 | priv->rx_currdescnum = 0; | |
380 | ||
381 | /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */ | |
382 | start = (u32)(&priv->rx_mac_descrtable[0]); | |
383 | end = start + sizeof(priv->rx_mac_descrtable); | |
384 | flush_dcache_range(start, end); | |
385 | invalidate_dcache_range(start, end); | |
386 | ||
387 | start = (u32)&priv->rxbuffs; | |
388 | end = start + sizeof(priv->rxbuffs); | |
389 | invalidate_dcache_range(start, end); | |
390 | } | |
391 | ||
392 | /* | |
393 | * Ethernet I/O | |
394 | */ | |
395 | static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length) | |
396 | { | |
397 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
398 | struct ag7xxx_dma_desc *curr; | |
399 | u32 start, end; | |
400 | ||
401 | curr = &priv->tx_mac_descrtable[priv->tx_currdescnum]; | |
402 | ||
403 | /* Cache: Invalidate descriptor. */ | |
404 | start = (u32)curr; | |
405 | end = start + sizeof(*curr); | |
406 | invalidate_dcache_range(start, end); | |
407 | ||
408 | if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) { | |
409 | printf("ag7xxx: Out of TX DMA descriptors!\n"); | |
410 | return -EPERM; | |
411 | } | |
412 | ||
413 | /* Copy the packet into the data buffer. */ | |
414 | memcpy(phys_to_virt(curr->data_addr), packet, length); | |
415 | curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK; | |
416 | ||
417 | /* Cache: Flush descriptor, Flush buffer. */ | |
418 | start = (u32)curr; | |
419 | end = start + sizeof(*curr); | |
420 | flush_dcache_range(start, end); | |
421 | start = (u32)phys_to_virt(curr->data_addr); | |
422 | end = start + length; | |
423 | flush_dcache_range(start, end); | |
424 | ||
425 | /* Load the DMA descriptor and start TX DMA. */ | |
426 | writel(AG7XXX_ETH_DMA_TX_CTRL_TXE, | |
427 | priv->regs + AG7XXX_ETH_DMA_TX_CTRL); | |
428 | ||
429 | /* Switch to next TX descriptor. */ | |
430 | priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM; | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
435 | static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp) | |
436 | { | |
437 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
438 | struct ag7xxx_dma_desc *curr; | |
439 | u32 start, end, length; | |
440 | ||
441 | curr = &priv->rx_mac_descrtable[priv->rx_currdescnum]; | |
442 | ||
443 | /* Cache: Invalidate descriptor. */ | |
444 | start = (u32)curr; | |
445 | end = start + sizeof(*curr); | |
446 | invalidate_dcache_range(start, end); | |
447 | ||
448 | /* No packets received. */ | |
449 | if (curr->config & AG7XXX_DMADESC_IS_EMPTY) | |
450 | return -EAGAIN; | |
451 | ||
452 | length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK; | |
453 | ||
454 | /* Cache: Invalidate buffer. */ | |
455 | start = (u32)phys_to_virt(curr->data_addr); | |
456 | end = start + length; | |
457 | invalidate_dcache_range(start, end); | |
458 | ||
459 | /* Receive one packet and return length. */ | |
460 | *packetp = phys_to_virt(curr->data_addr); | |
461 | return length; | |
462 | } | |
463 | ||
464 | static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet, | |
465 | int length) | |
466 | { | |
467 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
468 | struct ag7xxx_dma_desc *curr; | |
469 | u32 start, end; | |
470 | ||
471 | curr = &priv->rx_mac_descrtable[priv->rx_currdescnum]; | |
472 | ||
473 | curr->config = AG7XXX_DMADESC_IS_EMPTY; | |
474 | ||
475 | /* Cache: Flush descriptor. */ | |
476 | start = (u32)curr; | |
477 | end = start + sizeof(*curr); | |
478 | flush_dcache_range(start, end); | |
479 | ||
480 | /* Switch to next RX descriptor. */ | |
481 | priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM; | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static int ag7xxx_eth_start(struct udevice *dev) | |
487 | { | |
488 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
489 | ||
490 | /* FIXME: Check if link up */ | |
491 | ||
492 | /* Clear the DMA rings. */ | |
493 | ag7xxx_dma_clean_tx(dev); | |
494 | ag7xxx_dma_clean_rx(dev); | |
495 | ||
496 | /* Load DMA descriptors and start the RX DMA. */ | |
497 | writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]), | |
498 | priv->regs + AG7XXX_ETH_DMA_TX_DESC); | |
499 | writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]), | |
500 | priv->regs + AG7XXX_ETH_DMA_RX_DESC); | |
501 | writel(AG7XXX_ETH_DMA_RX_CTRL_RXE, | |
502 | priv->regs + AG7XXX_ETH_DMA_RX_CTRL); | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | static void ag7xxx_eth_stop(struct udevice *dev) | |
508 | { | |
509 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
510 | ||
511 | /* Stop the TX DMA. */ | |
512 | writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL); | |
513 | wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0, | |
514 | 1000, 0); | |
515 | ||
516 | /* Stop the RX DMA. */ | |
517 | writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL); | |
518 | wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0, | |
519 | 1000, 0); | |
520 | } | |
521 | ||
522 | /* | |
523 | * Hardware setup | |
524 | */ | |
525 | static int ag7xxx_eth_write_hwaddr(struct udevice *dev) | |
526 | { | |
527 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
528 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
529 | unsigned char *mac = pdata->enetaddr; | |
530 | u32 macid_lo, macid_hi; | |
531 | ||
532 | macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24); | |
533 | macid_lo = (mac[5] << 16) | (mac[4] << 24); | |
534 | ||
535 | writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1); | |
536 | writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2); | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | static void ag7xxx_hw_setup(struct udevice *dev) | |
542 | { | |
543 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
544 | u32 speed; | |
545 | ||
546 | setbits_be32(priv->regs + AG7XXX_ETH_CFG1, | |
547 | AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST | | |
548 | AG7XXX_ETH_CFG1_SOFT_RST); | |
549 | ||
550 | mdelay(10); | |
551 | ||
552 | writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN, | |
553 | priv->regs + AG7XXX_ETH_CFG1); | |
554 | ||
555 | if (priv->interface == PHY_INTERFACE_MODE_RMII) | |
556 | speed = AG7XXX_ETH_CFG2_IF_10_100; | |
557 | else | |
558 | speed = AG7XXX_ETH_CFG2_IF_1000; | |
559 | ||
560 | clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2, | |
561 | AG7XXX_ETH_CFG2_IF_SPEED_MASK, | |
562 | speed | AG7XXX_ETH_CFG2_PAD_CRC_EN | | |
563 | AG7XXX_ETH_CFG2_LEN_CHECK); | |
564 | ||
565 | writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1); | |
566 | writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2); | |
567 | ||
568 | writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0); | |
569 | setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff); | |
570 | writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1); | |
571 | writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2); | |
572 | writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5); | |
573 | writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3); | |
574 | } | |
575 | ||
576 | static int ag7xxx_mii_get_div(void) | |
577 | { | |
578 | ulong freq = get_bus_freq(0); | |
579 | ||
580 | switch (freq / 1000000) { | |
581 | case 150: return 0x7; | |
582 | case 175: return 0x5; | |
583 | case 200: return 0x4; | |
584 | case 210: return 0x9; | |
585 | case 220: return 0x9; | |
586 | default: return 0x7; | |
587 | } | |
588 | } | |
589 | ||
590 | static int ag7xxx_mii_setup(struct udevice *dev) | |
591 | { | |
592 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
593 | int i, ret, div = ag7xxx_mii_get_div(); | |
594 | u32 reg; | |
595 | ||
596 | if (priv->model == AG7XXX_MODEL_AG933X) { | |
597 | /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */ | |
598 | if (priv->interface == PHY_INTERFACE_MODE_RMII) | |
599 | return 0; | |
600 | } | |
601 | ||
602 | if (priv->model == AG7XXX_MODEL_AG934X) { | |
603 | writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | 0x4, | |
604 | priv->regs + AG7XXX_ETH_MII_MGMT_CFG); | |
605 | writel(0x4, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); | |
606 | return 0; | |
607 | } | |
608 | ||
609 | for (i = 0; i < 10; i++) { | |
610 | writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div, | |
611 | priv->regs + AG7XXX_ETH_MII_MGMT_CFG); | |
612 | writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); | |
613 | ||
614 | /* Check the switch */ | |
615 | ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®); | |
616 | if (ret) | |
617 | continue; | |
618 | ||
619 | if (reg != 0x18007fff) | |
620 | continue; | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
625 | return -EINVAL; | |
626 | } | |
627 | ||
628 | static int ag933x_phy_setup_wan(struct udevice *dev) | |
629 | { | |
630 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
631 | ||
632 | /* Configure switch port 4 (GMAC0) */ | |
633 | return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000); | |
634 | } | |
635 | ||
636 | static int ag933x_phy_setup_lan(struct udevice *dev) | |
637 | { | |
638 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
639 | int i, ret; | |
640 | u32 reg; | |
641 | ||
642 | /* Reset the switch */ | |
643 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); | |
644 | if (ret) | |
645 | return ret; | |
646 | reg |= BIT(31); | |
647 | ret = ag7xxx_switch_reg_write(priv->bus, 0, reg); | |
648 | if (ret) | |
649 | return ret; | |
650 | ||
651 | do { | |
652 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); | |
653 | if (ret) | |
654 | return ret; | |
655 | } while (reg & BIT(31)); | |
656 | ||
657 | /* Configure switch ports 0...3 (GMAC1) */ | |
658 | for (i = 0; i < 4; i++) { | |
659 | ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000); | |
660 | if (ret) | |
661 | return ret; | |
662 | } | |
663 | ||
664 | /* Enable CPU port */ | |
665 | ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8)); | |
666 | if (ret) | |
667 | return ret; | |
668 | ||
669 | for (i = 0; i < 4; i++) { | |
670 | ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9)); | |
671 | if (ret) | |
672 | return ret; | |
673 | } | |
674 | ||
675 | /* QM Control */ | |
676 | ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e); | |
677 | if (ret) | |
678 | return ret; | |
679 | ||
680 | /* Disable Atheros header */ | |
681 | ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004); | |
682 | if (ret) | |
683 | return ret; | |
684 | ||
685 | /* Tag priority mapping */ | |
686 | ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50); | |
687 | if (ret) | |
688 | return ret; | |
689 | ||
690 | /* Enable ARP packets to the CPU */ | |
691 | ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®); | |
692 | if (ret) | |
693 | return ret; | |
694 | reg |= 0x100000; | |
695 | ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg); | |
696 | if (ret) | |
697 | return ret; | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
702 | static int ag933x_phy_setup_reset_set(struct udevice *dev, int port) | |
703 | { | |
704 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
705 | int ret; | |
706 | ||
707 | ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE, | |
708 | ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | | |
709 | ADVERTISE_PAUSE_ASYM); | |
710 | if (ret) | |
711 | return ret; | |
712 | ||
713 | if (priv->model == AG7XXX_MODEL_AG934X) { | |
714 | ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000, | |
715 | ADVERTISE_1000FULL); | |
716 | if (ret) | |
717 | return ret; | |
718 | } | |
719 | ||
720 | return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR, | |
721 | BMCR_ANENABLE | BMCR_RESET); | |
722 | } | |
723 | ||
724 | static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port) | |
725 | { | |
726 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
727 | int ret; | |
728 | ||
729 | do { | |
730 | ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); | |
731 | if (ret < 0) | |
732 | return ret; | |
733 | mdelay(10); | |
734 | } while (ret & BMCR_RESET); | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
739 | static int ag933x_phy_setup_common(struct udevice *dev) | |
740 | { | |
741 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
742 | int i, ret, phymax; | |
743 | ||
744 | if (priv->model == AG7XXX_MODEL_AG933X) | |
745 | phymax = 4; | |
746 | else if (priv->model == AG7XXX_MODEL_AG934X) | |
747 | phymax = 5; | |
748 | else | |
749 | return -EINVAL; | |
750 | ||
751 | if (priv->interface == PHY_INTERFACE_MODE_RMII) { | |
752 | ret = ag933x_phy_setup_reset_set(dev, phymax); | |
753 | if (ret) | |
754 | return ret; | |
755 | ||
756 | ret = ag933x_phy_setup_reset_fin(dev, phymax); | |
757 | if (ret) | |
758 | return ret; | |
759 | ||
760 | /* Read out link status */ | |
761 | ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR); | |
762 | if (ret < 0) | |
763 | return ret; | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | /* Switch ports */ | |
769 | for (i = 0; i < phymax; i++) { | |
770 | ret = ag933x_phy_setup_reset_set(dev, i); | |
771 | if (ret) | |
772 | return ret; | |
773 | } | |
774 | ||
775 | for (i = 0; i < phymax; i++) { | |
776 | ret = ag933x_phy_setup_reset_fin(dev, i); | |
777 | if (ret) | |
778 | return ret; | |
779 | } | |
780 | ||
781 | for (i = 0; i < phymax; i++) { | |
782 | /* Read out link status */ | |
783 | ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); | |
784 | if (ret < 0) | |
785 | return ret; | |
786 | } | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
791 | static int ag934x_phy_setup(struct udevice *dev) | |
792 | { | |
793 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
794 | int i, ret; | |
795 | u32 reg; | |
796 | ||
797 | ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f); | |
798 | if (ret) | |
799 | return ret; | |
800 | ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000); | |
801 | if (ret) | |
802 | return ret; | |
803 | ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000); | |
804 | if (ret) | |
805 | return ret; | |
806 | ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000); | |
807 | if (ret) | |
808 | return ret; | |
809 | ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e); | |
810 | if (ret) | |
811 | return ret; | |
812 | ||
813 | /* AR8327/AR8328 v1.0 fixup */ | |
814 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); | |
815 | if (ret) | |
816 | return ret; | |
817 | if ((reg & 0xffff) == 0x1201) { | |
818 | for (i = 0; i < 5; i++) { | |
819 | ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0); | |
820 | if (ret) | |
821 | return ret; | |
822 | ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea); | |
823 | if (ret) | |
824 | return ret; | |
825 | ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d); | |
826 | if (ret) | |
827 | return ret; | |
828 | ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0); | |
829 | if (ret) | |
830 | return ret; | |
831 | } | |
832 | } | |
833 | ||
834 | ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®); | |
835 | if (ret) | |
836 | return ret; | |
837 | reg &= ~0x70000; | |
838 | ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg); | |
839 | if (ret) | |
840 | return ret; | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static int ag7xxx_mac_probe(struct udevice *dev) | |
846 | { | |
847 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
848 | int ret; | |
849 | ||
850 | ag7xxx_hw_setup(dev); | |
851 | ret = ag7xxx_mii_setup(dev); | |
852 | if (ret) | |
853 | return ret; | |
854 | ||
855 | ag7xxx_eth_write_hwaddr(dev); | |
856 | ||
857 | if (priv->model == AG7XXX_MODEL_AG933X) { | |
858 | if (priv->interface == PHY_INTERFACE_MODE_RMII) | |
859 | ret = ag933x_phy_setup_wan(dev); | |
860 | else | |
861 | ret = ag933x_phy_setup_lan(dev); | |
862 | } else if (priv->model == AG7XXX_MODEL_AG934X) { | |
863 | ret = ag934x_phy_setup(dev); | |
864 | } else { | |
865 | return -EINVAL; | |
866 | } | |
867 | ||
868 | if (ret) | |
869 | return ret; | |
870 | ||
871 | return ag933x_phy_setup_common(dev); | |
872 | } | |
873 | ||
874 | static int ag7xxx_mdio_probe(struct udevice *dev) | |
875 | { | |
876 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
877 | struct mii_dev *bus = mdio_alloc(); | |
878 | ||
879 | if (!bus) | |
880 | return -ENOMEM; | |
881 | ||
882 | bus->read = ag7xxx_mdio_read; | |
883 | bus->write = ag7xxx_mdio_write; | |
884 | snprintf(bus->name, sizeof(bus->name), dev->name); | |
885 | ||
886 | bus->priv = (void *)priv; | |
887 | ||
888 | return mdio_register(bus); | |
889 | } | |
890 | ||
891 | static int ag7xxx_get_phy_iface_offset(struct udevice *dev) | |
892 | { | |
893 | int offset; | |
894 | ||
e160f7d4 | 895 | offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy"); |
e40095f6 MV |
896 | if (offset <= 0) { |
897 | debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset); | |
898 | return -EINVAL; | |
899 | } | |
900 | ||
901 | offset = fdt_parent_offset(gd->fdt_blob, offset); | |
902 | if (offset <= 0) { | |
903 | debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n", | |
904 | __func__, offset); | |
905 | return -EINVAL; | |
906 | } | |
907 | ||
908 | offset = fdt_parent_offset(gd->fdt_blob, offset); | |
909 | if (offset <= 0) { | |
910 | debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n", | |
911 | __func__, offset); | |
912 | return -EINVAL; | |
913 | } | |
914 | ||
915 | return offset; | |
916 | } | |
917 | ||
918 | static int ag7xxx_eth_probe(struct udevice *dev) | |
919 | { | |
920 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
921 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
922 | void __iomem *iobase, *phyiobase; | |
923 | int ret, phyreg; | |
924 | ||
925 | /* Decoding of convoluted PHY wiring on Atheros MIPS. */ | |
926 | ret = ag7xxx_get_phy_iface_offset(dev); | |
927 | if (ret <= 0) | |
928 | return ret; | |
929 | phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1); | |
930 | ||
931 | iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE); | |
932 | phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE); | |
933 | ||
934 | debug("%s, iobase=%p, phyiobase=%p, priv=%p\n", | |
935 | __func__, iobase, phyiobase, priv); | |
936 | priv->regs = iobase; | |
937 | priv->phyregs = phyiobase; | |
938 | priv->interface = pdata->phy_interface; | |
939 | priv->model = dev_get_driver_data(dev); | |
940 | ||
941 | ret = ag7xxx_mdio_probe(dev); | |
942 | if (ret) | |
943 | return ret; | |
944 | ||
945 | priv->bus = miiphy_get_dev_by_name(dev->name); | |
946 | ||
947 | ret = ag7xxx_mac_probe(dev); | |
948 | debug("%s, ret=%d\n", __func__, ret); | |
949 | ||
950 | return ret; | |
951 | } | |
952 | ||
953 | static int ag7xxx_eth_remove(struct udevice *dev) | |
954 | { | |
955 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); | |
956 | ||
957 | free(priv->phydev); | |
958 | mdio_unregister(priv->bus); | |
959 | mdio_free(priv->bus); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
964 | static const struct eth_ops ag7xxx_eth_ops = { | |
965 | .start = ag7xxx_eth_start, | |
966 | .send = ag7xxx_eth_send, | |
967 | .recv = ag7xxx_eth_recv, | |
968 | .free_pkt = ag7xxx_eth_free_pkt, | |
969 | .stop = ag7xxx_eth_stop, | |
970 | .write_hwaddr = ag7xxx_eth_write_hwaddr, | |
971 | }; | |
972 | ||
973 | static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev) | |
974 | { | |
975 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
976 | const char *phy_mode; | |
977 | int ret; | |
978 | ||
a821c4af | 979 | pdata->iobase = devfdt_get_addr(dev); |
e40095f6 MV |
980 | pdata->phy_interface = -1; |
981 | ||
982 | /* Decoding of convoluted PHY wiring on Atheros MIPS. */ | |
983 | ret = ag7xxx_get_phy_iface_offset(dev); | |
984 | if (ret <= 0) | |
985 | return ret; | |
986 | ||
987 | phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL); | |
988 | if (phy_mode) | |
989 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
990 | if (pdata->phy_interface == -1) { | |
991 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
992 | return -EINVAL; | |
993 | } | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static const struct udevice_id ag7xxx_eth_ids[] = { | |
999 | { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X }, | |
1000 | { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X }, | |
1001 | { } | |
1002 | }; | |
1003 | ||
1004 | U_BOOT_DRIVER(eth_ag7xxx) = { | |
1005 | .name = "eth_ag7xxx", | |
1006 | .id = UCLASS_ETH, | |
1007 | .of_match = ag7xxx_eth_ids, | |
1008 | .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata, | |
1009 | .probe = ag7xxx_eth_probe, | |
1010 | .remove = ag7xxx_eth_remove, | |
1011 | .ops = &ag7xxx_eth_ops, | |
1012 | .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv), | |
1013 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
1014 | .flags = DM_FLAG_ALLOC_PRIV_DMA, | |
1015 | }; |