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c960b13e TC |
1 | /* |
2 | * Altera 10/100/1000 triple speed ethernet mac driver | |
3 | * | |
4 | * Copyright (C) 2008 Altera Corporation. | |
5 | * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <config.h> | |
12 | #include <common.h> | |
13 | #include <malloc.h> | |
14 | #include <net.h> | |
15 | #include <command.h> | |
16 | #include <asm/cache.h> | |
17 | #include <asm/dma-mapping.h> | |
18 | #include <miiphy.h> | |
19 | #include "altera_tse.h" | |
20 | ||
21 | /* sgdma debug - print descriptor */ | |
22 | static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc) | |
23 | { | |
24 | debug("SGDMA DEBUG :\n"); | |
25 | debug("desc->source : 0x%x \n", (unsigned int)desc->source); | |
26 | debug("desc->destination : 0x%x \n", (unsigned int)desc->destination); | |
27 | debug("desc->next : 0x%x \n", (unsigned int)desc->next); | |
28 | debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad); | |
29 | debug("desc->destination_pad : 0x%x \n", | |
30 | (unsigned int)desc->destination_pad); | |
31 | debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad); | |
32 | debug("desc->bytes_to_transfer : 0x%x \n", | |
33 | (unsigned int)desc->bytes_to_transfer); | |
34 | debug("desc->actual_bytes_transferred : 0x%x \n", | |
35 | (unsigned int)desc->actual_bytes_transferred); | |
36 | debug("desc->descriptor_status : 0x%x \n", | |
37 | (unsigned int)desc->descriptor_status); | |
38 | debug("desc->descriptor_control : 0x%x \n", | |
39 | (unsigned int)desc->descriptor_control); | |
40 | } | |
41 | ||
42 | /* This is a generic routine that the SGDMA mode-specific routines | |
43 | * call to populate a descriptor. | |
44 | * arg1 :pointer to first SGDMA descriptor. | |
45 | * arg2 :pointer to next SGDMA descriptor. | |
46 | * arg3 :Address to where data to be written. | |
47 | * arg4 :Address from where data to be read. | |
48 | * arg5 :no of byte to transaction. | |
49 | * arg6 :variable indicating to generate start of packet or not | |
50 | * arg7 :read fixed | |
51 | * arg8 :write fixed | |
52 | * arg9 :read burst | |
53 | * arg10 :write burst | |
54 | * arg11 :atlantic_channel number | |
55 | */ | |
56 | static void alt_sgdma_construct_descriptor_burst( | |
57 | volatile struct alt_sgdma_descriptor *desc, | |
58 | volatile struct alt_sgdma_descriptor *next, | |
59 | unsigned int *read_addr, | |
60 | unsigned int *write_addr, | |
61 | unsigned short length_or_eop, | |
62 | int generate_eop, | |
63 | int read_fixed, | |
64 | int write_fixed_or_sop, | |
65 | int read_burst, | |
66 | int write_burst, | |
67 | unsigned char atlantic_channel) | |
68 | { | |
69 | /* | |
70 | * Mark the "next" descriptor as "not" owned by hardware. This prevents | |
71 | * The SGDMA controller from continuing to process the chain. This is | |
72 | * done as a single IO write to bypass cache, without flushing | |
73 | * the entire descriptor, since only the 8-bit descriptor status must | |
74 | * be flushed. | |
75 | */ | |
76 | if (!next) | |
77 | debug("Next descriptor not defined!!\n"); | |
78 | ||
79 | next->descriptor_control = (next->descriptor_control & | |
80 | ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK); | |
81 | ||
82 | desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF); | |
83 | desc->destination = | |
84 | (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF); | |
85 | desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF); | |
86 | desc->source_pad = 0x0; | |
87 | desc->destination_pad = 0x0; | |
88 | desc->next_pad = 0x0; | |
89 | desc->bytes_to_transfer = length_or_eop; | |
90 | desc->actual_bytes_transferred = 0; | |
91 | desc->descriptor_status = 0x0; | |
92 | ||
93 | /* SGDMA burst not currently supported */ | |
94 | desc->read_burst = 0; | |
95 | desc->write_burst = 0; | |
96 | ||
97 | /* | |
98 | * Set the descriptor control block as follows: | |
99 | * - Set "owned by hardware" bit | |
100 | * - Optionally set "generate EOP" bit | |
101 | * - Optionally set the "read from fixed address" bit | |
102 | * - Optionally set the "write to fixed address bit (which serves | |
103 | * serves as a "generate SOP" control bit in memory-to-stream mode). | |
104 | * - Set the 4-bit atlantic channel, if specified | |
105 | * | |
106 | * Note this step is performed after all other descriptor information | |
107 | * has been filled out so that, if the controller already happens to be | |
108 | * pointing at this descriptor, it will not run (via the "owned by | |
109 | * hardware" bit) until all other descriptor has been set up. | |
110 | */ | |
111 | ||
112 | desc->descriptor_control = | |
113 | ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) | | |
114 | (generate_eop ? | |
115 | ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) | | |
116 | (read_fixed ? | |
117 | ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) | | |
118 | (write_fixed_or_sop ? | |
119 | ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) | | |
120 | (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0) | |
121 | ); | |
122 | } | |
123 | ||
124 | static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev, | |
125 | volatile struct alt_sgdma_descriptor *desc) | |
126 | { | |
127 | unsigned int status; | |
128 | int counter = 0; | |
129 | ||
130 | /* Wait for any pending transfers to complete */ | |
131 | alt_sgdma_print_desc(desc); | |
132 | status = dev->status; | |
133 | ||
134 | counter = 0; | |
135 | while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { | |
136 | if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) | |
137 | break; | |
138 | } | |
139 | ||
140 | if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) | |
141 | debug("Timeout waiting sgdma in do sync!\n"); | |
142 | ||
143 | /* | |
144 | * Clear any (previous) status register information | |
145 | * that might occlude our error checking later. | |
146 | */ | |
147 | dev->status = 0xFF; | |
148 | ||
149 | /* Point the controller at the descriptor */ | |
150 | dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; | |
151 | debug("next desc in sgdma 0x%x\n", | |
152 | (unsigned int)dev->next_descriptor_pointer); | |
153 | ||
154 | /* | |
155 | * Set up SGDMA controller to: | |
156 | * - Disable interrupt generation | |
157 | * - Run once a valid descriptor is written to controller | |
158 | * - Stop on an error with any particular descriptor | |
159 | */ | |
160 | dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | | |
161 | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); | |
162 | ||
163 | /* Wait for the descriptor (chain) to complete */ | |
164 | status = dev->status; | |
165 | debug("wait for sgdma...."); | |
166 | while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) | |
167 | ; | |
168 | debug("done\n"); | |
169 | ||
170 | /* Clear Run */ | |
171 | dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK)); | |
172 | ||
173 | /* Get & clear status register contents */ | |
174 | status = dev->status; | |
175 | dev->status = 0xFF; | |
176 | ||
177 | /* we really should check if the transfer completes properly */ | |
178 | debug("tx sgdma status = 0x%x", status); | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev, | |
183 | volatile struct alt_sgdma_descriptor *desc) | |
184 | { | |
185 | unsigned int status; | |
186 | int counter = 0; | |
187 | ||
188 | /* Wait for any pending transfers to complete */ | |
189 | alt_sgdma_print_desc(desc); | |
190 | status = dev->status; | |
191 | ||
192 | counter = 0; | |
193 | while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { | |
194 | if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) | |
195 | break; | |
196 | } | |
197 | ||
198 | if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) | |
199 | debug("Timeout waiting sgdma in do async!\n"); | |
200 | ||
201 | /* | |
202 | * Clear any (previous) status register information | |
203 | * that might occlude our error checking later. | |
204 | */ | |
205 | dev->status = 0xFF; | |
206 | ||
207 | /* Point the controller at the descriptor */ | |
208 | dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; | |
209 | ||
210 | /* | |
211 | * Set up SGDMA controller to: | |
212 | * - Disable interrupt generation | |
213 | * - Run once a valid descriptor is written to controller | |
214 | * - Stop on an error with any particular descriptor | |
215 | */ | |
216 | dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | | |
217 | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); | |
218 | ||
219 | /* we really should check if the transfer completes properly */ | |
220 | return 0; | |
221 | } | |
222 | ||
223 | /* u-boot interface */ | |
224 | static int tse_adjust_link(struct altera_tse_priv *priv) | |
225 | { | |
226 | unsigned int refvar; | |
227 | ||
228 | refvar = priv->mac_dev->command_config.image; | |
229 | ||
230 | if (!(priv->duplexity)) | |
231 | refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; | |
232 | else | |
233 | refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; | |
234 | ||
235 | switch (priv->speed) { | |
236 | case 1000: | |
237 | refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; | |
238 | refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; | |
239 | break; | |
240 | case 100: | |
241 | refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; | |
242 | refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; | |
243 | break; | |
244 | case 10: | |
245 | refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; | |
246 | refvar |= ALTERA_TSE_CMD_ENA_10_MSK; | |
247 | break; | |
248 | } | |
249 | priv->mac_dev->command_config.image = refvar; | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static int tse_eth_send(struct eth_device *dev, | |
255 | volatile void *packet, int length) | |
256 | { | |
257 | struct altera_tse_priv *priv = dev->priv; | |
258 | volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; | |
259 | volatile struct alt_sgdma_descriptor *tx_desc = | |
260 | (volatile struct alt_sgdma_descriptor *)priv->tx_desc; | |
261 | ||
262 | volatile struct alt_sgdma_descriptor *tx_desc_cur = | |
263 | (volatile struct alt_sgdma_descriptor *)&tx_desc[0]; | |
264 | ||
265 | flush_dcache((unsigned long)packet, length); | |
266 | alt_sgdma_construct_descriptor_burst( | |
267 | (volatile struct alt_sgdma_descriptor *)&tx_desc[0], | |
268 | (volatile struct alt_sgdma_descriptor *)&tx_desc[1], | |
269 | (unsigned int *)packet, /* read addr */ | |
270 | (unsigned int *)0, | |
271 | length, /* length or EOP ,will change for each tx */ | |
272 | 0x1, /* gen eop */ | |
273 | 0x0, /* read fixed */ | |
274 | 0x1, /* write fixed or sop */ | |
275 | 0x0, /* read burst */ | |
276 | 0x0, /* write burst */ | |
277 | 0x0 /* channel */ | |
278 | ); | |
279 | debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length); | |
280 | ||
281 | /* send the packet */ | |
282 | debug("sending packet\n"); | |
283 | alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur); | |
284 | debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred); | |
285 | return tx_desc_cur->actual_bytes_transferred; | |
286 | } | |
287 | ||
288 | static int tse_eth_rx(struct eth_device *dev) | |
289 | { | |
290 | int packet_length = 0; | |
291 | struct altera_tse_priv *priv = dev->priv; | |
292 | volatile struct alt_sgdma_descriptor *rx_desc = | |
293 | (volatile struct alt_sgdma_descriptor *)priv->rx_desc; | |
294 | volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0]; | |
295 | ||
296 | if (rx_desc_cur->descriptor_status & | |
297 | ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { | |
298 | debug("got packet\n"); | |
299 | packet_length = rx_desc->actual_bytes_transferred; | |
300 | NetReceive(NetRxPackets[0], packet_length); | |
301 | ||
302 | /* start descriptor again */ | |
303 | flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); | |
304 | alt_sgdma_construct_descriptor_burst( | |
305 | (volatile struct alt_sgdma_descriptor *)&rx_desc[0], | |
306 | (volatile struct alt_sgdma_descriptor *)&rx_desc[1], | |
307 | (unsigned int)0x0, /* read addr */ | |
308 | (unsigned int *)NetRxPackets[0], | |
309 | 0x0, /* length or EOP */ | |
310 | 0x0, /* gen eop */ | |
311 | 0x0, /* read fixed */ | |
312 | 0x0, /* write fixed or sop */ | |
313 | 0x0, /* read burst */ | |
314 | 0x0, /* write burst */ | |
315 | 0x0 /* channel */ | |
316 | ); | |
317 | ||
318 | /* setup the sgdma */ | |
319 | alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]); | |
320 | } | |
321 | ||
322 | return -1; | |
323 | } | |
324 | ||
325 | static void tse_eth_halt(struct eth_device *dev) | |
326 | { | |
327 | /* don't do anything! */ | |
328 | /* this gets called after each uboot */ | |
329 | /* network command. don't need to reset the thing all of the time */ | |
330 | } | |
331 | ||
332 | static void tse_eth_reset(struct eth_device *dev) | |
333 | { | |
334 | /* stop sgdmas, disable tse receive */ | |
335 | struct altera_tse_priv *priv = dev->priv; | |
336 | volatile struct alt_tse_mac *mac_dev = priv->mac_dev; | |
337 | volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; | |
338 | volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; | |
339 | int counter; | |
340 | volatile struct alt_sgdma_descriptor *rx_desc = | |
341 | (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0]; | |
342 | ||
343 | /* clear rx desc & wait for sgdma to complete */ | |
344 | rx_desc->descriptor_control = 0; | |
345 | rx_sgdma->control = 0; | |
346 | counter = 0; | |
347 | while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { | |
348 | if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) | |
349 | break; | |
350 | } | |
351 | ||
352 | if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { | |
353 | debug("Timeout waiting for rx sgdma!\n"); | |
354 | rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; | |
355 | rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; | |
356 | } | |
357 | ||
358 | counter = 0; | |
359 | tx_sgdma->control = 0; | |
360 | while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { | |
361 | if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) | |
362 | break; | |
363 | } | |
364 | ||
365 | if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { | |
366 | debug("Timeout waiting for tx sgdma!\n"); | |
367 | tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; | |
368 | tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; | |
369 | } | |
370 | /* reset the mac */ | |
371 | mac_dev->command_config.bits.transmit_enable = 1; | |
372 | mac_dev->command_config.bits.receive_enable = 1; | |
373 | mac_dev->command_config.bits.software_reset = 1; | |
374 | ||
375 | counter = 0; | |
376 | while (mac_dev->command_config.bits.software_reset) { | |
377 | if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR) | |
378 | break; | |
379 | } | |
380 | ||
381 | if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR) | |
382 | debug("TSEMAC SW reset bit never cleared!\n"); | |
383 | } | |
384 | ||
385 | static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum) | |
386 | { | |
387 | volatile struct alt_tse_mac *mac_dev; | |
388 | unsigned int *mdio_regs; | |
389 | unsigned int data; | |
390 | u16 value; | |
391 | ||
392 | mac_dev = priv->mac_dev; | |
393 | ||
394 | /* set mdio address */ | |
395 | mac_dev->mdio_phy1_addr = priv->phyaddr; | |
396 | mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; | |
397 | ||
398 | /* get the data */ | |
399 | data = mdio_regs[regnum]; | |
400 | ||
401 | value = data & 0xffff; | |
402 | ||
403 | return value; | |
404 | } | |
405 | ||
406 | static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum, | |
407 | unsigned int value) | |
408 | { | |
409 | volatile struct alt_tse_mac *mac_dev; | |
410 | unsigned int *mdio_regs; | |
411 | unsigned int data; | |
412 | ||
413 | mac_dev = priv->mac_dev; | |
414 | ||
415 | /* set mdio address */ | |
416 | mac_dev->mdio_phy1_addr = priv->phyaddr; | |
417 | mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; | |
418 | ||
419 | /* get the data */ | |
420 | data = (unsigned int)value; | |
421 | ||
422 | mdio_regs[regnum] = data; | |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
427 | /* MDIO access to phy */ | |
428 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) | |
429 | static int altera_tse_miiphy_write(char *devname, unsigned char addr, | |
430 | unsigned char reg, unsigned short value) | |
431 | { | |
432 | struct eth_device *dev; | |
433 | struct altera_tse_priv *priv; | |
434 | dev = eth_get_dev_by_name(devname); | |
435 | priv = dev->priv; | |
436 | ||
437 | tse_mdio_write(priv, (uint) reg, (uint) value); | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
442 | static int altera_tse_miiphy_read(char *devname, unsigned char addr, | |
443 | unsigned char reg, unsigned short *value) | |
444 | { | |
445 | struct eth_device *dev; | |
446 | struct altera_tse_priv *priv; | |
447 | volatile struct alt_tse_mac *mac_dev; | |
448 | unsigned int *mdio_regs; | |
449 | ||
450 | dev = eth_get_dev_by_name(devname); | |
451 | priv = dev->priv; | |
452 | ||
453 | mac_dev = priv->mac_dev; | |
454 | mac_dev->mdio_phy1_addr = (int)addr; | |
455 | mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; | |
456 | ||
457 | *value = 0xffff & mdio_regs[reg]; | |
458 | ||
459 | return 0; | |
460 | ||
461 | } | |
462 | #endif | |
463 | ||
464 | /* | |
465 | * Also copied from tsec.c | |
466 | */ | |
467 | /* Parse the status register for link, and then do | |
468 | * auto-negotiation | |
469 | */ | |
470 | static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) | |
471 | { | |
472 | /* | |
473 | * Wait if the link is up, and autonegotiation is in progress | |
474 | * (ie - we're capable and it's not done) | |
475 | */ | |
476 | mii_reg = tse_mdio_read(priv, MIIM_STATUS); | |
477 | ||
478 | if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) | |
479 | && !(mii_reg & PHY_BMSR_AUTN_COMP)) { | |
480 | int i = 0; | |
481 | ||
482 | puts("Waiting for PHY auto negotiation to complete"); | |
483 | while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { | |
484 | /* | |
485 | * Timeout reached ? | |
486 | */ | |
487 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
488 | puts(" TIMEOUT !\n"); | |
489 | priv->link = 0; | |
490 | return 0; | |
491 | } | |
492 | ||
493 | if ((i++ % 1000) == 0) | |
494 | putc('.'); | |
495 | udelay(1000); /* 1 ms */ | |
496 | mii_reg = tse_mdio_read(priv, MIIM_STATUS); | |
497 | } | |
498 | puts(" done\n"); | |
499 | priv->link = 1; | |
500 | udelay(500000); /* another 500 ms (results in faster booting) */ | |
501 | } else { | |
502 | if (mii_reg & MIIM_STATUS_LINK) { | |
503 | debug("Link is up\n"); | |
504 | priv->link = 1; | |
505 | } else { | |
506 | debug("Link is down\n"); | |
507 | priv->link = 0; | |
508 | } | |
509 | } | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | /* Parse the 88E1011's status register for speed and duplex | |
515 | * information | |
516 | */ | |
517 | static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv) | |
518 | { | |
519 | uint speed; | |
520 | ||
521 | mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); | |
522 | ||
523 | if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && | |
524 | !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { | |
525 | int i = 0; | |
526 | ||
527 | puts("Waiting for PHY realtime link"); | |
528 | while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { | |
529 | /* Timeout reached ? */ | |
530 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
531 | puts(" TIMEOUT !\n"); | |
532 | priv->link = 0; | |
533 | break; | |
534 | } | |
535 | ||
536 | if ((i++ == 1000) == 0) { | |
537 | i = 0; | |
538 | puts("."); | |
539 | } | |
540 | udelay(1000); /* 1 ms */ | |
541 | mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); | |
542 | } | |
543 | puts(" done\n"); | |
544 | udelay(500000); /* another 500 ms (results in faster booting) */ | |
545 | } else { | |
546 | if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) | |
547 | priv->link = 1; | |
548 | else | |
549 | priv->link = 0; | |
550 | } | |
551 | ||
552 | if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) | |
553 | priv->duplexity = 1; | |
554 | else | |
555 | priv->duplexity = 0; | |
556 | ||
557 | speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); | |
558 | ||
559 | switch (speed) { | |
560 | case MIIM_88E1011_PHYSTAT_GBIT: | |
561 | priv->speed = 1000; | |
562 | debug("PHY Speed is 1000Mbit\n"); | |
563 | break; | |
564 | case MIIM_88E1011_PHYSTAT_100: | |
565 | debug("PHY Speed is 100Mbit\n"); | |
566 | priv->speed = 100; | |
567 | break; | |
568 | default: | |
569 | debug("PHY Speed is 10Mbit\n"); | |
570 | priv->speed = 10; | |
571 | } | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
576 | static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv) | |
577 | { | |
578 | uint mii_data = tse_mdio_read(priv, mii_reg); | |
579 | mii_data &= 0xfff0; | |
580 | mii_data |= 0xb; | |
581 | return mii_data; | |
582 | } | |
583 | ||
584 | static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv) | |
585 | { | |
586 | uint mii_data = tse_mdio_read(priv, mii_reg); | |
587 | mii_data &= ~0x82; | |
588 | mii_data |= 0x82; | |
589 | return mii_data; | |
590 | } | |
591 | ||
592 | /* | |
593 | * Returns which value to write to the control register. | |
594 | * For 10/100, the value is slightly different | |
595 | */ | |
596 | static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv) | |
597 | { | |
598 | return MIIM_CONTROL_INIT; | |
599 | } | |
600 | ||
601 | /* | |
602 | * PHY & MDIO code | |
603 | * Need to add SGMII stuff | |
604 | * | |
605 | */ | |
606 | ||
607 | static struct phy_info phy_info_M88E1111S = { | |
608 | 0x01410cc, | |
609 | "Marvell 88E1111S", | |
610 | 4, | |
611 | (struct phy_cmd[]){ /* config */ | |
612 | /* Reset and configure the PHY */ | |
613 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
614 | {MIIM_88E1111_PHY_EXT_SR, 0x848f, | |
615 | &mii_m88e1111s_setmode_sr}, | |
616 | /* Delay RGMII TX and RX */ | |
617 | {MIIM_88E1111_PHY_EXT_CR, 0x0cd2, | |
618 | &mii_m88e1111s_setmode_cr}, | |
619 | {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, | |
620 | {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, | |
621 | {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, | |
622 | {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, | |
623 | {miim_end,} | |
624 | }, | |
625 | (struct phy_cmd[]){ /* startup */ | |
626 | /* Status is read once to clear old link state */ | |
627 | {MIIM_STATUS, miim_read, NULL}, | |
628 | /* Auto-negotiate */ | |
629 | {MIIM_STATUS, miim_read, &mii_parse_sr}, | |
630 | /* Read the status */ | |
631 | {MIIM_88E1011_PHY_STATUS, miim_read, | |
632 | &mii_parse_88E1011_psr}, | |
633 | {miim_end,} | |
634 | }, | |
635 | (struct phy_cmd[]){ /* shutdown */ | |
636 | {miim_end,} | |
637 | }, | |
638 | }; | |
639 | ||
640 | /* a generic flavor. */ | |
641 | static struct phy_info phy_info_generic = { | |
642 | 0, | |
643 | "Unknown/Generic PHY", | |
644 | 32, | |
645 | (struct phy_cmd[]){ /* config */ | |
646 | {PHY_BMCR, PHY_BMCR_RESET, NULL}, | |
647 | {PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG, NULL}, | |
648 | {miim_end,} | |
649 | }, | |
650 | (struct phy_cmd[]){ /* startup */ | |
651 | {PHY_BMSR, miim_read, NULL}, | |
652 | {PHY_BMSR, miim_read, &mii_parse_sr}, | |
653 | {miim_end,} | |
654 | }, | |
655 | (struct phy_cmd[]){ /* shutdown */ | |
656 | {miim_end,} | |
657 | } | |
658 | }; | |
659 | ||
660 | static struct phy_info *phy_info[] = { | |
661 | &phy_info_M88E1111S, | |
662 | NULL | |
663 | }; | |
664 | ||
665 | /* Grab the identifier of the device's PHY, and search through | |
666 | * all of the known PHYs to see if one matches. If so, return | |
667 | * it, if not, return NULL | |
668 | */ | |
669 | static struct phy_info *get_phy_info(struct eth_device *dev) | |
670 | { | |
671 | struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; | |
672 | uint phy_reg, phy_ID; | |
673 | int i; | |
674 | struct phy_info *theInfo = NULL; | |
675 | ||
676 | /* Grab the bits from PHYIR1, and put them in the upper half */ | |
677 | phy_reg = tse_mdio_read(priv, MIIM_PHYIR1); | |
678 | phy_ID = (phy_reg & 0xffff) << 16; | |
679 | ||
680 | /* Grab the bits from PHYIR2, and put them in the lower half */ | |
681 | phy_reg = tse_mdio_read(priv, MIIM_PHYIR2); | |
682 | phy_ID |= (phy_reg & 0xffff); | |
683 | ||
684 | /* loop through all the known PHY types, and find one that */ | |
685 | /* matches the ID we read from the PHY. */ | |
686 | for (i = 0; phy_info[i]; i++) { | |
687 | if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { | |
688 | theInfo = phy_info[i]; | |
689 | break; | |
690 | } | |
691 | } | |
692 | ||
693 | if (theInfo == NULL) { | |
694 | theInfo = &phy_info_generic; | |
695 | debug("%s: No support for PHY id %x; assuming generic\n", | |
696 | dev->name, phy_ID); | |
697 | } else | |
698 | debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); | |
699 | ||
700 | return theInfo; | |
701 | } | |
702 | ||
703 | /* Execute the given series of commands on the given device's | |
704 | * PHY, running functions as necessary | |
705 | */ | |
706 | static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd) | |
707 | { | |
708 | int i; | |
709 | uint result; | |
710 | ||
711 | for (i = 0; cmd->mii_reg != miim_end; i++) { | |
712 | if (cmd->mii_data == miim_read) { | |
713 | result = tse_mdio_read(priv, cmd->mii_reg); | |
714 | ||
715 | if (cmd->funct != NULL) | |
716 | (*(cmd->funct)) (result, priv); | |
717 | ||
718 | } else { | |
719 | if (cmd->funct != NULL) | |
720 | result = (*(cmd->funct)) (cmd->mii_reg, priv); | |
721 | else | |
722 | result = cmd->mii_data; | |
723 | ||
724 | tse_mdio_write(priv, cmd->mii_reg, result); | |
725 | ||
726 | } | |
727 | cmd++; | |
728 | } | |
729 | } | |
730 | ||
731 | /* Phy init code */ | |
732 | static int init_phy(struct eth_device *dev) | |
733 | { | |
734 | struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; | |
735 | struct phy_info *curphy; | |
736 | ||
737 | /* Get the cmd structure corresponding to the attached | |
738 | * PHY */ | |
739 | curphy = get_phy_info(dev); | |
740 | ||
741 | if (curphy == NULL) { | |
742 | priv->phyinfo = NULL; | |
743 | debug("%s: No PHY found\n", dev->name); | |
744 | ||
745 | return 0; | |
746 | } else | |
747 | debug("%s found\n", curphy->name); | |
748 | priv->phyinfo = curphy; | |
749 | ||
750 | phy_run_commands(priv, priv->phyinfo->config); | |
751 | ||
752 | return 1; | |
753 | } | |
754 | ||
6c7c4447 TC |
755 | static int tse_set_mac_address(struct eth_device *dev) |
756 | { | |
757 | struct altera_tse_priv *priv = dev->priv; | |
758 | volatile struct alt_tse_mac *mac_dev = priv->mac_dev; | |
759 | ||
760 | debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n", | |
761 | dev->enetaddr[5], dev->enetaddr[4], | |
762 | dev->enetaddr[3], dev->enetaddr[2], | |
763 | dev->enetaddr[1], dev->enetaddr[0]); | |
764 | mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 | | |
765 | (dev->enetaddr[2]) << 16 | | |
766 | (dev->enetaddr[1]) << 8 | (dev->enetaddr[0])); | |
767 | ||
768 | mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 | | |
769 | (dev->enetaddr[4])) & 0xFFFF); | |
770 | ||
771 | /* Set the MAC address */ | |
772 | mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0; | |
773 | mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1; | |
774 | ||
775 | /* Set the MAC address */ | |
776 | mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0; | |
777 | mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1; | |
778 | ||
779 | /* Set the MAC address */ | |
780 | mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0; | |
781 | mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1; | |
782 | ||
783 | /* Set the MAC address */ | |
784 | mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0; | |
785 | mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1; | |
786 | return 0; | |
787 | } | |
788 | ||
c960b13e TC |
789 | static int tse_eth_init(struct eth_device *dev, bd_t * bd) |
790 | { | |
791 | int dat; | |
792 | struct altera_tse_priv *priv = dev->priv; | |
793 | volatile struct alt_tse_mac *mac_dev = priv->mac_dev; | |
794 | volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; | |
795 | volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; | |
796 | volatile struct alt_sgdma_descriptor *rx_desc_cur = | |
797 | (volatile struct alt_sgdma_descriptor *)&rx_desc[0]; | |
798 | ||
799 | /* stop controller */ | |
800 | debug("Reseting TSE & SGDMAs\n"); | |
801 | tse_eth_reset(dev); | |
802 | ||
803 | /* start the phy */ | |
804 | debug("Configuring PHY\n"); | |
805 | phy_run_commands(priv, priv->phyinfo->startup); | |
806 | ||
807 | /* need to create sgdma */ | |
808 | debug("Configuring tx desc\n"); | |
809 | alt_sgdma_construct_descriptor_burst( | |
810 | (volatile struct alt_sgdma_descriptor *)&tx_desc[0], | |
811 | (volatile struct alt_sgdma_descriptor *)&tx_desc[1], | |
812 | (unsigned int *)NULL, /* read addr */ | |
813 | (unsigned int *)0, | |
814 | 0, /* length or EOP ,will change for each tx */ | |
815 | 0x1, /* gen eop */ | |
816 | 0x0, /* read fixed */ | |
817 | 0x1, /* write fixed or sop */ | |
818 | 0x0, /* read burst */ | |
819 | 0x0, /* write burst */ | |
820 | 0x0 /* channel */ | |
821 | ); | |
822 | debug("Configuring rx desc\n"); | |
823 | flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); | |
824 | alt_sgdma_construct_descriptor_burst( | |
825 | (volatile struct alt_sgdma_descriptor *)&rx_desc[0], | |
826 | (volatile struct alt_sgdma_descriptor *)&rx_desc[1], | |
827 | (unsigned int)0x0, /* read addr */ | |
828 | (unsigned int *)NetRxPackets[0], | |
829 | 0x0, /* length or EOP */ | |
830 | 0x0, /* gen eop */ | |
831 | 0x0, /* read fixed */ | |
832 | 0x0, /* write fixed or sop */ | |
833 | 0x0, /* read burst */ | |
834 | 0x0, /* write burst */ | |
835 | 0x0 /* channel */ | |
836 | ); | |
837 | /* start rx async transfer */ | |
838 | debug("Starting rx sgdma\n"); | |
839 | alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur); | |
840 | ||
841 | /* start TSE */ | |
842 | debug("Configuring TSE Mac\n"); | |
843 | /* Initialize MAC registers */ | |
844 | mac_dev->max_frame_length = PKTSIZE_ALIGN; | |
845 | mac_dev->rx_almost_empty_threshold = 8; | |
846 | mac_dev->rx_almost_full_threshold = 8; | |
847 | mac_dev->tx_almost_empty_threshold = 8; | |
848 | mac_dev->tx_almost_full_threshold = 3; | |
849 | mac_dev->tx_sel_empty_threshold = | |
850 | CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; | |
851 | mac_dev->tx_sel_full_threshold = 0; | |
852 | mac_dev->rx_sel_empty_threshold = | |
853 | CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; | |
854 | mac_dev->rx_sel_full_threshold = 0; | |
855 | ||
856 | /* NO Shift */ | |
857 | mac_dev->rx_cmd_stat.bits.rx_shift16 = 0; | |
858 | mac_dev->tx_cmd_stat.bits.tx_shift16 = 0; | |
859 | ||
860 | /* enable MAC */ | |
861 | dat = 0; | |
862 | dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; | |
863 | ||
864 | mac_dev->command_config.image = dat; | |
865 | ||
c960b13e TC |
866 | /* configure the TSE core */ |
867 | /* -- output clocks, */ | |
868 | /* -- and later config stuff for SGMII */ | |
869 | if (priv->link) { | |
870 | debug("Adjusting TSE to link speed\n"); | |
871 | tse_adjust_link(priv); | |
872 | } | |
873 | ||
874 | return priv->link ? 0 : -1; | |
875 | } | |
876 | ||
877 | /* TSE init code */ | |
878 | int altera_tse_initialize(u8 dev_num, int mac_base, | |
879 | int sgdma_rx_base, int sgdma_tx_base) | |
880 | { | |
881 | struct altera_tse_priv *priv; | |
882 | struct eth_device *dev; | |
883 | struct alt_sgdma_descriptor *rx_desc; | |
884 | struct alt_sgdma_descriptor *tx_desc; | |
885 | unsigned long dma_handle; | |
886 | ||
887 | dev = (struct eth_device *)malloc(sizeof *dev); | |
888 | ||
889 | if (NULL == dev) | |
890 | return 0; | |
891 | ||
892 | memset(dev, 0, sizeof *dev); | |
893 | ||
894 | priv = malloc(sizeof(*priv)); | |
895 | ||
896 | if (!priv) { | |
897 | free(dev); | |
898 | return 0; | |
899 | } | |
900 | tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), | |
901 | &dma_handle); | |
902 | rx_desc = tx_desc + 2; | |
903 | debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc); | |
904 | debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc); | |
905 | ||
906 | if (!tx_desc) { | |
907 | free(priv); | |
908 | free(dev); | |
909 | return 0; | |
910 | } | |
911 | memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); | |
912 | memset(tx_desc, 0, (sizeof *tx_desc) * 2); | |
913 | ||
914 | /* initialize tse priv */ | |
915 | priv->mac_dev = (volatile struct alt_tse_mac *)mac_base; | |
916 | priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base; | |
917 | priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base; | |
918 | priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR; | |
919 | priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS; | |
920 | priv->rx_desc = rx_desc; | |
921 | priv->tx_desc = tx_desc; | |
922 | ||
923 | /* init eth structure */ | |
924 | dev->priv = priv; | |
925 | dev->init = tse_eth_init; | |
926 | dev->halt = tse_eth_halt; | |
927 | dev->send = tse_eth_send; | |
928 | dev->recv = tse_eth_rx; | |
6c7c4447 | 929 | dev->write_hwaddr = tse_set_mac_address; |
c960b13e TC |
930 | sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num); |
931 | ||
932 | eth_register(dev); | |
933 | ||
934 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) | |
935 | miiphy_register(dev->name, altera_tse_miiphy_read, | |
936 | altera_tse_miiphy_write); | |
937 | #endif | |
938 | ||
939 | init_phy(dev); | |
940 | ||
941 | return 1; | |
942 | } |