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Commit | Line | Data |
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c960b13e TC |
1 | /* |
2 | * Altera 10/100/1000 triple speed ethernet mac driver | |
3 | * | |
4 | * Copyright (C) 2008 Altera Corporation. | |
5 | * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
c960b13e | 11 | #include <common.h> |
96fa1e43 TC |
12 | #include <dm.h> |
13 | #include <errno.h> | |
14 | #include <fdt_support.h> | |
15 | #include <memalign.h> | |
16 | #include <miiphy.h> | |
c960b13e | 17 | #include <net.h> |
c960b13e TC |
18 | #include <asm/cache.h> |
19 | #include <asm/dma-mapping.h> | |
96fa1e43 | 20 | #include <asm/io.h> |
c960b13e TC |
21 | #include "altera_tse.h" |
22 | ||
96fa1e43 | 23 | DECLARE_GLOBAL_DATA_PTR; |
c960b13e | 24 | |
96fa1e43 TC |
25 | static inline void alt_sgdma_construct_descriptor( |
26 | struct alt_sgdma_descriptor *desc, | |
27 | struct alt_sgdma_descriptor *next, | |
28 | void *read_addr, | |
29 | void *write_addr, | |
2cd0a52e | 30 | u16 length_or_eop, |
c960b13e TC |
31 | int generate_eop, |
32 | int read_fixed, | |
96fa1e43 | 33 | int write_fixed_or_sop) |
c960b13e | 34 | { |
2cd0a52e | 35 | u8 val; |
96fa1e43 | 36 | |
c960b13e TC |
37 | /* |
38 | * Mark the "next" descriptor as "not" owned by hardware. This prevents | |
96fa1e43 | 39 | * The SGDMA controller from continuing to process the chain. |
c960b13e | 40 | */ |
96fa1e43 TC |
41 | next->descriptor_control = next->descriptor_control & |
42 | ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; | |
c960b13e | 43 | |
96fa1e43 TC |
44 | memset(desc, 0, sizeof(struct alt_sgdma_descriptor)); |
45 | desc->source = virt_to_phys(read_addr); | |
46 | desc->destination = virt_to_phys(write_addr); | |
47 | desc->next = virt_to_phys(next); | |
48 | desc->bytes_to_transfer = length_or_eop; | |
c960b13e TC |
49 | |
50 | /* | |
51 | * Set the descriptor control block as follows: | |
52 | * - Set "owned by hardware" bit | |
53 | * - Optionally set "generate EOP" bit | |
54 | * - Optionally set the "read from fixed address" bit | |
55 | * - Optionally set the "write to fixed address bit (which serves | |
56 | * serves as a "generate SOP" control bit in memory-to-stream mode). | |
57 | * - Set the 4-bit atlantic channel, if specified | |
58 | * | |
59 | * Note this step is performed after all other descriptor information | |
60 | * has been filled out so that, if the controller already happens to be | |
61 | * pointing at this descriptor, it will not run (via the "owned by | |
62 | * hardware" bit) until all other descriptor has been set up. | |
63 | */ | |
96fa1e43 TC |
64 | val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; |
65 | if (generate_eop) | |
66 | val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK; | |
67 | if (read_fixed) | |
68 | val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK; | |
69 | if (write_fixed_or_sop) | |
70 | val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK; | |
71 | desc->descriptor_control = val; | |
c960b13e TC |
72 | } |
73 | ||
96fa1e43 | 74 | static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs) |
c960b13e | 75 | { |
96fa1e43 TC |
76 | int status; |
77 | ulong ctime; | |
c960b13e | 78 | |
96fa1e43 TC |
79 | /* Wait for the descriptor (chain) to complete */ |
80 | ctime = get_timer(0); | |
81 | while (1) { | |
82 | status = readl(®s->status); | |
83 | if (!(status & ALT_SGDMA_STATUS_BUSY_MSK)) | |
84 | break; | |
85 | if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { | |
86 | status = -ETIMEDOUT; | |
87 | debug("sgdma timeout\n"); | |
c960b13e | 88 | break; |
96fa1e43 | 89 | } |
c960b13e TC |
90 | } |
91 | ||
c960b13e | 92 | /* Clear Run */ |
96fa1e43 TC |
93 | writel(0, ®s->control); |
94 | /* Clear status */ | |
95 | writel(0xff, ®s->status); | |
c960b13e | 96 | |
96fa1e43 | 97 | return status; |
c960b13e TC |
98 | } |
99 | ||
96fa1e43 TC |
100 | static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs, |
101 | struct alt_sgdma_descriptor *desc) | |
c960b13e | 102 | { |
2cd0a52e | 103 | u32 val; |
c960b13e TC |
104 | |
105 | /* Point the controller at the descriptor */ | |
96fa1e43 | 106 | writel(virt_to_phys(desc), ®s->next_descriptor_pointer); |
c960b13e TC |
107 | |
108 | /* | |
109 | * Set up SGDMA controller to: | |
110 | * - Disable interrupt generation | |
111 | * - Run once a valid descriptor is written to controller | |
112 | * - Stop on an error with any particular descriptor | |
113 | */ | |
96fa1e43 TC |
114 | val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK; |
115 | writel(val, ®s->control); | |
c960b13e | 116 | |
c960b13e TC |
117 | return 0; |
118 | } | |
119 | ||
96fa1e43 TC |
120 | static void tse_adjust_link(struct altera_tse_priv *priv, |
121 | struct phy_device *phydev) | |
c960b13e | 122 | { |
96fa1e43 | 123 | struct alt_tse_mac *mac_dev = priv->mac_dev; |
2cd0a52e | 124 | u32 refvar; |
c960b13e | 125 | |
96fa1e43 TC |
126 | if (!phydev->link) { |
127 | debug("%s: No link.\n", phydev->dev->name); | |
128 | return; | |
129 | } | |
130 | ||
131 | refvar = readl(&mac_dev->command_config); | |
c960b13e | 132 | |
96fa1e43 | 133 | if (phydev->duplex) |
c960b13e TC |
134 | refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; |
135 | else | |
136 | refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; | |
137 | ||
96fa1e43 | 138 | switch (phydev->speed) { |
c960b13e TC |
139 | case 1000: |
140 | refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; | |
141 | refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; | |
142 | break; | |
143 | case 100: | |
144 | refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; | |
145 | refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; | |
146 | break; | |
147 | case 10: | |
148 | refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; | |
149 | refvar |= ALTERA_TSE_CMD_ENA_10_MSK; | |
150 | break; | |
151 | } | |
96fa1e43 | 152 | writel(refvar, &mac_dev->command_config); |
c960b13e TC |
153 | } |
154 | ||
38fa4aca | 155 | static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length) |
c960b13e | 156 | { |
96fa1e43 TC |
157 | struct altera_tse_priv *priv = dev_get_priv(dev); |
158 | struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; | |
96fa1e43 | 159 | |
96fa1e43 TC |
160 | alt_sgdma_construct_descriptor( |
161 | tx_desc, | |
162 | tx_desc + 1, | |
163 | packet, /* read addr */ | |
164 | NULL, /* write addr */ | |
c960b13e | 165 | length, /* length or EOP ,will change for each tx */ |
96fa1e43 TC |
166 | 1, /* gen eop */ |
167 | 0, /* read fixed */ | |
168 | 1 /* write fixed or sop */ | |
c960b13e | 169 | ); |
c960b13e TC |
170 | |
171 | /* send the packet */ | |
96fa1e43 TC |
172 | alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc); |
173 | alt_sgdma_wait_transfer(priv->sgdma_tx); | |
174 | debug("sent %d bytes\n", tx_desc->actual_bytes_transferred); | |
175 | ||
176 | return tx_desc->actual_bytes_transferred; | |
c960b13e TC |
177 | } |
178 | ||
38fa4aca TC |
179 | static int altera_tse_recv_sgdma(struct udevice *dev, int flags, |
180 | uchar **packetp) | |
c960b13e | 181 | { |
96fa1e43 TC |
182 | struct altera_tse_priv *priv = dev_get_priv(dev); |
183 | struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; | |
184 | int packet_length; | |
c960b13e | 185 | |
96fa1e43 | 186 | if (rx_desc->descriptor_status & |
c960b13e | 187 | ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { |
577662f0 | 188 | alt_sgdma_wait_transfer(priv->sgdma_rx); |
c960b13e | 189 | packet_length = rx_desc->actual_bytes_transferred; |
96fa1e43 TC |
190 | debug("recv %d bytes\n", packet_length); |
191 | *packetp = priv->rx_buf; | |
70d52f9a JF |
192 | |
193 | return packet_length; | |
c960b13e TC |
194 | } |
195 | ||
96fa1e43 | 196 | return -EAGAIN; |
c960b13e TC |
197 | } |
198 | ||
38fa4aca TC |
199 | static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet, |
200 | int length) | |
c960b13e | 201 | { |
96fa1e43 TC |
202 | struct altera_tse_priv *priv = dev_get_priv(dev); |
203 | struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; | |
96fa1e43 | 204 | |
96fa1e43 TC |
205 | alt_sgdma_construct_descriptor( |
206 | rx_desc, | |
207 | rx_desc + 1, | |
208 | NULL, /* read addr */ | |
209 | priv->rx_buf, /* write addr */ | |
210 | 0, /* length or EOP */ | |
211 | 0, /* gen eop */ | |
212 | 0, /* read fixed */ | |
213 | 0 /* write fixed or sop */ | |
214 | ); | |
215 | ||
216 | /* setup the sgdma */ | |
217 | alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc); | |
218 | debug("recv setup\n"); | |
219 | ||
220 | return 0; | |
c960b13e TC |
221 | } |
222 | ||
acd71c32 TC |
223 | static void altera_tse_stop_mac(struct altera_tse_priv *priv) |
224 | { | |
225 | struct alt_tse_mac *mac_dev = priv->mac_dev; | |
226 | u32 status; | |
227 | ulong ctime; | |
228 | ||
229 | /* reset the mac */ | |
230 | writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config); | |
231 | ctime = get_timer(0); | |
232 | while (1) { | |
233 | status = readl(&mac_dev->command_config); | |
234 | if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK)) | |
235 | break; | |
236 | if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { | |
237 | debug("Reset mac timeout\n"); | |
238 | break; | |
239 | } | |
240 | } | |
241 | } | |
242 | ||
38fa4aca | 243 | static void altera_tse_stop_sgdma(struct udevice *dev) |
c960b13e | 244 | { |
96fa1e43 | 245 | struct altera_tse_priv *priv = dev_get_priv(dev); |
96fa1e43 TC |
246 | struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; |
247 | struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; | |
248 | struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; | |
96fa1e43 | 249 | int ret; |
c960b13e TC |
250 | |
251 | /* clear rx desc & wait for sgdma to complete */ | |
252 | rx_desc->descriptor_control = 0; | |
96fa1e43 TC |
253 | writel(0, &rx_sgdma->control); |
254 | ret = alt_sgdma_wait_transfer(rx_sgdma); | |
255 | if (ret == -ETIMEDOUT) | |
256 | writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, | |
257 | &rx_sgdma->control); | |
258 | ||
259 | writel(0, &tx_sgdma->control); | |
260 | ret = alt_sgdma_wait_transfer(tx_sgdma); | |
261 | if (ret == -ETIMEDOUT) | |
262 | writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, | |
263 | &tx_sgdma->control); | |
c960b13e TC |
264 | } |
265 | ||
e3e87260 TC |
266 | static void msgdma_reset(struct msgdma_csr *csr) |
267 | { | |
268 | u32 status; | |
269 | ulong ctime; | |
270 | ||
271 | /* Reset mSGDMA */ | |
272 | writel(MSGDMA_CSR_STAT_MASK, &csr->status); | |
273 | writel(MSGDMA_CSR_CTL_RESET, &csr->control); | |
274 | ctime = get_timer(0); | |
275 | while (1) { | |
276 | status = readl(&csr->status); | |
277 | if (!(status & MSGDMA_CSR_STAT_RESETTING)) | |
278 | break; | |
279 | if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { | |
280 | debug("Reset msgdma timeout\n"); | |
281 | break; | |
282 | } | |
283 | } | |
284 | /* Clear status */ | |
285 | writel(MSGDMA_CSR_STAT_MASK, &csr->status); | |
286 | } | |
287 | ||
288 | static u32 msgdma_wait(struct msgdma_csr *csr) | |
289 | { | |
290 | u32 status; | |
291 | ulong ctime; | |
292 | ||
293 | /* Wait for the descriptor to complete */ | |
294 | ctime = get_timer(0); | |
295 | while (1) { | |
296 | status = readl(&csr->status); | |
297 | if (!(status & MSGDMA_CSR_STAT_BUSY)) | |
298 | break; | |
299 | if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { | |
300 | debug("sgdma timeout\n"); | |
301 | break; | |
302 | } | |
303 | } | |
304 | /* Clear status */ | |
305 | writel(MSGDMA_CSR_STAT_MASK, &csr->status); | |
306 | ||
307 | return status; | |
308 | } | |
309 | ||
310 | static int altera_tse_send_msgdma(struct udevice *dev, void *packet, | |
311 | int length) | |
312 | { | |
313 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
314 | struct msgdma_extended_desc *desc = priv->tx_desc; | |
315 | u32 tx_buf = virt_to_phys(packet); | |
316 | u32 status; | |
317 | ||
318 | writel(tx_buf, &desc->read_addr_lo); | |
319 | writel(0, &desc->read_addr_hi); | |
320 | writel(0, &desc->write_addr_lo); | |
321 | writel(0, &desc->write_addr_hi); | |
322 | writel(length, &desc->len); | |
323 | writel(0, &desc->burst_seq_num); | |
324 | writel(MSGDMA_DESC_TX_STRIDE, &desc->stride); | |
325 | writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control); | |
326 | status = msgdma_wait(priv->sgdma_tx); | |
327 | debug("sent %d bytes, status %08x\n", length, status); | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | static int altera_tse_recv_msgdma(struct udevice *dev, int flags, | |
333 | uchar **packetp) | |
334 | { | |
335 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
336 | struct msgdma_csr *csr = priv->sgdma_rx; | |
337 | struct msgdma_response *resp = priv->rx_resp; | |
338 | u32 level, length, status; | |
339 | ||
340 | level = readl(&csr->resp_fill_level); | |
341 | if (level & 0xffff) { | |
342 | length = readl(&resp->bytes_transferred); | |
343 | status = readl(&resp->status); | |
344 | debug("recv %d bytes, status %08x\n", length, status); | |
345 | *packetp = priv->rx_buf; | |
346 | ||
347 | return length; | |
348 | } | |
349 | ||
350 | return -EAGAIN; | |
351 | } | |
352 | ||
353 | static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet, | |
354 | int length) | |
355 | { | |
356 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
357 | struct msgdma_extended_desc *desc = priv->rx_desc; | |
358 | u32 rx_buf = virt_to_phys(priv->rx_buf); | |
359 | ||
360 | writel(0, &desc->read_addr_lo); | |
361 | writel(0, &desc->read_addr_hi); | |
362 | writel(rx_buf, &desc->write_addr_lo); | |
363 | writel(0, &desc->write_addr_hi); | |
364 | writel(PKTSIZE_ALIGN, &desc->len); | |
365 | writel(0, &desc->burst_seq_num); | |
366 | writel(MSGDMA_DESC_RX_STRIDE, &desc->stride); | |
367 | writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control); | |
368 | debug("recv setup\n"); | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static void altera_tse_stop_msgdma(struct udevice *dev) | |
374 | { | |
375 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
376 | ||
377 | msgdma_reset(priv->sgdma_rx); | |
378 | msgdma_reset(priv->sgdma_tx); | |
379 | } | |
380 | ||
96fa1e43 | 381 | static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
c960b13e | 382 | { |
96fa1e43 TC |
383 | struct altera_tse_priv *priv = bus->priv; |
384 | struct alt_tse_mac *mac_dev = priv->mac_dev; | |
2cd0a52e | 385 | u32 value; |
c960b13e TC |
386 | |
387 | /* set mdio address */ | |
96fa1e43 | 388 | writel(addr, &mac_dev->mdio_phy1_addr); |
c960b13e | 389 | /* get the data */ |
96fa1e43 | 390 | value = readl(&mac_dev->mdio_phy1[reg]); |
c960b13e | 391 | |
96fa1e43 | 392 | return value & 0xffff; |
c960b13e TC |
393 | } |
394 | ||
96fa1e43 TC |
395 | static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
396 | u16 val) | |
c960b13e | 397 | { |
96fa1e43 TC |
398 | struct altera_tse_priv *priv = bus->priv; |
399 | struct alt_tse_mac *mac_dev = priv->mac_dev; | |
c960b13e TC |
400 | |
401 | /* set mdio address */ | |
96fa1e43 TC |
402 | writel(addr, &mac_dev->mdio_phy1_addr); |
403 | /* set the data */ | |
404 | writel(val, &mac_dev->mdio_phy1[reg]); | |
c960b13e TC |
405 | |
406 | return 0; | |
407 | } | |
408 | ||
96fa1e43 | 409 | static int tse_mdio_init(const char *name, struct altera_tse_priv *priv) |
c960b13e | 410 | { |
96fa1e43 | 411 | struct mii_dev *bus = mdio_alloc(); |
c960b13e | 412 | |
96fa1e43 TC |
413 | if (!bus) { |
414 | printf("Failed to allocate MDIO bus\n"); | |
415 | return -ENOMEM; | |
c960b13e TC |
416 | } |
417 | ||
96fa1e43 TC |
418 | bus->read = tse_mdio_read; |
419 | bus->write = tse_mdio_write; | |
192bc694 | 420 | snprintf(bus->name, sizeof(bus->name), "%s", name); |
c960b13e | 421 | |
96fa1e43 | 422 | bus->priv = (void *)priv; |
15eb1069 | 423 | |
96fa1e43 | 424 | return mdio_register(bus); |
c960b13e TC |
425 | } |
426 | ||
96fa1e43 | 427 | static int tse_phy_init(struct altera_tse_priv *priv, void *dev) |
c960b13e | 428 | { |
96fa1e43 TC |
429 | struct phy_device *phydev; |
430 | unsigned int mask = 0xffffffff; | |
c960b13e | 431 | |
96fa1e43 TC |
432 | if (priv->phyaddr) |
433 | mask = 1 << priv->phyaddr; | |
c960b13e | 434 | |
96fa1e43 TC |
435 | phydev = phy_find_by_mask(priv->bus, mask, priv->interface); |
436 | if (!phydev) | |
437 | return -ENODEV; | |
c960b13e | 438 | |
96fa1e43 | 439 | phy_connect_dev(phydev, dev); |
c960b13e | 440 | |
96fa1e43 TC |
441 | phydev->supported &= PHY_GBIT_FEATURES; |
442 | phydev->advertising = phydev->supported; | |
c960b13e | 443 | |
96fa1e43 TC |
444 | priv->phydev = phydev; |
445 | phy_config(phydev); | |
c960b13e | 446 | |
96fa1e43 | 447 | return 0; |
c960b13e TC |
448 | } |
449 | ||
96fa1e43 | 450 | static int altera_tse_write_hwaddr(struct udevice *dev) |
c960b13e | 451 | { |
96fa1e43 TC |
452 | struct altera_tse_priv *priv = dev_get_priv(dev); |
453 | struct alt_tse_mac *mac_dev = priv->mac_dev; | |
454 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
455 | u8 *hwaddr = pdata->enetaddr; | |
2cd0a52e | 456 | u32 mac_lo, mac_hi; |
96fa1e43 TC |
457 | |
458 | mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) | | |
459 | (hwaddr[1] << 8) | hwaddr[0]; | |
460 | mac_hi = (hwaddr[5] << 8) | hwaddr[4]; | |
461 | debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo); | |
462 | ||
463 | writel(mac_lo, &mac_dev->mac_addr_0); | |
464 | writel(mac_hi, &mac_dev->mac_addr_1); | |
465 | writel(mac_lo, &mac_dev->supp_mac_addr_0_0); | |
466 | writel(mac_hi, &mac_dev->supp_mac_addr_0_1); | |
467 | writel(mac_lo, &mac_dev->supp_mac_addr_1_0); | |
468 | writel(mac_hi, &mac_dev->supp_mac_addr_1_1); | |
469 | writel(mac_lo, &mac_dev->supp_mac_addr_2_0); | |
470 | writel(mac_hi, &mac_dev->supp_mac_addr_2_1); | |
471 | writel(mac_lo, &mac_dev->supp_mac_addr_3_0); | |
472 | writel(mac_hi, &mac_dev->supp_mac_addr_3_1); | |
c960b13e | 473 | |
6c7c4447 TC |
474 | return 0; |
475 | } | |
476 | ||
38fa4aca TC |
477 | static int altera_tse_send(struct udevice *dev, void *packet, int length) |
478 | { | |
479 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
480 | unsigned long tx_buf = (unsigned long)packet; | |
481 | ||
482 | flush_dcache_range(tx_buf, tx_buf + length); | |
483 | ||
484 | return priv->ops->send(dev, packet, length); | |
485 | } | |
486 | ||
487 | static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) | |
488 | { | |
489 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
490 | ||
491 | return priv->ops->recv(dev, flags, packetp); | |
492 | } | |
493 | ||
494 | static int altera_tse_free_pkt(struct udevice *dev, uchar *packet, | |
495 | int length) | |
496 | { | |
497 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
498 | unsigned long rx_buf = (unsigned long)priv->rx_buf; | |
499 | ||
500 | invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN); | |
501 | ||
502 | return priv->ops->free_pkt(dev, packet, length); | |
503 | } | |
504 | ||
505 | static void altera_tse_stop(struct udevice *dev) | |
506 | { | |
507 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
508 | ||
509 | priv->ops->stop(dev); | |
510 | altera_tse_stop_mac(priv); | |
511 | } | |
512 | ||
96fa1e43 | 513 | static int altera_tse_start(struct udevice *dev) |
c960b13e | 514 | { |
96fa1e43 TC |
515 | struct altera_tse_priv *priv = dev_get_priv(dev); |
516 | struct alt_tse_mac *mac_dev = priv->mac_dev; | |
2cd0a52e | 517 | u32 val; |
96fa1e43 | 518 | int ret; |
c960b13e TC |
519 | |
520 | /* need to create sgdma */ | |
c960b13e | 521 | debug("Configuring rx desc\n"); |
96fa1e43 | 522 | altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN); |
c960b13e TC |
523 | /* start TSE */ |
524 | debug("Configuring TSE Mac\n"); | |
525 | /* Initialize MAC registers */ | |
96fa1e43 TC |
526 | writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length); |
527 | writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold); | |
528 | writel(0, &mac_dev->rx_sel_full_threshold); | |
529 | writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold); | |
530 | writel(0, &mac_dev->tx_sel_full_threshold); | |
531 | writel(8, &mac_dev->rx_almost_empty_threshold); | |
532 | writel(8, &mac_dev->rx_almost_full_threshold); | |
533 | writel(8, &mac_dev->tx_almost_empty_threshold); | |
534 | writel(3, &mac_dev->tx_almost_full_threshold); | |
c960b13e TC |
535 | |
536 | /* NO Shift */ | |
96fa1e43 TC |
537 | writel(0, &mac_dev->rx_cmd_stat); |
538 | writel(0, &mac_dev->tx_cmd_stat); | |
c960b13e TC |
539 | |
540 | /* enable MAC */ | |
96fa1e43 TC |
541 | val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; |
542 | writel(val, &mac_dev->command_config); | |
543 | ||
544 | /* Start up the PHY */ | |
545 | ret = phy_startup(priv->phydev); | |
546 | if (ret) { | |
547 | debug("Could not initialize PHY %s\n", | |
548 | priv->phydev->dev->name); | |
549 | return ret; | |
550 | } | |
c960b13e | 551 | |
96fa1e43 | 552 | tse_adjust_link(priv, priv->phydev); |
c960b13e | 553 | |
96fa1e43 TC |
554 | if (!priv->phydev->link) |
555 | return -EIO; | |
c960b13e | 556 | |
96fa1e43 | 557 | return 0; |
c960b13e TC |
558 | } |
559 | ||
38fa4aca TC |
560 | static const struct tse_ops tse_sgdma_ops = { |
561 | .send = altera_tse_send_sgdma, | |
562 | .recv = altera_tse_recv_sgdma, | |
563 | .free_pkt = altera_tse_free_pkt_sgdma, | |
564 | .stop = altera_tse_stop_sgdma, | |
565 | }; | |
566 | ||
e3e87260 TC |
567 | static const struct tse_ops tse_msgdma_ops = { |
568 | .send = altera_tse_send_msgdma, | |
569 | .recv = altera_tse_recv_msgdma, | |
570 | .free_pkt = altera_tse_free_pkt_msgdma, | |
571 | .stop = altera_tse_stop_msgdma, | |
572 | }; | |
573 | ||
96fa1e43 | 574 | static int altera_tse_probe(struct udevice *dev) |
c960b13e | 575 | { |
96fa1e43 TC |
576 | struct eth_pdata *pdata = dev_get_platdata(dev); |
577 | struct altera_tse_priv *priv = dev_get_priv(dev); | |
75199d6f | 578 | void *blob = (void *)gd->fdt_blob; |
96fa1e43 TC |
579 | int node = dev->of_offset; |
580 | const char *list, *end; | |
581 | const fdt32_t *cell; | |
582 | void *base, *desc_mem = NULL; | |
583 | unsigned long addr, size; | |
75199d6f | 584 | int parent, addrc, sizec; |
96fa1e43 TC |
585 | int len, idx; |
586 | int ret; | |
c960b13e | 587 | |
38fa4aca TC |
588 | priv->dma_type = dev_get_driver_data(dev); |
589 | if (priv->dma_type == ALT_SGDMA) | |
590 | priv->ops = &tse_sgdma_ops; | |
e3e87260 TC |
591 | else |
592 | priv->ops = &tse_msgdma_ops; | |
96fa1e43 | 593 | /* |
75199d6f TC |
594 | * decode regs. there are multiple reg tuples, and they need to |
595 | * match with reg-names. | |
96fa1e43 | 596 | */ |
75199d6f TC |
597 | parent = fdt_parent_offset(blob, node); |
598 | of_bus_default_count_cells(blob, parent, &addrc, &sizec); | |
96fa1e43 TC |
599 | list = fdt_getprop(blob, node, "reg-names", &len); |
600 | if (!list) | |
601 | return -ENOENT; | |
602 | end = list + len; | |
603 | cell = fdt_getprop(blob, node, "reg", &len); | |
604 | if (!cell) | |
605 | return -ENOENT; | |
606 | idx = 0; | |
607 | while (list < end) { | |
608 | addr = fdt_translate_address((void *)blob, | |
609 | node, cell + idx); | |
75199d6f | 610 | size = fdt_addr_to_cpu(cell[idx + addrc]); |
e2b259f7 | 611 | base = map_physmem(addr, size, MAP_NOCACHE); |
96fa1e43 TC |
612 | len = strlen(list); |
613 | if (strcmp(list, "control_port") == 0) | |
614 | priv->mac_dev = base; | |
615 | else if (strcmp(list, "rx_csr") == 0) | |
616 | priv->sgdma_rx = base; | |
e3e87260 TC |
617 | else if (strcmp(list, "rx_desc") == 0) |
618 | priv->rx_desc = base; | |
619 | else if (strcmp(list, "rx_resp") == 0) | |
620 | priv->rx_resp = base; | |
96fa1e43 TC |
621 | else if (strcmp(list, "tx_csr") == 0) |
622 | priv->sgdma_tx = base; | |
e3e87260 TC |
623 | else if (strcmp(list, "tx_desc") == 0) |
624 | priv->tx_desc = base; | |
96fa1e43 TC |
625 | else if (strcmp(list, "s1") == 0) |
626 | desc_mem = base; | |
75199d6f | 627 | idx += addrc + sizec; |
96fa1e43 TC |
628 | list += (len + 1); |
629 | } | |
630 | /* decode fifo depth */ | |
631 | priv->rx_fifo_depth = fdtdec_get_int(blob, node, | |
632 | "rx-fifo-depth", 0); | |
633 | priv->tx_fifo_depth = fdtdec_get_int(blob, node, | |
634 | "tx-fifo-depth", 0); | |
635 | /* decode phy */ | |
636 | addr = fdtdec_get_int(blob, node, | |
637 | "phy-handle", 0); | |
638 | addr = fdt_node_offset_by_phandle(blob, addr); | |
639 | priv->phyaddr = fdtdec_get_int(blob, addr, | |
640 | "reg", 0); | |
641 | /* init desc */ | |
38fa4aca TC |
642 | if (priv->dma_type == ALT_SGDMA) { |
643 | len = sizeof(struct alt_sgdma_descriptor) * 4; | |
644 | if (!desc_mem) { | |
645 | desc_mem = dma_alloc_coherent(len, &addr); | |
646 | if (!desc_mem) | |
647 | return -ENOMEM; | |
648 | } | |
649 | memset(desc_mem, 0, len); | |
650 | priv->tx_desc = desc_mem; | |
651 | priv->rx_desc = priv->tx_desc + | |
652 | 2 * sizeof(struct alt_sgdma_descriptor); | |
96fa1e43 | 653 | } |
96fa1e43 TC |
654 | /* allocate recv packet buffer */ |
655 | priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN); | |
656 | if (!priv->rx_buf) | |
657 | return -ENOMEM; | |
c960b13e | 658 | |
96fa1e43 TC |
659 | /* stop controller */ |
660 | debug("Reset TSE & SGDMAs\n"); | |
661 | altera_tse_stop(dev); | |
c960b13e | 662 | |
96fa1e43 TC |
663 | /* start the phy */ |
664 | priv->interface = pdata->phy_interface; | |
665 | tse_mdio_init(dev->name, priv); | |
666 | priv->bus = miiphy_get_dev_by_name(dev->name); | |
c960b13e | 667 | |
96fa1e43 | 668 | ret = tse_phy_init(priv, dev); |
b962ac79 | 669 | |
96fa1e43 TC |
670 | return ret; |
671 | } | |
c960b13e | 672 | |
96fa1e43 TC |
673 | static int altera_tse_ofdata_to_platdata(struct udevice *dev) |
674 | { | |
675 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
676 | const char *phy_mode; | |
677 | ||
678 | pdata->phy_interface = -1; | |
679 | phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); | |
680 | if (phy_mode) | |
681 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
682 | if (pdata->phy_interface == -1) { | |
683 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
684 | return -EINVAL; | |
c960b13e | 685 | } |
96fa1e43 TC |
686 | |
687 | return 0; | |
c960b13e | 688 | } |
96fa1e43 TC |
689 | |
690 | static const struct eth_ops altera_tse_ops = { | |
691 | .start = altera_tse_start, | |
692 | .send = altera_tse_send, | |
693 | .recv = altera_tse_recv, | |
694 | .free_pkt = altera_tse_free_pkt, | |
695 | .stop = altera_tse_stop, | |
696 | .write_hwaddr = altera_tse_write_hwaddr, | |
697 | }; | |
698 | ||
699 | static const struct udevice_id altera_tse_ids[] = { | |
e3e87260 | 700 | { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA }, |
38fa4aca TC |
701 | { .compatible = "altr,tse-1.0", .data = ALT_SGDMA }, |
702 | {} | |
96fa1e43 TC |
703 | }; |
704 | ||
705 | U_BOOT_DRIVER(altera_tse) = { | |
706 | .name = "altera_tse", | |
707 | .id = UCLASS_ETH, | |
708 | .of_match = altera_tse_ids, | |
709 | .ops = &altera_tse_ops, | |
710 | .ofdata_to_platdata = altera_tse_ofdata_to_platdata, | |
711 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
712 | .priv_auto_alloc_size = sizeof(struct altera_tse_priv), | |
713 | .probe = altera_tse_probe, | |
714 | }; |