[people/ms/u-boot.git] / drivers / net / armada100_fec.c

/*
 * (C) Copyright 2011
 * eInfochips Ltd. <www.einfochips.com>
 * Written-by: Ajay Bhargav <contact@8051projects.net>
 *
 * (C) Copyright 2010
 * Marvell Semiconductor <www.marvell.com>
 * Contributor: Mahavir Jain <mjain@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <net.h>
#include <malloc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/types.h>
#include <asm/byteorder.h>
#include <linux/err.h>
#include <linux/mii.h>
#include <asm/io.h>
#include <asm/arch/armada100.h>
#include "armada100_fec.h"

#define  PHY_ADR_REQ     0xFF	/* Magic number to read/write PHY address */

#ifdef DEBUG
static int eth_dump_regs(struct eth_device *dev)
{
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct armdfec_reg *regs = darmdfec->regs;
	unsigned int i = 0;

	printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr));
	printf("offset: smi, value: 0x%x\n", readl(&regs->smi));
	for (i = 0x400; i <= 0x4e4; i += 4)
		printf("offset: 0x%x, value: 0x%x\n",
			i, readl(ARMD1_FEC_BASE + i));
	return 0;
}
#endif

static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
{
	u32 timeout = PHY_WAIT_ITERATIONS;
	u32 reg_val;

	while (--timeout) {
		reg_val = readl(reg);
		if (cond && (reg_val & flag))
			break;
		else if (!cond && !(reg_val & flag))
			break;
		udelay(PHY_WAIT_MICRO_SECONDS);
	}
	return !timeout;
}

static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
			int phy_reg)
{
	u16 value = 0;
	struct eth_device *dev = eth_get_dev_by_name(bus->name);
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct armdfec_reg *regs = darmdfec->regs;
	u32 val;

	if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
		val = readl(&regs->phyadr);
		value = val & 0x1f;
		return value;
	}

	/* check parameters */
	if (phy_addr > PHY_MASK) {
		printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
				__func__, phy_addr);
		return -EINVAL;
	}
	if (phy_reg > PHY_MASK) {
		printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
				__func__, phy_reg);
		return -EINVAL;
	}

	/* wait for the SMI register to become available */
	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
		printf("ARMD100 FEC: (%s) PHY busy timeout\n",	__func__);
		return -1;
	}

	writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, &regs->smi);

	/* now wait for the data to be valid */
	if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, true)) {
		val = readl(&regs->smi);
		printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
				__func__, val);
		return -1;
	}
	val = readl(&regs->smi);
	value = val & 0xffff;

	return value;
}

static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
			 int phy_reg, u16 value)
{
	struct eth_device *dev = eth_get_dev_by_name(bus->name);
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct armdfec_reg *regs = darmdfec->regs;

	if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
		clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f);
		return 0;
	}

	/* check parameters */
	if (phy_addr > PHY_MASK) {
		printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
		return -EINVAL;
	}
	if (phy_reg > PHY_MASK) {
		printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
		return -EINVAL;
	}

	/* wait for the SMI register to become available */
	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
		printf("ARMD100 FEC: (%s) PHY busy timeout\n",	__func__);
		return -1;
	}

	writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
			&regs->smi);
	return 0;
}

/*
 * Abort any transmit and receive operations and put DMA
 * in idle state. AT and AR bits are cleared upon entering
 * in IDLE state. So poll those bits to verify operation.
 */
static void abortdma(struct eth_device *dev)
{
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct armdfec_reg *regs = darmdfec->regs;
	int delay;
	int maxretries = 40;
	u32 tmp;

	while (--maxretries) {
		writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd);
		udelay(100);

		delay = 10;
		while (--delay) {
			tmp = readl(&regs->sdma_cmd);
			if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
				break;
			udelay(10);
		}
		if (delay)
			break;
	}

	if (!maxretries)
		printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
}

static inline u32 nibble_swapping_32_bit(u32 x)
{
	return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
}

static inline u32 nibble_swapping_16_bit(u32 x)
{
	return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
}

static inline u32 flip_4_bits(u32 x)
{
	return ((x & 0x01) << 3) | ((x & 0x002) << 1)
		| ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
}

/*
 * This function will calculate the hash function of the address.
 * depends on the hash mode and hash size.
 * Inputs
 * mach             - the 2 most significant bytes of the MAC address.
 * macl             - the 4 least significant bytes of the MAC address.
 * Outputs
 * return the calculated entry.
 */
static u32 hash_function(u32 mach, u32 macl)
{
	u32 hashresult;
	u32 addrh;
	u32 addrl;
	u32 addr0;
	u32 addr1;
	u32 addr2;
	u32 addr3;
	u32 addrhswapped;
	u32 addrlswapped;

	addrh = nibble_swapping_16_bit(mach);
	addrl = nibble_swapping_32_bit(macl);

	addrhswapped = flip_4_bits(addrh & 0xf)
		+ ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
		+ ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
		+ ((flip_4_bits((addrh >> 12) & 0xf)) << 12);

	addrlswapped = flip_4_bits(addrl & 0xf)
		+ ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
		+ ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
		+ ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
		+ ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
		+ ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
		+ ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
		+ ((flip_4_bits((addrl >> 28) & 0xf)) << 28);

	addrh = addrhswapped;
	addrl = addrlswapped;

	addr0 = (addrl >> 2) & 0x03f;
	addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
	addr2 = (addrl >> 15) & 0x1ff;
	addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);

	hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
	hashresult = hashresult & 0x07ff;
	return hashresult;
}

/*
 * This function will add an entry to the address table.
 * depends on the hash mode and hash size that was initialized.
 * Inputs
 * mach - the 2 most significant bytes of the MAC address.
 * macl - the 4 least significant bytes of the MAC address.
 * skip - if 1, skip this address.
 * rd   - the RD field in the address table.
 * Outputs
 * address table entry is added.
 * 0 if success.
 * -ENOSPC if table full
 */
static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
			      u32 macl, u32 rd, u32 skip, int del)
{
	struct addr_table_entry_t *entry, *start;
	u32 newhi;
	u32 newlo;
	u32 i;

	newlo = (((mach >> 4) & 0xf) << 15)
		| (((mach >> 0) & 0xf) << 11)
		| (((mach >> 12) & 0xf) << 7)
		| (((mach >> 8) & 0xf) << 3)
		| (((macl >> 20) & 0x1) << 31)
		| (((macl >> 16) & 0xf) << 27)
		| (((macl >> 28) & 0xf) << 23)
		| (((macl >> 24) & 0xf) << 19)
		| (skip << HTESKIP) | (rd << HTERDBIT)
		| HTEVALID;

	newhi = (((macl >> 4) & 0xf) << 15)
		| (((macl >> 0) & 0xf) << 11)
		| (((macl >> 12) & 0xf) << 7)
		| (((macl >> 8) & 0xf) << 3)
		| (((macl >> 21) & 0x7) << 0);

	/*
	 * Pick the appropriate table, start scanning for free/reusable
	 * entries at the index obtained by hashing the specified MAC address
	 */
	start = (struct addr_table_entry_t *)(darmdfec->htpr);
	entry = start + hash_function(mach, macl);
	for (i = 0; i < HOP_NUMBER; i++) {
		if (!(entry->lo & HTEVALID)) {
			break;
		} else {
			/* if same address put in same position */
			if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
					&& (entry->hi == newhi))
				break;
		}
		if (entry == start + 0x7ff)
			entry = start;
		else
			entry++;
	}

	if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
		(entry->hi != newhi) && del)
		return 0;

	if (i == HOP_NUMBER) {
		if (!del) {
			printf("ARMD100 FEC: (%s) table section is full\n",
					__func__);
			return -ENOSPC;
		} else {
			return 0;
		}
	}

	/*
	 * Update the selected entry
	 */
	if (del) {
		entry->hi = 0;
		entry->lo = 0;
	} else {
		entry->hi = newhi;
		entry->lo = newlo;
	}

	return 0;
}

/*
 *  Create an addressTable entry from MAC address info
 *  found in the specifed net_device struct
 *
 *  Input : pointer to ethernet interface network device structure
 *  Output : N/A
 */
static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
					  u8 *oaddr, u8 *addr)
{
	u32 mach;
	u32 macl;

	/* Delete old entry */
	if (oaddr) {
		mach = (oaddr[0] << 8) | oaddr[1];
		macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
			(oaddr[4] << 8) | oaddr[5];
		add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
	}

	/* Add new entry */
	mach = (addr[0] << 8) | addr[1];
	macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
	add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
}

/* Address Table Initialization */
static void init_hashtable(struct eth_device *dev)
{
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct armdfec_reg *regs = darmdfec->regs;
	memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
	writel((u32)darmdfec->htpr, &regs->htpr);
}

/*
 * This detects PHY chip from address 0-31 by reading PHY status
 * registers. PHY chip can be connected at any of this address.
 */
static int ethernet_phy_detect(struct eth_device *dev)
{
	u32 val;
	u16 tmp, mii_status;
	u8 addr;

	for (addr = 0; addr < 32; addr++) {
		if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status)	!= 0)
			/* try next phy */
			continue;

		/* invalid MII status. More validation required here... */
		if (mii_status == 0 || mii_status == 0xffff)
			/* try next phy */
			continue;

		if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
			/* try next phy */
			continue;

		val = tmp << 16;
		if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
			/* try next phy */
			continue;

		val |= tmp;

		if ((val & 0xfffffff0) != 0)
			return addr;
	}
	return -1;
}

static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
{
	struct rx_desc *p_rx_desc;
	int i;

	/* initialize the Rx descriptors ring */
	p_rx_desc = darmdfec->p_rxdesc;
	for (i = 0; i < RINGSZ; i++) {
		p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
		p_rx_desc->buf_size = PKTSIZE_ALIGN;
		p_rx_desc->byte_cnt = 0;
		p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
		if (i == (RINGSZ - 1)) {
			p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
		} else {
			p_rx_desc->nxtdesc_p = (struct rx_desc *)
			    ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
			p_rx_desc = p_rx_desc->nxtdesc_p;
		}
	}
	darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
}

static int armdfec_init(struct eth_device *dev, bd_t *bd)
{
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct armdfec_reg *regs = darmdfec->regs;
	int phy_adr;
	u32 temp;

	armdfec_init_rx_desc_ring(darmdfec);

	/* Disable interrupts */
	writel(0, &regs->im);
	writel(0, &regs->ic);
	/* Write to ICR to clear interrupts. */
	writel(0, &regs->iwc);

	/*
	 * Abort any transmit and receive operations and put DMA
	 * in idle state.
	 */
	abortdma(dev);

	/* Initialize address hash table */
	init_hashtable(dev);

	/* SDMA configuration */
	writel(SDCR_BSZ8 |	/* Burst size = 32 bytes */
		SDCR_RIFB |	/* Rx interrupt on frame */
		SDCR_BLMT |	/* Little endian transmit */
		SDCR_BLMR |	/* Little endian receive */
		SDCR_RC_MAX_RETRANS,	/* Max retransmit count */
		&regs->sdma_conf);
	/* Port Configuration */
	writel(PCR_HS, &regs->pconf);	/* Hash size is 1/2kb */

	/* Set extended port configuration */
	writel(PCXR_2BSM |		/* Two byte suffix aligns IP hdr */
		PCXR_DSCP_EN |		/* Enable DSCP in IP */
		PCXR_MFL_1536 |		/* Set MTU = 1536 */
		PCXR_FLP |		/* do not force link pass */
		PCXR_TX_HIGH_PRI,	/* Transmit - high priority queue */
		&regs->pconf_ext);

	update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);

	/* Update TX and RX queue descriptor register */
	temp = (u32)&regs->txcdp[TXQ];
	writel((u32)darmdfec->p_txdesc, temp);
	temp = (u32)&regs->rxfdp[RXQ];
	writel((u32)darmdfec->p_rxdesc, temp);
	temp = (u32)&regs->rxcdp[RXQ];
	writel((u32)darmdfec->p_rxdesc_curr, temp);

	/* Enable Interrupts */
	writel(ALL_INTS, &regs->im);

	/* Enable Ethernet Port */
	setbits_le32(&regs->pconf, PCR_EN);

	/* Enable RX DMA engine */
	setbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);

#ifdef DEBUG
	eth_dump_regs(dev);
#endif

#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))

#if defined(CONFIG_PHY_BASE_ADR)
	miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
#else
	/* Search phy address from range 0-31 */
	phy_adr = ethernet_phy_detect(dev);
	if (phy_adr < 0) {
		printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
		return -1;
	} else {
		debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
		miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
	}
#endif

#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
	/* Wait up to 5s for the link status */
	for (i = 0; i < 5; i++) {
		u16 phy_adr;

		miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
		/* Return if we get link up */
		if (miiphy_link(dev->name, phy_adr))
			return 0;
		udelay(1000000);
	}

	printf("ARMD100 FEC: No link on %s\n", dev->name);
	return -1;
#endif
#endif
	return 0;
}

static void armdfec_halt(struct eth_device *dev)
{
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct armdfec_reg *regs = darmdfec->regs;

	/* Stop RX DMA */
	clrbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);

	/*
	 * Abort any transmit and receive operations and put DMA
	 * in idle state.
	 */
	abortdma(dev);

	/* Disable interrupts */
	writel(0, &regs->im);
	writel(0, &regs->ic);
	writel(0, &regs->iwc);

	/* Disable Port */
	clrbits_le32(&regs->pconf, PCR_EN);
}

static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
{
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct armdfec_reg *regs = darmdfec->regs;
	struct tx_desc *p_txdesc = darmdfec->p_txdesc;
	void *p = (void *)dataptr;
	int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
	u32 cmd_sts, temp;

	/* Copy buffer if it's misaligned */
	if ((u32)dataptr & 0x07) {
		if (datasize > PKTSIZE_ALIGN) {
			printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
					datasize);
			return -1;
		}
		memcpy(darmdfec->p_aligned_txbuf, p, datasize);
		p = darmdfec->p_aligned_txbuf;
	}

	p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
	p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
	p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
	p_txdesc->cmd_sts |= TX_EN_INT;
	p_txdesc->buf_ptr = p;
	p_txdesc->byte_cnt = datasize;

	/* Apply send command using high priority TX queue */
	temp = (u32)&regs->txcdp[TXQ];
	writel((u32)p_txdesc, temp);
	writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, &regs->sdma_cmd);

	/*
	 * wait for packet xmit completion
	 */
	cmd_sts = readl(&p_txdesc->cmd_sts);
	while (cmd_sts & BUF_OWNED_BY_DMA) {
		/* return fail if error is detected */
		if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
			(TX_ERROR | TX_LAST_DESC)) {
			printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
			return -1;
		}
		cmd_sts = readl(&p_txdesc->cmd_sts);
		if (!(retry--)) {
			printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
					__func__);
			return -1;
		}
	}

	return 0;
}

static int armdfec_recv(struct eth_device *dev)
{
	struct armdfec_device *darmdfec = to_darmdfec(dev);
	struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
	u32 cmd_sts;
	u32 timeout = 0;
	u32 temp;

	/* wait untill rx packet available or timeout */
	do {
		if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
			timeout++;
		} else {
			debug("ARMD100 FEC: %s time out...\n", __func__);
			return -1;
		}
	} while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);

	if (p_rxdesc_curr->byte_cnt != 0) {
		debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
				"(cmd_sts= %08x)\n", __func__,
				(u32)p_rxdesc_curr->byte_cnt,
				(u32)p_rxdesc_curr->buf_ptr,
				(u32)p_rxdesc_curr->cmd_sts);
	}

	/*
	 * In case received a packet without first/last bits on
	 * OR the error summary bit is on,
	 * the packets needs to be dropeed.
	 */
	cmd_sts = readl(&p_rxdesc_curr->cmd_sts);

	if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
			(RX_FIRST_DESC | RX_LAST_DESC)) {
		printf("ARMD100 FEC: (%s) Dropping packet spread on"
			" multiple descriptors\n", __func__);
	} else if (cmd_sts & RX_ERROR) {
		printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
				__func__);
	} else {
		/* !!! call higher layer processing */
		debug("ARMD100 FEC: (%s) Sending Received packet to"
		      " upper layer (net_process_received_packet)\n", __func__);

		/*
		 * let the upper layer handle the packet, subtract offset
		 * as two dummy bytes are added in received buffer see
		 * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
		 */
		net_process_received_packet(
			p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
			(int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
	}
	/*
	 * free these descriptors and point next in the ring
	 */
	p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
	p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
	p_rxdesc_curr->byte_cnt = 0;

	temp = (u32)&darmdfec->p_rxdesc_curr;
	writel((u32)p_rxdesc_curr->nxtdesc_p, temp);

	return 0;
}

int armada100_fec_register(unsigned long base_addr)
{
	struct armdfec_device *darmdfec;
	struct eth_device *dev;

	darmdfec = malloc(sizeof(struct armdfec_device));
	if (!darmdfec)
		goto error;

	memset(darmdfec, 0, sizeof(struct armdfec_device));

	darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
	if (!darmdfec->htpr)
		goto error1;

	darmdfec->p_rxdesc = memalign(PKTALIGN,
			ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);

	if (!darmdfec->p_rxdesc)
		goto error1;

	darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
	if (!darmdfec->p_rxbuf)
		goto error1;

	darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
	if (!darmdfec->p_aligned_txbuf)
		goto error1;

	darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
	if (!darmdfec->p_txdesc)
		goto error1;

	dev = &darmdfec->dev;
	/* Assign ARMADA100 Fast Ethernet Controller Base Address */
	darmdfec->regs = (void *)base_addr;

	/* must be less than sizeof(dev->name) */
	strcpy(dev->name, "armd-fec0");

	dev->init = armdfec_init;
	dev->halt = armdfec_halt;
	dev->send = armdfec_send;
	dev->recv = armdfec_recv;

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	int retval;
	struct mii_dev *mdiodev = mdio_alloc();
	if (!mdiodev)
		return -ENOMEM;
	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
	mdiodev->read = smi_reg_read;
	mdiodev->write = smi_reg_write;

	retval = mdio_register(mdiodev);
	if (retval < 0)
		return retval;
#endif
	return 0;

error1:
	free(darmdfec->p_aligned_txbuf);
	free(darmdfec->p_rxbuf);
	free(darmdfec->p_rxdesc);
	free(darmdfec->htpr);
error:
	free(darmdfec);
	printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
	return -1;
}
Commit	Line	Data
79788bb1 AB	1	/*
	2	* (C) Copyright 2011
	3	* eInfochips Ltd. <www.einfochips.com>
c7c47ca2	4	* Written-by: Ajay Bhargav <contact@8051projects.net>
79788bb1 AB	5	*
	6	* (C) Copyright 2010
	7	* Marvell Semiconductor <www.marvell.com>
	8	* Contributor: Mahavir Jain <mjain@marvell.com>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
79788bb1 AB	11	*/
	12
	13	#include <common.h>
	14	#include <net.h>
	15	#include <malloc.h>
	16	#include <miiphy.h>
	17	#include <netdev.h>
	18	#include <asm/types.h>
	19	#include <asm/byteorder.h>
	20	#include <linux/err.h>
	21	#include <linux/mii.h>
	22	#include <asm/io.h>
	23	#include <asm/arch/armada100.h>
	24	#include "armada100_fec.h"
	25
	26	#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
	27
	28	#ifdef DEBUG
	29	static int eth_dump_regs(struct eth_device *dev)
	30	{
	31	struct armdfec_device *darmdfec = to_darmdfec(dev);
	32	struct armdfec_reg *regs = darmdfec->regs;
	33	unsigned int i = 0;
	34
	35	printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr));
	36	printf("offset: smi, value: 0x%x\n", readl(&regs->smi));
	37	for (i = 0x400; i <= 0x4e4; i += 4)
	38	printf("offset: 0x%x, value: 0x%x\n",
	39	i, readl(ARMD1_FEC_BASE + i));
	40	return 0;
	41	}
	42	#endif
	43
	44	static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
	45	{
	46	u32 timeout = PHY_WAIT_ITERATIONS;
	47	u32 reg_val;
	48
	49	while (--timeout) {
	50	reg_val = readl(reg);
	51	if (cond && (reg_val & flag))
	52	break;
	53	else if (!cond && !(reg_val & flag))
	54	break;
	55	udelay(PHY_WAIT_MICRO_SECONDS);
	56	}
	57	return !timeout;
	58	}
	59
5a49f174 JH	60	static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
5a49f174 JH	61	int phy_reg)
79788bb1	62	{
5a49f174 JH	63	u16 value = 0;
5a49f174 JH	64	struct eth_device *dev = eth_get_dev_by_name(bus->name);
79788bb1 AB	65	struct armdfec_device *darmdfec = to_darmdfec(dev);
	66	struct armdfec_reg *regs = darmdfec->regs;
	67	u32 val;
	68
	69	if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
	70	val = readl(&regs->phyadr);
5a49f174 JH	71	value = val & 0x1f;
5a49f174 JH	72	return value;
79788bb1 AB	73	}
	74
	75	/* check parameters */
	76	if (phy_addr > PHY_MASK) {
	77	printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
	78	__func__, phy_addr);
	79	return -EINVAL;
	80	}
	81	if (phy_reg > PHY_MASK) {
	82	printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
	83	__func__, phy_reg);
	84	return -EINVAL;
	85	}
	86
	87	/* wait for the SMI register to become available */
472d5460	88	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
79788bb1 AB	89	printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
	90	return -1;
	91	}
	92
	93	writel((phy_addr << 16) \| (phy_reg << 21) \| SMI_OP_R, &regs->smi);
	94
	95	/* now wait for the data to be valid */
472d5460	96	if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, true)) {
79788bb1 AB	97	val = readl(&regs->smi);
	98	printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
	99	__func__, val);
	100	return -1;
	101	}
	102	val = readl(&regs->smi);
5a49f174	103	value = val & 0xffff;
79788bb1	104
5a49f174	105	return value;
79788bb1 AB	106	}
79788bb1 AB	107
5a49f174 JH	108	static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
5a49f174 JH	109	int phy_reg, u16 value)
79788bb1	110	{
5a49f174	111	struct eth_device *dev = eth_get_dev_by_name(bus->name);
79788bb1 AB	112	struct armdfec_device *darmdfec = to_darmdfec(dev);
	113	struct armdfec_reg *regs = darmdfec->regs;
	114
	115	if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
	116	clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f);
	117	return 0;
	118	}
	119
	120	/* check parameters */
	121	if (phy_addr > PHY_MASK) {
	122	printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
	123	return -EINVAL;
	124	}
	125	if (phy_reg > PHY_MASK) {
	126	printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
	127	return -EINVAL;
	128	}
	129
	130	/* wait for the SMI register to become available */
472d5460	131	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
79788bb1 AB	132	printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
	133	return -1;
	134	}
	135
	136	writel((phy_addr << 16) \| (phy_reg << 21) \| SMI_OP_W \| (value & 0xffff),
	137	&regs->smi);
	138	return 0;
	139	}
	140
	141	/*
	142	* Abort any transmit and receive operations and put DMA
	143	* in idle state. AT and AR bits are cleared upon entering
	144	* in IDLE state. So poll those bits to verify operation.
	145	*/
	146	static void abortdma(struct eth_device *dev)
	147	{
	148	struct armdfec_device *darmdfec = to_darmdfec(dev);
	149	struct armdfec_reg *regs = darmdfec->regs;
	150	int delay;
	151	int maxretries = 40;
	152	u32 tmp;
	153
	154	while (--maxretries) {
	155	writel(SDMA_CMD_AR \| SDMA_CMD_AT, &regs->sdma_cmd);
	156	udelay(100);
	157
	158	delay = 10;
	159	while (--delay) {
	160	tmp = readl(&regs->sdma_cmd);
	161	if (!(tmp & (SDMA_CMD_AR \| SDMA_CMD_AT)))
	162	break;
	163	udelay(10);
	164	}
	165	if (delay)
	166	break;
	167	}
	168
	169	if (!maxretries)
	170	printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
	171	}
	172
	173	static inline u32 nibble_swapping_32_bit(u32 x)
	174	{
	175	return ((x & 0xf0f0f0f0) >> 4) \| ((x & 0x0f0f0f0f) << 4);
	176	}
	177
	178	static inline u32 nibble_swapping_16_bit(u32 x)
	179	{
	180	return ((x & 0x0000f0f0) >> 4) \| ((x & 0x00000f0f) << 4);
	181	}
	182
	183	static inline u32 flip_4_bits(u32 x)
	184	{
	185	return ((x & 0x01) << 3) \| ((x & 0x002) << 1)
	186	\| ((x & 0x04) >> 1) \| ((x & 0x008) >> 3);
	187	}
	188
	189	/*
	190	* This function will calculate the hash function of the address.
	191	* depends on the hash mode and hash size.
	192	* Inputs
	193	* mach - the 2 most significant bytes of the MAC address.
	194	* macl - the 4 least significant bytes of the MAC address.
	195	* Outputs
196	* return the calculated entry.
197	*/
198	static u32 hash_function(u32 mach, u32 macl)
199	{
200	u32 hashresult;
201	u32 addrh;
202	u32 addrl;
203	u32 addr0;
204	u32 addr1;
205	u32 addr2;
206	u32 addr3;
207	u32 addrhswapped;
208	u32 addrlswapped;
209
210	addrh = nibble_swapping_16_bit(mach);
211	addrl = nibble_swapping_32_bit(macl);
212
213	addrhswapped = flip_4_bits(addrh & 0xf)
214	+ ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
215	+ ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
216	+ ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
217
218	addrlswapped = flip_4_bits(addrl & 0xf)
219	+ ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
220	+ ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
221	+ ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
222	+ ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
223	+ ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
224	+ ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
225	+ ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
226
227	addrh = addrhswapped;
228	addrl = addrlswapped;
229
230	addr0 = (addrl >> 2) & 0x03f;
231	addr1 = (addrl & 0x003) \| (((addrl >> 8) & 0x7f) << 2);
232	addr2 = (addrl >> 15) & 0x1ff;
233	addr3 = ((addrl >> 24) & 0x0ff) \| ((addrh & 1) << 8);
234
235	hashresult = (addr0 << 9) \| (addr1 ^ addr2 ^ addr3);
236	hashresult = hashresult & 0x07ff;
237	return hashresult;
238	}
239
240	/*
241	* This function will add an entry to the address table.
242	* depends on the hash mode and hash size that was initialized.
243	* Inputs
244	* mach - the 2 most significant bytes of the MAC address.
245	* macl - the 4 least significant bytes of the MAC address.
246	* skip - if 1, skip this address.
247	* rd - the RD field in the address table.
248	* Outputs
249	* address table entry is added.
250	* 0 if success.
251	* -ENOSPC if table full
252	*/
253	static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
254	u32 macl, u32 rd, u32 skip, int del)
255	{
256	struct addr_table_entry_t entry, start;
257	u32 newhi;
258	u32 newlo;
259	u32 i;
260
261	newlo = (((mach >> 4) & 0xf) << 15)
262	\| (((mach >> 0) & 0xf) << 11)
263	\| (((mach >> 12) & 0xf) << 7)
264	\| (((mach >> 8) & 0xf) << 3)
265	\| (((macl >> 20) & 0x1) << 31)
266	\| (((macl >> 16) & 0xf) << 27)
267	\| (((macl >> 28) & 0xf) << 23)
268	\| (((macl >> 24) & 0xf) << 19)
269	\| (skip << HTESKIP) \| (rd << HTERDBIT)
270	\| HTEVALID;
271
272	newhi = (((macl >> 4) & 0xf) << 15)
273	\| (((macl >> 0) & 0xf) << 11)
274	\| (((macl >> 12) & 0xf) << 7)
275	\| (((macl >> 8) & 0xf) << 3)
276	\| (((macl >> 21) & 0x7) << 0);
277
278	/*
279	* Pick the appropriate table, start scanning for free/reusable
280	* entries at the index obtained by hashing the specified MAC address
281	*/
282	start = (struct addr_table_entry_t *)(darmdfec->htpr);
283	entry = start + hash_function(mach, macl);
284	for (i = 0; i < HOP_NUMBER; i++) {
285	if (!(entry->lo & HTEVALID)) {
286	break;
287	} else {
288	/* if same address put in same position */
289	if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
290	&& (entry->hi == newhi))
291	break;
292	}
293	if (entry == start + 0x7ff)
294	entry = start;
295	else
296	entry++;
297	}
298
299	if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
300	(entry->hi != newhi) && del)
301	return 0;
302
303	if (i == HOP_NUMBER) {
304	if (!del) {
305	printf("ARMD100 FEC: (%s) table section is full\n",
306	__func__);
307	return -ENOSPC;
308	} else {
309	return 0;
310	}
311	}
312
313	/*
314	* Update the selected entry
315	*/
316	if (del) {
317	entry->hi = 0;
318	entry->lo = 0;
319	} else {
320	entry->hi = newhi;
321	entry->lo = newlo;
322	}
323
324	return 0;
325	}
326
327	/*
328	* Create an addressTable entry from MAC address info
329	* found in the specifed net_device struct
330	*
331	* Input : pointer to ethernet interface network device structure
332	* Output : N/A
333	*/
334	static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
335	u8 oaddr, u8 addr)
336	{
337	u32 mach;
338	u32 macl;
339
340	/* Delete old entry */
341	if (oaddr) {
342	mach = (oaddr[0] << 8) \| oaddr[1];
343	macl = (oaddr[2] << 24) \| (oaddr[3] << 16) \|
344	(oaddr[4] << 8) \| oaddr[5];
345	add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
346	}
347
348	/* Add new entry */
349	mach = (addr[0] << 8) \| addr[1];
350	macl = (addr[2] << 24) \| (addr[3] << 16) \| (addr[4] << 8) \| addr[5];
351	add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
352	}
353
354	/* Address Table Initialization */
355	static void init_hashtable(struct eth_device *dev)
356	{
357	struct armdfec_device *darmdfec = to_darmdfec(dev);
358	struct armdfec_reg *regs = darmdfec->regs;
359	memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
360	writel((u32)darmdfec->htpr, &regs->htpr);
361	}
362
363	/*
364	* This detects PHY chip from address 0-31 by reading PHY status
365	* registers. PHY chip can be connected at any of this address.
366	*/
367	static int ethernet_phy_detect(struct eth_device *dev)
368	{
369	u32 val;
370	u16 tmp, mii_status;
371	u8 addr;
372
373	for (addr = 0; addr < 32; addr++) {
374	if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
375	/* try next phy */
376	continue;
377
378	/* invalid MII status. More validation required here... */
379	if (mii_status == 0 \|\| mii_status == 0xffff)
380	/* try next phy */
381	continue;
382
383	if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
384	/* try next phy */
385	continue;
386
387	val = tmp << 16;
388	if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
389	/* try next phy */
390	continue;
391
392	val \|= tmp;
393
394	if ((val & 0xfffffff0) != 0)
395	return addr;
396	}
397	return -1;
398	}
399
400	static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
401	{
402	struct rx_desc *p_rx_desc;
403	int i;
404
405	/* initialize the Rx descriptors ring */
406	p_rx_desc = darmdfec->p_rxdesc;
407	for (i = 0; i < RINGSZ; i++) {
408	p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA \| RX_EN_INT;
409	p_rx_desc->buf_size = PKTSIZE_ALIGN;
410	p_rx_desc->byte_cnt = 0;
411	p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
412	if (i == (RINGSZ - 1)) {
413	p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
414	} else {
415	p_rx_desc->nxtdesc_p = (struct rx_desc *)
416	((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
417	p_rx_desc = p_rx_desc->nxtdesc_p;
418	}
419	}
420	darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
421	}
422
423	static int armdfec_init(struct eth_device dev, bd_t bd)
424	{
425	struct armdfec_device *darmdfec = to_darmdfec(dev);
426	struct armdfec_reg *regs = darmdfec->regs;
427	int phy_adr;
28cb465f	428	u32 temp;
79788bb1 AB	429
	430	armdfec_init_rx_desc_ring(darmdfec);
	431
	432	/* Disable interrupts */
	433	writel(0, &regs->im);
	434	writel(0, &regs->ic);
	435	/* Write to ICR to clear interrupts. */
	436	writel(0, &regs->iwc);
	437
	438	/*
	439	* Abort any transmit and receive operations and put DMA
	440	* in idle state.
	441	*/
	442	abortdma(dev);
	443
	444	/* Initialize address hash table */
	445	init_hashtable(dev);
	446
	447	/* SDMA configuration */
	448	writel(SDCR_BSZ8 \| /* Burst size = 32 bytes */
	449	SDCR_RIFB \| /* Rx interrupt on frame */
	450	SDCR_BLMT \| /* Little endian transmit */
	451	SDCR_BLMR \| /* Little endian receive */
	452	SDCR_RC_MAX_RETRANS, /* Max retransmit count */
	453	&regs->sdma_conf);
	454	/* Port Configuration */
	455	writel(PCR_HS, &regs->pconf); /* Hash size is 1/2kb */
	456
	457	/* Set extended port configuration */
	458	writel(PCXR_2BSM \| /* Two byte suffix aligns IP hdr */
	459	PCXR_DSCP_EN \| /* Enable DSCP in IP */
	460	PCXR_MFL_1536 \| /* Set MTU = 1536 */
	461	PCXR_FLP \| /* do not force link pass */
	462	PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
	463	&regs->pconf_ext);
	464
	465	update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
	466
	467	/* Update TX and RX queue descriptor register */
28cb465f AB	468	temp = (u32)&regs->txcdp[TXQ];
	469	writel((u32)darmdfec->p_txdesc, temp);
	470	temp = (u32)&regs->rxfdp[RXQ];
	471	writel((u32)darmdfec->p_rxdesc, temp);
	472	temp = (u32)&regs->rxcdp[RXQ];
	473	writel((u32)darmdfec->p_rxdesc_curr, temp);
79788bb1 AB	474
	475	/* Enable Interrupts */
	476	writel(ALL_INTS, &regs->im);
	477
	478	/* Enable Ethernet Port */
	479	setbits_le32(&regs->pconf, PCR_EN);
	480
	481	/* Enable RX DMA engine */
	482	setbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
	483
	484	#ifdef DEBUG
	485	eth_dump_regs(dev);
	486	#endif
	487
	488	#if (defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII))
	489
	490	#if defined(CONFIG_PHY_BASE_ADR)
	491	miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
	492	#else
	493	/* Search phy address from range 0-31 */
	494	phy_adr = ethernet_phy_detect(dev);
	495	if (phy_adr < 0) {
	496	printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
	497	return -1;
	498	} else {
	499	debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
	500	miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
	501	}
	502	#endif
	503
	504	#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
	505	/* Wait up to 5s for the link status */
	506	for (i = 0; i < 5; i++) {
	507	u16 phy_adr;
	508
	509	miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
	510	/* Return if we get link up */
	511	if (miiphy_link(dev->name, phy_adr))
	512	return 0;
	513	udelay(1000000);
	514	}
	515
	516	printf("ARMD100 FEC: No link on %s\n", dev->name);
	517	return -1;
	518	#endif
	519	#endif
	520	return 0;
	521	}
	522
	523	static void armdfec_halt(struct eth_device *dev)
	524	{
	525	struct armdfec_device *darmdfec = to_darmdfec(dev);
	526	struct armdfec_reg *regs = darmdfec->regs;
	527
	528	/* Stop RX DMA */
	529	clrbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
	530
	531	/*
	532	* Abort any transmit and receive operations and put DMA
	533	* in idle state.
	534	*/
	535	abortdma(dev);
	536
	537	/* Disable interrupts */
538	writel(0, &regs->im);
539	writel(0, &regs->ic);
540	writel(0, &regs->iwc);
541
542	/* Disable Port */
543	clrbits_le32(&regs->pconf, PCR_EN);
544	}
545
74e738e8	546	static int armdfec_send(struct eth_device dev, void dataptr, int datasize)
79788bb1 AB	547	{
	548	struct armdfec_device *darmdfec = to_darmdfec(dev);
	549	struct armdfec_reg *regs = darmdfec->regs;
	550	struct tx_desc *p_txdesc = darmdfec->p_txdesc;
	551	void p = (void )dataptr;
	552	int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
905b3b00	553	u32 cmd_sts, temp;
79788bb1 AB	554
	555	/* Copy buffer if it's misaligned */
	556	if ((u32)dataptr & 0x07) {
	557	if (datasize > PKTSIZE_ALIGN) {
	558	printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
	559	datasize);
	560	return -1;
	561	}
	562	memcpy(darmdfec->p_aligned_txbuf, p, datasize);
	563	p = darmdfec->p_aligned_txbuf;
	564	}
	565
	566	p_txdesc->cmd_sts = TX_ZERO_PADDING \| TX_GEN_CRC;
	567	p_txdesc->cmd_sts \|= TX_FIRST_DESC \| TX_LAST_DESC;
	568	p_txdesc->cmd_sts \|= BUF_OWNED_BY_DMA;
	569	p_txdesc->cmd_sts \|= TX_EN_INT;
	570	p_txdesc->buf_ptr = p;
	571	p_txdesc->byte_cnt = datasize;
	572
	573	/* Apply send command using high priority TX queue */
905b3b00 MV	574	temp = (u32)&regs->txcdp[TXQ];
905b3b00 MV	575	writel((u32)p_txdesc, temp);
79788bb1 AB	576	writel(SDMA_CMD_TXDL \| SDMA_CMD_TXDH \| SDMA_CMD_ERD, &regs->sdma_cmd);
	577
	578	/*
	579	* wait for packet xmit completion
	580	*/
	581	cmd_sts = readl(&p_txdesc->cmd_sts);
	582	while (cmd_sts & BUF_OWNED_BY_DMA) {
	583	/* return fail if error is detected */
	584	if ((cmd_sts & (TX_ERROR \| TX_LAST_DESC)) ==
	585	(TX_ERROR \| TX_LAST_DESC)) {
	586	printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
	587	return -1;
	588	}
	589	cmd_sts = readl(&p_txdesc->cmd_sts);
	590	if (!(retry--)) {
	591	printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
	592	__func__);
	593	return -1;
	594	}
	595	}
	596
	597	return 0;
	598	}
	599
	600	static int armdfec_recv(struct eth_device *dev)
	601	{
	602	struct armdfec_device *darmdfec = to_darmdfec(dev);
	603	struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
	604	u32 cmd_sts;
	605	u32 timeout = 0;
28cb465f	606	u32 temp;
79788bb1 AB	607
	608	/* wait untill rx packet available or timeout */
	609	do {
	610	if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
	611	timeout++;
	612	} else {
	613	debug("ARMD100 FEC: %s time out...\n", __func__);
	614	return -1;
	615	}
	616	} while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
	617
	618	if (p_rxdesc_curr->byte_cnt != 0) {
	619	debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
	620	"(cmd_sts= %08x)\n", __func__,
	621	(u32)p_rxdesc_curr->byte_cnt,
	622	(u32)p_rxdesc_curr->buf_ptr,
	623	(u32)p_rxdesc_curr->cmd_sts);
	624	}
	625
	626	/*
	627	* In case received a packet without first/last bits on
	628	* OR the error summary bit is on,
	629	* the packets needs to be dropeed.
	630	*/
	631	cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
	632
	633	if ((cmd_sts & (RX_FIRST_DESC \| RX_LAST_DESC)) !=
	634	(RX_FIRST_DESC \| RX_LAST_DESC)) {
	635	printf("ARMD100 FEC: (%s) Dropping packet spread on"
	636	" multiple descriptors\n", __func__);
	637	} else if (cmd_sts & RX_ERROR) {
	638	printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
	639	__func__);
	640	} else {
	641	/* !!! call higher layer processing */
	642	debug("ARMD100 FEC: (%s) Sending Received packet to"
1fd92db8	643	" upper layer (net_process_received_packet)\n", __func__);
79788bb1 AB	644
	645	/*
	646	* let the upper layer handle the packet, subtract offset
	647	* as two dummy bytes are added in received buffer see
	648	* PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
	649	*/
1fd92db8 JH	650	net_process_received_packet(
	651	p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
	652	(int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
79788bb1 AB	653	}
	654	/*
	655	* free these descriptors and point next in the ring
	656	*/
	657	p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA \| RX_EN_INT;
	658	p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
	659	p_rxdesc_curr->byte_cnt = 0;
	660
28cb465f AB	661	temp = (u32)&darmdfec->p_rxdesc_curr;
28cb465f AB	662	writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
79788bb1 AB	663
	664	return 0;
	665	}
	666
	667	int armada100_fec_register(unsigned long base_addr)
	668	{
	669	struct armdfec_device *darmdfec;
	670	struct eth_device *dev;
	671
	672	darmdfec = malloc(sizeof(struct armdfec_device));
	673	if (!darmdfec)
	674	goto error;
	675
	676	memset(darmdfec, 0, sizeof(struct armdfec_device));
	677
	678	darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
	679	if (!darmdfec->htpr)
	680	goto error1;
	681
	682	darmdfec->p_rxdesc = memalign(PKTALIGN,
	683	ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
	684
	685	if (!darmdfec->p_rxdesc)
	686	goto error1;
	687
	688	darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
	689	if (!darmdfec->p_rxbuf)
	690	goto error1;
	691
	692	darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
	693	if (!darmdfec->p_aligned_txbuf)
	694	goto error1;
	695
	696	darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
	697	if (!darmdfec->p_txdesc)
	698	goto error1;
	699
	700	dev = &darmdfec->dev;
	701	/* Assign ARMADA100 Fast Ethernet Controller Base Address */
	702	darmdfec->regs = (void *)base_addr;
	703
f6add132	704	/* must be less than sizeof(dev->name) */
79788bb1 AB	705	strcpy(dev->name, "armd-fec0");
	706
	707	dev->init = armdfec_init;
	708	dev->halt = armdfec_halt;
	709	dev->send = armdfec_send;
	710	dev->recv = armdfec_recv;
	711
	712	eth_register(dev);
	713
	714	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
5a49f174 JH	715	int retval;
	716	struct mii_dev *mdiodev = mdio_alloc();
	717	if (!mdiodev)
	718	return -ENOMEM;
	719	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
	720	mdiodev->read = smi_reg_read;
	721	mdiodev->write = smi_reg_write;
	722
	723	retval = mdio_register(mdiodev);
	724	if (retval < 0)
	725	return retval;
79788bb1 AB	726	#endif
	727	return 0;
	728
	729	error1:
	730	free(darmdfec->p_aligned_txbuf);
	731	free(darmdfec->p_rxbuf);
	732	free(darmdfec->p_rxdesc);
	733	free(darmdfec->htpr);
	734	error:
	735	free(darmdfec);
	736	printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
	737	return -1;
	738	}