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6a8a5dc4 | 1 | /* |
2 | * AX88796L(NE2000) support | |
3 | * | |
4 | * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
6a8a5dc4 | 7 | */ |
8 | ||
9 | #ifndef __DRIVERS_AX88796L_H__ | |
10 | #define __DRIVERS_AX88796L_H__ | |
11 | ||
4acbc6c7 JCPV |
12 | #define DP_DATA (0x10 << 1) |
13 | #define START_PG 0x40 /* First page of TX buffer */ | |
14 | #define START_PG2 0x48 | |
15 | #define STOP_PG 0x80 /* Last page +1 of RX ring */ | |
16 | #define TX_PAGES 12 | |
17 | #define RX_START (START_PG+TX_PAGES) | |
18 | #define RX_END STOP_PG | |
6a8a5dc4 | 19 | |
20 | #define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE | |
4acbc6c7 JCPV |
21 | #define AX88796L_BYTE_ACCESS 0x00001000 |
22 | #define AX88796L_OFFSET 0x00000400 | |
23 | #define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ | |
6a8a5dc4 | 24 | AX88796L_BYTE_ACCESS + AX88796L_OFFSET |
4acbc6c7 JCPV |
25 | #define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) |
26 | #define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) | |
6a8a5dc4 | 27 | |
28 | #define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) | |
4acbc6c7 | 29 | #define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) |
6a8a5dc4 | 30 | |
31 | #define EECS_HIGH (AX88796L_MEMR |= 0x10) | |
32 | #define EECS_LOW (AX88796L_MEMR &= 0xef) | |
33 | #define EECLK_HIGH (AX88796L_MEMR |= 0x80) | |
34 | #define EECLK_LOW (AX88796L_MEMR &= 0x7f) | |
35 | #define EEDI_HIGH (AX88796L_MEMR |= 0x20) | |
36 | #define EEDI_LOW (AX88796L_MEMR &= 0xdf) | |
37 | #define EEDO ((AX88796L_MEMR & 0x40)>>6) | |
38 | ||
39 | #define PAGE0_SET (AX88796L_CR &= 0x3f) | |
40 | #define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) | |
41 | ||
4acbc6c7 | 42 | #define BIT_DUMMY 0 |
6a8a5dc4 | 43 | #define MAC_EEP_READ 1 |
44 | #define MAC_EEP_WRITE 2 | |
45 | #define MAC_EEP_ERACE 3 | |
46 | #define MAC_EEP_EWEN 4 | |
47 | #define MAC_EEP_EWDS 5 | |
48 | ||
49 | /* R7780MP Specific code */ | |
50 | #if defined(CONFIG_R7780MP) | |
4acbc6c7 JCPV |
51 | #define ISA_OFFSET 0x1400 |
52 | #define DP_IN(_b_, _o_, _d_) (_d_) = \ | |
6a8a5dc4 | 53 | *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) |
54 | #define DP_OUT(_b_, _o_, _d_) \ | |
55 | *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) | |
4acbc6c7 JCPV |
56 | #define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) |
57 | #define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) | |
6a8a5dc4 | 58 | #else |
59 | /* Please change for your target boards */ | |
4acbc6c7 JCPV |
60 | #define ISA_OFFSET 0x0000 |
61 | #define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) | |
62 | #define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) | |
63 | #define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) | |
64 | #define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) | |
6a8a5dc4 | 65 | #endif |
66 | ||
6a8a5dc4 | 67 | #endif /* __DRIVERS_AX88796L_H__ */ |