[people/ms/u-boot.git] / drivers / net / bfin_mac.c

/*
 * Driver for Blackfin On-Chip MAC device
 *
 * Copyright (c) 2005-2008 Analog Device, Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
#include <command.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mdio.h>
#include <linux/mii.h>

#include <asm/blackfin.h>
#include <asm/clock.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>

#include "bfin_mac.h"

#ifndef CONFIG_PHY_ADDR
# define CONFIG_PHY_ADDR 1
#endif
#ifndef CONFIG_PHY_CLOCK_FREQ
# define CONFIG_PHY_CLOCK_FREQ 2500000
#endif

#ifdef CONFIG_POST
#include <post.h>
#endif

#define RXBUF_BASE_ADDR		0xFF900000
#define TXBUF_BASE_ADDR		0xFF800000
#define TX_BUF_CNT		1

#define TOUT_LOOP		1000000

static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx;		/* index of the current RX buffer */
static u16 rxIdx;		/* index of the current TX buffer */

/* DMAx_CONFIG values at DMA Restart */
static const union {
	u16 data;
	ADI_DMA_CONFIG_REG reg;
} txdmacfg = {
	.reg = {
		.b_DMA_EN  = 1,	/* enabled */
		.b_WNR     = 0,	/* read from memory */
		.b_WDSIZE  = 2,	/* wordsize is 32 bits */
		.b_DMA2D   = 0,
		.b_RESTART = 0,
		.b_DI_SEL  = 0,
		.b_DI_EN   = 0,	/* no interrupt */
		.b_NDSIZE  = 5,	/* 5 half words is desc size */
		.b_FLOW    = 7	/* large desc flow */
	},
};

static int bfin_miiphy_wait(void)
{
	/* poll the STABUSY bit */
	while (bfin_read_EMAC_STAADD() & STABUSY)
		continue;
	return 0;
}

static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	ushort val = 0;
	if (bfin_miiphy_wait())
		return 1;
	bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
	if (bfin_miiphy_wait())
		return 1;
	val = bfin_read_EMAC_STADAT();
	return val;
}

static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad,
			     int reg, u16 val)
{
	if (bfin_miiphy_wait())
		return 1;
	bfin_write_EMAC_STADAT(val);
	bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
	return 0;
}

int bfin_EMAC_initialize(bd_t *bis)
{
	struct eth_device *dev;
	dev = malloc(sizeof(*dev));
	if (dev == NULL)
		hang();

	memset(dev, 0, sizeof(*dev));
	strcpy(dev->name, "bfin_mac");

	dev->iobase = 0;
	dev->priv = 0;
	dev->init = bfin_EMAC_init;
	dev->halt = bfin_EMAC_halt;
	dev->send = bfin_EMAC_send;
	dev->recv = bfin_EMAC_recv;
	dev->write_hwaddr = bfin_EMAC_setup_addr;

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	int retval;
	struct mii_dev *mdiodev = mdio_alloc();
	if (!mdiodev)
		return -ENOMEM;
	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
	mdiodev->read = bfin_miiphy_read;
	mdiodev->write = bfin_miiphy_write;

	retval = mdio_register(mdiodev);
	if (retval < 0)
		return retval;

	dev->priv = mdiodev;
#endif

	return 0;
}

static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
{
	int i;
	int result = 0;

	if (length <= 0) {
		printf("Ethernet: bad packet size: %d\n", length);
		goto out;
	}

	if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
		printf("Ethernet: tx DMA error\n");
		goto out;
	}

	for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
		if (i > TOUT_LOOP) {
			puts("Ethernet: tx time out\n");
			goto out;
		}
	}
	txbuf[txIdx]->FrmData->NoBytes = length;
	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
	bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
	bfin_write_DMA2_CONFIG(txdmacfg.data);
	bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);

	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
		if (i > TOUT_LOOP) {
			puts("Ethernet: tx error\n");
			goto out;
		}
	}
	result = txbuf[txIdx]->StatusWord;
	txbuf[txIdx]->StatusWord = 0;
	if ((txIdx + 1) >= TX_BUF_CNT)
		txIdx = 0;
	else
		txIdx++;
 out:
	debug("BFIN EMAC send: length = %d\n", length);
	return result;
}

static int bfin_EMAC_recv(struct eth_device *dev)
{
	int length = 0;

	for (;;) {
		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
			length = -1;
			break;
		}
		if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
			printf("Ethernet: rx dma overrun\n");
			break;
		}
		if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
			printf("Ethernet: rx error\n");
			break;
		}
		length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
		if (length <= 4) {
			printf("Ethernet: bad frame\n");
			break;
		}

		debug("%s: len = %d\n", __func__, length - 4);

		net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
		net_process_received_packet(net_rx_packets[rxIdx], length - 4);
		bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
		rxbuf[rxIdx]->StatusWord = 0x00000000;
		if ((rxIdx + 1) >= PKTBUFSRX)
			rxIdx = 0;
		else
			rxIdx++;
	}

	return length;
}

/**************************************************************
 *
 * Ethernet Initialization Routine
 *
 *************************************************************/

/* MDC = SCLK / MDC_freq / 2 - 1 */
#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)

#ifndef CONFIG_BFIN_MAC_PINS
# ifdef CONFIG_RMII
#  define CONFIG_BFIN_MAC_PINS P_RMII0
# else
#  define CONFIG_BFIN_MAC_PINS P_MII0
# endif
#endif

static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
	const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
	int phydat;
	size_t count;
	struct mii_dev *mdiodev = dev->priv;

	/* Enable PHY output */
	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);

	/* Set all the pins to peripheral mode */
	peripheral_request_list(pins, "bfin_mac");

	/* Odd word alignment for Receive Frame DMA word */
	/* Configure checksum support and rcve frame word alignment */
	bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));

	/* turn on auto-negotiation and wait for link to come up */
	bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR,
			  BMCR_ANENABLE);
	count = 0;
	while (1) {
		++count;
		phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR,
					  MDIO_DEVAD_NONE, MII_BMSR);
		if (phydat < 0)
			return phydat;
		if (phydat & BMSR_LSTATUS)
			break;
		if (count > 30000) {
			printf("%s: link down, check cable\n", dev->name);
			return -1;
		}
		udelay(100);
	}

	/* see what kind of link we have */
	phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE,
				  MII_LPA);
	if (phydat < 0)
		return phydat;
	if (phydat & LPA_DUPLEX)
		*opmode = FDMODE;
	else
		*opmode = 0;

	bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
	bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
	bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);

	/* Initialize the TX DMA channel registers */
	bfin_write_DMA2_X_COUNT(0);
	bfin_write_DMA2_X_MODIFY(4);
	bfin_write_DMA2_Y_COUNT(0);
	bfin_write_DMA2_Y_MODIFY(0);

	/* Initialize the RX DMA channel registers */
	bfin_write_DMA1_X_COUNT(0);
	bfin_write_DMA1_X_MODIFY(4);
	bfin_write_DMA1_Y_COUNT(0);
	bfin_write_DMA1_Y_MODIFY(0);

	return 0;
}

static int bfin_EMAC_setup_addr(struct eth_device *dev)
{
	bfin_write_EMAC_ADDRLO(
		dev->enetaddr[0] |
		dev->enetaddr[1] << 8 |
		dev->enetaddr[2] << 16 |
		dev->enetaddr[3] << 24
	);
	bfin_write_EMAC_ADDRHI(
		dev->enetaddr[4] |
		dev->enetaddr[5] << 8
	);
	return 0;
}

static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
{
	u32 opmode;
	int dat;
	int i;
	debug("Eth_init: ......\n");

	txIdx = 0;
	rxIdx = 0;

	/* Initialize System Register */
	if (bfin_miiphy_init(dev, &dat) < 0)
		return -1;

	/* Initialize EMAC address */
	bfin_EMAC_setup_addr(dev);

	/* Initialize TX and RX buffer */
	for (i = 0; i < PKTBUFSRX; i++) {
		rxbuf[i] = SetupRxBuffer(i);
		if (i > 0) {
			rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
			if (i == (PKTBUFSRX - 1))
				rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
		}
	}
	for (i = 0; i < TX_BUF_CNT; i++) {
		txbuf[i] = SetupTxBuffer(i);
		if (i > 0) {
			txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
			if (i == (TX_BUF_CNT - 1))
				txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
		}
	}

	/* Set RX DMA */
	bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
	bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);

	/* Wait MII done */
	bfin_miiphy_wait();

	/* We enable only RX here */
	/* ASTP   : Enable Automatic Pad Stripping
	   PR     : Promiscuous Mode for test
	   PSF    : Receive frames with total length less than 64 bytes.
	   FDMODE : Full Duplex Mode
	   LB	  : Internal Loopback for test
	   RE     : Receiver Enable */
	if (dat == FDMODE)
		opmode = ASTP | FDMODE | PSF;
	else
		opmode = ASTP | PSF;
	opmode |= RE;
#ifdef CONFIG_RMII
	opmode |= TE | RMII;
#endif
	/* Turn on the EMAC */
	bfin_write_EMAC_OPMODE(opmode);
	return 0;
}

static void bfin_EMAC_halt(struct eth_device *dev)
{
	debug("Eth_halt: ......\n");
	/* Turn off the EMAC */
	bfin_write_EMAC_OPMODE(0);
	/* Turn off the EMAC RX DMA */
	bfin_write_DMA1_CONFIG(0);
	bfin_write_DMA2_CONFIG(0);
}

ADI_ETHER_BUFFER *SetupRxBuffer(int no)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
	int total_size = nobytes_buffer + RECV_BUFSIZE;

	buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
	frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);

	memset(buf, 0x00, nobytes_buffer);
	buf->FrmData = frmbuf;
	memset(frmbuf, 0xfe, RECV_BUFSIZE);

	/* set up first desc to point to receive frame buffer */
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[0].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */

	/* set up second desc to point to status word */
	buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
	buf->Dma[1].CONFIG.b_NDSIZE = 5;	/* must be 0 when FLOW is 0 */
	buf->Dma[1].CONFIG.b_FLOW = 7;	/* stop */

	return buf;
}

ADI_ETHER_BUFFER *SetupTxBuffer(int no)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
	int total_size = nobytes_buffer + RECV_BUFSIZE;

	buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
	frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);

	memset(buf, 0x00, nobytes_buffer);
	buf->FrmData = frmbuf;
	memset(frmbuf, 0x00, RECV_BUFSIZE);

	/* set up first desc to point to receive frame buffer */
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[0].CONFIG.b_WNR = 0;	/* Read to memory */
	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */

	/* set up second desc to point to status word */
	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
	buf->Dma[1].CONFIG.b_NDSIZE = 0;	/* must be 0 when FLOW is 0 */
	buf->Dma[1].CONFIG.b_FLOW = 0;	/* stop */

	return buf;
}

#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
int ether_post_test(int flags)
{
	uchar buf[64];
	int i, value = 0;
	int length;
	uint addr;

	printf("\n--------");
	bfin_EMAC_init(NULL, NULL);
	/* construct the package */
	addr = bfin_read_EMAC_ADDRLO();
	buf[0] = buf[6] = addr;
	buf[1] = buf[7] = addr >> 8;
	buf[2] = buf[8] = addr >> 16;
	buf[3] = buf[9] = addr >> 24;
	addr = bfin_read_EMAC_ADDRHI();
	buf[4] = buf[10] = addr;
	buf[5] = buf[11] = addr >> 8;
	buf[12] = 0x08;		/* Type: ARP */
	buf[13] = 0x06;
	buf[14] = 0x00;		/* Hardware type: Ethernet */
	buf[15] = 0x01;
	buf[16] = 0x08;		/* Protocal type: IP */
	buf[17] = 0x00;
	buf[18] = 0x06;		/* Hardware size    */
	buf[19] = 0x04;		/* Protocol size    */
	buf[20] = 0x00;		/* Opcode: request  */
	buf[21] = 0x01;

	for (i = 0; i < 42; i++)
		buf[i + 22] = i;
	printf("--------Send 64 bytes......\n");
	bfin_EMAC_send(NULL, buf, 64);
	for (i = 0; i < 100; i++) {
		udelay(10000);
		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
			value = 1;
			break;
		}
	}
	if (value == 0) {
		printf("--------EMAC can't receive any data\n");
		eth_halt();
		return -1;
	}
	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
	for (i = 0; i < length; i++) {
		if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
			printf("--------EMAC receive error data!\n");
			eth_halt();
			return -1;
		}
	}
	printf("--------receive %d bytes, matched\n", length);
	bfin_EMAC_halt(NULL);
	return 0;
}
#endif
Commit	Line	Data
26bf7dec	1	/*
395bce4f	2	* Driver for Blackfin On-Chip MAC device
26bf7dec	3	*
395bce4f	4	* Copyright (c) 2005-2008 Analog Device, Inc.
26bf7dec	5	*
395bce4f	6	* Licensed under the GPL-2 or later.
26bf7dec AL	7	*/
	8
	9	#include <common.h>
	10	#include <config.h>
26bf7dec	11	#include <net.h>
89973f8a	12	#include <netdev.h>
26bf7dec AL	13	#include <command.h>
26bf7dec AL	14	#include <malloc.h>
ac45af4e	15	#include <miiphy.h>
875e0bc6	16	#include <linux/mdio.h>
ac45af4e	17	#include <linux/mii.h>
26bf7dec	18
395bce4f	19	#include <asm/blackfin.h>
130fbeb1	20	#include <asm/clock.h>
8339ad73	21	#include <asm/portmux.h>
d4d77308 MF	22	#include <asm/mach-common/bits/dma.h>
	23	#include <asm/mach-common/bits/emac.h>
	24	#include <asm/mach-common/bits/pll.h>
	25
395bce4f MF	26	#include "bfin_mac.h"
395bce4f MF	27
a7ec6ac8 MF	28	#ifndef CONFIG_PHY_ADDR
	29	# define CONFIG_PHY_ADDR 1
	30	#endif
	31	#ifndef CONFIG_PHY_CLOCK_FREQ
	32	# define CONFIG_PHY_CLOCK_FREQ 2500000
	33	#endif
	34
26bf7dec AL	35	#ifdef CONFIG_POST
	36	#include <post.h>
	37	#endif
	38
26bf7dec AL	39	#define RXBUF_BASE_ADDR 0xFF900000
	40	#define TXBUF_BASE_ADDR 0xFF800000
	41	#define TX_BUF_CNT 1
	42
53677ef1	43	#define TOUT_LOOP 1000000
26bf7dec	44
6d7d4803 MF	45	static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
6d7d4803 MF	46	static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
26bf7dec AL	47	static u16 txIdx; /* index of the current RX buffer */
	48	static u16 rxIdx; /* index of the current TX buffer */
	49
26bf7dec	50	/* DMAx_CONFIG values at DMA Restart */
6d7d4803 MF	51	static const union {
	52	u16 data;
	53	ADI_DMA_CONFIG_REG reg;
	54	} txdmacfg = {
	55	.reg = {
	56	.b_DMA_EN = 1, /* enabled */
	57	.b_WNR = 0, /* read from memory */
	58	.b_WDSIZE = 2, /* wordsize is 32 bits */
	59	.b_DMA2D = 0,
	60	.b_RESTART = 0,
	61	.b_DI_SEL = 0,
	62	.b_DI_EN = 0, /* no interrupt */
	63	.b_NDSIZE = 5, /* 5 half words is desc size */
	64	.b_FLOW = 7 /* large desc flow */
	65	},
395bce4f MF	66	};
395bce4f MF	67
ac45af4e MF	68	static int bfin_miiphy_wait(void)
	69	{
	70	/* poll the STABUSY bit */
	71	while (bfin_read_EMAC_STAADD() & STABUSY)
	72	continue;
	73	return 0;
	74	}
	75
5a49f174	76	static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
ac45af4e	77	{
5a49f174	78	ushort val = 0;
ac45af4e MF	79	if (bfin_miiphy_wait())
	80	return 1;
	81	bfin_write_EMAC_STAADD(SET_PHYAD(addr) \| SET_REGAD(reg) \| STABUSY);
	82	if (bfin_miiphy_wait())
	83	return 1;
5a49f174 JH	84	val = bfin_read_EMAC_STADAT();
5a49f174 JH	85	return val;
ac45af4e MF	86	}
ac45af4e MF	87
5a49f174 JH	88	static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad,
5a49f174 JH	89	int reg, u16 val)
ac45af4e MF	90	{
	91	if (bfin_miiphy_wait())
	92	return 1;
	93	bfin_write_EMAC_STADAT(val);
	94	bfin_write_EMAC_STAADD(SET_PHYAD(addr) \| SET_REGAD(reg) \| STAOP \| STABUSY);
	95	return 0;
	96	}
	97
395bce4f	98	int bfin_EMAC_initialize(bd_t *bis)
26bf7dec AL	99	{
26bf7dec AL	100	struct eth_device *dev;
ac45af4e	101	dev = malloc(sizeof(*dev));
26bf7dec AL	102	if (dev == NULL)
	103	hang();
	104
	105	memset(dev, 0, sizeof(*dev));
94060a15	106	strcpy(dev->name, "bfin_mac");
26bf7dec AL	107
	108	dev->iobase = 0;
	109	dev->priv = 0;
	110	dev->init = bfin_EMAC_init;
	111	dev->halt = bfin_EMAC_halt;
	112	dev->send = bfin_EMAC_send;
	113	dev->recv = bfin_EMAC_recv;
4324dc72	114	dev->write_hwaddr = bfin_EMAC_setup_addr;
26bf7dec AL	115
	116	eth_register(dev);
	117
ac45af4e	118	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
5a49f174 JH	119	int retval;
	120	struct mii_dev *mdiodev = mdio_alloc();
	121	if (!mdiodev)
	122	return -ENOMEM;
	123	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
	124	mdiodev->read = bfin_miiphy_read;
	125	mdiodev->write = bfin_miiphy_write;
	126
	127	retval = mdio_register(mdiodev);
	128	if (retval < 0)
	129	return retval;
875e0bc6 JH	130
875e0bc6 JH	131	dev->priv = mdiodev;
ac45af4e MF	132	#endif
ac45af4e MF	133
91494731	134	return 0;
26bf7dec AL	135	}
26bf7dec AL	136
10cbe3b6	137	static int bfin_EMAC_send(struct eth_device dev, void packet, int length)
26bf7dec AL	138	{
	139	int i;
	140	int result = 0;
26bf7dec AL	141
	142	if (length <= 0) {
	143	printf("Ethernet: bad packet size: %d\n", length);
	144	goto out;
	145	}
	146
0c714817	147	if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
26bf7dec AL	148	printf("Ethernet: tx DMA error\n");
	149	goto out;
	150	}
	151
0c714817	152	for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
26bf7dec AL	153	if (i > TOUT_LOOP) {
	154	puts("Ethernet: tx time out\n");
	155	goto out;
	156	}
	157	}
	158	txbuf[txIdx]->FrmData->NoBytes = length;
	159	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
	160	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
0c714817 MF	161	bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
	162	bfin_write_DMA2_CONFIG(txdmacfg.data);
	163	bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() \| TE);
26bf7dec AL	164
	165	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
	166	if (i > TOUT_LOOP) {
	167	puts("Ethernet: tx error\n");
	168	goto out;
	169	}
	170	}
	171	result = txbuf[txIdx]->StatusWord;
	172	txbuf[txIdx]->StatusWord = 0;
	173	if ((txIdx + 1) >= TX_BUF_CNT)
	174	txIdx = 0;
	175	else
	176	txIdx++;
395bce4f	177	out:
8eed6ca5	178	debug("BFIN EMAC send: length = %d\n", length);
26bf7dec AL	179	return result;
	180	}
	181
	182	static int bfin_EMAC_recv(struct eth_device *dev)
	183	{
	184	int length = 0;
	185
	186	for (;;) {
	187	if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
	188	length = -1;
	189	break;
	190	}
	191	if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
	192	printf("Ethernet: rx dma overrun\n");
	193	break;
	194	}
	195	if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
	196	printf("Ethernet: rx error\n");
	197	break;
	198	}
	199	length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
	200	if (length <= 4) {
	201	printf("Ethernet: bad frame\n");
	202	break;
	203	}
488feef8 RG	204
	205	debug("%s: len = %d\n", __func__, length - 4);
	206
1fd92db8 JH	207	net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
1fd92db8 JH	208	net_process_received_packet(net_rx_packets[rxIdx], length - 4);
0c714817	209	bfin_write_DMA1_IRQ_STATUS(DMA_DONE \| DMA_ERR);
26bf7dec AL	210	rxbuf[rxIdx]->StatusWord = 0x00000000;
	211	if ((rxIdx + 1) >= PKTBUFSRX)
	212	rxIdx = 0;
	213	else
	214	rxIdx++;
	215	}
	216
	217	return length;
	218	}
	219
	220	/**************************************************************
	221	*
	222	* Ethernet Initialization Routine
	223	*
	224	*************************************************************/
	225
ac45af4e MF	226	/* MDC = SCLK / MDC_freq / 2 - 1 */
	227	#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
	228
8339ad73 MF	229	#ifndef CONFIG_BFIN_MAC_PINS
	230	# ifdef CONFIG_RMII
	231	# define CONFIG_BFIN_MAC_PINS P_RMII0
	232	# else
	233	# define CONFIG_BFIN_MAC_PINS P_MII0
	234	# endif
	235	#endif
	236
ac45af4e MF	237	static int bfin_miiphy_init(struct eth_device dev, int opmode)
ac45af4e MF	238	{
8339ad73	239	const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
875e0bc6	240	int phydat;
ac45af4e	241	size_t count;
875e0bc6	242	struct mii_dev *mdiodev = dev->priv;
ac45af4e MF	243
ac45af4e MF	244	/* Enable PHY output */
0c714817	245	bfin_write_VR_CTL(bfin_read_VR_CTL() \| CLKBUFOE);
ac45af4e MF	246
ac45af4e MF	247	/* Set all the pins to peripheral mode */
8339ad73	248	peripheral_request_list(pins, "bfin_mac");
ac45af4e MF	249
	250	/* Odd word alignment for Receive Frame DMA word */
	251	/* Configure checksum support and rcve frame word alignment */
a7ec6ac8	252	bfin_write_EMAC_SYSCTL(RXDWA \| RXCKS \| SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
ac45af4e MF	253
ac45af4e MF	254	/* turn on auto-negotiation and wait for link to come up */
875e0bc6 JH	255	bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR,
875e0bc6 JH	256	BMCR_ANENABLE);
ac45af4e MF	257	count = 0;
	258	while (1) {
	259	++count;
875e0bc6 JH	260	phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR,
	261	MDIO_DEVAD_NONE, MII_BMSR);
	262	if (phydat < 0)
	263	return phydat;
ac45af4e MF	264	if (phydat & BMSR_LSTATUS)
	265	break;
	266	if (count > 30000) {
	267	printf("%s: link down, check cable\n", dev->name);
	268	return -1;
	269	}
	270	udelay(100);
	271	}
	272
	273	/* see what kind of link we have */
875e0bc6 JH	274	phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE,
	275	MII_LPA);
	276	if (phydat < 0)
	277	return phydat;
ac45af4e MF	278	if (phydat & LPA_DUPLEX)
	279	*opmode = FDMODE;
	280	else
	281	*opmode = 0;
	282
	283	bfin_write_EMAC_MMC_CTL(RSTC \| CROLL);
819ca38f AW	284	bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
819ca38f AW	285	bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
ac45af4e MF	286
ac45af4e MF	287	/* Initialize the TX DMA channel registers */
0c714817 MF	288	bfin_write_DMA2_X_COUNT(0);
	289	bfin_write_DMA2_X_MODIFY(4);
	290	bfin_write_DMA2_Y_COUNT(0);
	291	bfin_write_DMA2_Y_MODIFY(0);
ac45af4e MF	292
ac45af4e MF	293	/* Initialize the RX DMA channel registers */
0c714817 MF	294	bfin_write_DMA1_X_COUNT(0);
	295	bfin_write_DMA1_X_MODIFY(4);
	296	bfin_write_DMA1_Y_COUNT(0);
	297	bfin_write_DMA1_Y_MODIFY(0);
ac45af4e MF	298
	299	return 0;
	300	}
	301
4324dc72 MF	302	static int bfin_EMAC_setup_addr(struct eth_device *dev)
4324dc72 MF	303	{
0c714817	304	bfin_write_EMAC_ADDRLO(
4324dc72 MF	305	dev->enetaddr[0] \|
	306	dev->enetaddr[1] << 8 \|
	307	dev->enetaddr[2] << 16 \|
0c714817 MF	308	dev->enetaddr[3] << 24
	309	);
	310	bfin_write_EMAC_ADDRHI(
4324dc72	311	dev->enetaddr[4] \|
0c714817 MF	312	dev->enetaddr[5] << 8
0c714817 MF	313	);
4324dc72 MF	314	return 0;
	315	}
	316
395bce4f	317	static int bfin_EMAC_init(struct eth_device dev, bd_t bd)
26bf7dec AL	318	{
	319	u32 opmode;
	320	int dat;
	321	int i;
8eed6ca5	322	debug("Eth_init: ......\n");
26bf7dec AL	323
	324	txIdx = 0;
	325	rxIdx = 0;
	326
ac45af4e MF	327	/* Initialize System Register */
ac45af4e MF	328	if (bfin_miiphy_init(dev, &dat) < 0)
26bf7dec AL	329	return -1;
26bf7dec AL	330
ac45af4e	331	/* Initialize EMAC address */
4324dc72	332	bfin_EMAC_setup_addr(dev);
26bf7dec	333
ac45af4e	334	/* Initialize TX and RX buffer */
26bf7dec AL	335	for (i = 0; i < PKTBUFSRX; i++) {
	336	rxbuf[i] = SetupRxBuffer(i);
	337	if (i > 0) {
6d7d4803	338	rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
26bf7dec	339	if (i == (PKTBUFSRX - 1))
6d7d4803	340	rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
26bf7dec AL	341	}
	342	}
	343	for (i = 0; i < TX_BUF_CNT; i++) {
	344	txbuf[i] = SetupTxBuffer(i);
	345	if (i > 0) {
6d7d4803	346	txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
26bf7dec	347	if (i == (TX_BUF_CNT - 1))
6d7d4803	348	txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
26bf7dec AL	349	}
	350	}
	351
	352	/* Set RX DMA */
0c714817 MF	353	bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
0c714817 MF	354	bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
26bf7dec AL	355
26bf7dec AL	356	/* Wait MII done */
ac45af4e	357	bfin_miiphy_wait();
26bf7dec AL	358
	359	/* We enable only RX here */
	360	/* ASTP : Enable Automatic Pad Stripping
	361	PR : Promiscuous Mode for test
	362	PSF : Receive frames with total length less than 64 bytes.
	363	FDMODE : Full Duplex Mode
	364	LB : Internal Loopback for test
	365	RE : Receiver Enable */
	366	if (dat == FDMODE)
	367	opmode = ASTP \| FDMODE \| PSF;
	368	else
	369	opmode = ASTP \| PSF;
	370	opmode \|= RE;
092d2487	371	#ifdef CONFIG_RMII
26bf7dec AL	372	opmode \|= TE \| RMII;
	373	#endif
	374	/* Turn on the EMAC */
0c714817	375	bfin_write_EMAC_OPMODE(opmode);
26bf7dec AL	376	return 0;
	377	}
	378
	379	static void bfin_EMAC_halt(struct eth_device *dev)
	380	{
8eed6ca5	381	debug("Eth_halt: ......\n");
26bf7dec	382	/* Turn off the EMAC */
0c714817	383	bfin_write_EMAC_OPMODE(0);
26bf7dec	384	/* Turn off the EMAC RX DMA */
0c714817 MF	385	bfin_write_DMA1_CONFIG(0);
0c714817 MF	386	bfin_write_DMA2_CONFIG(0);
26bf7dec AL	387	}
26bf7dec AL	388
26bf7dec AL	389	ADI_ETHER_BUFFER *SetupRxBuffer(int no)
	390	{
	391	ADI_ETHER_FRAME_BUFFER *frmbuf;
	392	ADI_ETHER_BUFFER *buf;
	393	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
	394	int total_size = nobytes_buffer + RECV_BUFSIZE;
	395
6d7d4803 MF	396	buf = (void ) (RXBUF_BASE_ADDR + no total_size);
6d7d4803 MF	397	frmbuf = (void ) (RXBUF_BASE_ADDR + no total_size + nobytes_buffer);
26bf7dec AL	398
	399	memset(buf, 0x00, nobytes_buffer);
	400	buf->FrmData = frmbuf;
	401	memset(frmbuf, 0xfe, RECV_BUFSIZE);
	402
	403	/* set up first desc to point to receive frame buffer */
	404	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	405	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	406	buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
	407	buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
	408	buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	409	buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
	410	buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
	411
	412	/* set up second desc to point to status word */
6d7d4803	413	buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
26bf7dec AL	414	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
	415	buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
	416	buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
	417	buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	418	buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
	419	buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
	420	buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
	421
	422	return buf;
	423	}
	424
	425	ADI_ETHER_BUFFER *SetupTxBuffer(int no)
	426	{
	427	ADI_ETHER_FRAME_BUFFER *frmbuf;
	428	ADI_ETHER_BUFFER *buf;
	429	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
	430	int total_size = nobytes_buffer + RECV_BUFSIZE;
	431
6d7d4803 MF	432	buf = (void ) (TXBUF_BASE_ADDR + no total_size);
6d7d4803 MF	433	frmbuf = (void ) (TXBUF_BASE_ADDR + no total_size + nobytes_buffer);
26bf7dec AL	434
	435	memset(buf, 0x00, nobytes_buffer);
	436	buf->FrmData = frmbuf;
	437	memset(frmbuf, 0x00, RECV_BUFSIZE);
	438
	439	/* set up first desc to point to receive frame buffer */
	440	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	441	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	442	buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
	443	buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
	444	buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	445	buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
	446	buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
	447
	448	/* set up second desc to point to status word */
	449	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	450	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
	451	buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
	452	buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
	453	buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
	454	buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
	455	buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
	456	buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
	457
	458	return buf;
	459	}
	460
6d0f6bcf	461	#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
26bf7dec AL	462	int ether_post_test(int flags)
	463	{
	464	uchar buf[64];
	465	int i, value = 0;
	466	int length;
0c714817	467	uint addr;
26bf7dec AL	468
	469	printf("\n--------");
	470	bfin_EMAC_init(NULL, NULL);
	471	/* construct the package */
0c714817 MF	472	addr = bfin_read_EMAC_ADDRLO();
	473	buf[0] = buf[6] = addr;
	474	buf[1] = buf[7] = addr >> 8;
	475	buf[2] = buf[8] = addr >> 16;
	476	buf[3] = buf[9] = addr >> 24;
	477	addr = bfin_read_EMAC_ADDRHI();
	478	buf[4] = buf[10] = addr;
	479	buf[5] = buf[11] = addr >> 8;
26bf7dec AL	480	buf[12] = 0x08; /* Type: ARP */
	481	buf[13] = 0x06;
	482	buf[14] = 0x00; /* Hardware type: Ethernet */
	483	buf[15] = 0x01;
	484	buf[16] = 0x08; /* Protocal type: IP */
	485	buf[17] = 0x00;
	486	buf[18] = 0x06; /* Hardware size */
	487	buf[19] = 0x04; /* Protocol size */
	488	buf[20] = 0x00; /* Opcode: request */
	489	buf[21] = 0x01;
	490
	491	for (i = 0; i < 42; i++)
	492	buf[i + 22] = i;
	493	printf("--------Send 64 bytes......\n");
10cbe3b6	494	bfin_EMAC_send(NULL, buf, 64);
26bf7dec AL	495	for (i = 0; i < 100; i++) {
	496	udelay(10000);
	497	if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
	498	value = 1;
	499	break;
	500	}
	501	}
	502	if (value == 0) {
	503	printf("--------EMAC can't receive any data\n");
	504	eth_halt();
	505	return -1;
	506	}
	507	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
	508	for (i = 0; i < length; i++) {
	509	if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
	510	printf("--------EMAC receive error data!\n");
	511	eth_halt();
	512	return -1;
	513	}
	514	}
	515	printf("--------receive %d bytes, matched\n", length);
	516	bfin_EMAC_halt(NULL);
	517	return 0;
	518	}
	519	#endif