[people/ms/u-boot.git] / drivers / net / bfin_mac.c

/*
 * Driver for Blackfin On-Chip MAC device
 *
 * Copyright (c) 2005-2008 Analog Device, Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
#include <command.h>
#include <malloc.h>

#include <asm/blackfin.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>

#include "bfin_mac.h"

#ifdef CONFIG_POST
#include <post.h>
#endif

#undef DEBUG_ETHERNET

#ifdef DEBUG_ETHERNET
#define DEBUGF(fmt, args...) printf(fmt, ##args)
#else
#define DEBUGF(fmt, args...)
#endif

#define RXBUF_BASE_ADDR		0xFF900000
#define TXBUF_BASE_ADDR		0xFF800000
#define TX_BUF_CNT		1

#define TOUT_LOOP		1000000

ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx;		/* index of the current RX buffer */
static u16 rxIdx;		/* index of the current TX buffer */

u16 PHYregs[NO_PHY_REGS];	/* u16 PHYADDR; */

/* DMAx_CONFIG values at DMA Restart */
const ADI_DMA_CONFIG_REG rxdmacfg = {
	.b_DMA_EN  = 1,	/* enabled */
	.b_WNR     = 1,	/* write to memory */
	.b_WDSIZE  = 2,	/* wordsize is 32 bits */
	.b_DMA2D   = 0,
	.b_RESTART = 0,
	.b_DI_SEL  = 0,
	.b_DI_EN   = 0,	/* no interrupt */
	.b_NDSIZE  = 5,	/* 5 half words is desc size */
	.b_FLOW    = 7	/* large desc flow */
};

const ADI_DMA_CONFIG_REG txdmacfg = {
	.b_DMA_EN  = 1,	/* enabled */
	.b_WNR     = 0,	/* read from memory */
	.b_WDSIZE  = 2,	/* wordsize is 32 bits */
	.b_DMA2D   = 0,
	.b_RESTART = 0,
	.b_DI_SEL  = 0,
	.b_DI_EN   = 0,	/* no interrupt */
	.b_NDSIZE  = 5,	/* 5 half words is desc size */
	.b_FLOW    = 7	/* large desc flow */
};

int bfin_EMAC_initialize(bd_t *bis)
{
	struct eth_device *dev;
	dev = (struct eth_device *)malloc(sizeof(*dev));
	if (dev == NULL)
		hang();

	memset(dev, 0, sizeof(*dev));
	sprintf(dev->name, "Blackfin EMAC");

	dev->iobase = 0;
	dev->priv = 0;
	dev->init = bfin_EMAC_init;
	dev->halt = bfin_EMAC_halt;
	dev->send = bfin_EMAC_send;
	dev->recv = bfin_EMAC_recv;

	eth_register(dev);

	return 0;
}

static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
			  int length)
{
	int i;
	int result = 0;
	unsigned int *buf;
	buf = (unsigned int *)packet;

	if (length <= 0) {
		printf("Ethernet: bad packet size: %d\n", length);
		goto out;
	}

	if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
		printf("Ethernet: tx DMA error\n");
		goto out;
	}

	for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
		if (i > TOUT_LOOP) {
			puts("Ethernet: tx time out\n");
			goto out;
		}
	}
	txbuf[txIdx]->FrmData->NoBytes = length;
	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
	*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
	*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
	*pEMAC_OPMODE |= TE;

	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
		if (i > TOUT_LOOP) {
			puts("Ethernet: tx error\n");
			goto out;
		}
	}
	result = txbuf[txIdx]->StatusWord;
	txbuf[txIdx]->StatusWord = 0;
	if ((txIdx + 1) >= TX_BUF_CNT)
		txIdx = 0;
	else
		txIdx++;
 out:
	DEBUGF("BFIN EMAC send: length = %d\n", length);
	return result;
}

static int bfin_EMAC_recv(struct eth_device *dev)
{
	int length = 0;

	for (;;) {
		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
			length = -1;
			break;
		}
		if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
			printf("Ethernet: rx dma overrun\n");
			break;
		}
		if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
			printf("Ethernet: rx error\n");
			break;
		}
		length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
		if (length <= 4) {
			printf("Ethernet: bad frame\n");
			break;
		}
		NetRxPackets[rxIdx] =
		    (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
		NetReceive(NetRxPackets[rxIdx], length - 4);
		*pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
		rxbuf[rxIdx]->StatusWord = 0x00000000;
		if ((rxIdx + 1) >= PKTBUFSRX)
			rxIdx = 0;
		else
			rxIdx++;
	}

	return length;
}

/**************************************************************
 *
 * Ethernet Initialization Routine
 *
 *************************************************************/

static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
{
	u32 opmode;
	int dat;
	int i;
	DEBUGF("Eth_init: ......\n");

	txIdx = 0;
	rxIdx = 0;

/* Initialize System Register */
	if (SetupSystemRegs(&dat) < 0)
		return -1;

/* Initialize EMAC address */
	bfin_EMAC_setup_addr(bd);

/* Initialize TX and RX buffer */
	for (i = 0; i < PKTBUFSRX; i++) {
		rxbuf[i] = SetupRxBuffer(i);
		if (i > 0) {
			rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
			    &(rxbuf[i]->Dma[0]);
			if (i == (PKTBUFSRX - 1))
				rxbuf[i]->Dma[1].NEXT_DESC_PTR =
				    &(rxbuf[0]->Dma[0]);
		}
	}
	for (i = 0; i < TX_BUF_CNT; i++) {
		txbuf[i] = SetupTxBuffer(i);
		if (i > 0) {
			txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
			    &(txbuf[i]->Dma[0]);
			if (i == (TX_BUF_CNT - 1))
				txbuf[i]->Dma[1].NEXT_DESC_PTR =
				    &(txbuf[0]->Dma[0]);
		}
	}

	/* Set RX DMA */
	*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
	*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);

	/* Wait MII done */
	PollMdcDone();

	/* We enable only RX here */
	/* ASTP   : Enable Automatic Pad Stripping
	   PR     : Promiscuous Mode for test
	   PSF    : Receive frames with total length less than 64 bytes.
	   FDMODE : Full Duplex Mode
	   LB	  : Internal Loopback for test
	   RE     : Receiver Enable */
	if (dat == FDMODE)
		opmode = ASTP | FDMODE | PSF;
	else
		opmode = ASTP | PSF;
	opmode |= RE;
#ifdef CONFIG_BFIN_MAC_RMII
	opmode |= TE | RMII;
#endif
	/* Turn on the EMAC */
	*pEMAC_OPMODE = opmode;
	return 0;
}

static void bfin_EMAC_halt(struct eth_device *dev)
{
	DEBUGF("Eth_halt: ......\n");
	/* Turn off the EMAC */
	*pEMAC_OPMODE = 0x00000000;
	/* Turn off the EMAC RX DMA */
	*pDMA1_CONFIG = 0x0000;
	*pDMA2_CONFIG = 0x0000;

}

void bfin_EMAC_setup_addr(bd_t *bd)
{
	*pEMAC_ADDRLO =
		bd->bi_enetaddr[0] |
		bd->bi_enetaddr[1] << 8 |
		bd->bi_enetaddr[2] << 16 |
		bd->bi_enetaddr[3] << 24;
	*pEMAC_ADDRHI =
		bd->bi_enetaddr[4] |
		bd->bi_enetaddr[5] << 8;
}

static void PollMdcDone(void)
{
	/* poll the STABUSY bit */
	while (*pEMAC_STAADD & STABUSY) ;
}

static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
{
	PollMdcDone();

	*pEMAC_STADAT = Data;

	*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
	    STAOP | STAIE | STABUSY;
}

/*********************************************************************************
 *		Read an off-chip register in a PHY through the MDC/MDIO port     *
 *********************************************************************************/
static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
{
	u16 Data;

	PollMdcDone();

	*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
	    STAIE | STABUSY;

	PollMdcDone();

	Data = (u16) * pEMAC_STADAT;

	PHYregs[RegAddr] = Data;	/* save shadow copy */

	return Data;
}

#if 0 /* dead code ? */
static void SoftResetPHY(void)
{
	u16 phydat;
	/* set the reset bit */
	WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
	/* and clear it again */
	WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
	do {
		/* poll until reset is complete */
		phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
	} while ((phydat & PHY_RESET) != 0);
}
#endif

static int SetupSystemRegs(int *opmode)
{
	u16 sysctl, phydat;
	int count = 0;
	/* Enable PHY output */
	*pVR_CTL |= CLKBUFOE;
	/* Set all the pins to peripheral mode */

#ifndef CONFIG_BFIN_MAC_RMII
	*pPORTH_FER = 0xFFFF;
#ifdef __ADSPBF52x__
	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
#endif
#else
#if defined(__ADSPBF536__) || defined(__ADSPBF537__)
	*pPORTH_FER = 0xC373;
#endif
#ifdef __ADSPBF52x__
	*pPORTH_FER = 0x01FF;
	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
#endif
#endif
	/* MDC  = 2.5 MHz */
	sysctl = SET_MDCDIV(24);
	/* Odd word alignment for Receive Frame DMA word */
	/* Configure checksum support and rcve frame word alignment */
	sysctl |= RXDWA | RXCKS;
	*pEMAC_SYSCTL = sysctl;
	/* auto negotiation on  */
	/* full duplex */
	/* 100 Mbps */
	phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
	WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
	do {
		udelay(1000);
		phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
		if (count > 3000) {
			printf
			    ("Link is down, please check your network connection\n");
			return -1;
		}
		count++;
	} while (!(phydat & 0x0004));

	phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);

	if ((phydat & 0x0100) || (phydat & 0x0040))
		*opmode = FDMODE;
	else
		*opmode = 0;

	*pEMAC_MMC_CTL = RSTC | CROLL;

	/* Initialize the TX DMA channel registers */
	*pDMA2_X_COUNT = 0;
	*pDMA2_X_MODIFY = 4;
	*pDMA2_Y_COUNT = 0;
	*pDMA2_Y_MODIFY = 0;

	/* Initialize the RX DMA channel registers */
	*pDMA1_X_COUNT = 0;
	*pDMA1_X_MODIFY = 4;
	*pDMA1_Y_COUNT = 0;
	*pDMA1_Y_MODIFY = 0;
	return 0;
}

ADI_ETHER_BUFFER *SetupRxBuffer(int no)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
	int total_size = nobytes_buffer + RECV_BUFSIZE;

	buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
	frmbuf =
	    (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
					nobytes_buffer);

	memset(buf, 0x00, nobytes_buffer);
	buf->FrmData = frmbuf;
	memset(frmbuf, 0xfe, RECV_BUFSIZE);

	/* set up first desc to point to receive frame buffer */
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[0].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */

	/* set up second desc to point to status word */
	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
	buf->Dma[1].CONFIG.b_NDSIZE = 5;	/* must be 0 when FLOW is 0 */
	buf->Dma[1].CONFIG.b_FLOW = 7;	/* stop */

	return buf;
}

ADI_ETHER_BUFFER *SetupTxBuffer(int no)
{
	ADI_ETHER_FRAME_BUFFER *frmbuf;
	ADI_ETHER_BUFFER *buf;
	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
	int total_size = nobytes_buffer + RECV_BUFSIZE;

	buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
	frmbuf =
	    (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
					nobytes_buffer);

	memset(buf, 0x00, nobytes_buffer);
	buf->FrmData = frmbuf;
	memset(frmbuf, 0x00, RECV_BUFSIZE);

	/* set up first desc to point to receive frame buffer */
	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[0].CONFIG.b_WNR = 0;	/* Read to memory */
	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */

	/* set up second desc to point to status word */
	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
	buf->Dma[1].CONFIG.b_NDSIZE = 0;	/* must be 0 when FLOW is 0 */
	buf->Dma[1].CONFIG.b_FLOW = 0;	/* stop */

	return buf;
}

#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
int ether_post_test(int flags)
{
	uchar buf[64];
	int i, value = 0;
	int length;

	printf("\n--------");
	bfin_EMAC_init(NULL, NULL);
	/* construct the package */
	buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
	buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
	buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
	buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
	buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
	buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
	buf[12] = 0x08;		/* Type: ARP */
	buf[13] = 0x06;
	buf[14] = 0x00;		/* Hardware type: Ethernet */
	buf[15] = 0x01;
	buf[16] = 0x08;		/* Protocal type: IP */
	buf[17] = 0x00;
	buf[18] = 0x06;		/* Hardware size    */
	buf[19] = 0x04;		/* Protocol size    */
	buf[20] = 0x00;		/* Opcode: request  */
	buf[21] = 0x01;

	for (i = 0; i < 42; i++)
		buf[i + 22] = i;
	printf("--------Send 64 bytes......\n");
	bfin_EMAC_send(NULL, (volatile void *)buf, 64);
	for (i = 0; i < 100; i++) {
		udelay(10000);
		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
			value = 1;
			break;
		}
	}
	if (value == 0) {
		printf("--------EMAC can't receive any data\n");
		eth_halt();
		return -1;
	}
	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
	for (i = 0; i < length; i++) {
		if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
			printf("--------EMAC receive error data!\n");
			eth_halt();
			return -1;
		}
	}
	printf("--------receive %d bytes, matched\n", length);
	bfin_EMAC_halt(NULL);
	return 0;
}
#endif
Commit	Line	Data
26bf7dec	1	/*
395bce4f	2	* Driver for Blackfin On-Chip MAC device
26bf7dec	3	*
395bce4f	4	* Copyright (c) 2005-2008 Analog Device, Inc.
26bf7dec	5	*
395bce4f	6	* Licensed under the GPL-2 or later.
26bf7dec AL	7	*/
	8
	9	#include <common.h>
	10	#include <config.h>
26bf7dec	11	#include <net.h>
89973f8a	12	#include <netdev.h>
26bf7dec AL	13	#include <command.h>
26bf7dec AL	14	#include <malloc.h>
26bf7dec	15
395bce4f	16	#include <asm/blackfin.h>
d4d77308 MF	17	#include <asm/mach-common/bits/dma.h>
	18	#include <asm/mach-common/bits/emac.h>
	19	#include <asm/mach-common/bits/pll.h>
	20
395bce4f MF	21	#include "bfin_mac.h"
395bce4f MF	22
26bf7dec AL	23	#ifdef CONFIG_POST
	24	#include <post.h>
	25	#endif
	26
	27	#undef DEBUG_ETHERNET
	28
	29	#ifdef DEBUG_ETHERNET
395bce4f	30	#define DEBUGF(fmt, args...) printf(fmt, ##args)
26bf7dec	31	#else
395bce4f	32	#define DEBUGF(fmt, args...)
26bf7dec AL	33	#endif
26bf7dec AL	34
26bf7dec AL	35	#define RXBUF_BASE_ADDR 0xFF900000
	36	#define TXBUF_BASE_ADDR 0xFF800000
	37	#define TX_BUF_CNT 1
	38
53677ef1	39	#define TOUT_LOOP 1000000
26bf7dec AL	40
	41	ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
	42	ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
	43	static u16 txIdx; /* index of the current RX buffer */
	44	static u16 rxIdx; /* index of the current TX buffer */
	45
26bf7dec AL	46	u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
	47
	48	/* DMAx_CONFIG values at DMA Restart */
395bce4f MF	49	const ADI_DMA_CONFIG_REG rxdmacfg = {
	50	.b_DMA_EN = 1, /* enabled */
	51	.b_WNR = 1, /* write to memory */
	52	.b_WDSIZE = 2, /* wordsize is 32 bits */
	53	.b_DMA2D = 0,
	54	.b_RESTART = 0,
	55	.b_DI_SEL = 0,
	56	.b_DI_EN = 0, /* no interrupt */
	57	.b_NDSIZE = 5, /* 5 half words is desc size */
	58	.b_FLOW = 7 /* large desc flow */
	59	};
	60
	61	const ADI_DMA_CONFIG_REG txdmacfg = {
	62	.b_DMA_EN = 1, /* enabled */
	63	.b_WNR = 0, /* read from memory */
	64	.b_WDSIZE = 2, /* wordsize is 32 bits */
	65	.b_DMA2D = 0,
	66	.b_RESTART = 0,
	67	.b_DI_SEL = 0,
	68	.b_DI_EN = 0, /* no interrupt */
	69	.b_NDSIZE = 5, /* 5 half words is desc size */
	70	.b_FLOW = 7 /* large desc flow */
	71	};
	72
	73	int bfin_EMAC_initialize(bd_t *bis)
26bf7dec AL	74	{
	75	struct eth_device *dev;
	76	dev = (struct eth_device )malloc(sizeof(dev));
	77	if (dev == NULL)
	78	hang();
	79
	80	memset(dev, 0, sizeof(*dev));
395bce4f	81	sprintf(dev->name, "Blackfin EMAC");
26bf7dec AL	82
	83	dev->iobase = 0;
	84	dev->priv = 0;
	85	dev->init = bfin_EMAC_init;
	86	dev->halt = bfin_EMAC_halt;
	87	dev->send = bfin_EMAC_send;
	88	dev->recv = bfin_EMAC_recv;
	89
	90	eth_register(dev);
	91
91494731	92	return 0;
26bf7dec AL	93	}
	94
	95	static int bfin_EMAC_send(struct eth_device dev, volatile void packet,
	96	int length)
	97	{
	98	int i;
	99	int result = 0;
	100	unsigned int *buf;
	101	buf = (unsigned int *)packet;
	102
	103	if (length <= 0) {
	104	printf("Ethernet: bad packet size: %d\n", length);
	105	goto out;
	106	}
	107
	108	if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
	109	printf("Ethernet: tx DMA error\n");
	110	goto out;
	111	}
	112
	113	for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
	114	if (i > TOUT_LOOP) {
	115	puts("Ethernet: tx time out\n");
	116	goto out;
	117	}
	118	}
	119	txbuf[txIdx]->FrmData->NoBytes = length;
	120	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
	121	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
	122	*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
	123	pDMA2_CONFIG = (u16 ) (void )(&txdmacfg);
	124	*pEMAC_OPMODE \|= TE;
	125
	126	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
	127	if (i > TOUT_LOOP) {
	128	puts("Ethernet: tx error\n");
	129	goto out;
	130	}
	131	}
	132	result = txbuf[txIdx]->StatusWord;
	133	txbuf[txIdx]->StatusWord = 0;
	134	if ((txIdx + 1) >= TX_BUF_CNT)
	135	txIdx = 0;
	136	else
	137	txIdx++;
395bce4f	138	out:
26bf7dec AL	139	DEBUGF("BFIN EMAC send: length = %d\n", length);
	140	return result;
	141	}
	142
	143	static int bfin_EMAC_recv(struct eth_device *dev)
	144	{
	145	int length = 0;
	146
	147	for (;;) {
	148	if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
	149	length = -1;
	150	break;
	151	}
	152	if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
	153	printf("Ethernet: rx dma overrun\n");
	154	break;
	155	}
	156	if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
	157	printf("Ethernet: rx error\n");
	158	break;
	159	}
	160	length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
	161	if (length <= 4) {
	162	printf("Ethernet: bad frame\n");
	163	break;
	164	}
	165	NetRxPackets[rxIdx] =
	166	(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
	167	NetReceive(NetRxPackets[rxIdx], length - 4);
	168	*pDMA1_IRQ_STATUS \|= DMA_DONE \| DMA_ERR;
	169	rxbuf[rxIdx]->StatusWord = 0x00000000;
	170	if ((rxIdx + 1) >= PKTBUFSRX)
	171	rxIdx = 0;
	172	else
	173	rxIdx++;
	174	}
	175
	176	return length;
	177	}
	178
	179	/**************************************************************
	180	*
	181	* Ethernet Initialization Routine
	182	*
	183	*************************************************************/
	184
395bce4f	185	static int bfin_EMAC_init(struct eth_device dev, bd_t bd)
26bf7dec AL	186	{
	187	u32 opmode;
	188	int dat;
	189	int i;
	190	DEBUGF("Eth_init: ......\n");
	191
	192	txIdx = 0;
	193	rxIdx = 0;
	194
	195	/* Initialize System Register */
	196	if (SetupSystemRegs(&dat) < 0)
	197	return -1;
	198
	199	/* Initialize EMAC address */
395bce4f	200	bfin_EMAC_setup_addr(bd);
26bf7dec AL	201
	202	/* Initialize TX and RX buffer */
	203	for (i = 0; i < PKTBUFSRX; i++) {
	204	rxbuf[i] = SetupRxBuffer(i);
	205	if (i > 0) {
	206	rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
	207	&(rxbuf[i]->Dma[0]);
	208	if (i == (PKTBUFSRX - 1))
	209	rxbuf[i]->Dma[1].NEXT_DESC_PTR =
	210	&(rxbuf[0]->Dma[0]);
	211	}
	212	}
	213	for (i = 0; i < TX_BUF_CNT; i++) {
	214	txbuf[i] = SetupTxBuffer(i);
	215	if (i > 0) {
	216	txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
	217	&(txbuf[i]->Dma[0]);
	218	if (i == (TX_BUF_CNT - 1))
	219	txbuf[i]->Dma[1].NEXT_DESC_PTR =
	220	&(txbuf[0]->Dma[0]);
	221	}
	222	}
	223
	224	/* Set RX DMA */
	225	*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
	226	pDMA1_CONFIG = ((u16 ) (void )&rxbuf[0]->Dma[0].CONFIG);
	227
	228	/* Wait MII done */
	229	PollMdcDone();
	230
	231	/* We enable only RX here */
	232	/* ASTP : Enable Automatic Pad Stripping
	233	PR : Promiscuous Mode for test
	234	PSF : Receive frames with total length less than 64 bytes.
	235	FDMODE : Full Duplex Mode
	236	LB : Internal Loopback for test
	237	RE : Receiver Enable */
	238	if (dat == FDMODE)
	239	opmode = ASTP \| FDMODE \| PSF;
	240	else
	241	opmode = ASTP \| PSF;
	242	opmode \|= RE;
	243	#ifdef CONFIG_BFIN_MAC_RMII
	244	opmode \|= TE \| RMII;
	245	#endif
	246	/* Turn on the EMAC */
	247	*pEMAC_OPMODE = opmode;
	248	return 0;
	249	}
	250
	251	static void bfin_EMAC_halt(struct eth_device *dev)
	252	{
	253	DEBUGF("Eth_halt: ......\n");
	254	/* Turn off the EMAC */
	255	*pEMAC_OPMODE = 0x00000000;
	256	/* Turn off the EMAC RX DMA */
	257	*pDMA1_CONFIG = 0x0000;
	258	*pDMA2_CONFIG = 0x0000;
	259
	260	}
	261
395bce4f	262	void bfin_EMAC_setup_addr(bd_t *bd)
26bf7dec	263	{
395bce4f MF	264	*pEMAC_ADDRLO =
	265	bd->bi_enetaddr[0] \|
	266	bd->bi_enetaddr[1] << 8 \|
	267	bd->bi_enetaddr[2] << 16 \|
	268	bd->bi_enetaddr[3] << 24;
	269	*pEMAC_ADDRHI =
	270	bd->bi_enetaddr[4] \|
	271	bd->bi_enetaddr[5] << 8;
26bf7dec AL	272	}
26bf7dec AL	273
395bce4f	274	static void PollMdcDone(void)
26bf7dec AL	275	{
	276	/* poll the STABUSY bit */
	277	while (*pEMAC_STAADD & STABUSY) ;
	278	}
	279
395bce4f	280	static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
26bf7dec AL	281	{
	282	PollMdcDone();
	283
	284	*pEMAC_STADAT = Data;
	285
	286	*pEMAC_STAADD = SET_PHYAD(PHYAddr) \| SET_REGAD(RegAddr) \|
	287	STAOP \| STAIE \| STABUSY;
	288	}
	289
	290	/*********************************************************************************
	291	* Read an off-chip register in a PHY through the MDC/MDIO port *
	292	*********************************************************************************/
395bce4f	293	static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
26bf7dec AL	294	{
	295	u16 Data;
	296
	297	PollMdcDone();
	298
	299	*pEMAC_STAADD = SET_PHYAD(PHYAddr) \| SET_REGAD(RegAddr) \|
	300	STAIE \| STABUSY;
	301
	302	PollMdcDone();
	303
	304	Data = (u16) * pEMAC_STADAT;
	305
	306	PHYregs[RegAddr] = Data; /* save shadow copy */
	307
	308	return Data;
	309	}
	310
395bce4f MF	311	#if 0 /* dead code ? */
395bce4f MF	312	static void SoftResetPHY(void)
26bf7dec AL	313	{
	314	u16 phydat;
	315	/* set the reset bit */
	316	WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
	317	/* and clear it again */
	318	WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
	319	do {
	320	/* poll until reset is complete */
	321	phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
	322	} while ((phydat & PHY_RESET) != 0);
	323	}
395bce4f	324	#endif
26bf7dec	325
395bce4f	326	static int SetupSystemRegs(int *opmode)
26bf7dec AL	327	{
	328	u16 sysctl, phydat;
	329	int count = 0;
	330	/* Enable PHY output */
d4d77308	331	*pVR_CTL \|= CLKBUFOE;
395bce4f MF	332	/* Set all the pins to peripheral mode */
	333
	334	#ifndef CONFIG_BFIN_MAC_RMII
	335	*pPORTH_FER = 0xFFFF;
	336	#ifdef __ADSPBF52x__
	337	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 \| PORT_x_MUX_1_FUNC_2 \| PORT_x_MUX_2_FUNC_2;
	338	#endif
	339	#else
	340	#if defined(__ADSPBF536__) \|\| defined(__ADSPBF537__)
	341	*pPORTH_FER = 0xC373;
	342	#endif
	343	#ifdef __ADSPBF52x__
	344	*pPORTH_FER = 0x01FF;
	345	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 \| PORT_x_MUX_1_FUNC_2;
	346	#endif
	347	#endif
26bf7dec AL	348	/* MDC = 2.5 MHz */
	349	sysctl = SET_MDCDIV(24);
	350	/* Odd word alignment for Receive Frame DMA word */
	351	/* Configure checksum support and rcve frame word alignment */
	352	sysctl \|= RXDWA \| RXCKS;
	353	*pEMAC_SYSCTL = sysctl;
	354	/* auto negotiation on */
	355	/* full duplex */
	356	/* 100 Mbps */
	357	phydat = PHY_ANEG_EN \| PHY_DUPLEX \| PHY_SPD_SET;
	358	WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
	359	do {
	360	udelay(1000);
	361	phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
	362	if (count > 3000) {
	363	printf
	364	("Link is down, please check your network connection\n");
	365	return -1;
	366	}
	367	count++;
	368	} while (!(phydat & 0x0004));
	369
	370	phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
	371
	372	if ((phydat & 0x0100) \|\| (phydat & 0x0040))
	373	*opmode = FDMODE;
	374	else
	375	*opmode = 0;
	376
	377	*pEMAC_MMC_CTL = RSTC \| CROLL;
	378
	379	/* Initialize the TX DMA channel registers */
	380	*pDMA2_X_COUNT = 0;
	381	*pDMA2_X_MODIFY = 4;
	382	*pDMA2_Y_COUNT = 0;
	383	*pDMA2_Y_MODIFY = 0;
	384
	385	/* Initialize the RX DMA channel registers */
	386	*pDMA1_X_COUNT = 0;
	387	*pDMA1_X_MODIFY = 4;
	388	*pDMA1_Y_COUNT = 0;
	389	*pDMA1_Y_MODIFY = 0;
	390	return 0;
	391	}
	392
	393	ADI_ETHER_BUFFER *SetupRxBuffer(int no)
	394	{
	395	ADI_ETHER_FRAME_BUFFER *frmbuf;
	396	ADI_ETHER_BUFFER *buf;
	397	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
	398	int total_size = nobytes_buffer + RECV_BUFSIZE;
	399
	400	buf = (ADI_ETHER_BUFFER ) (RXBUF_BASE_ADDR + no total_size);
	401	frmbuf =
	402	(ADI_ETHER_FRAME_BUFFER ) (RXBUF_BASE_ADDR + no total_size +
	403	nobytes_buffer);
	404
	405	memset(buf, 0x00, nobytes_buffer);
	406	buf->FrmData = frmbuf;
	407	memset(frmbuf, 0xfe, RECV_BUFSIZE);
	408
	409	/* set up first desc to point to receive frame buffer */
	410	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
	411	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
412	buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
413	buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
414	buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
415	buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
416	buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
417
418	/* set up second desc to point to status word */
419	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
420	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
421	buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
422	buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
423	buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
424	buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
425	buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
426	buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
427
428	return buf;
429	}
430
431	ADI_ETHER_BUFFER *SetupTxBuffer(int no)
432	{
433	ADI_ETHER_FRAME_BUFFER *frmbuf;
434	ADI_ETHER_BUFFER *buf;
435	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
436	int total_size = nobytes_buffer + RECV_BUFSIZE;
437
438	buf = (ADI_ETHER_BUFFER ) (TXBUF_BASE_ADDR + no total_size);
439	frmbuf =
440	(ADI_ETHER_FRAME_BUFFER ) (TXBUF_BASE_ADDR + no total_size +
441	nobytes_buffer);
442
443	memset(buf, 0x00, nobytes_buffer);
444	buf->FrmData = frmbuf;
445	memset(frmbuf, 0x00, RECV_BUFSIZE);
446
447	/* set up first desc to point to receive frame buffer */
448	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
449	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
450	buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
451	buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
452	buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
453	buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
454	buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
455
456	/* set up second desc to point to status word */
457	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
458	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
459	buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
460	buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
461	buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
462	buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
463	buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
464	buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
465
466	return buf;
467	}
468
6d0f6bcf	469	#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
26bf7dec AL	470	int ether_post_test(int flags)
	471	{
	472	uchar buf[64];
	473	int i, value = 0;
	474	int length;
	475
	476	printf("\n--------");
	477	bfin_EMAC_init(NULL, NULL);
	478	/* construct the package */
	479	buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
	480	buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
	481	buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
	482	buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
	483	buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
	484	buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
	485	buf[12] = 0x08; /* Type: ARP */
	486	buf[13] = 0x06;
	487	buf[14] = 0x00; /* Hardware type: Ethernet */
	488	buf[15] = 0x01;
	489	buf[16] = 0x08; /* Protocal type: IP */
	490	buf[17] = 0x00;
	491	buf[18] = 0x06; /* Hardware size */
	492	buf[19] = 0x04; /* Protocol size */
	493	buf[20] = 0x00; /* Opcode: request */
	494	buf[21] = 0x01;
	495
	496	for (i = 0; i < 42; i++)
	497	buf[i + 22] = i;
	498	printf("--------Send 64 bytes......\n");
	499	bfin_EMAC_send(NULL, (volatile void *)buf, 64);
	500	for (i = 0; i < 100; i++) {
	501	udelay(10000);
	502	if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
	503	value = 1;
	504	break;
	505	}
	506	}
	507	if (value == 0) {
	508	printf("--------EMAC can't receive any data\n");
	509	eth_halt();
	510	return -1;
	511	}
	512	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
	513	for (i = 0; i < length; i++) {
	514	if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
	515	printf("--------EMAC receive error data!\n");
	516	eth_halt();
	517	return -1;
	518	}
	519	}
	520	printf("--------receive %d bytes, matched\n", length);
	521	bfin_EMAC_halt(NULL);
	522	return 0;
	523	}
	524	#endif