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bnx2x: init fw_seq after undi_unload is done
[thirdparty/linux.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea 41#include <net/ip.h>
619c5cb6 42#include <net/ipv6.h>
a2fbb9ea
ET		 43#include <net/tcp.h>
44#include <net/checksum.h>
34f80b04 45#include <net/ip6_checksum.h>
a2fbb9ea
ET		 46#include <linux/workqueue.h>
47#include <linux/crc32.h>
34f80b04 48#include <linux/crc32c.h>
a2fbb9ea
ET		 49#include <linux/prefetch.h>
50#include <linux/zlib.h>
a2fbb9ea 51#include <linux/io.h>
45229b42 52#include <linux/stringify.h>
7ab24bfd 53#include <linux/vmalloc.h>
a2fbb9ea 54
a2fbb9ea
ET		 55#include "bnx2x.h"
56#include "bnx2x_init.h"
94a78b79 57#include "bnx2x_init_ops.h"
9f6c9258 58#include "bnx2x_cmn.h"
e4901dde 59#include "bnx2x_dcb.h"
042181f5 60#include "bnx2x_sp.h"
a2fbb9ea 61
94a78b79
VZ		 62#include <linux/firmware.h>
63#include "bnx2x_fw_file_hdr.h"
64/* FW files */
45229b42
BH		 65#define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 70#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 72#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 73
34f80b04
EG		 74/* Time in jiffies before concluding the transmitter is hung */
75#define TX_TIMEOUT (5*HZ)
a2fbb9ea 76
53a10565 77static char version[] __devinitdata =
619c5cb6 78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80
24e3fcef 81MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 82MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
a2fbb9ea
ET		 86MODULE_LICENSE("GPL");
87MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 88MODULE_FIRMWARE(FW_FILE_NAME_E1);
89MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 90MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 91
555f6c78
EG		 92static int multi_mode = 1;
93module_param(multi_mode, int, 0);
ca00392c
EG		 94MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
96
d6214d7a 97int num_queues;
54b9ddaa
VZ		 98module_param(num_queues, int, 0);
99MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
19680c48 103module_param(disable_tpa, int, 0);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
9ee3d37b
DK		 106#define INT_MODE_INTx 1
107#define INT_MODE_MSI 2
8badd27a
EG		 108static int int_mode;
109module_param(int_mode, int, 0);
619c5cb6 110MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 111 "(1 INT#x; 2 MSI)");
8badd27a 112
a18f5128
EG		 113static int dropless_fc;
114module_param(dropless_fc, int, 0);
115MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
9898f86d 117static int poll;
a2fbb9ea 118module_param(poll, int, 0);
9898f86d 119MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 120
121static int mrrs = -1;
122module_param(mrrs, int, 0);
123MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
124
9898f86d 125static int debug;
a2fbb9ea 126module_param(debug, int, 0);
9898f86d
EG		 127MODULE_PARM_DESC(debug, " Default debug msglevel");
128
a2fbb9ea 129
619c5cb6
VZ		 130
131struct workqueue_struct *bnx2x_wq;
ec6ba945 132
a2fbb9ea
ET		 133enum bnx2x_board_type {
134 BCM57710 = 0,
619c5cb6
VZ		 135 BCM57711,
136 BCM57711E,
137 BCM57712,
138 BCM57712_MF,
139 BCM57800,
140 BCM57800_MF,
141 BCM57810,
142 BCM57810_MF,
143 BCM57840,
144 BCM57840_MF
a2fbb9ea
ET		 145};
146
34f80b04 147/* indexed by board_type, above */
53a10565 148static struct {
a2fbb9ea
ET		 149 char *name;
150} board_info[] __devinitdata = {
619c5cb6
VZ		 151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
a2fbb9ea
ET		 163};
164
619c5cb6
VZ		 165#ifndef PCI_DEVICE_ID_NX2_57710
166#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
167#endif
168#ifndef PCI_DEVICE_ID_NX2_57711
169#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
170#endif
171#ifndef PCI_DEVICE_ID_NX2_57711E
172#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
173#endif
174#ifndef PCI_DEVICE_ID_NX2_57712
175#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
176#endif
177#ifndef PCI_DEVICE_ID_NX2_57712_MF
178#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
179#endif
180#ifndef PCI_DEVICE_ID_NX2_57800
181#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
182#endif
183#ifndef PCI_DEVICE_ID_NX2_57800_MF
184#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57810
187#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57810_MF
190#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57840
193#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57840_MF
196#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
197#endif
a3aa1884 198static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
a2fbb9ea
ET		 210 { 0 }
211};
212
213MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
214
215/****************************************************************************
216* General service functions
217****************************************************************************/
218
619c5cb6
VZ		 219static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
221{
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
224}
225
226static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
228{
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
231
232 __storm_memset_dma_mapping(bp, addr, mapping);
233}
234
235static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
236 u16 pf_id)
523224a3 237{
619c5cb6
VZ		 238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
239 pf_id);
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
241 pf_id);
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
243 pf_id);
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
245 pf_id);
523224a3
DK		 246}
247
619c5cb6
VZ		 248static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
249 u8 enable)
250{
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
252 enable);
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
254 enable);
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
256 enable);
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
258 enable);
259}
523224a3
DK		 260
261static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
263 u16 pfid)
264{
265 size_t size = sizeof(struct event_ring_data);
266
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
268
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
270}
271
272static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
273 u16 pfid)
274{
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
277}
278
a2fbb9ea
ET		 279/* used only at init
280 * locking is done by mcp
281 */
8d96286a 282static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 283{
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
288}
289
a2fbb9ea
ET		 290static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
291{
292 u32 val;
293
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
298
299 return val;
300}
a2fbb9ea 301
f2e0899f
DK		 302#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306#define DMAE_DP_DST_NONE "dst_addr [none]"
307
8d96286a 308static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
309 int msglvl)
f2e0899f
DK		 310{
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
312
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
322 dmae->comp_val);
323 else
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
330 dmae->comp_val);
331 break;
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
340 dmae->comp_val);
341 else
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
348 dmae->comp_val);
349 break;
350 default:
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
354 "dst_addr [none]\n"
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
358 dmae->comp_val);
359 else
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
362 "dst_addr [none]\n"
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
366 dmae->comp_val);
367 break;
368 }
369
370}
371
a2fbb9ea 372/* copy command into DMAE command memory and set DMAE command go */
6c719d00 373void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 374{
375 u32 cmd_offset;
376 int i;
377
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
381
ad8d3948
EG		 382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 384 }
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
386}
387
f2e0899f 388u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 389{
f2e0899f
DK		 390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
391 DMAE_CMD_C_ENABLE);
392}
ad8d3948 393
f2e0899f
DK		 394u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
395{
396 return opcode & ~DMAE_CMD_SRC_RESET;
397}
ad8d3948 398
f2e0899f
DK		 399u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
401{
402 u32 opcode = 0;
403
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 406
f2e0899f
DK		 407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 410 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 413
a2fbb9ea 414#ifdef __BIG_ENDIAN
f2e0899f 415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 416#else
f2e0899f 417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 418#endif
f2e0899f
DK		 419 if (with_comp)
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
421 return opcode;
422}
423
8d96286a 424static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
f2e0899f
DK		 427{
428 memset(dmae, 0, sizeof(struct dmae_command));
429
430 /* set the opcode */
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
433
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
438}
439
440/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 441static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
f2e0899f
DK		 443{
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 446 int rc = 0;
447
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 451
619c5cb6
VZ		 452 /*
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
456 */
6e30dd4e 457 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 458
f2e0899f 459 /* reset completion */
a2fbb9ea
ET		 460 *wb_comp = 0;
461
f2e0899f
DK		 462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 464
f2e0899f 465 /* wait for completion */
a2fbb9ea 466 udelay(5);
f2e0899f 467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
469
ad8d3948 470 if (!cnt) {
c3eefaf6 471 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 472 rc = DMAE_TIMEOUT;
473 goto unlock;
a2fbb9ea 474 }
ad8d3948 475 cnt--;
f2e0899f 476 udelay(50);
a2fbb9ea 477 }
f2e0899f
DK		 478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
480 rc = DMAE_PCI_ERROR;
481 }
482
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 486
f2e0899f 487unlock:
6e30dd4e 488 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 489 return rc;
490}
491
492void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
493 u32 len32)
494{
495 struct dmae_command dmae;
496
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
499
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
503 return;
504 }
505
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
508
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
514 dmae.len = len32;
515
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
517
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 520}
521
c18487ee 522void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 523{
5ff7b6d4 524 struct dmae_command dmae;
ad8d3948
EG		 525
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
528 int i;
529
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
534 return;
535 }
536
f2e0899f
DK		 537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 539
f2e0899f 540 /* fill in addresses and len */
5ff7b6d4
EG		 541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
545 dmae.len = len32;
ad8d3948 546
f2e0899f 547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 548
f2e0899f
DK		 549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 551}
552
8d96286a 553static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
554 u32 addr, u32 len)
573f2035 555{
02e3c6cb 556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 557 int offset = 0;
558
02e3c6cb 559 while (len > dmae_wr_max) {
573f2035 560 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
563 len -= dmae_wr_max;
573f2035
EG		 564 }
565
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
567}
568
ad8d3948
EG		 569/* used only for slowpath so not inlined */
570static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
571{
572 u32 wb_write[2];
573
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 577}
a2fbb9ea 578
ad8d3948
EG		 579#ifdef USE_WB_RD
580static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
581{
582 u32 wb_data[2];
583
584 REG_RD_DMAE(bp, reg, wb_data, 2);
585
586 return HILO_U64(wb_data[0], wb_data[1]);
587}
588#endif
589
a2fbb9ea
ET		 590static int bnx2x_mc_assert(struct bnx2x *bp)
591{
a2fbb9ea 592 char last_idx;
34f80b04
EG		 593 int i, rc = 0;
594 u32 row0, row1, row2, row3;
595
596 /* XSTORM */
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
599 if (last_idx)
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
601
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
604
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
613
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
618 rc++;
619 } else {
620 break;
621 }
622 }
623
624 /* TSTORM */
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
627 if (last_idx)
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
629
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
632
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
641
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
646 rc++;
647 } else {
648 break;
649 }
650 }
651
652 /* CSTORM */
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
655 if (last_idx)
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
657
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
660
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
669
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
674 rc++;
675 } else {
676 break;
677 }
678 }
679
680 /* USTORM */
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
683 if (last_idx)
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
685
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
688
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
697
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
a2fbb9ea
ET		 705 }
706 }
34f80b04 707
a2fbb9ea
ET		 708 return rc;
709}
c14423fe 710
7a25cc73 711void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 712{
7a25cc73 713 u32 addr, val;
a2fbb9ea 714 u32 mark, offset;
4781bfad 715 __be32 data[9];
a2fbb9ea 716 int word;
f2e0899f 717 u32 trace_shmem_base;
2145a920
VZ		 718 if (BP_NOMCP(bp)) {
719 BNX2X_ERR("NO MCP - can not dump\n");
720 return;
721 }
7a25cc73
DK		 722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
726
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 730
f2e0899f
DK		 731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
733 else
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 736 mark = REG_RD(bp, addr);
f2e0899f
DK		 737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 740
7a25cc73 741 printk("%s", lvl);
f2e0899f 742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 743 for (word = 0; word < 8; word++)
cdaa7cb8 744 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 745 data[8] = 0x0;
7995c64e 746 pr_cont("%s", (char *)data);
a2fbb9ea 747 }
cdaa7cb8 748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 749 for (word = 0; word < 8; word++)
cdaa7cb8 750 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 751 data[8] = 0x0;
7995c64e 752 pr_cont("%s", (char *)data);
a2fbb9ea 753 }
7a25cc73
DK		 754 printk("%s" "end of fw dump\n", lvl);
755}
756
757static inline void bnx2x_fw_dump(struct bnx2x *bp)
758{
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 760}
761
6c719d00 762void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 763{
764 int i;
523224a3
DK		 765 u16 j;
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768#ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
6383c0b3 770 u8 cos;
523224a3 771#endif
a2fbb9ea 772
66e855f3
YG		 773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
775
a2fbb9ea
ET		 776 BNX2X_ERR("begin crash dump -----------------\n");
777
8440d2b6
EG		 778 /* Indices */
779 /* Common */
523224a3 780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
619c5cb6
VZ		 781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
789 BNX2X_ERR(" def (");
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
791 pr_cont("0x%x%s",
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
794
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
798 i*sizeof(u32));
799
619c5cb6 800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
523224a3 801 "pf_id(0x%x) vnic_id(0x%x) "
619c5cb6
VZ		 802 "vf_id(0x%x) vf_valid (0x%x) "
803 "state(0x%x)\n",
523224a3
DK		 804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 809 sp_sb_data.p_func.vf_valid,
810 sp_sb_data.state);
523224a3 811
8440d2b6 812
ec6ba945 813 for_each_eth_queue(bp, i) {
a2fbb9ea 814 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 815 int loop;
f2e0899f 816 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 819 CHIP_IS_E1x(bp) ?
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
523224a3 822 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 823 CHIP_IS_E1x(bp) ?
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
6383c0b3 826 u8 data_size, cos;
523224a3 827 u32 *sb_data_p;
6383c0b3 828 struct bnx2x_fp_txdata txdata;
523224a3
DK		 829
830 /* Rx */
cdaa7cb8 831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 832 " rx_comp_prod(0x%x)"
cdaa7cb8 833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 834 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 835 fp->rx_comp_prod,
66e855f3 836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 838 " fp_hc_idx(0x%x)\n",
8440d2b6 839 fp->rx_sge_prod, fp->last_max_sge,
523224a3 840 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 841
523224a3 842 /* Tx */
6383c0b3
AE		 843 for_each_cos_in_tx_queue(fp, cos)
844 {
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
851 txdata.tx_bd_cons,
852 le16_to_cpu(*txdata.tx_cons_sb));
853 }
523224a3 854
619c5cb6
VZ		 855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 857
858 /* host sb data */
859
ec6ba945
VZ		 860#ifdef BCM_CNIC
861 if (IS_FCOE_FP(fp))
862 continue;
863#endif
523224a3
DK		 864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
866 pr_cont("0x%x%s",
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
869
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
872 pr_cont("0x%x%s",
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
875 /* fw sb data */
619c5cb6
VZ		 876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
523224a3 879 data_size /= sizeof(u32);
619c5cb6
VZ		 880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
882 (u32 *)&sb_data_e2;
523224a3
DK		 883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
887 j * sizeof(u32));
888
619c5cb6
VZ		 889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
892 "state(0x%x)\n",
f2e0899f
DK		 893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
f2e0899f 899 } else {
619c5cb6
VZ		 900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
902 "state(0x%x)\n",
f2e0899f
DK		 903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
f2e0899f 909 }
523224a3
DK		 910
911 /* SB_SMs data */
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
917 hc_sm_p[j].__flags,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
922 }
923
924 /* Indecies data */
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
928 hc_index_p[j].flags,
929 hc_index_p[j].timeout);
930 }
8440d2b6 931 }
a2fbb9ea 932
523224a3 933#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 934 /* Rings */
935 /* Rx */
ec6ba945 936 for_each_rx_queue(bp, i) {
8440d2b6 937 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 938
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 941 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
944
c3eefaf6
EG		 945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 947 }
948
3196a88a
EG		 949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
8440d2b6 951 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
954
c3eefaf6
EG		 955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 957 }
958
a2fbb9ea
ET		 959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
963
c3eefaf6
EG		 964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 966 }
967 }
968
8440d2b6 969 /* Tx */
ec6ba945 970 for_each_tx_queue(bp, i) {
8440d2b6 971 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3
AE		 972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
974
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
980
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
984 sw_bd->first_bd);
985 }
8440d2b6 986
6383c0b3
AE		 987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 991
6383c0b3
AE		 992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
993 "[%x:%x:%x:%x]\n",
994 i, cos, j, tx_bd[0], tx_bd[1],
995 tx_bd[2], tx_bd[3]);
996 }
8440d2b6
EG		 997 }
998 }
523224a3 999#endif
34f80b04 1000 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1003}
1004
619c5cb6
VZ		 1005/*
1006 * FLR Support for E2
1007 *
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1009 * initialization.
1010 */
1011#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012#define FLR_WAIT_INTERAVAL 50 /* usec */
1013#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1014
1015struct pbf_pN_buf_regs {
1016 int pN;
1017 u32 init_crd;
1018 u32 crd;
1019 u32 crd_freed;
1020};
1021
1022struct pbf_pN_cmd_regs {
1023 int pN;
1024 u32 lines_occup;
1025 u32 lines_freed;
1026};
1027
1028static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1030 u32 poll_count)
1031{
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1034
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1038
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1042
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1045 if (cur_cnt--) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1049 } else {
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1051 regs->pN);
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1053 regs->pN, crd);
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1056 break;
1057 }
1058 }
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1061}
1062
1063static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1065 u32 poll_count)
1066{
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1069
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1072
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1075
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1077 if (cur_cnt--) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1081 } else {
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1083 regs->pN);
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1085 regs->pN, occup);
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1087 regs->pN, freed);
1088 break;
1089 }
1090 }
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1093}
1094
1095static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1097{
1098 u32 cur_cnt = poll_count;
1099 u32 val;
1100
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1103
1104 return val;
1105}
1106
1107static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1109{
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1111 if (val != 0) {
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1113 return 1;
1114 }
1115 return 0;
1116}
1117
1118static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1119{
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1123
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1126
1127 return FLR_POLL_CNT;
1128}
1129
1130static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1131{
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1151 };
1152
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1158 PBF_REG_CREDIT_Q0 :
1159 PBF_REG_P0_CREDIT,
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1167 PBF_REG_CREDIT_Q1 :
1168 PBF_REG_P1_CREDIT,
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1177 PBF_REG_P4_CREDIT,
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1181 };
1182
1183 int i;
1184
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1188
1189
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1193}
1194
1195#define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1197
1198#define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1200
1201#define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1203
1204
1205static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1206 u32 poll_cnt)
1207{
1208 struct sdm_op_gen op_gen = {0};
1209
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1212 int ret = 0;
1213
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1216 return 1;
1217 }
1218
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1223
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1226
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1229 ret = 1;
1230 }
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1233
1234 return ret;
1235}
1236
1237static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1238{
1239 int pos;
1240 u16 status;
1241
77c98e6a 1242 pos = pci_pcie_cap(dev);
619c5cb6
VZ		 1243 if (!pos)
1244 return false;
1245
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1248}
1249
1250/* PF FLR specific routines
1251*/
1252static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1253{
1254
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1259 poll_cnt))
1260 return 1;
1261
1262
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1267 poll_cnt))
1268 return 1;
1269
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1274 poll_cnt))
1275 return 1;
1276
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1281 poll_cnt))
1282 return 1;
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1286 poll_cnt))
1287 return 1;
1288
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1293 poll_cnt))
1294 return 1;
1295
1296 return 0;
1297}
1298
1299static void bnx2x_hw_enable_status(struct bnx2x *bp)
1300{
1301 u32 val;
1302
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1305
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1308
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1311
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1314
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1317
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1320
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1323
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1326 val);
1327}
1328
1329static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1330{
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1332
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1334
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1337
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1340 return -EBUSY;
1341
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1343
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1346 return -EBUSY;
1347
1348 /* ATC cleanup */
1349
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1352
1353 /* Wait 100ms (not adjusted according to platform) */
1354 msleep(100);
1355
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1359
1360 /* Debug */
1361 bnx2x_hw_enable_status(bp);
1362
1363 /*
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1366 */
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1368
1369 return 0;
1370}
1371
f2e0899f 1372static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1373{
34f80b04 1374 int port = BP_PORT(bp);
a2fbb9ea
ET		 1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1379
1380 if (msix) {
8badd27a
EG		 1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1385 } else if (msi) {
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1390 } else {
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1395
a0fd065c
DK		 1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1398 val, port, addr);
615f8fd9 1399
a0fd065c 1400 REG_WR(bp, addr, val);
615f8fd9 1401
a0fd065c
DK		 1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1403 }
a2fbb9ea
ET		 1404 }
1405
a0fd065c
DK		 1406 if (CHIP_IS_E1(bp))
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1408
8badd27a
EG		 1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1411
1412 REG_WR(bp, addr, val);
37dbbf32
EG		 1413 /*
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1415 */
1416 mmiowb();
1417 barrier();
34f80b04 1418
f2e0899f 1419 if (!CHIP_IS_E1(bp)) {
34f80b04 1420 /* init leading/trailing edge */
fb3bff17 1421 if (IS_MF(bp)) {
3395a033 1422 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1423 if (bp->port.pmf)
4acac6a5
EG		 1424 /* enable nig and gpio3 attention */
1425 val |= 0x1100;
34f80b04
EG		 1426 } else
1427 val = 0xffff;
1428
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1431 }
37dbbf32
EG		 1432
1433 /* Make sure that interrupts are indeed enabled from here on */
1434 mmiowb();
a2fbb9ea
ET		 1435}
1436
f2e0899f
DK		 1437static void bnx2x_igu_int_enable(struct bnx2x *bp)
1438{
1439 u32 val;
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1442
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1444
1445 if (msix) {
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1451 } else if (msi) {
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1457 } else {
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1463 }
1464
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1467
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1469
1470 barrier();
1471
1472 /* init leading/trailing edge */
1473 if (IS_MF(bp)) {
3395a033 1474 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1475 if (bp->port.pmf)
1476 /* enable nig and gpio3 attention */
1477 val |= 0x1100;
1478 } else
1479 val = 0xffff;
1480
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1483
1484 /* Make sure that interrupts are indeed enabled from here on */
1485 mmiowb();
1486}
1487
1488void bnx2x_int_enable(struct bnx2x *bp)
1489{
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1492 else
1493 bnx2x_igu_int_enable(bp);
1494}
1495
1496static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1497{
34f80b04 1498 int port = BP_PORT(bp);
a2fbb9ea
ET		 1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1501
a0fd065c
DK		 1502 /*
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1506 */
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1511 */
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1513
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517 } else
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1522
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1524 val, port, addr);
1525
8badd27a
EG		 1526 /* flush all outstanding writes */
1527 mmiowb();
1528
a2fbb9ea
ET		 1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1532}
1533
f2e0899f
DK		 1534static void bnx2x_igu_int_disable(struct bnx2x *bp)
1535{
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1537
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1541
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1543
1544 /* flush all outstanding writes */
1545 mmiowb();
1546
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1550}
1551
6383c0b3 1552void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1553{
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1556 else
1557 bnx2x_igu_int_disable(bp);
1558}
1559
9f6c9258 1560void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1561{
a2fbb9ea 1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1563 int i, offset;
a2fbb9ea 1564
f8ef6e44
YG		 1565 if (disable_hw)
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1568
1569 /* make sure all ISRs are done */
1570 if (msix) {
8badd27a
EG		 1571 synchronize_irq(bp->msix_table[0].vector);
1572 offset = 1;
37b091ba
MC		 1573#ifdef BCM_CNIC
1574 offset++;
1575#endif
ec6ba945 1576 for_each_eth_queue(bp, i)
754a2f52 1577 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1578 } else
1579 synchronize_irq(bp->pdev->irq);
1580
1581 /* make sure sp_task is not running */
1cf167f2 1582 cancel_delayed_work(&bp->sp_task);
3deb8167 1583 cancel_delayed_work(&bp->period_task);
1cf167f2 1584 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1585}
1586
34f80b04 1587/* fast path */
a2fbb9ea
ET		 1588
1589/*
34f80b04 1590 * General service functions
a2fbb9ea
ET		 1591 */
1592
72fd0718
VZ		 1593/* Return true if succeeded to acquire the lock */
1594static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1595{
1596 u32 lock_status;
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1600
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1602
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1605 DP(NETIF_MSG_HW,
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1608 return false;
72fd0718
VZ		 1609 }
1610
1611 if (func <= 5)
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1613 else
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1616
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1621 return true;
1622
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1624 return false;
1625}
1626
c9ee9206
VZ		 1627/**
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1629 *
1630 * @bp: driver handle
1631 *
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1634 */
1635static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1636{
1637 if (BP_PATH(bp))
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1639 else
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1641}
1642
1643/**
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1645 *
1646 * @bp: driver handle
1647 *
1648 * Tries to aquire a leader lock for cuurent engine.
1649 */
1650static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1651{
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1653}
1654
993ac7b5 1655#ifdef BCM_CNIC
619c5cb6 1656static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1657#endif
3196a88a 1658
619c5cb6 1659void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1660{
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1666
34f80b04 1667 DP(BNX2X_MSG_SP,
a2fbb9ea 1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1669 fp->index, cid, command, bp->state,
34f80b04 1670 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1671
619c5cb6
VZ		 1672 switch (command) {
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1674 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1676 break;
d6cae238 1677
619c5cb6 1678 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1679 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1680 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1681 break;
1682
6383c0b3
AE		 1683 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1684 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1685 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1686 break;
1687
619c5cb6 1688 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1689 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1690 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1691 break;
1692
619c5cb6 1693 case (RAMROD_CMD_ID_ETH_TERMINATE):
d6cae238 1694 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1695 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1696 break;
1697
619c5cb6 1698 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1699 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1700 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1701 break;
619c5cb6
VZ		 1702
1703 default:
1704 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1705 command, fp->index);
1706 return;
523224a3 1707 }
3196a88a 1708
619c5cb6
VZ		 1709 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1710 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1711 /* q_obj->complete_cmd() failure means that this was
1712 * an unexpected completion.
1713 *
1714 * In this case we don't want to increase the bp->spq_left
1715 * because apparently we haven't sent this command the first
1716 * place.
1717 */
1718#ifdef BNX2X_STOP_ON_ERROR
1719 bnx2x_panic();
1720#else
1721 return;
1722#endif
1723
8fe23fbd 1724 smp_mb__before_atomic_inc();
6e30dd4e 1725 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1726 /* push the change in bp->spq_left and towards the memory */
1727 smp_mb__after_atomic_inc();
49d66772 1728
d6cae238
VZ		 1729 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1730
523224a3 1731 return;
a2fbb9ea
ET		 1732}
1733
619c5cb6
VZ		 1734void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1735 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1736{
1737 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1738
1739 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1740 start);
1741}
1742
9f6c9258 1743irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1744{
555f6c78 1745 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1746 u16 status = bnx2x_ack_int(bp);
34f80b04 1747 u16 mask;
ca00392c 1748 int i;
6383c0b3 1749 u8 cos;
a2fbb9ea 1750
34f80b04 1751 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1752 if (unlikely(status == 0)) {
1753 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1754 return IRQ_NONE;
1755 }
f5372251 1756 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1757
3196a88a
EG		 1758#ifdef BNX2X_STOP_ON_ERROR
1759 if (unlikely(bp->panic))
1760 return IRQ_HANDLED;
1761#endif
1762
ec6ba945 1763 for_each_eth_queue(bp, i) {
ca00392c 1764 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1765
6383c0b3 1766 mask = 0x2 << (fp->index + CNIC_PRESENT);
ca00392c 1767 if (status & mask) {
619c5cb6 1768 /* Handle Rx or Tx according to SB id */
54b9ddaa 1769 prefetch(fp->rx_cons_sb);
6383c0b3
AE		 1770 for_each_cos_in_tx_queue(fp, cos)
1771 prefetch(fp->txdata[cos].tx_cons_sb);
523224a3 1772 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1773 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1774 status &= ~mask;
1775 }
a2fbb9ea
ET		 1776 }
1777
993ac7b5 1778#ifdef BCM_CNIC
523224a3 1779 mask = 0x2;
993ac7b5
MC		 1780 if (status & (mask | 0x1)) {
1781 struct cnic_ops *c_ops = NULL;
1782
619c5cb6
VZ		 1783 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1784 rcu_read_lock();
1785 c_ops = rcu_dereference(bp->cnic_ops);
1786 if (c_ops)
1787 c_ops->cnic_handler(bp->cnic_data, NULL);
1788 rcu_read_unlock();
1789 }
993ac7b5
MC		 1790
1791 status &= ~mask;
1792 }
1793#endif
a2fbb9ea 1794
34f80b04 1795 if (unlikely(status & 0x1)) {
1cf167f2 1796 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1797
1798 status &= ~0x1;
1799 if (!status)
1800 return IRQ_HANDLED;
1801 }
1802
cdaa7cb8
VZ		 1803 if (unlikely(status))
1804 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1805 status);
a2fbb9ea 1806
c18487ee 1807 return IRQ_HANDLED;
a2fbb9ea
ET		 1808}
1809
c18487ee
YR		 1810/* Link */
1811
1812/*
1813 * General service functions
1814 */
a2fbb9ea 1815
9f6c9258 1816int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1817{
1818 u32 lock_status;
1819 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1820 int func = BP_FUNC(bp);
1821 u32 hw_lock_control_reg;
c18487ee 1822 int cnt;
a2fbb9ea 1823
c18487ee
YR		 1824 /* Validating that the resource is within range */
1825 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1826 DP(NETIF_MSG_HW,
1827 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1828 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1829 return -EINVAL;
1830 }
a2fbb9ea 1831
4a37fb66
YG		 1832 if (func <= 5) {
1833 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1834 } else {
1835 hw_lock_control_reg =
1836 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1837 }
1838
c18487ee 1839 /* Validating that the resource is not already taken */
4a37fb66 1840 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1841 if (lock_status & resource_bit) {
1842 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1843 lock_status, resource_bit);
1844 return -EEXIST;
1845 }
a2fbb9ea 1846
46230476
EG		 1847 /* Try for 5 second every 5ms */
1848 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1849 /* Try to acquire the lock */
4a37fb66
YG		 1850 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1851 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1852 if (lock_status & resource_bit)
1853 return 0;
a2fbb9ea 1854
c18487ee 1855 msleep(5);
a2fbb9ea 1856 }
c18487ee
YR		 1857 DP(NETIF_MSG_HW, "Timeout\n");
1858 return -EAGAIN;
1859}
a2fbb9ea 1860
c9ee9206
VZ		 1861int bnx2x_release_leader_lock(struct bnx2x *bp)
1862{
1863 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1864}
1865
9f6c9258 1866int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1867{
1868 u32 lock_status;
1869 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1870 int func = BP_FUNC(bp);
1871 u32 hw_lock_control_reg;
a2fbb9ea 1872
72fd0718
VZ		 1873 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1874
c18487ee
YR		 1875 /* Validating that the resource is within range */
1876 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1877 DP(NETIF_MSG_HW,
1878 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1879 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1880 return -EINVAL;
1881 }
1882
4a37fb66
YG		 1883 if (func <= 5) {
1884 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1885 } else {
1886 hw_lock_control_reg =
1887 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1888 }
1889
c18487ee 1890 /* Validating that the resource is currently taken */
4a37fb66 1891 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1892 if (!(lock_status & resource_bit)) {
1893 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1894 lock_status, resource_bit);
1895 return -EFAULT;
a2fbb9ea
ET		 1896 }
1897
9f6c9258
DK		 1898 REG_WR(bp, hw_lock_control_reg, resource_bit);
1899 return 0;
c18487ee 1900}
a2fbb9ea 1901
9f6c9258 1902
4acac6a5
EG		 1903int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1904{
1905 /* The GPIO should be swapped if swap register is set and active */
1906 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1907 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1908 int gpio_shift = gpio_num +
1909 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1910 u32 gpio_mask = (1 << gpio_shift);
1911 u32 gpio_reg;
1912 int value;
1913
1914 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1915 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1916 return -EINVAL;
1917 }
1918
1919 /* read GPIO value */
1920 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1921
1922 /* get the requested pin value */
1923 if ((gpio_reg & gpio_mask) == gpio_mask)
1924 value = 1;
1925 else
1926 value = 0;
1927
1928 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1929
1930 return value;
1931}
1932
17de50b7 1933int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1934{
1935 /* The GPIO should be swapped if swap register is set and active */
1936 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1937 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1938 int gpio_shift = gpio_num +
1939 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1940 u32 gpio_mask = (1 << gpio_shift);
1941 u32 gpio_reg;
a2fbb9ea 1942
c18487ee
YR		 1943 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1944 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1945 return -EINVAL;
1946 }
a2fbb9ea 1947
4a37fb66 1948 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1949 /* read GPIO and mask except the float bits */
1950 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1951
c18487ee
YR		 1952 switch (mode) {
1953 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1954 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1955 gpio_num, gpio_shift);
1956 /* clear FLOAT and set CLR */
1957 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1959 break;
a2fbb9ea 1960
c18487ee
YR		 1961 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1963 gpio_num, gpio_shift);
1964 /* clear FLOAT and set SET */
1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1966 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1967 break;
a2fbb9ea 1968
17de50b7 1969 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1971 gpio_num, gpio_shift);
1972 /* set FLOAT */
1973 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1974 break;
a2fbb9ea 1975
c18487ee
YR		 1976 default:
1977 break;
a2fbb9ea
ET		 1978 }
1979
c18487ee 1980 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1981 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1982
c18487ee 1983 return 0;
a2fbb9ea
ET		 1984}
1985
0d40f0d4
YR		 1986int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1987{
1988 u32 gpio_reg = 0;
1989 int rc = 0;
1990
1991 /* Any port swapping should be handled by caller. */
1992
1993 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1994 /* read GPIO and mask except the float bits */
1995 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1997 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1998 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1999
2000 switch (mode) {
2001 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2002 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2003 /* set CLR */
2004 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2005 break;
2006
2007 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2008 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2009 /* set SET */
2010 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2011 break;
2012
2013 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2014 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2015 /* set FLOAT */
2016 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2017 break;
2018
2019 default:
2020 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2021 rc = -EINVAL;
2022 break;
2023 }
2024
2025 if (rc == 0)
2026 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2027
2028 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2029
2030 return rc;
2031}
2032
4acac6a5
EG		 2033int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2034{
2035 /* The GPIO should be swapped if swap register is set and active */
2036 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2037 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2038 int gpio_shift = gpio_num +
2039 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2040 u32 gpio_mask = (1 << gpio_shift);
2041 u32 gpio_reg;
2042
2043 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2044 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 return -EINVAL;
2046 }
2047
2048 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2049 /* read GPIO int */
2050 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2051
2052 switch (mode) {
2053 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2054 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2055 "output low\n", gpio_num, gpio_shift);
2056 /* clear SET and set CLR */
2057 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2058 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2059 break;
2060
2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2062 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2063 "output high\n", gpio_num, gpio_shift);
2064 /* clear CLR and set SET */
2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2067 break;
2068
2069 default:
2070 break;
2071 }
2072
2073 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2075
2076 return 0;
2077}
2078
c18487ee 2079static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 2080{
c18487ee
YR		 2081 u32 spio_mask = (1 << spio_num);
2082 u32 spio_reg;
a2fbb9ea 2083
c18487ee
YR		 2084 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2085 (spio_num > MISC_REGISTERS_SPIO_7)) {
2086 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2087 return -EINVAL;
a2fbb9ea
ET		 2088 }
2089
4a37fb66 2090 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 2091 /* read SPIO and mask except the float bits */
2092 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 2093
c18487ee 2094 switch (mode) {
6378c025 2095 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 2096 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2097 /* clear FLOAT and set CLR */
2098 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2099 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2100 break;
a2fbb9ea 2101
6378c025 2102 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 2103 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2104 /* clear FLOAT and set SET */
2105 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2106 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2107 break;
a2fbb9ea 2108
c18487ee
YR		 2109 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2110 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2111 /* set FLOAT */
2112 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2113 break;
a2fbb9ea 2114
c18487ee
YR		 2115 default:
2116 break;
a2fbb9ea
ET		 2117 }
2118
c18487ee 2119 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2120 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2121
a2fbb9ea
ET		 2122 return 0;
2123}
2124
9f6c9258 2125void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2126{
a22f0788 2127 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2128 switch (bp->link_vars.ieee_fc &
2129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2130 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2131 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2132 ADVERTISED_Pause);
c18487ee 2133 break;
356e2385 2134
c18487ee 2135 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2136 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2137 ADVERTISED_Pause);
c18487ee 2138 break;
356e2385 2139
c18487ee 2140 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2141 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2142 break;
356e2385 2143
c18487ee 2144 default:
a22f0788 2145 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2146 ADVERTISED_Pause);
c18487ee
YR		 2147 break;
2148 }
2149}
f1410647 2150
9f6c9258 2151u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2152{
19680c48
EG		 2153 if (!BP_NOMCP(bp)) {
2154 u8 rc;
a22f0788
YR		 2155 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2156 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1cb0c788
YR		 2157 /*
2158 * Initialize link parameters structure variables
2159 * It is recommended to turn off RX FC for jumbo frames
2160 * for better performance
2161 */
2162 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
c0700f90 2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2164 else
c0700f90 2165 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2166
4a37fb66 2167 bnx2x_acquire_phy_lock(bp);
b5bf9068 2168
a22f0788 2169 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2170 struct link_params *lp = &bp->link_params;
2171 lp->loopback_mode = LOOPBACK_XGXS;
2172 /* do PHY loopback at 10G speed, if possible */
2173 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2174 if (lp->speed_cap_mask[cfx_idx] &
2175 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2176 lp->req_line_speed[cfx_idx] =
2177 SPEED_10000;
2178 else
2179 lp->req_line_speed[cfx_idx] =
2180 SPEED_1000;
2181 }
a22f0788 2182 }
b5bf9068 2183
19680c48 2184 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2185
4a37fb66 2186 bnx2x_release_phy_lock(bp);
a2fbb9ea 2187
3c96c68b
EG		 2188 bnx2x_calc_fc_adv(bp);
2189
b5bf9068
EG		 2190 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2191 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2192 bnx2x_link_report(bp);
3deb8167
YR		 2193 } else
2194 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2195 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2196 return rc;
2197 }
f5372251 2198 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2199 return -EINVAL;
a2fbb9ea
ET		 2200}
2201
9f6c9258 2202void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2203{
19680c48 2204 if (!BP_NOMCP(bp)) {
4a37fb66 2205 bnx2x_acquire_phy_lock(bp);
54c2fb78 2206 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2207 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2208 bnx2x_release_phy_lock(bp);
a2fbb9ea 2209
19680c48
EG		 2210 bnx2x_calc_fc_adv(bp);
2211 } else
f5372251 2212 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2213}
a2fbb9ea 2214
c18487ee
YR		 2215static void bnx2x__link_reset(struct bnx2x *bp)
2216{
19680c48 2217 if (!BP_NOMCP(bp)) {
4a37fb66 2218 bnx2x_acquire_phy_lock(bp);
589abe3a 2219 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2220 bnx2x_release_phy_lock(bp);
19680c48 2221 } else
f5372251 2222 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2223}
a2fbb9ea 2224
a22f0788 2225u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2226{
2145a920 2227 u8 rc = 0;
a2fbb9ea 2228
2145a920
VZ		 2229 if (!BP_NOMCP(bp)) {
2230 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2231 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2232 is_serdes);
2145a920
VZ		 2233 bnx2x_release_phy_lock(bp);
2234 } else
2235 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2236
c18487ee
YR		 2237 return rc;
2238}
a2fbb9ea 2239
8a1c38d1 2240static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 2241{
8a1c38d1
EG		 2242 u32 r_param = bp->link_vars.line_speed / 8;
2243 u32 fair_periodic_timeout_usec;
2244 u32 t_fair;
34f80b04 2245
8a1c38d1
EG		 2246 memset(&(bp->cmng.rs_vars), 0,
2247 sizeof(struct rate_shaping_vars_per_port));
2248 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 2249
8a1c38d1
EG		 2250 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2251 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 2252
8a1c38d1
EG		 2253 /* this is the threshold below which no timer arming will occur
2254 1.25 coefficient is for the threshold to be a little bigger
2255 than the real time, to compensate for timer in-accuracy */
2256 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 2257 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2258
8a1c38d1
EG		 2259 /* resolution of fairness timer */
2260 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2261 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2262 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 2263
8a1c38d1
EG		 2264 /* this is the threshold below which we won't arm the timer anymore */
2265 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 2266
8a1c38d1
EG		 2267 /* we multiply by 1e3/8 to get bytes/msec.
2268 We don't want the credits to pass a credit
2269 of the t_fair*FAIR_MEM (algorithm resolution) */
2270 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2271 /* since each tick is 4 usec */
2272 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 2273}
2274
2691d51d
EG		 2275/* Calculates the sum of vn_min_rates.
2276 It's needed for further normalizing of the min_rates.
2277 Returns:
2278 sum of vn_min_rates.
2279 or
2280 0 - if all the min_rates are 0.
2281 In the later case fainess algorithm should be deactivated.
2282 If not all min_rates are zero then those that are zeroes will be set to 1.
2283 */
2284static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2285{
2286 int all_zero = 1;
2691d51d
EG		 2287 int vn;
2288
2289 bp->vn_weight_sum = 0;
3395a033 2290 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2291 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2292 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2293 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2294
2295 /* Skip hidden vns */
2296 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2297 continue;
2298
2299 /* If min rate is zero - set it to 1 */
2300 if (!vn_min_rate)
2301 vn_min_rate = DEF_MIN_RATE;
2302 else
2303 all_zero = 0;
2304
2305 bp->vn_weight_sum += vn_min_rate;
2306 }
2307
30ae438b
DK		 2308 /* if ETS or all min rates are zeros - disable fairness */
2309 if (BNX2X_IS_ETS_ENABLED(bp)) {
2310 bp->cmng.flags.cmng_enables &=
2311 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2312 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2313 } else if (all_zero) {
b015e3d1
EG		 2314 bp->cmng.flags.cmng_enables &=
2315 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2316 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2317 " fairness will be disabled\n");
2318 } else
2319 bp->cmng.flags.cmng_enables |=
2320 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2321}
2322
3395a033
DK		 2323/* returns func by VN for current port */
2324static inline int func_by_vn(struct bnx2x *bp, int vn)
2325{
2326 return 2 * vn + BP_PORT(bp);
2327}
2328
f2e0899f 2329static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 2330{
2331 struct rate_shaping_vars_per_vn m_rs_vn;
2332 struct fairness_vars_per_vn m_fair_vn;
f2e0899f 2333 u32 vn_cfg = bp->mf_config[vn];
3395a033 2334 int func = func_by_vn(bp, vn);
34f80b04
EG		 2335 u16 vn_min_rate, vn_max_rate;
2336 int i;
2337
2338 /* If function is hidden - set min and max to zeroes */
2339 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2340 vn_min_rate = 0;
2341 vn_max_rate = 0;
2342
2343 } else {
faa6fcbb
DK		 2344 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2345
34f80b04
EG		 2346 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2347 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 2348 /* If fairness is enabled (not all min rates are zeroes) and
2349 if current min rate is zero - set it to 1.
2350 This is a requirement of the algorithm. */
f2e0899f 2351 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 2352 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 2353
2354 if (IS_MF_SI(bp))
2355 /* maxCfg in percents of linkspeed */
2356 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2357 else
2358 /* maxCfg is absolute in 100Mb units */
2359 vn_max_rate = maxCfg * 100;
34f80b04 2360 }
f85582f8 2361
8a1c38d1 2362 DP(NETIF_MSG_IFUP,
b015e3d1 2363 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 2364 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 2365
2366 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2367 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2368
2369 /* global vn counter - maximal Mbps for this vn */
2370 m_rs_vn.vn_counter.rate = vn_max_rate;
2371
2372 /* quota - number of bytes transmitted in this period */
2373 m_rs_vn.vn_counter.quota =
2374 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2375
8a1c38d1 2376 if (bp->vn_weight_sum) {
34f80b04
EG		 2377 /* credit for each period of the fairness algorithm:
2378 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2379 vn_weight_sum should not be larger than 10000, thus
2380 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2381 than zero */
34f80b04 2382 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2383 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2384 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2385 (bp->cmng.fair_vars.fair_threshold +
2386 MIN_ABOVE_THRESH));
cdaa7cb8 2387 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2388 m_fair_vn.vn_credit_delta);
2389 }
2390
34f80b04
EG		 2391 /* Store it to internal memory */
2392 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2393 REG_WR(bp, BAR_XSTRORM_INTMEM +
2394 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2395 ((u32 *)(&m_rs_vn))[i]);
2396
2397 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2398 REG_WR(bp, BAR_XSTRORM_INTMEM +
2399 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2400 ((u32 *)(&m_fair_vn))[i]);
2401}
f85582f8 2402
523224a3
DK		 2403static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2404{
2405 if (CHIP_REV_IS_SLOW(bp))
2406 return CMNG_FNS_NONE;
fb3bff17 2407 if (IS_MF(bp))
523224a3
DK		 2408 return CMNG_FNS_MINMAX;
2409
2410 return CMNG_FNS_NONE;
2411}
2412
2ae17f66 2413void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2414{
0793f83f 2415 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2416
2417 if (BP_NOMCP(bp))
2418 return; /* what should be the default bvalue in this case */
2419
0793f83f
DK		 2420 /* For 2 port configuration the absolute function number formula
2421 * is:
2422 * abs_func = 2 * vn + BP_PORT + BP_PATH
2423 *
2424 * and there are 4 functions per port
2425 *
2426 * For 4 port configuration it is
2427 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2428 *
2429 * and there are 2 functions per port
2430 */
3395a033 2431 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2432 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2433
2434 if (func >= E1H_FUNC_MAX)
2435 break;
2436
f2e0899f 2437 bp->mf_config[vn] =
523224a3
DK		 2438 MF_CFG_RD(bp, func_mf_config[func].config);
2439 }
2440}
2441
2442static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2443{
2444
2445 if (cmng_type == CMNG_FNS_MINMAX) {
2446 int vn;
2447
2448 /* clear cmng_enables */
2449 bp->cmng.flags.cmng_enables = 0;
2450
2451 /* read mf conf from shmem */
2452 if (read_cfg)
2453 bnx2x_read_mf_cfg(bp);
2454
2455 /* Init rate shaping and fairness contexts */
2456 bnx2x_init_port_minmax(bp);
2457
2458 /* vn_weight_sum and enable fairness if not 0 */
2459 bnx2x_calc_vn_weight_sum(bp);
2460
2461 /* calculate and set min-max rate for each vn */
c4154f25 2462 if (bp->port.pmf)
3395a033 2463 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
c4154f25 2464 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2465
2466 /* always enable rate shaping and fairness */
2467 bp->cmng.flags.cmng_enables |=
2468 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2469 if (!bp->vn_weight_sum)
2470 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2471 " fairness will be disabled\n");
2472 return;
2473 }
2474
2475 /* rate shaping and fairness are disabled */
2476 DP(NETIF_MSG_IFUP,
2477 "rate shaping and fairness are disabled\n");
2478}
34f80b04 2479
523224a3
DK		 2480static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2481{
523224a3
DK		 2482 int func;
2483 int vn;
2484
2485 /* Set the attention towards other drivers on the same port */
3395a033
DK		 2486 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2487 if (vn == BP_VN(bp))
523224a3
DK		 2488 continue;
2489
3395a033 2490 func = func_by_vn(bp, vn);
523224a3
DK		 2491 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2492 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2493 }
2494}
8a1c38d1 2495
c18487ee
YR		 2496/* This function is called upon link interrupt */
2497static void bnx2x_link_attn(struct bnx2x *bp)
2498{
bb2a0f7a
YG		 2499 /* Make sure that we are synced with the current statistics */
2500 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2501
c18487ee 2502 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2503
bb2a0f7a
YG		 2504 if (bp->link_vars.link_up) {
2505
1c06328c 2506 /* dropless flow control */
f2e0899f 2507 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2508 int port = BP_PORT(bp);
2509 u32 pause_enabled = 0;
2510
2511 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2512 pause_enabled = 1;
2513
2514 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2515 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2516 pause_enabled);
2517 }
2518
619c5cb6 2519 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2520 struct host_port_stats *pstats;
2521
2522 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2523 /* reset old mac stats */
bb2a0f7a
YG		 2524 memset(&(pstats->mac_stx[0]), 0,
2525 sizeof(struct mac_stx));
2526 }
f34d28ea 2527 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2528 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2529 }
2530
f2e0899f
DK		 2531 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2532 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2533
f2e0899f
DK		 2534 if (cmng_fns != CMNG_FNS_NONE) {
2535 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2536 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2537 } else
2538 /* rate shaping and fairness are disabled */
2539 DP(NETIF_MSG_IFUP,
2540 "single function mode without fairness\n");
34f80b04 2541 }
9fdc3e95 2542
2ae17f66
VZ		 2543 __bnx2x_link_report(bp);
2544
9fdc3e95
DK		 2545 if (IS_MF(bp))
2546 bnx2x_link_sync_notify(bp);
c18487ee 2547}
a2fbb9ea 2548
9f6c9258 2549void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2550{
2ae17f66 2551 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2552 return;
a2fbb9ea 2553
c18487ee 2554 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2555
bb2a0f7a
YG		 2556 if (bp->link_vars.link_up)
2557 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2558 else
2559 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2560
c18487ee
YR		 2561 /* indicate link status */
2562 bnx2x_link_report(bp);
a2fbb9ea 2563}
a2fbb9ea 2564
34f80b04
EG		 2565static void bnx2x_pmf_update(struct bnx2x *bp)
2566{
2567 int port = BP_PORT(bp);
2568 u32 val;
2569
2570 bp->port.pmf = 1;
2571 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2572
3deb8167
YR		 2573 /*
2574 * We need the mb() to ensure the ordering between the writing to
2575 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2576 */
2577 smp_mb();
2578
2579 /* queue a periodic task */
2580 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2581
ef01854e
DK		 2582 bnx2x_dcbx_pmf_update(bp);
2583
34f80b04 2584 /* enable nig attention */
3395a033 2585 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2586 if (bp->common.int_block == INT_BLOCK_HC) {
2587 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2588 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2589 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2590 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2591 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2592 }
bb2a0f7a
YG		 2593
2594 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2595}
2596
c18487ee 2597/* end of Link */
a2fbb9ea
ET		 2598
2599/* slow path */
2600
2601/*
2602 * General service functions
2603 */
2604
2691d51d 2605/* send the MCP a request, block until there is a reply */
a22f0788 2606u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2607{
f2e0899f 2608 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2609 u32 seq;
2691d51d
EG		 2610 u32 rc = 0;
2611 u32 cnt = 1;
2612 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2613
c4ff7cbf 2614 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2615 seq = ++bp->fw_seq;
f2e0899f
DK		 2616 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2617 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2618
754a2f52
DK		 2619 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2620 (command | seq), param);
2691d51d
EG		 2621
2622 do {
2623 /* let the FW do it's magic ... */
2624 msleep(delay);
2625
f2e0899f 2626 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2627
c4ff7cbf
EG		 2628 /* Give the FW up to 5 second (500*10ms) */
2629 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2630
2631 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2632 cnt*delay, rc, seq);
2633
2634 /* is this a reply to our command? */
2635 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2636 rc &= FW_MSG_CODE_MASK;
2637 else {
2638 /* FW BUG! */
2639 BNX2X_ERR("FW failed to respond!\n");
2640 bnx2x_fw_dump(bp);
2641 rc = 0;
2642 }
c4ff7cbf 2643 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2644
2645 return rc;
2646}
2647
ec6ba945
VZ		 2648static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2649{
2650#ifdef BCM_CNIC
619c5cb6
VZ		 2651 /* Statistics are not supported for CNIC Clients at the moment */
2652 if (IS_FCOE_FP(fp))
ec6ba945
VZ		 2653 return false;
2654#endif
2655 return true;
2656}
2657
619c5cb6
VZ		 2658void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2659{
2660 if (CHIP_IS_E1x(bp)) {
2661 struct tstorm_eth_function_common_config tcfg = {0};
2662
2663 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2664 }
2665
2666 /* Enable the function in the FW */
2667 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2668 storm_memset_func_en(bp, p->func_id, 1);
2669
2670 /* spq */
2671 if (p->func_flgs & FUNC_FLG_SPQ) {
2672 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2673 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2674 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2675 }
2676}
2677
6383c0b3
AE		 2678/**
2679 * bnx2x_get_tx_only_flags - Return common flags
2680 *
2681 * @bp device handle
2682 * @fp queue handle
2683 * @zero_stats TRUE if statistics zeroing is needed
2684 *
2685 * Return the flags that are common for the Tx-only and not normal connections.
2686 */
2687static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2688 struct bnx2x_fastpath *fp,
2689 bool zero_stats)
28912902 2690{
619c5cb6
VZ		 2691 unsigned long flags = 0;
2692
2693 /* PF driver will always initialize the Queue to an ACTIVE state */
2694 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2695
6383c0b3
AE		 2696 /* tx only connections collect statistics (on the same index as the
2697 * parent connection). The statistics are zeroed when the parent
2698 * connection is initialized.
2699 */
2700 if (stat_counter_valid(bp, fp)) {
2701 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2702 if (zero_stats)
2703 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2704 }
2705
2706 return flags;
2707}
2708
2709static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2710 struct bnx2x_fastpath *fp,
2711 bool leading)
2712{
2713 unsigned long flags = 0;
2714
619c5cb6
VZ		 2715 /* calculate other queue flags */
2716 if (IS_MF_SD(bp))
2717 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2718
619c5cb6
VZ		 2719 if (IS_FCOE_FP(fp))
2720 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3 2721
f5219d8e 2722 if (!fp->disable_tpa) {
619c5cb6 2723 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e
VZ		 2724 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2725 }
619c5cb6 2726
619c5cb6
VZ		 2727 if (leading) {
2728 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2729 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2730 }
523224a3 2731
619c5cb6
VZ		 2732 /* Always set HW VLAN stripping */
2733 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2734
6383c0b3
AE		 2735
2736 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2737}
2738
619c5cb6 2739static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2740 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2741 u8 cos)
619c5cb6
VZ		 2742{
2743 gen_init->stat_id = bnx2x_stats_id(fp);
2744 gen_init->spcl_id = fp->cl_id;
2745
2746 /* Always use mini-jumbo MTU for FCoE L2 ring */
2747 if (IS_FCOE_FP(fp))
2748 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2749 else
2750 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2751
2752 gen_init->cos = cos;
619c5cb6
VZ		 2753}
2754
2755static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2756 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2757 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2758{
619c5cb6 2759 u8 max_sge = 0;
523224a3
DK		 2760 u16 sge_sz = 0;
2761 u16 tpa_agg_size = 0;
2762
523224a3 2763 if (!fp->disable_tpa) {
dfacf138
DK		 2764 pause->sge_th_lo = SGE_TH_LO(bp);
2765 pause->sge_th_hi = SGE_TH_HI(bp);
2766
2767 /* validate SGE ring has enough to cross high threshold */
2768 WARN_ON(bp->dropless_fc &&
2769 pause->sge_th_hi + FW_PREFETCH_CNT >
2770 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2771
523224a3
DK		 2772 tpa_agg_size = min_t(u32,
2773 (min_t(u32, 8, MAX_SKB_FRAGS) *
2774 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2775 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2776 SGE_PAGE_SHIFT;
2777 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2778 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2779 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2780 0xffff);
2781 }
2782
2783 /* pause - not for e1 */
2784 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 2785 pause->bd_th_lo = BD_TH_LO(bp);
2786 pause->bd_th_hi = BD_TH_HI(bp);
2787
2788 pause->rcq_th_lo = RCQ_TH_LO(bp);
2789 pause->rcq_th_hi = RCQ_TH_HI(bp);
2790 /*
2791 * validate that rings have enough entries to cross
2792 * high thresholds
2793 */
2794 WARN_ON(bp->dropless_fc &&
2795 pause->bd_th_hi + FW_PREFETCH_CNT >
2796 bp->rx_ring_size);
2797 WARN_ON(bp->dropless_fc &&
2798 pause->rcq_th_hi + FW_PREFETCH_CNT >
2799 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 2800
523224a3
DK		 2801 pause->pri_map = 1;
2802 }
2803
2804 /* rxq setup */
523224a3
DK		 2805 rxq_init->dscr_map = fp->rx_desc_mapping;
2806 rxq_init->sge_map = fp->rx_sge_mapping;
2807 rxq_init->rcq_map = fp->rx_comp_mapping;
2808 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2809
619c5cb6
VZ		 2810 /* This should be a maximum number of data bytes that may be
2811 * placed on the BD (not including paddings).
2812 */
2813 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2814 IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2815
523224a3 2816 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2817 rxq_init->tpa_agg_sz = tpa_agg_size;
2818 rxq_init->sge_buf_sz = sge_sz;
2819 rxq_init->max_sges_pkt = max_sge;
619c5cb6
VZ		 2820 rxq_init->rss_engine_id = BP_FUNC(bp);
2821
2822 /* Maximum number or simultaneous TPA aggregation for this Queue.
2823 *
2824 * For PF Clients it should be the maximum avaliable number.
2825 * VF driver(s) may want to define it to a smaller value.
2826 */
dfacf138 2827 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 2828
523224a3
DK		 2829 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2830 rxq_init->fw_sb_id = fp->fw_sb_id;
2831
ec6ba945
VZ		 2832 if (IS_FCOE_FP(fp))
2833 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2834 else
6383c0b3 2835 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
523224a3
DK		 2836}
2837
619c5cb6 2838static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 2839 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2840 u8 cos)
523224a3 2841{
6383c0b3
AE		 2842 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2843 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 2844 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2845 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2846
619c5cb6
VZ		 2847 /*
2848 * set the tss leading client id for TX classfication ==
2849 * leading RSS client id
2850 */
2851 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2852
ec6ba945
VZ		 2853 if (IS_FCOE_FP(fp)) {
2854 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2855 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2856 }
523224a3
DK		 2857}
2858
8d96286a 2859static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2860{
2861 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2862 struct event_ring_data eq_data = { {0} };
2863 u16 flags;
2864
619c5cb6 2865 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2866 /* reset IGU PF statistics: MSIX + ATTN */
2867 /* PF */
2868 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2869 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2870 (CHIP_MODE_IS_4_PORT(bp) ?
2871 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2872 /* ATTN */
2873 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2874 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2875 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2876 (CHIP_MODE_IS_4_PORT(bp) ?
2877 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2878 }
2879
523224a3
DK		 2880 /* function setup flags */
2881 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2882
619c5cb6
VZ		 2883 /* This flag is relevant for E1x only.
2884 * E2 doesn't have a TPA configuration in a function level.
523224a3 2885 */
619c5cb6 2886 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2887
2888 func_init.func_flgs = flags;
2889 func_init.pf_id = BP_FUNC(bp);
2890 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2891 func_init.spq_map = bp->spq_mapping;
2892 func_init.spq_prod = bp->spq_prod_idx;
2893
2894 bnx2x_func_init(bp, &func_init);
2895
2896 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2897
2898 /*
619c5cb6
VZ		 2899 * Congestion management values depend on the link rate
2900 * There is no active link so initial link rate is set to 10 Gbps.
2901 * When the link comes up The congestion management values are
2902 * re-calculated according to the actual link rate.
2903 */
523224a3
DK		 2904 bp->link_vars.line_speed = SPEED_10000;
2905 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2906
2907 /* Only the PMF sets the HW */
2908 if (bp->port.pmf)
2909 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2910
523224a3
DK		 2911 /* init Event Queue */
2912 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2913 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2914 eq_data.producer = bp->eq_prod;
2915 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2916 eq_data.sb_id = DEF_SB_ID;
2917 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2918}
2919
2920
2921static void bnx2x_e1h_disable(struct bnx2x *bp)
2922{
2923 int port = BP_PORT(bp);
2924
619c5cb6 2925 bnx2x_tx_disable(bp);
523224a3
DK		 2926
2927 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2928}
2929
2930static void bnx2x_e1h_enable(struct bnx2x *bp)
2931{
2932 int port = BP_PORT(bp);
2933
2934 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2935
2936 /* Tx queue should be only reenabled */
2937 netif_tx_wake_all_queues(bp->dev);
2938
2939 /*
2940 * Should not call netif_carrier_on since it will be called if the link
2941 * is up when checking for link state
2942 */
2943}
2944
0793f83f
DK		 2945/* called due to MCP event (on pmf):
2946 * reread new bandwidth configuration
2947 * configure FW
2948 * notify others function about the change
2949 */
2950static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2951{
2952 if (bp->link_vars.link_up) {
2953 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2954 bnx2x_link_sync_notify(bp);
2955 }
2956 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2957}
2958
2959static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2960{
2961 bnx2x_config_mf_bw(bp);
2962 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2963}
2964
523224a3
DK		 2965static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2966{
2967 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2968
2969 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2970
2971 /*
2972 * This is the only place besides the function initialization
2973 * where the bp->flags can change so it is done without any
2974 * locks
2975 */
f2e0899f 2976 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2977 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2978 bp->flags |= MF_FUNC_DIS;
2979
2980 bnx2x_e1h_disable(bp);
2981 } else {
2982 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2983 bp->flags &= ~MF_FUNC_DIS;
2984
2985 bnx2x_e1h_enable(bp);
2986 }
2987 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2988 }
2989 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2990 bnx2x_config_mf_bw(bp);
523224a3
DK		 2991 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2992 }
2993
2994 /* Report results to MCP */
2995 if (dcc_event)
2996 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2997 else
2998 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2999}
3000
3001/* must be called under the spq lock */
3002static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3003{
3004 struct eth_spe *next_spe = bp->spq_prod_bd;
3005
3006 if (bp->spq_prod_bd == bp->spq_last_bd) {
3007 bp->spq_prod_bd = bp->spq;
3008 bp->spq_prod_idx = 0;
3009 DP(NETIF_MSG_TIMER, "end of spq\n");
3010 } else {
3011 bp->spq_prod_bd++;
3012 bp->spq_prod_idx++;
3013 }
3014 return next_spe;
3015}
3016
3017/* must be called under the spq lock */
28912902
MC		 3018static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3019{
3020 int func = BP_FUNC(bp);
3021
53e51e2f
VZ		 3022 /*
3023 * Make sure that BD data is updated before writing the producer:
3024 * BD data is written to the memory, the producer is read from the
3025 * memory, thus we need a full memory barrier to ensure the ordering.
3026 */
3027 mb();
28912902 3028
523224a3 3029 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3030 bp->spq_prod_idx);
28912902
MC		 3031 mmiowb();
3032}
3033
619c5cb6
VZ		 3034/**
3035 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3036 *
3037 * @cmd: command to check
3038 * @cmd_type: command type
3039 */
3040static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3041{
3042 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3043 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3044 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3045 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3046 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3047 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3048 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3049 return true;
3050 else
3051 return false;
3052
3053}
3054
3055
3056/**
3057 * bnx2x_sp_post - place a single command on an SP ring
3058 *
3059 * @bp: driver handle
3060 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3061 * @cid: SW CID the command is related to
3062 * @data_hi: command private data address (high 32 bits)
3063 * @data_lo: command private data address (low 32 bits)
3064 * @cmd_type: command type (e.g. NONE, ETH)
3065 *
3066 * SP data is handled as if it's always an address pair, thus data fields are
3067 * not swapped to little endian in upper functions. Instead this function swaps
3068 * data as if it's two u32 fields.
3069 */
9f6c9258 3070int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3071 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3072{
28912902 3073 struct eth_spe *spe;
523224a3 3074 u16 type;
619c5cb6 3075 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3076
a2fbb9ea
ET		 3077#ifdef BNX2X_STOP_ON_ERROR
3078 if (unlikely(bp->panic))
3079 return -EIO;
3080#endif
3081
34f80b04 3082 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3083
6e30dd4e
VZ		 3084 if (common) {
3085 if (!atomic_read(&bp->eq_spq_left)) {
3086 BNX2X_ERR("BUG! EQ ring full!\n");
3087 spin_unlock_bh(&bp->spq_lock);
3088 bnx2x_panic();
3089 return -EBUSY;
3090 }
3091 } else if (!atomic_read(&bp->cq_spq_left)) {
3092 BNX2X_ERR("BUG! SPQ ring full!\n");
3093 spin_unlock_bh(&bp->spq_lock);
3094 bnx2x_panic();
3095 return -EBUSY;
a2fbb9ea 3096 }
f1410647 3097
28912902
MC		 3098 spe = bnx2x_sp_get_next(bp);
3099
a2fbb9ea 3100 /* CID needs port number to be encoded int it */
28912902 3101 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3102 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3103 HW_CID(bp, cid));
523224a3 3104
619c5cb6 3105 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3106
523224a3
DK		 3107 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3108 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3109
523224a3
DK		 3110 spe->hdr.type = cpu_to_le16(type);
3111
3112 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3113 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3114
d6cae238
VZ		 3115 /*
3116 * It's ok if the actual decrement is issued towards the memory
3117 * somewhere between the spin_lock and spin_unlock. Thus no
3118 * more explict memory barrier is needed.
3119 */
3120 if (common)
3121 atomic_dec(&bp->eq_spq_left);
3122 else
3123 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3124
a2fbb9ea 3125
cdaa7cb8 3126 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
d6cae238
VZ		 3127 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3128 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3129 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3130 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3131 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3132 HW_CID(bp, cid), data_hi, data_lo, type,
3133 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3134
28912902 3135 bnx2x_sp_prod_update(bp);
34f80b04 3136 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3137 return 0;
3138}
3139
3140/* acquire split MCP access lock register */
4a37fb66 3141static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3142{
72fd0718 3143 u32 j, val;
34f80b04 3144 int rc = 0;
a2fbb9ea
ET		 3145
3146 might_sleep();
72fd0718 3147 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3148 val = (1UL << 31);
3149 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3150 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3151 if (val & (1L << 31))
3152 break;
3153
3154 msleep(5);
3155 }
a2fbb9ea 3156 if (!(val & (1L << 31))) {
19680c48 3157 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3158 rc = -EBUSY;
3159 }
3160
3161 return rc;
3162}
3163
4a37fb66
YG		 3164/* release split MCP access lock register */
3165static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3166{
72fd0718 3167 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3168}
3169
523224a3
DK		 3170#define BNX2X_DEF_SB_ATT_IDX 0x0001
3171#define BNX2X_DEF_SB_IDX 0x0002
3172
a2fbb9ea
ET		 3173static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3174{
523224a3 3175 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3176 u16 rc = 0;
3177
3178 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3179 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3180 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3181 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3182 }
523224a3
DK		 3183
3184 if (bp->def_idx != def_sb->sp_sb.running_index) {
3185 bp->def_idx = def_sb->sp_sb.running_index;
3186 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3187 }
523224a3
DK		 3188
3189 /* Do not reorder: indecies reading should complete before handling */
3190 barrier();
a2fbb9ea
ET		 3191 return rc;
3192}
3193
3194/*
3195 * slow path service functions
3196 */
3197
3198static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3199{
34f80b04 3200 int port = BP_PORT(bp);
a2fbb9ea
ET		 3201 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3202 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3203 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3204 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3205 u32 aeu_mask;
87942b46 3206 u32 nig_mask = 0;
f2e0899f 3207 u32 reg_addr;
a2fbb9ea 3208
a2fbb9ea
ET		 3209 if (bp->attn_state & asserted)
3210 BNX2X_ERR("IGU ERROR\n");
3211
3fcaf2e5
EG		 3212 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3213 aeu_mask = REG_RD(bp, aeu_addr);
3214
a2fbb9ea 3215 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3216 aeu_mask, asserted);
72fd0718 3217 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3218 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3219
3fcaf2e5
EG		 3220 REG_WR(bp, aeu_addr, aeu_mask);
3221 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3222
3fcaf2e5 3223 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3224 bp->attn_state |= asserted;
3fcaf2e5 3225 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3226
3227 if (asserted & ATTN_HARD_WIRED_MASK) {
3228 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3229
a5e9a7cf
EG		 3230 bnx2x_acquire_phy_lock(bp);
3231
877e9aa4 3232 /* save nig interrupt mask */
87942b46 3233 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3234
361c391e
YR		 3235 /* If nig_mask is not set, no need to call the update
3236 * function.
3237 */
3238 if (nig_mask) {
3239 REG_WR(bp, nig_int_mask_addr, 0);
3240
3241 bnx2x_link_attn(bp);
3242 }
a2fbb9ea
ET		 3243
3244 /* handle unicore attn? */
3245 }
3246 if (asserted & ATTN_SW_TIMER_4_FUNC)
3247 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3248
3249 if (asserted & GPIO_2_FUNC)
3250 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3251
3252 if (asserted & GPIO_3_FUNC)
3253 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3254
3255 if (asserted & GPIO_4_FUNC)
3256 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3257
3258 if (port == 0) {
3259 if (asserted & ATTN_GENERAL_ATTN_1) {
3260 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3262 }
3263 if (asserted & ATTN_GENERAL_ATTN_2) {
3264 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3265 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3266 }
3267 if (asserted & ATTN_GENERAL_ATTN_3) {
3268 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3269 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3270 }
3271 } else {
3272 if (asserted & ATTN_GENERAL_ATTN_4) {
3273 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3274 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3275 }
3276 if (asserted & ATTN_GENERAL_ATTN_5) {
3277 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3278 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3279 }
3280 if (asserted & ATTN_GENERAL_ATTN_6) {
3281 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3282 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3283 }
3284 }
3285
3286 } /* if hardwired */
3287
f2e0899f
DK		 3288 if (bp->common.int_block == INT_BLOCK_HC)
3289 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3290 COMMAND_REG_ATTN_BITS_SET);
3291 else
3292 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3293
3294 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3295 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3296 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3297
3298 /* now set back the mask */
a5e9a7cf 3299 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3300 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3301 bnx2x_release_phy_lock(bp);
3302 }
a2fbb9ea
ET		 3303}
3304
fd4ef40d
EG		 3305static inline void bnx2x_fan_failure(struct bnx2x *bp)
3306{
3307 int port = BP_PORT(bp);
b7737c9b 3308 u32 ext_phy_config;
fd4ef40d 3309 /* mark the failure */
b7737c9b
YR		 3310 ext_phy_config =
3311 SHMEM_RD(bp,
3312 dev_info.port_hw_config[port].external_phy_config);
3313
3314 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3315 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3316 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3317 ext_phy_config);
fd4ef40d
EG		 3318
3319 /* log the failure */
cdaa7cb8
VZ		 3320 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3321 " the driver to shutdown the card to prevent permanent"
3322 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 3323}
ab6ad5a4 3324
877e9aa4 3325static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3326{
34f80b04 3327 int port = BP_PORT(bp);
877e9aa4 3328 int reg_offset;
d90d96ba 3329 u32 val;
877e9aa4 3330
34f80b04
EG		 3331 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3332 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3333
34f80b04 3334 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3335
3336 val = REG_RD(bp, reg_offset);
3337 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3338 REG_WR(bp, reg_offset, val);
3339
3340 BNX2X_ERR("SPIO5 hw attention\n");
3341
fd4ef40d 3342 /* Fan failure attention */
d90d96ba 3343 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3344 bnx2x_fan_failure(bp);
877e9aa4 3345 }
34f80b04 3346
3deb8167 3347 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3348 bnx2x_acquire_phy_lock(bp);
3349 bnx2x_handle_module_detect_int(&bp->link_params);
3350 bnx2x_release_phy_lock(bp);
3351 }
3352
34f80b04
EG		 3353 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3354
3355 val = REG_RD(bp, reg_offset);
3356 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3357 REG_WR(bp, reg_offset, val);
3358
3359 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3360 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3361 bnx2x_panic();
3362 }
877e9aa4
ET		 3363}
3364
3365static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3366{
3367 u32 val;
3368
0626b899 3369 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3370
3371 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3372 BNX2X_ERR("DB hw attention 0x%x\n", val);
3373 /* DORQ discard attention */
3374 if (val & 0x2)
3375 BNX2X_ERR("FATAL error from DORQ\n");
3376 }
34f80b04
EG		 3377
3378 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3379
3380 int port = BP_PORT(bp);
3381 int reg_offset;
3382
3383 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3384 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3385
3386 val = REG_RD(bp, reg_offset);
3387 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3388 REG_WR(bp, reg_offset, val);
3389
3390 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3391 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3392 bnx2x_panic();
3393 }
877e9aa4
ET		 3394}
3395
3396static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3397{
3398 u32 val;
3399
3400 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3401
3402 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3403 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3404 /* CFC error attention */
3405 if (val & 0x2)
3406 BNX2X_ERR("FATAL error from CFC\n");
3407 }
3408
3409 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3410 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3411 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3412 /* RQ_USDMDP_FIFO_OVERFLOW */
3413 if (val & 0x18000)
3414 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3415
3416 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3417 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3418 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3419 }
877e9aa4 3420 }
34f80b04
EG		 3421
3422 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3423
3424 int port = BP_PORT(bp);
3425 int reg_offset;
3426
3427 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3428 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3429
3430 val = REG_RD(bp, reg_offset);
3431 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3432 REG_WR(bp, reg_offset, val);
3433
3434 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3435 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3436 bnx2x_panic();
3437 }
877e9aa4
ET		 3438}
3439
3440static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3441{
34f80b04
EG		 3442 u32 val;
3443
877e9aa4
ET		 3444 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3445
34f80b04
EG		 3446 if (attn & BNX2X_PMF_LINK_ASSERT) {
3447 int func = BP_FUNC(bp);
3448
3449 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3450 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3451 func_mf_config[BP_ABS_FUNC(bp)].config);
3452 val = SHMEM_RD(bp,
3453 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3454 if (val & DRV_STATUS_DCC_EVENT_MASK)
3455 bnx2x_dcc_event(bp,
3456 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3457
3458 if (val & DRV_STATUS_SET_MF_BW)
3459 bnx2x_set_mf_bw(bp);
3460
2691d51d 3461 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3462 bnx2x_pmf_update(bp);
3463
e4901dde 3464 if (bp->port.pmf &&
785b9b1a
SR		 3465 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3466 bp->dcbx_enabled > 0)
e4901dde
VZ		 3467 /* start dcbx state machine */
3468 bnx2x_dcbx_set_params(bp,
3469 BNX2X_DCBX_STATE_NEG_RECEIVED);
3deb8167
YR		 3470 if (bp->link_vars.periodic_flags &
3471 PERIODIC_FLAGS_LINK_EVENT) {
3472 /* sync with link */
3473 bnx2x_acquire_phy_lock(bp);
3474 bp->link_vars.periodic_flags &=
3475 ~PERIODIC_FLAGS_LINK_EVENT;
3476 bnx2x_release_phy_lock(bp);
3477 if (IS_MF(bp))
3478 bnx2x_link_sync_notify(bp);
3479 bnx2x_link_report(bp);
3480 }
3481 /* Always call it here: bnx2x_link_report() will
3482 * prevent the link indication duplication.
3483 */
3484 bnx2x__link_status_update(bp);
34f80b04 3485 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3486
3487 BNX2X_ERR("MC assert!\n");
d6cae238 3488 bnx2x_mc_assert(bp);
877e9aa4
ET		 3489 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3490 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3491 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3492 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3493 bnx2x_panic();
3494
3495 } else if (attn & BNX2X_MCP_ASSERT) {
3496
3497 BNX2X_ERR("MCP assert!\n");
3498 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3499 bnx2x_fw_dump(bp);
877e9aa4
ET		 3500
3501 } else
3502 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3503 }
3504
3505 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3506 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3507 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3508 val = CHIP_IS_E1(bp) ? 0 :
3509 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3510 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3511 }
3512 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3513 val = CHIP_IS_E1(bp) ? 0 :
3514 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3515 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3516 }
877e9aa4 3517 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3518 }
3519}
3520
c9ee9206
VZ		 3521/*
3522 * Bits map:
3523 * 0-7 - Engine0 load counter.
3524 * 8-15 - Engine1 load counter.
3525 * 16 - Engine0 RESET_IN_PROGRESS bit.
3526 * 17 - Engine1 RESET_IN_PROGRESS bit.
3527 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3528 * on the engine
3529 * 19 - Engine1 ONE_IS_LOADED.
3530 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3531 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3532 * just the one belonging to its engine).
3533 *
3534 */
3535#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3536
3537#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3538#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3539#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3540#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3541#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3542#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3543#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3544
3545/*
3546 * Set the GLOBAL_RESET bit.
3547 *
3548 * Should be run under rtnl lock
3549 */
3550void bnx2x_set_reset_global(struct bnx2x *bp)
3551{
3552 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3553
3554 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3555 barrier();
3556 mmiowb();
3557}
3558
3559/*
3560 * Clear the GLOBAL_RESET bit.
3561 *
3562 * Should be run under rtnl lock
3563 */
3564static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3565{
3566 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3567
3568 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3569 barrier();
3570 mmiowb();
3571}
f85582f8 3572
72fd0718 3573/*
c9ee9206
VZ		 3574 * Checks the GLOBAL_RESET bit.
3575 *
72fd0718
VZ		 3576 * should be run under rtnl lock
3577 */
c9ee9206
VZ		 3578static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3579{
3580 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3581
3582 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3583 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3584}
3585
3586/*
3587 * Clear RESET_IN_PROGRESS bit for the current engine.
3588 *
3589 * Should be run under rtnl lock
3590 */
72fd0718
VZ		 3591static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3592{
c9ee9206
VZ		 3593 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3594 u32 bit = BP_PATH(bp) ?
3595 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3596
3597 /* Clear the bit */
3598 val &= ~bit;
3599 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3600 barrier();
3601 mmiowb();
3602}
3603
3604/*
c9ee9206
VZ		 3605 * Set RESET_IN_PROGRESS for the current engine.
3606 *
72fd0718
VZ		 3607 * should be run under rtnl lock
3608 */
c9ee9206 3609void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 3610{
c9ee9206
VZ		 3611 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3612 u32 bit = BP_PATH(bp) ?
3613 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3614
3615 /* Set the bit */
3616 val |= bit;
3617 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3618 barrier();
3619 mmiowb();
3620}
3621
3622/*
c9ee9206 3623 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 3624 * should be run under rtnl lock
3625 */
c9ee9206 3626bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 3627{
c9ee9206
VZ		 3628 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3629 u32 bit = engine ?
3630 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3631
3632 /* return false if bit is set */
3633 return (val & bit) ? false : true;
72fd0718
VZ		 3634}
3635
3636/*
c9ee9206
VZ		 3637 * Increment the load counter for the current engine.
3638 *
72fd0718
VZ		 3639 * should be run under rtnl lock
3640 */
c9ee9206 3641void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718 3642{
c9ee9206
VZ		 3643 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3644 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3645 BNX2X_PATH0_LOAD_CNT_MASK;
3646 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3647 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3648
3649 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3650
c9ee9206
VZ		 3651 /* get the current counter value */
3652 val1 = (val & mask) >> shift;
3653
3654 /* increment... */
3655 val1++;
3656
3657 /* clear the old value */
3658 val &= ~mask;
3659
3660 /* set the new one */
3661 val |= ((val1 << shift) & mask);
3662
3663 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3664 barrier();
3665 mmiowb();
3666}
3667
c9ee9206
VZ		 3668/**
3669 * bnx2x_dec_load_cnt - decrement the load counter
3670 *
3671 * @bp: driver handle
3672 *
3673 * Should be run under rtnl lock.
3674 * Decrements the load counter for the current engine. Returns
3675 * the new counter value.
72fd0718 3676 */
9f6c9258 3677u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718 3678{
c9ee9206
VZ		 3679 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3680 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3681 BNX2X_PATH0_LOAD_CNT_MASK;
3682 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3683 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3684
3685 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3686
c9ee9206
VZ		 3687 /* get the current counter value */
3688 val1 = (val & mask) >> shift;
3689
3690 /* decrement... */
3691 val1--;
3692
3693 /* clear the old value */
3694 val &= ~mask;
3695
3696 /* set the new one */
3697 val |= ((val1 << shift) & mask);
3698
3699 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3700 barrier();
3701 mmiowb();
3702
3703 return val1;
3704}
3705
3706/*
c9ee9206
VZ		 3707 * Read the load counter for the current engine.
3708 *
72fd0718
VZ		 3709 * should be run under rtnl lock
3710 */
c9ee9206 3711static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
72fd0718 3712{
c9ee9206
VZ		 3713 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3714 BNX2X_PATH0_LOAD_CNT_MASK);
3715 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3716 BNX2X_PATH0_LOAD_CNT_SHIFT);
3717 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3718
3719 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3720
3721 val = (val & mask) >> shift;
3722
3723 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3724
3725 return val;
72fd0718
VZ		 3726}
3727
c9ee9206
VZ		 3728/*
3729 * Reset the load counter for the current engine.
3730 *
3731 * should be run under rtnl lock
3732 */
72fd0718
VZ		 3733static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3734{
c9ee9206
VZ		 3735 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3736 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3737 BNX2X_PATH0_LOAD_CNT_MASK);
3738
3739 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
72fd0718
VZ		 3740}
3741
3742static inline void _print_next_block(int idx, const char *blk)
3743{
3744 if (idx)
3745 pr_cont(", ");
3746 pr_cont("%s", blk);
3747}
3748
c9ee9206
VZ		 3749static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3750 bool print)
72fd0718
VZ		 3751{
3752 int i = 0;
3753 u32 cur_bit = 0;
3754 for (i = 0; sig; i++) {
3755 cur_bit = ((u32)0x1 << i);
3756 if (sig & cur_bit) {
3757 switch (cur_bit) {
3758 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 3759 if (print)
3760 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 3761 break;
3762 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 3763 if (print)
3764 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 3765 break;
3766 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 3767 if (print)
3768 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 3769 break;
3770 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 3771 if (print)
3772 _print_next_block(par_num++,
3773 "SEARCHER");
3774 break;
3775 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3776 if (print)
3777 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 3778 break;
3779 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 3780 if (print)
3781 _print_next_block(par_num++, "TSEMI");
3782 break;
3783 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3784 if (print)
3785 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 3786 break;
3787 }
3788
3789 /* Clear the bit */
3790 sig &= ~cur_bit;
3791 }
3792 }
3793
3794 return par_num;
3795}
3796
c9ee9206
VZ		 3797static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3798 bool *global, bool print)
72fd0718
VZ		 3799{
3800 int i = 0;
3801 u32 cur_bit = 0;
3802 for (i = 0; sig; i++) {
3803 cur_bit = ((u32)0x1 << i);
3804 if (sig & cur_bit) {
3805 switch (cur_bit) {
c9ee9206
VZ		 3806 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3807 if (print)
3808 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 3809 break;
3810 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 3811 if (print)
3812 _print_next_block(par_num++, "QM");
3813 break;
3814 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3815 if (print)
3816 _print_next_block(par_num++, "TM");
72fd0718
VZ		 3817 break;
3818 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 3819 if (print)
3820 _print_next_block(par_num++, "XSDM");
3821 break;
3822 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3823 if (print)
3824 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 3825 break;
3826 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 3827 if (print)
3828 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 3829 break;
3830 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 3831 if (print)
3832 _print_next_block(par_num++,
3833 "DOORBELLQ");
3834 break;
3835 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3836 if (print)
3837 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 3838 break;
3839 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 3840 if (print)
3841 _print_next_block(par_num++,
3842 "VAUX PCI CORE");
3843 *global = true;
72fd0718
VZ		 3844 break;
3845 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 3846 if (print)
3847 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 3848 break;
3849 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 3850 if (print)
3851 _print_next_block(par_num++, "USDM");
72fd0718 3852 break;
8736c826
VZ		 3853 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3854 if (print)
3855 _print_next_block(par_num++, "UCM");
3856 break;
72fd0718 3857 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 3858 if (print)
3859 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 3860 break;
3861 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 3862 if (print)
3863 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 3864 break;
3865 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 3866 if (print)
3867 _print_next_block(par_num++, "CSDM");
72fd0718 3868 break;
8736c826
VZ		 3869 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3870 if (print)
3871 _print_next_block(par_num++, "CCM");
3872 break;
72fd0718
VZ		 3873 }
3874
3875 /* Clear the bit */
3876 sig &= ~cur_bit;
3877 }
3878 }
3879
3880 return par_num;
3881}
3882
c9ee9206
VZ		 3883static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3884 bool print)
72fd0718
VZ		 3885{
3886 int i = 0;
3887 u32 cur_bit = 0;
3888 for (i = 0; sig; i++) {
3889 cur_bit = ((u32)0x1 << i);
3890 if (sig & cur_bit) {
3891 switch (cur_bit) {
3892 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 3893 if (print)
3894 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 3895 break;
3896 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 3897 if (print)
3898 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 3899 break;
3900 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 3901 if (print)
3902 _print_next_block(par_num++,
72fd0718
VZ		 3903 "PXPPCICLOCKCLIENT");
3904 break;
3905 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 3906 if (print)
3907 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 3908 break;
3909 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 3910 if (print)
3911 _print_next_block(par_num++, "CDU");
3912 break;
3913 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3914 if (print)
3915 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 3916 break;
3917 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 3918 if (print)
3919 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 3920 break;
3921 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 3922 if (print)
3923 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 3924 break;
3925 }
3926
3927 /* Clear the bit */
3928 sig &= ~cur_bit;
3929 }
3930 }
3931
3932 return par_num;
3933}
3934
c9ee9206
VZ		 3935static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3936 bool *global, bool print)
72fd0718
VZ		 3937{
3938 int i = 0;
3939 u32 cur_bit = 0;
3940 for (i = 0; sig; i++) {
3941 cur_bit = ((u32)0x1 << i);
3942 if (sig & cur_bit) {
3943 switch (cur_bit) {
3944 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 3945 if (print)
3946 _print_next_block(par_num++, "MCP ROM");
3947 *global = true;
72fd0718
VZ		 3948 break;
3949 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 3950 if (print)
3951 _print_next_block(par_num++,
3952 "MCP UMP RX");
3953 *global = true;
72fd0718
VZ		 3954 break;
3955 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 3956 if (print)
3957 _print_next_block(par_num++,
3958 "MCP UMP TX");
3959 *global = true;
72fd0718
VZ		 3960 break;
3961 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 3962 if (print)
3963 _print_next_block(par_num++,
3964 "MCP SCPAD");
3965 *global = true;
72fd0718
VZ		 3966 break;
3967 }
3968
3969 /* Clear the bit */
3970 sig &= ~cur_bit;
3971 }
3972 }
3973
3974 return par_num;
3975}
3976
8736c826
VZ		 3977static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3978 bool print)
3979{
3980 int i = 0;
3981 u32 cur_bit = 0;
3982 for (i = 0; sig; i++) {
3983 cur_bit = ((u32)0x1 << i);
3984 if (sig & cur_bit) {
3985 switch (cur_bit) {
3986 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3987 if (print)
3988 _print_next_block(par_num++, "PGLUE_B");
3989 break;
3990 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3991 if (print)
3992 _print_next_block(par_num++, "ATC");
3993 break;
3994 }
3995
3996 /* Clear the bit */
3997 sig &= ~cur_bit;
3998 }
3999 }
4000
4001 return par_num;
4002}
4003
c9ee9206 4004static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
8736c826 4005 u32 *sig)
72fd0718 4006{
8736c826
VZ		 4007 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4008 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4009 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4010 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4011 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718
VZ		 4012 int par_num = 0;
4013 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
8736c826
VZ		 4014 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4015 "[4]:0x%08x\n",
4016 sig[0] & HW_PRTY_ASSERT_SET_0,
4017 sig[1] & HW_PRTY_ASSERT_SET_1,
4018 sig[2] & HW_PRTY_ASSERT_SET_2,
4019 sig[3] & HW_PRTY_ASSERT_SET_3,
4020 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4021 if (print)
4022 netdev_err(bp->dev,
4023 "Parity errors detected in blocks: ");
4024 par_num = bnx2x_check_blocks_with_parity0(
8736c826 4025 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 4026 par_num = bnx2x_check_blocks_with_parity1(
8736c826 4027 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 4028 par_num = bnx2x_check_blocks_with_parity2(
8736c826 4029 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 4030 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 4031 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4032 par_num = bnx2x_check_blocks_with_parity4(
4033 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4034
c9ee9206
VZ		 4035 if (print)
4036 pr_cont("\n");
8736c826 4037
72fd0718
VZ		 4038 return true;
4039 } else
4040 return false;
4041}
4042
c9ee9206
VZ		 4043/**
4044 * bnx2x_chk_parity_attn - checks for parity attentions.
4045 *
4046 * @bp: driver handle
4047 * @global: true if there was a global attention
4048 * @print: show parity attention in syslog
4049 */
4050bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4051{
8736c826 4052 struct attn_route attn = { {0} };
72fd0718
VZ		 4053 int port = BP_PORT(bp);
4054
4055 attn.sig[0] = REG_RD(bp,
4056 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4057 port*4);
4058 attn.sig[1] = REG_RD(bp,
4059 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4060 port*4);
4061 attn.sig[2] = REG_RD(bp,
4062 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4063 port*4);
4064 attn.sig[3] = REG_RD(bp,
4065 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4066 port*4);
4067
8736c826
VZ		 4068 if (!CHIP_IS_E1x(bp))
4069 attn.sig[4] = REG_RD(bp,
4070 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4071 port*4);
4072
4073 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4074}
4075
f2e0899f
DK		 4076
4077static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4078{
4079 u32 val;
4080 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4081
4082 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4083 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4084 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4085 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4086 "ADDRESS_ERROR\n");
4087 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4088 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4089 "INCORRECT_RCV_BEHAVIOR\n");
4090 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4091 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4092 "WAS_ERROR_ATTN\n");
4093 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4094 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4095 "VF_LENGTH_VIOLATION_ATTN\n");
4096 if (val &
4097 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4098 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4099 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4100 if (val &
4101 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4102 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4103 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4104 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4105 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4106 "TCPL_ERROR_ATTN\n");
4107 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4108 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4109 "TCPL_IN_TWO_RCBS_ATTN\n");
4110 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4111 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4112 "CSSNOOP_FIFO_OVERFLOW\n");
4113 }
4114 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4115 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4116 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4117 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4118 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4119 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4120 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4121 "_ATC_TCPL_TO_NOT_PEND\n");
4122 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4123 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4124 "ATC_GPA_MULTIPLE_HITS\n");
4125 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4126 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4127 "ATC_RCPL_TO_EMPTY_CNT\n");
4128 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4129 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4130 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4131 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4132 "ATC_IREQ_LESS_THAN_STU\n");
4133 }
4134
4135 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4136 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4137 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4138 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4139 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4140 }
4141
4142}
4143
72fd0718
VZ		 4144static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4145{
4146 struct attn_route attn, *group_mask;
34f80b04 4147 int port = BP_PORT(bp);
877e9aa4 4148 int index;
a2fbb9ea
ET		 4149 u32 reg_addr;
4150 u32 val;
3fcaf2e5 4151 u32 aeu_mask;
c9ee9206 4152 bool global = false;
a2fbb9ea
ET		 4153
4154 /* need to take HW lock because MCP or other port might also
4155 try to handle this event */
4a37fb66 4156 bnx2x_acquire_alr(bp);
a2fbb9ea 4157
c9ee9206
VZ		 4158 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4159#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4160 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4161 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4162 /* Disable HW interrupts */
4163 bnx2x_int_disable(bp);
72fd0718
VZ		 4164 /* In case of parity errors don't handle attentions so that
4165 * other function would "see" parity errors.
4166 */
c9ee9206
VZ		 4167#else
4168 bnx2x_panic();
4169#endif
4170 bnx2x_release_alr(bp);
72fd0718
VZ		 4171 return;
4172 }
4173
a2fbb9ea
ET		 4174 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4175 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4176 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4177 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4178 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4179 attn.sig[4] =
4180 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4181 else
4182 attn.sig[4] = 0;
4183
4184 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4185 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4186
4187 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4188 if (deasserted & (1 << index)) {
72fd0718 4189 group_mask = &bp->attn_group[index];
a2fbb9ea 4190
f2e0899f
DK		 4191 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4192 "%08x %08x %08x\n",
4193 index,
4194 group_mask->sig[0], group_mask->sig[1],
4195 group_mask->sig[2], group_mask->sig[3],
4196 group_mask->sig[4]);
a2fbb9ea 4197
f2e0899f
DK		 4198 bnx2x_attn_int_deasserted4(bp,
4199 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4200 bnx2x_attn_int_deasserted3(bp,
72fd0718 4201 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4202 bnx2x_attn_int_deasserted1(bp,
72fd0718 4203 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4204 bnx2x_attn_int_deasserted2(bp,
72fd0718 4205 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4206 bnx2x_attn_int_deasserted0(bp,
72fd0718 4207 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4208 }
4209 }
4210
4a37fb66 4211 bnx2x_release_alr(bp);
a2fbb9ea 4212
f2e0899f
DK		 4213 if (bp->common.int_block == INT_BLOCK_HC)
4214 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4215 COMMAND_REG_ATTN_BITS_CLR);
4216 else
4217 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4218
4219 val = ~deasserted;
f2e0899f
DK		 4220 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4221 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4222 REG_WR(bp, reg_addr, val);
a2fbb9ea 4223
a2fbb9ea 4224 if (~bp->attn_state & deasserted)
3fcaf2e5 4225 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4226
4227 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4228 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4229
3fcaf2e5
EG		 4230 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4231 aeu_mask = REG_RD(bp, reg_addr);
4232
4233 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4234 aeu_mask, deasserted);
72fd0718 4235 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4236 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4237
3fcaf2e5
EG		 4238 REG_WR(bp, reg_addr, aeu_mask);
4239 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4240
4241 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4242 bp->attn_state &= ~deasserted;
4243 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4244}
4245
4246static void bnx2x_attn_int(struct bnx2x *bp)
4247{
4248 /* read local copy of bits */
68d59484
EG		 4249 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4250 attn_bits);
4251 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4252 attn_bits_ack);
a2fbb9ea
ET		 4253 u32 attn_state = bp->attn_state;
4254
4255 /* look for changed bits */
4256 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4257 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4258
4259 DP(NETIF_MSG_HW,
4260 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4261 attn_bits, attn_ack, asserted, deasserted);
4262
4263 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4264 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4265
4266 /* handle bits that were raised */
4267 if (asserted)
4268 bnx2x_attn_int_asserted(bp, asserted);
4269
4270 if (deasserted)
4271 bnx2x_attn_int_deasserted(bp, deasserted);
4272}
4273
619c5cb6
VZ		 4274void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4275 u16 index, u8 op, u8 update)
4276{
4277 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4278
4279 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4280 igu_addr);
4281}
4282
523224a3
DK		 4283static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4284{
4285 /* No memory barriers */
4286 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4287 mmiowb(); /* keep prod updates ordered */
4288}
4289
4290#ifdef BCM_CNIC
4291static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4292 union event_ring_elem *elem)
4293{
619c5cb6
VZ		 4294 u8 err = elem->message.error;
4295
523224a3 4296 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4297 (cid < bp->cnic_eth_dev.starting_cid &&
4298 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4299 return 1;
4300
4301 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4302
619c5cb6
VZ		 4303 if (unlikely(err)) {
4304
523224a3
DK		 4305 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4306 cid);
4307 bnx2x_panic_dump(bp);
4308 }
619c5cb6 4309 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4310 return 0;
4311}
4312#endif
4313
619c5cb6
VZ		 4314static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4315{
4316 struct bnx2x_mcast_ramrod_params rparam;
4317 int rc;
4318
4319 memset(&rparam, 0, sizeof(rparam));
4320
4321 rparam.mcast_obj = &bp->mcast_obj;
4322
4323 netif_addr_lock_bh(bp->dev);
4324
4325 /* Clear pending state for the last command */
4326 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4327
4328 /* If there are pending mcast commands - send them */
4329 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4330 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4331 if (rc < 0)
4332 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4333 rc);
4334 }
4335
4336 netif_addr_unlock_bh(bp->dev);
4337}
4338
4339static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4340 union event_ring_elem *elem)
4341{
4342 unsigned long ramrod_flags = 0;
4343 int rc = 0;
4344 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4345 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4346
4347 /* Always push next commands out, don't wait here */
4348 __set_bit(RAMROD_CONT, &ramrod_flags);
4349
4350 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4351 case BNX2X_FILTER_MAC_PENDING:
4352#ifdef BCM_CNIC
4353 if (cid == BNX2X_ISCSI_ETH_CID)
4354 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4355 else
4356#endif
4357 vlan_mac_obj = &bp->fp[cid].mac_obj;
4358
4359 break;
4360 vlan_mac_obj = &bp->fp[cid].mac_obj;
4361
4362 case BNX2X_FILTER_MCAST_PENDING:
4363 /* This is only relevant for 57710 where multicast MACs are
4364 * configured as unicast MACs using the same ramrod.
4365 */
4366 bnx2x_handle_mcast_eqe(bp);
4367 return;
4368 default:
4369 BNX2X_ERR("Unsupported classification command: %d\n",
4370 elem->message.data.eth_event.echo);
4371 return;
4372 }
4373
4374 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4375
4376 if (rc < 0)
4377 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4378 else if (rc > 0)
4379 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4380
4381}
4382
4383#ifdef BCM_CNIC
4384static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4385#endif
4386
4387static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4388{
4389 netif_addr_lock_bh(bp->dev);
4390
4391 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4392
4393 /* Send rx_mode command again if was requested */
4394 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4395 bnx2x_set_storm_rx_mode(bp);
4396#ifdef BCM_CNIC
4397 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4398 &bp->sp_state))
4399 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4400 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4401 &bp->sp_state))
4402 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4403#endif
4404
4405 netif_addr_unlock_bh(bp->dev);
4406}
4407
4408static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4409 struct bnx2x *bp, u32 cid)
4410{
6383c0b3 4411 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
619c5cb6
VZ		 4412#ifdef BCM_CNIC
4413 if (cid == BNX2X_FCOE_ETH_CID)
4414 return &bnx2x_fcoe(bp, q_obj);
4415 else
4416#endif
6383c0b3 4417 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
619c5cb6
VZ		 4418}
4419
523224a3
DK		 4420static void bnx2x_eq_int(struct bnx2x *bp)
4421{
4422 u16 hw_cons, sw_cons, sw_prod;
4423 union event_ring_elem *elem;
4424 u32 cid;
4425 u8 opcode;
4426 int spqe_cnt = 0;
619c5cb6
VZ		 4427 struct bnx2x_queue_sp_obj *q_obj;
4428 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4429 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4430
4431 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4432
4433 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4434 * when we get the the next-page we nned to adjust so the loop
4435 * condition below will be met. The next element is the size of a
4436 * regular element and hence incrementing by 1
4437 */
4438 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4439 hw_cons++;
4440
25985edc 4441 /* This function may never run in parallel with itself for a
523224a3
DK		 4442 * specific bp, thus there is no need in "paired" read memory
4443 * barrier here.
4444 */
4445 sw_cons = bp->eq_cons;
4446 sw_prod = bp->eq_prod;
4447
d6cae238 4448 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 4449 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4450
4451 for (; sw_cons != hw_cons;
4452 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4453
4454
4455 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4456
4457 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4458 opcode = elem->message.opcode;
4459
4460
4461 /* handle eq element */
4462 switch (opcode) {
4463 case EVENT_RING_OPCODE_STAT_QUERY:
619c5cb6
VZ		 4464 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4465 bp->stats_comp++);
523224a3 4466 /* nothing to do with stats comp */
d6cae238 4467 goto next_spqe;
523224a3
DK		 4468
4469 case EVENT_RING_OPCODE_CFC_DEL:
4470 /* handle according to cid range */
4471 /*
4472 * we may want to verify here that the bp state is
4473 * HALTING
4474 */
d6cae238 4475 DP(BNX2X_MSG_SP,
523224a3
DK		 4476 "got delete ramrod for MULTI[%d]\n", cid);
4477#ifdef BCM_CNIC
4478 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4479 goto next_spqe;
4480#endif
619c5cb6
VZ		 4481 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4482
4483 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4484 break;
4485
4486
523224a3
DK		 4487
4488 goto next_spqe;
e4901dde
VZ		 4489
4490 case EVENT_RING_OPCODE_STOP_TRAFFIC:
d6cae238 4491 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
6debea87
DK		 4492 if (f_obj->complete_cmd(bp, f_obj,
4493 BNX2X_F_CMD_TX_STOP))
4494 break;
e4901dde
VZ		 4495 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4496 goto next_spqe;
619c5cb6 4497
e4901dde 4498 case EVENT_RING_OPCODE_START_TRAFFIC:
d6cae238 4499 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
6debea87
DK		 4500 if (f_obj->complete_cmd(bp, f_obj,
4501 BNX2X_F_CMD_TX_START))
4502 break;
e4901dde
VZ		 4503 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4504 goto next_spqe;
619c5cb6 4505 case EVENT_RING_OPCODE_FUNCTION_START:
d6cae238 4506 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
619c5cb6
VZ		 4507 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4508 break;
4509
4510 goto next_spqe;
4511
4512 case EVENT_RING_OPCODE_FUNCTION_STOP:
d6cae238 4513 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 4514 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4515 break;
4516
4517 goto next_spqe;
523224a3
DK		 4518 }
4519
4520 switch (opcode | bp->state) {
619c5cb6
VZ		 4521 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4522 BNX2X_STATE_OPEN):
4523 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4524 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4525 cid = elem->message.data.eth_event.echo &
4526 BNX2X_SWCID_MASK;
d6cae238 4527 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 4528 cid);
4529 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4530 break;
4531
619c5cb6
VZ		 4532 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4533 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4534 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4535 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4536 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4537 BNX2X_STATE_OPEN):
4538 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4539 BNX2X_STATE_DIAG):
4540 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4541 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4542 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 4543 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4544 break;
4545
619c5cb6
VZ		 4546 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4547 BNX2X_STATE_OPEN):
4548 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4549 BNX2X_STATE_DIAG):
4550 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4551 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4552 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 4553 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4554 break;
4555
619c5cb6
VZ		 4556 case (EVENT_RING_OPCODE_FILTERS_RULES |
4557 BNX2X_STATE_OPEN):
4558 case (EVENT_RING_OPCODE_FILTERS_RULES |
4559 BNX2X_STATE_DIAG):
4560 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4561 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4562 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 4563 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4564 break;
4565 default:
4566 /* unknown event log error and continue */
619c5cb6
VZ		 4567 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4568 elem->message.opcode, bp->state);
523224a3
DK		 4569 }
4570next_spqe:
4571 spqe_cnt++;
4572 } /* for */
4573
8fe23fbd 4574 smp_mb__before_atomic_inc();
6e30dd4e 4575 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4576
4577 bp->eq_cons = sw_cons;
4578 bp->eq_prod = sw_prod;
4579 /* Make sure that above mem writes were issued towards the memory */
4580 smp_wmb();
4581
4582 /* update producer */
4583 bnx2x_update_eq_prod(bp, bp->eq_prod);
4584}
4585
a2fbb9ea
ET		 4586static void bnx2x_sp_task(struct work_struct *work)
4587{
1cf167f2 4588 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4589 u16 status;
4590
a2fbb9ea 4591 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4592/* if (status == 0) */
4593/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4594
cdaa7cb8 4595 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4596
877e9aa4 4597 /* HW attentions */
523224a3 4598 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4599 bnx2x_attn_int(bp);
523224a3 4600 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4601 }
4602
523224a3
DK		 4603 /* SP events: STAT_QUERY and others */
4604 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4605#ifdef BCM_CNIC
4606 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4607
ec6ba945 4608 if ((!NO_FCOE(bp)) &&
019dbb4c
VZ		 4609 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4610 /*
4611 * Prevent local bottom-halves from running as
4612 * we are going to change the local NAPI list.
4613 */
4614 local_bh_disable();
ec6ba945 4615 napi_schedule(&bnx2x_fcoe(bp, napi));
019dbb4c
VZ		 4616 local_bh_enable();
4617 }
ec6ba945 4618#endif
523224a3
DK		 4619 /* Handle EQ completions */
4620 bnx2x_eq_int(bp);
4621
4622 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4623 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4624
4625 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4626 }
4627
4628 if (unlikely(status))
4629 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4630 status);
a2fbb9ea 4631
523224a3
DK		 4632 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4633 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4634}
4635
9f6c9258 4636irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4637{
4638 struct net_device *dev = dev_instance;
4639 struct bnx2x *bp = netdev_priv(dev);
4640
523224a3
DK		 4641 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4642 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4643
4644#ifdef BNX2X_STOP_ON_ERROR
4645 if (unlikely(bp->panic))
4646 return IRQ_HANDLED;
4647#endif
4648
993ac7b5
MC		 4649#ifdef BCM_CNIC
4650 {
4651 struct cnic_ops *c_ops;
4652
4653 rcu_read_lock();
4654 c_ops = rcu_dereference(bp->cnic_ops);
4655 if (c_ops)
4656 c_ops->cnic_handler(bp->cnic_data, NULL);
4657 rcu_read_unlock();
4658 }
4659#endif
1cf167f2 4660 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4661
4662 return IRQ_HANDLED;
4663}
4664
4665/* end of slow path */
4666
619c5cb6
VZ		 4667
4668void bnx2x_drv_pulse(struct bnx2x *bp)
4669{
4670 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4671 bp->fw_drv_pulse_wr_seq);
4672}
4673
4674
a2fbb9ea
ET		 4675static void bnx2x_timer(unsigned long data)
4676{
6383c0b3 4677 u8 cos;
a2fbb9ea
ET		 4678 struct bnx2x *bp = (struct bnx2x *) data;
4679
4680 if (!netif_running(bp->dev))
4681 return;
4682
a2fbb9ea
ET		 4683 if (poll) {
4684 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 4685
6383c0b3
AE		 4686 for_each_cos_in_tx_queue(fp, cos)
4687 bnx2x_tx_int(bp, &fp->txdata[cos]);
b8ee8328 4688 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 4689 }
4690
34f80b04 4691 if (!BP_NOMCP(bp)) {
f2e0899f 4692 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4693 u32 drv_pulse;
4694 u32 mcp_pulse;
4695
4696 ++bp->fw_drv_pulse_wr_seq;
4697 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4698 /* TBD - add SYSTEM_TIME */
4699 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4700 bnx2x_drv_pulse(bp);
a2fbb9ea 4701
f2e0899f 4702 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4703 MCP_PULSE_SEQ_MASK);
4704 /* The delta between driver pulse and mcp response
4705 * should be 1 (before mcp response) or 0 (after mcp response)
4706 */
4707 if ((drv_pulse != mcp_pulse) &&
4708 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4709 /* someone lost a heartbeat... */
4710 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4711 drv_pulse, mcp_pulse);
4712 }
4713 }
4714
f34d28ea 4715 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4716 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4717
a2fbb9ea
ET		 4718 mod_timer(&bp->timer, jiffies + bp->current_interval);
4719}
4720
4721/* end of Statistics */
4722
4723/* nic init */
4724
4725/*
4726 * nic init service functions
4727 */
4728
523224a3 4729static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4730{
523224a3
DK		 4731 u32 i;
4732 if (!(len%4) && !(addr%4))
4733 for (i = 0; i < len; i += 4)
4734 REG_WR(bp, addr + i, fill);
4735 else
4736 for (i = 0; i < len; i++)
4737 REG_WR8(bp, addr + i, fill);
34f80b04 4738
34f80b04
EG		 4739}
4740
523224a3
DK		 4741/* helper: writes FP SP data to FW - data_size in dwords */
4742static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4743 int fw_sb_id,
4744 u32 *sb_data_p,
4745 u32 data_size)
34f80b04 4746{
a2fbb9ea 4747 int index;
523224a3
DK		 4748 for (index = 0; index < data_size; index++)
4749 REG_WR(bp, BAR_CSTRORM_INTMEM +
4750 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4751 sizeof(u32)*index,
4752 *(sb_data_p + index));
4753}
a2fbb9ea 4754
523224a3
DK		 4755static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4756{
4757 u32 *sb_data_p;
4758 u32 data_size = 0;
f2e0899f 4759 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4760 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4761
523224a3 4762 /* disable the function first */
619c5cb6 4763 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4764 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4765 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4766 sb_data_e2.common.p_func.vf_valid = false;
4767 sb_data_p = (u32 *)&sb_data_e2;
4768 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4769 } else {
4770 memset(&sb_data_e1x, 0,
4771 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4772 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4773 sb_data_e1x.common.p_func.vf_valid = false;
4774 sb_data_p = (u32 *)&sb_data_e1x;
4775 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4776 }
523224a3 4777 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4778
523224a3
DK		 4779 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4780 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4781 CSTORM_STATUS_BLOCK_SIZE);
4782 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4783 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4784 CSTORM_SYNC_BLOCK_SIZE);
4785}
34f80b04 4786
523224a3
DK		 4787/* helper: writes SP SB data to FW */
4788static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4789 struct hc_sp_status_block_data *sp_sb_data)
4790{
4791 int func = BP_FUNC(bp);
4792 int i;
4793 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4794 REG_WR(bp, BAR_CSTRORM_INTMEM +
4795 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4796 i*sizeof(u32),
4797 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4798}
4799
523224a3 4800static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4801{
4802 int func = BP_FUNC(bp);
523224a3
DK		 4803 struct hc_sp_status_block_data sp_sb_data;
4804 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4805
619c5cb6 4806 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4807 sp_sb_data.p_func.vf_valid = false;
4808
4809 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4810
4811 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4812 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4813 CSTORM_SP_STATUS_BLOCK_SIZE);
4814 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4815 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4816 CSTORM_SP_SYNC_BLOCK_SIZE);
4817
4818}
4819
4820
4821static inline
4822void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4823 int igu_sb_id, int igu_seg_id)
4824{
4825 hc_sm->igu_sb_id = igu_sb_id;
4826 hc_sm->igu_seg_id = igu_seg_id;
4827 hc_sm->timer_value = 0xFF;
4828 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4829}
4830
8d96286a 4831static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4832 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4833{
523224a3
DK		 4834 int igu_seg_id;
4835
f2e0899f 4836 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4837 struct hc_status_block_data_e1x sb_data_e1x;
4838 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4839 int data_size;
4840 u32 *sb_data_p;
4841
f2e0899f
DK		 4842 if (CHIP_INT_MODE_IS_BC(bp))
4843 igu_seg_id = HC_SEG_ACCESS_NORM;
4844 else
4845 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4846
4847 bnx2x_zero_fp_sb(bp, fw_sb_id);
4848
619c5cb6 4849 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4850 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4851 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 4852 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4853 sb_data_e2.common.p_func.vf_id = vfid;
4854 sb_data_e2.common.p_func.vf_valid = vf_valid;
4855 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4856 sb_data_e2.common.same_igu_sb_1b = true;
4857 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4858 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4859 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4860 sb_data_p = (u32 *)&sb_data_e2;
4861 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4862 } else {
4863 memset(&sb_data_e1x, 0,
4864 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4865 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 4866 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4867 sb_data_e1x.common.p_func.vf_id = 0xff;
4868 sb_data_e1x.common.p_func.vf_valid = false;
4869 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4870 sb_data_e1x.common.same_igu_sb_1b = true;
4871 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4872 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4873 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4874 sb_data_p = (u32 *)&sb_data_e1x;
4875 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4876 }
523224a3
DK		 4877
4878 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4879 igu_sb_id, igu_seg_id);
4880 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4881 igu_sb_id, igu_seg_id);
4882
4883 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4884
4885 /* write indecies to HW */
4886 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4887}
4888
619c5cb6 4889static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 4890 u16 tx_usec, u16 rx_usec)
4891{
6383c0b3 4892 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 4893 false, rx_usec);
6383c0b3
AE		 4894 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4895 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4896 tx_usec);
4897 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4898 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4899 tx_usec);
4900 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4901 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4902 tx_usec);
523224a3 4903}
f2e0899f 4904
523224a3
DK		 4905static void bnx2x_init_def_sb(struct bnx2x *bp)
4906{
4907 struct host_sp_status_block *def_sb = bp->def_status_blk;
4908 dma_addr_t mapping = bp->def_status_blk_mapping;
4909 int igu_sp_sb_index;
4910 int igu_seg_id;
34f80b04
EG		 4911 int port = BP_PORT(bp);
4912 int func = BP_FUNC(bp);
523224a3 4913 int reg_offset;
a2fbb9ea 4914 u64 section;
523224a3
DK		 4915 int index;
4916 struct hc_sp_status_block_data sp_sb_data;
4917 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4918
f2e0899f
DK		 4919 if (CHIP_INT_MODE_IS_BC(bp)) {
4920 igu_sp_sb_index = DEF_SB_IGU_ID;
4921 igu_seg_id = HC_SEG_ACCESS_DEF;
4922 } else {
4923 igu_sp_sb_index = bp->igu_dsb_id;
4924 igu_seg_id = IGU_SEG_ACCESS_DEF;
4925 }
a2fbb9ea
ET		 4926
4927 /* ATTN */
523224a3 4928 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4929 atten_status_block);
523224a3 4930 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4931
49d66772
ET		 4932 bp->attn_state = 0;
4933
a2fbb9ea
ET		 4934 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4935 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4936 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4937 int sindex;
4938 /* take care of sig[0]..sig[4] */
4939 for (sindex = 0; sindex < 4; sindex++)
4940 bp->attn_group[index].sig[sindex] =
4941 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 4942
619c5cb6 4943 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4944 /*
4945 * enable5 is separate from the rest of the registers,
4946 * and therefore the address skip is 4
4947 * and not 16 between the different groups
4948 */
4949 bp->attn_group[index].sig[4] = REG_RD(bp,
4950 reg_offset + 0x10 + 0x4*index);
4951 else
4952 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4953 }
4954
f2e0899f
DK		 4955 if (bp->common.int_block == INT_BLOCK_HC) {
4956 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4957 HC_REG_ATTN_MSG0_ADDR_L);
4958
4959 REG_WR(bp, reg_offset, U64_LO(section));
4960 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 4961 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4962 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4963 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4964 }
a2fbb9ea 4965
523224a3
DK		 4966 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4967 sp_sb);
a2fbb9ea 4968
523224a3 4969 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4970
619c5cb6 4971 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 4972 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4973 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4974 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4975 sp_sb_data.igu_seg_id = igu_seg_id;
4976 sp_sb_data.p_func.pf_id = func;
f2e0899f 4977 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4978 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4979
523224a3 4980 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4981
523224a3 4982 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4983}
4984
9f6c9258 4985void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4986{
a2fbb9ea
ET		 4987 int i;
4988
ec6ba945 4989 for_each_eth_queue(bp, i)
523224a3 4990 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 4991 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 4992}
4993
a2fbb9ea
ET		 4994static void bnx2x_init_sp_ring(struct bnx2x *bp)
4995{
a2fbb9ea 4996 spin_lock_init(&bp->spq_lock);
6e30dd4e 4997 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4998
a2fbb9ea 4999 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5000 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5001 bp->spq_prod_bd = bp->spq;
5002 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5003}
5004
523224a3 5005static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5006{
5007 int i;
523224a3
DK		 5008 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5009 union event_ring_elem *elem =
5010 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5011
523224a3
DK		 5012 elem->next_page.addr.hi =
5013 cpu_to_le32(U64_HI(bp->eq_mapping +
5014 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5015 elem->next_page.addr.lo =
5016 cpu_to_le32(U64_LO(bp->eq_mapping +
5017 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5018 }
523224a3
DK		 5019 bp->eq_cons = 0;
5020 bp->eq_prod = NUM_EQ_DESC;
5021 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 5022 /* we want a warning message before it gets rought... */
5023 atomic_set(&bp->eq_spq_left,
5024 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5025}
5026
619c5cb6
VZ		 5027
5028/* called with netif_addr_lock_bh() */
5029void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5030 unsigned long rx_mode_flags,
5031 unsigned long rx_accept_flags,
5032 unsigned long tx_accept_flags,
5033 unsigned long ramrod_flags)
ab532cf3 5034{
619c5cb6
VZ		 5035 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5036 int rc;
5037
5038 memset(&ramrod_param, 0, sizeof(ramrod_param));
5039
5040 /* Prepare ramrod parameters */
5041 ramrod_param.cid = 0;
5042 ramrod_param.cl_id = cl_id;
5043 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5044 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5045
619c5cb6
VZ		 5046 ramrod_param.pstate = &bp->sp_state;
5047 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5048
619c5cb6
VZ		 5049 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5050 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5051
5052 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5053
5054 ramrod_param.ramrod_flags = ramrod_flags;
5055 ramrod_param.rx_mode_flags = rx_mode_flags;
5056
5057 ramrod_param.rx_accept_flags = rx_accept_flags;
5058 ramrod_param.tx_accept_flags = tx_accept_flags;
5059
5060 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5061 if (rc < 0) {
5062 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5063 return;
5064 }
a2fbb9ea
ET		 5065}
5066
619c5cb6
VZ		 5067/* called with netif_addr_lock_bh() */
5068void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5069{
619c5cb6
VZ		 5070 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5071 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5072
619c5cb6
VZ		 5073#ifdef BCM_CNIC
5074 if (!NO_FCOE(bp))
5075
5076 /* Configure rx_mode of FCoE Queue */
5077 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5078#endif
5079
5080 switch (bp->rx_mode) {
5081 case BNX2X_RX_MODE_NONE:
5082 /*
5083 * 'drop all' supersedes any accept flags that may have been
5084 * passed to the function.
5085 */
5086 break;
5087 case BNX2X_RX_MODE_NORMAL:
5088 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5089 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5090 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5091
5092 /* internal switching mode */
5093 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5094 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5095 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5096
5097 break;
5098 case BNX2X_RX_MODE_ALLMULTI:
5099 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5100 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5101 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5102
5103 /* internal switching mode */
5104 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5105 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5106 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5107
5108 break;
5109 case BNX2X_RX_MODE_PROMISC:
5110 /* According to deffinition of SI mode, iface in promisc mode
5111 * should receive matched and unmatched (in resolution of port)
5112 * unicast packets.
5113 */
5114 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5115 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5116 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5117 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5118
5119 /* internal switching mode */
5120 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5121 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5122
5123 if (IS_MF_SI(bp))
5124 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5125 else
5126 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5127
5128 break;
5129 default:
5130 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5131 return;
5132 }
de832a55 5133
619c5cb6
VZ		 5134 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5135 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5136 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5137 }
5138
619c5cb6
VZ		 5139 __set_bit(RAMROD_RX, &ramrod_flags);
5140 __set_bit(RAMROD_TX, &ramrod_flags);
5141
5142 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5143 tx_accept_flags, ramrod_flags);
5144}
5145
5146static void bnx2x_init_internal_common(struct bnx2x *bp)
5147{
5148 int i;
5149
0793f83f
DK		 5150 if (IS_MF_SI(bp))
5151 /*
5152 * In switch independent mode, the TSTORM needs to accept
5153 * packets that failed classification, since approximate match
5154 * mac addresses aren't written to NIG LLH
5155 */
5156 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5157 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5158 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5159 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5160 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5161
523224a3
DK		 5162 /* Zero this manually as its initialization is
5163 currently missing in the initTool */
5164 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5165 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5166 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5167 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5168 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5169 CHIP_INT_MODE_IS_BC(bp) ?
5170 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5171 }
523224a3 5172}
8a1c38d1 5173
471de716
EG		 5174static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5175{
5176 switch (load_code) {
5177 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5178 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5179 bnx2x_init_internal_common(bp);
5180 /* no break */
5181
5182 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5183 /* nothing to do */
471de716
EG		 5184 /* no break */
5185
5186 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5187 /* internal memory per function is
5188 initialized inside bnx2x_pf_init */
471de716
EG		 5189 break;
5190
5191 default:
5192 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5193 break;
5194 }
5195}
5196
619c5cb6 5197static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5198{
6383c0b3 5199 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
619c5cb6 5200}
523224a3 5201
619c5cb6
VZ		 5202static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5203{
6383c0b3 5204 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
619c5cb6
VZ		 5205}
5206
5207static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5208{
5209 if (CHIP_IS_E1x(fp->bp))
5210 return BP_L_ID(fp->bp) + fp->index;
5211 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5212 return bnx2x_fp_igu_sb_id(fp);
5213}
5214
6383c0b3 5215static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5216{
5217 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5218 u8 cos;
619c5cb6 5219 unsigned long q_type = 0;
6383c0b3 5220 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
523224a3 5221
b3b83c3f 5222 fp->cid = fp_idx;
619c5cb6
VZ		 5223 fp->cl_id = bnx2x_fp_cl_id(fp);
5224 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5225 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5226 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5227 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5228
523224a3 5229 /* init shortcut */
619c5cb6 5230 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
523224a3
DK		 5231 /* Setup SB indicies */
5232 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5233
619c5cb6
VZ		 5234 /* Configure Queue State object */
5235 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5236 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5237
5238 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5239
5240 /* init tx data */
5241 for_each_cos_in_tx_queue(fp, cos) {
5242 bnx2x_init_txdata(bp, &fp->txdata[cos],
5243 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5244 FP_COS_TO_TXQ(fp, cos),
5245 BNX2X_TX_SB_INDEX_BASE + cos);
5246 cids[cos] = fp->txdata[cos].cid;
5247 }
5248
5249 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5250 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5251 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5252
5253 /**
5254 * Configure classification DBs: Always enable Tx switching
5255 */
5256 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5257
523224a3
DK		 5258 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5259 "cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 5260 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 5261 fp->igu_sb_id);
5262 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5263 fp->fw_sb_id, fp->igu_sb_id);
5264
5265 bnx2x_update_fpsb_idx(fp);
5266}
5267
9f6c9258 5268void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 5269{
5270 int i;
5271
ec6ba945 5272 for_each_eth_queue(bp, i)
6383c0b3 5273 bnx2x_init_eth_fp(bp, i);
37b091ba 5274#ifdef BCM_CNIC
ec6ba945
VZ		 5275 if (!NO_FCOE(bp))
5276 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5277
5278 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5279 BNX2X_VF_ID_INVALID, false,
619c5cb6 5280 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5281
37b091ba 5282#endif
a2fbb9ea 5283
020c7e3f
YR		 5284 /* Initialize MOD_ABS interrupts */
5285 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5286 bp->common.shmem_base, bp->common.shmem2_base,
5287 BP_PORT(bp));
16119785
EG		 5288 /* ensure status block indices were read */
5289 rmb();
5290
523224a3 5291 bnx2x_init_def_sb(bp);
5c862848 5292 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5293 bnx2x_init_rx_rings(bp);
523224a3 5294 bnx2x_init_tx_rings(bp);
a2fbb9ea 5295 bnx2x_init_sp_ring(bp);
523224a3 5296 bnx2x_init_eq_ring(bp);
471de716 5297 bnx2x_init_internal(bp, load_code);
523224a3 5298 bnx2x_pf_init(bp);
0ef00459
EG		 5299 bnx2x_stats_init(bp);
5300
0ef00459
EG		 5301 /* flush all before enabling interrupts */
5302 mb();
5303 mmiowb();
5304
615f8fd9 5305 bnx2x_int_enable(bp);
eb8da205
EG		 5306
5307 /* Check for SPIO5 */
5308 bnx2x_attn_int_deasserted0(bp,
5309 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5310 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5311}
5312
5313/* end of nic init */
5314
5315/*
5316 * gzip service functions
5317 */
5318
5319static int bnx2x_gunzip_init(struct bnx2x *bp)
5320{
1a983142
FT		 5321 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5322 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5323 if (bp->gunzip_buf == NULL)
5324 goto gunzip_nomem1;
5325
5326 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5327 if (bp->strm == NULL)
5328 goto gunzip_nomem2;
5329
7ab24bfd 5330 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5331 if (bp->strm->workspace == NULL)
5332 goto gunzip_nomem3;
5333
5334 return 0;
5335
5336gunzip_nomem3:
5337 kfree(bp->strm);
5338 bp->strm = NULL;
5339
5340gunzip_nomem2:
1a983142
FT		 5341 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5342 bp->gunzip_mapping);
a2fbb9ea
ET		 5343 bp->gunzip_buf = NULL;
5344
5345gunzip_nomem1:
cdaa7cb8
VZ		 5346 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5347 " un-compression\n");
a2fbb9ea
ET		 5348 return -ENOMEM;
5349}
5350
5351static void bnx2x_gunzip_end(struct bnx2x *bp)
5352{
b3b83c3f 5353 if (bp->strm) {
7ab24bfd 5354 vfree(bp->strm->workspace);
b3b83c3f
DK		 5355 kfree(bp->strm);
5356 bp->strm = NULL;
5357 }
a2fbb9ea
ET		 5358
5359 if (bp->gunzip_buf) {
1a983142
FT		 5360 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5361 bp->gunzip_mapping);
a2fbb9ea
ET		 5362 bp->gunzip_buf = NULL;
5363 }
5364}
5365
94a78b79 5366static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 5367{
5368 int n, rc;
5369
5370 /* check gzip header */
94a78b79
VZ		 5371 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5372 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 5373 return -EINVAL;
94a78b79 5374 }
a2fbb9ea
ET		 5375
5376 n = 10;
5377
34f80b04 5378#define FNAME 0x8
a2fbb9ea
ET		 5379
5380 if (zbuf[3] & FNAME)
5381 while ((zbuf[n++] != 0) && (n < len));
5382
94a78b79 5383 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 5384 bp->strm->avail_in = len - n;
5385 bp->strm->next_out = bp->gunzip_buf;
5386 bp->strm->avail_out = FW_BUF_SIZE;
5387
5388 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5389 if (rc != Z_OK)
5390 return rc;
5391
5392 rc = zlib_inflate(bp->strm, Z_FINISH);
5393 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 5394 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5395 bp->strm->msg);
a2fbb9ea
ET		 5396
5397 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5398 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 5399 netdev_err(bp->dev, "Firmware decompression error:"
5400 " gunzip_outlen (%d) not aligned\n",
5401 bp->gunzip_outlen);
a2fbb9ea
ET		 5402 bp->gunzip_outlen >>= 2;
5403
5404 zlib_inflateEnd(bp->strm);
5405
5406 if (rc == Z_STREAM_END)
5407 return 0;
5408
5409 return rc;
5410}
5411
5412/* nic load/unload */
5413
5414/*
34f80b04 5415 * General service functions
a2fbb9ea
ET		 5416 */
5417
5418/* send a NIG loopback debug packet */
5419static void bnx2x_lb_pckt(struct bnx2x *bp)
5420{
a2fbb9ea 5421 u32 wb_write[3];
a2fbb9ea
ET		 5422
5423 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 5424 wb_write[0] = 0x55555555;
5425 wb_write[1] = 0x55555555;
34f80b04 5426 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 5427 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5428
5429 /* NON-IP protocol */
a2fbb9ea
ET		 5430 wb_write[0] = 0x09000000;
5431 wb_write[1] = 0x55555555;
34f80b04 5432 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 5433 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5434}
5435
5436/* some of the internal memories
5437 * are not directly readable from the driver
5438 * to test them we send debug packets
5439 */
5440static int bnx2x_int_mem_test(struct bnx2x *bp)
5441{
5442 int factor;
5443 int count, i;
5444 u32 val = 0;
5445
ad8d3948 5446 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 5447 factor = 120;
ad8d3948
EG		 5448 else if (CHIP_REV_IS_EMUL(bp))
5449 factor = 200;
5450 else
a2fbb9ea 5451 factor = 1;
a2fbb9ea 5452
a2fbb9ea
ET		 5453 /* Disable inputs of parser neighbor blocks */
5454 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5455 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5456 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5457 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5458
5459 /* Write 0 to parser credits for CFC search request */
5460 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5461
5462 /* send Ethernet packet */
5463 bnx2x_lb_pckt(bp);
5464
5465 /* TODO do i reset NIG statistic? */
5466 /* Wait until NIG register shows 1 packet of size 0x10 */
5467 count = 1000 * factor;
5468 while (count) {
34f80b04 5469
a2fbb9ea
ET		 5470 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5471 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5472 if (val == 0x10)
5473 break;
5474
5475 msleep(10);
5476 count--;
5477 }
5478 if (val != 0x10) {
5479 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5480 return -1;
5481 }
5482
5483 /* Wait until PRS register shows 1 packet */
5484 count = 1000 * factor;
5485 while (count) {
5486 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 5487 if (val == 1)
5488 break;
5489
5490 msleep(10);
5491 count--;
5492 }
5493 if (val != 0x1) {
5494 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5495 return -2;
5496 }
5497
5498 /* Reset and init BRB, PRS */
34f80b04 5499 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5500 msleep(50);
34f80b04 5501 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5502 msleep(50);
619c5cb6
VZ		 5503 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5504 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5505
5506 DP(NETIF_MSG_HW, "part2\n");
5507
5508 /* Disable inputs of parser neighbor blocks */
5509 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5510 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5511 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5512 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5513
5514 /* Write 0 to parser credits for CFC search request */
5515 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5516
5517 /* send 10 Ethernet packets */
5518 for (i = 0; i < 10; i++)
5519 bnx2x_lb_pckt(bp);
5520
5521 /* Wait until NIG register shows 10 + 1
5522 packets of size 11*0x10 = 0xb0 */
5523 count = 1000 * factor;
5524 while (count) {
34f80b04 5525
a2fbb9ea
ET		 5526 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5527 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5528 if (val == 0xb0)
5529 break;
5530
5531 msleep(10);
5532 count--;
5533 }
5534 if (val != 0xb0) {
5535 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5536 return -3;
5537 }
5538
5539 /* Wait until PRS register shows 2 packets */
5540 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5541 if (val != 2)
5542 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5543
5544 /* Write 1 to parser credits for CFC search request */
5545 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5546
5547 /* Wait until PRS register shows 3 packets */
5548 msleep(10 * factor);
5549 /* Wait until NIG register shows 1 packet of size 0x10 */
5550 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5551 if (val != 3)
5552 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5553
5554 /* clear NIG EOP FIFO */
5555 for (i = 0; i < 11; i++)
5556 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5557 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5558 if (val != 1) {
5559 BNX2X_ERR("clear of NIG failed\n");
5560 return -4;
5561 }
5562
5563 /* Reset and init BRB, PRS, NIG */
5564 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5565 msleep(50);
5566 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5567 msleep(50);
619c5cb6
VZ		 5568 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5569 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5570#ifndef BCM_CNIC
a2fbb9ea
ET		 5571 /* set NIC mode */
5572 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5573#endif
5574
5575 /* Enable inputs of parser neighbor blocks */
5576 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5577 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5578 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5579 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5580
5581 DP(NETIF_MSG_HW, "done\n");
5582
5583 return 0; /* OK */
5584}
5585
4a33bc03 5586static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5587{
5588 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5589 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5590 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5591 else
5592 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5593 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5594 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5595 /*
5596 * mask read length error interrupts in brb for parser
5597 * (parsing unit and 'checksum and crc' unit)
5598 * these errors are legal (PU reads fixed length and CAC can cause
5599 * read length error on truncated packets)
5600 */
5601 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5602 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5603 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5604 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5605 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5606 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5607/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5608/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5609 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5610 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5611 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5612/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5613/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5614 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5615 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5616 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5617 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5618/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5619/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5620
34f80b04
EG		 5621 if (CHIP_REV_IS_FPGA(bp))
5622 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5623 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5624 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5625 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5626 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5627 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5628 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5629 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5630 else
5631 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5632 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5633 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5634 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5635/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5636
5637 if (!CHIP_IS_E1x(bp))
5638 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5639 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5640
a2fbb9ea
ET		 5641 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5642 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5643/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5644 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5645}
5646
81f75bbf
EG		 5647static void bnx2x_reset_common(struct bnx2x *bp)
5648{
619c5cb6
VZ		 5649 u32 val = 0x1400;
5650
81f75bbf
EG		 5651 /* reset_common */
5652 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5653 0xd3ffff7f);
619c5cb6
VZ		 5654
5655 if (CHIP_IS_E3(bp)) {
5656 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5657 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5658 }
5659
5660 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5661}
5662
5663static void bnx2x_setup_dmae(struct bnx2x *bp)
5664{
5665 bp->dmae_ready = 0;
5666 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5667}
5668
573f2035
EG		 5669static void bnx2x_init_pxp(struct bnx2x *bp)
5670{
5671 u16 devctl;
5672 int r_order, w_order;
5673
5674 pci_read_config_word(bp->pdev,
b6c2f86e 5675 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 5676 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5677 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5678 if (bp->mrrs == -1)
5679 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5680 else {
5681 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5682 r_order = bp->mrrs;
5683 }
5684
5685 bnx2x_init_pxp_arb(bp, r_order, w_order);
5686}
fd4ef40d
EG		 5687
5688static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5689{
2145a920 5690 int is_required;
fd4ef40d 5691 u32 val;
2145a920 5692 int port;
fd4ef40d 5693
2145a920
VZ		 5694 if (BP_NOMCP(bp))
5695 return;
5696
5697 is_required = 0;
fd4ef40d
EG		 5698 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5699 SHARED_HW_CFG_FAN_FAILURE_MASK;
5700
5701 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5702 is_required = 1;
5703
5704 /*
5705 * The fan failure mechanism is usually related to the PHY type since
5706 * the power consumption of the board is affected by the PHY. Currently,
5707 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5708 */
5709 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5710 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5711 is_required |=
d90d96ba
YR		 5712 bnx2x_fan_failure_det_req(
5713 bp,
5714 bp->common.shmem_base,
a22f0788 5715 bp->common.shmem2_base,
d90d96ba 5716 port);
fd4ef40d
EG		 5717 }
5718
5719 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5720
5721 if (is_required == 0)
5722 return;
5723
5724 /* Fan failure is indicated by SPIO 5 */
5725 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5726 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5727
5728 /* set to active low mode */
5729 val = REG_RD(bp, MISC_REG_SPIO_INT);
5730 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5731 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5732 REG_WR(bp, MISC_REG_SPIO_INT, val);
5733
5734 /* enable interrupt to signal the IGU */
5735 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5736 val |= (1 << MISC_REGISTERS_SPIO_5);
5737 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5738}
5739
f2e0899f
DK		 5740static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5741{
5742 u32 offset = 0;
5743
5744 if (CHIP_IS_E1(bp))
5745 return;
5746 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5747 return;
5748
5749 switch (BP_ABS_FUNC(bp)) {
5750 case 0:
5751 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5752 break;
5753 case 1:
5754 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5755 break;
5756 case 2:
5757 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5758 break;
5759 case 3:
5760 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5761 break;
5762 case 4:
5763 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5764 break;
5765 case 5:
5766 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5767 break;
5768 case 6:
5769 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5770 break;
5771 case 7:
5772 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5773 break;
5774 default:
5775 return;
5776 }
5777
5778 REG_WR(bp, offset, pretend_func_num);
5779 REG_RD(bp, offset);
5780 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5781}
5782
c9ee9206 5783void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 5784{
5785 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5786 val &= ~IGU_PF_CONF_FUNC_EN;
5787
5788 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5789 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5790 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5791}
5792
619c5cb6
VZ		 5793static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5794{
5795 u32 shmem_base[2], shmem2_base[2];
5796 shmem_base[0] = bp->common.shmem_base;
5797 shmem2_base[0] = bp->common.shmem2_base;
5798 if (!CHIP_IS_E1x(bp)) {
5799 shmem_base[1] =
5800 SHMEM2_RD(bp, other_shmem_base_addr);
5801 shmem2_base[1] =
5802 SHMEM2_RD(bp, other_shmem2_base_addr);
5803 }
5804 bnx2x_acquire_phy_lock(bp);
5805 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5806 bp->common.chip_id);
5807 bnx2x_release_phy_lock(bp);
5808}
5809
5810/**
5811 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5812 *
5813 * @bp: driver handle
5814 */
5815static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 5816{
619c5cb6 5817 u32 val;
a2fbb9ea 5818
f2e0899f 5819 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 5820
2031bd3a
DK		 5821 /*
5822 * take the UNDI lock to protect undi_unload flow from accessing
5823 * registers while we're resetting the chip
5824 */
7a06a122 5825 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 5826
81f75bbf 5827 bnx2x_reset_common(bp);
34f80b04 5828 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 5829
619c5cb6
VZ		 5830 val = 0xfffc;
5831 if (CHIP_IS_E3(bp)) {
5832 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5833 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5834 }
5835 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5836
7a06a122 5837 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 5838
619c5cb6 5839 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 5840
619c5cb6
VZ		 5841 if (!CHIP_IS_E1x(bp)) {
5842 u8 abs_func_id;
f2e0899f
DK		 5843
5844 /**
5845 * 4-port mode or 2-port mode we need to turn of master-enable
5846 * for everyone, after that, turn it back on for self.
5847 * so, we disregard multi-function or not, and always disable
5848 * for all functions on the given path, this means 0,2,4,6 for
5849 * path 0 and 1,3,5,7 for path 1
5850 */
619c5cb6
VZ		 5851 for (abs_func_id = BP_PATH(bp);
5852 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5853 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 5854 REG_WR(bp,
5855 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5856 1);
5857 continue;
5858 }
5859
619c5cb6 5860 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 5861 /* clear pf enable */
5862 bnx2x_pf_disable(bp);
5863 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5864 }
5865 }
a2fbb9ea 5866
619c5cb6 5867 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 5868 if (CHIP_IS_E1(bp)) {
5869 /* enable HW interrupt from PXP on USDM overflow
5870 bit 16 on INT_MASK_0 */
5871 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5872 }
a2fbb9ea 5873
619c5cb6 5874 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 5875 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5876
5877#ifdef __BIG_ENDIAN
34f80b04
EG		 5878 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5879 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5880 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5881 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5882 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5883 /* make sure this value is 0 */
5884 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5885
5886/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5887 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5888 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5889 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5890 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5891#endif
5892
523224a3
DK		 5893 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5894
34f80b04
EG		 5895 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5896 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5897
34f80b04
EG		 5898 /* let the HW do it's magic ... */
5899 msleep(100);
5900 /* finish PXP init */
5901 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5902 if (val != 1) {
5903 BNX2X_ERR("PXP2 CFG failed\n");
5904 return -EBUSY;
5905 }
5906 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5907 if (val != 1) {
5908 BNX2X_ERR("PXP2 RD_INIT failed\n");
5909 return -EBUSY;
5910 }
a2fbb9ea 5911
f2e0899f
DK		 5912 /* Timers bug workaround E2 only. We need to set the entire ILT to
5913 * have entries with value "0" and valid bit on.
5914 * This needs to be done by the first PF that is loaded in a path
5915 * (i.e. common phase)
5916 */
619c5cb6
VZ		 5917 if (!CHIP_IS_E1x(bp)) {
5918/* In E2 there is a bug in the timers block that can cause function 6 / 7
5919 * (i.e. vnic3) to start even if it is marked as "scan-off".
5920 * This occurs when a different function (func2,3) is being marked
5921 * as "scan-off". Real-life scenario for example: if a driver is being
5922 * load-unloaded while func6,7 are down. This will cause the timer to access
5923 * the ilt, translate to a logical address and send a request to read/write.
5924 * Since the ilt for the function that is down is not valid, this will cause
5925 * a translation error which is unrecoverable.
5926 * The Workaround is intended to make sure that when this happens nothing fatal
5927 * will occur. The workaround:
5928 * 1. First PF driver which loads on a path will:
5929 * a. After taking the chip out of reset, by using pretend,
5930 * it will write "0" to the following registers of
5931 * the other vnics.
5932 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5933 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5934 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5935 * And for itself it will write '1' to
5936 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5937 * dmae-operations (writing to pram for example.)
5938 * note: can be done for only function 6,7 but cleaner this
5939 * way.
5940 * b. Write zero+valid to the entire ILT.
5941 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5942 * VNIC3 (of that port). The range allocated will be the
5943 * entire ILT. This is needed to prevent ILT range error.
5944 * 2. Any PF driver load flow:
5945 * a. ILT update with the physical addresses of the allocated
5946 * logical pages.
5947 * b. Wait 20msec. - note that this timeout is needed to make
5948 * sure there are no requests in one of the PXP internal
5949 * queues with "old" ILT addresses.
5950 * c. PF enable in the PGLC.
5951 * d. Clear the was_error of the PF in the PGLC. (could have
5952 * occured while driver was down)
5953 * e. PF enable in the CFC (WEAK + STRONG)
5954 * f. Timers scan enable
5955 * 3. PF driver unload flow:
5956 * a. Clear the Timers scan_en.
5957 * b. Polling for scan_on=0 for that PF.
5958 * c. Clear the PF enable bit in the PXP.
5959 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5960 * e. Write zero+valid to all ILT entries (The valid bit must
5961 * stay set)
5962 * f. If this is VNIC 3 of a port then also init
5963 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5964 * to the last enrty in the ILT.
5965 *
5966 * Notes:
5967 * Currently the PF error in the PGLC is non recoverable.
5968 * In the future the there will be a recovery routine for this error.
5969 * Currently attention is masked.
5970 * Having an MCP lock on the load/unload process does not guarantee that
5971 * there is no Timer disable during Func6/7 enable. This is because the
5972 * Timers scan is currently being cleared by the MCP on FLR.
5973 * Step 2.d can be done only for PF6/7 and the driver can also check if
5974 * there is error before clearing it. But the flow above is simpler and
5975 * more general.
5976 * All ILT entries are written by zero+valid and not just PF6/7
5977 * ILT entries since in the future the ILT entries allocation for
5978 * PF-s might be dynamic.
5979 */
f2e0899f
DK		 5980 struct ilt_client_info ilt_cli;
5981 struct bnx2x_ilt ilt;
5982 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5983 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5984
b595076a 5985 /* initialize dummy TM client */
f2e0899f
DK		 5986 ilt_cli.start = 0;
5987 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5988 ilt_cli.client_num = ILT_CLIENT_TM;
5989
5990 /* Step 1: set zeroes to all ilt page entries with valid bit on
5991 * Step 2: set the timers first/last ilt entry to point
5992 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 5993 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 5994 *
5995 * both steps performed by call to bnx2x_ilt_client_init_op()
5996 * with dummy TM client
5997 *
5998 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5999 * and his brother are split registers
6000 */
6001 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6002 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6003 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6004
6005 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6006 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6007 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6008 }
6009
6010
34f80b04
EG		 6011 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6012 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6013
619c5cb6 6014 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6015 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6016 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6017 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6018
619c5cb6 6019 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6020
6021 /* let the HW do it's magic ... */
6022 do {
6023 msleep(200);
6024 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6025 } while (factor-- && (val != 1));
6026
6027 if (val != 1) {
6028 BNX2X_ERR("ATC_INIT failed\n");
6029 return -EBUSY;
6030 }
6031 }
6032
619c5cb6 6033 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6034
34f80b04
EG		 6035 /* clean the DMAE memory */
6036 bp->dmae_ready = 1;
619c5cb6
VZ		 6037 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6038
6039 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6040
6041 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6042
6043 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6044
619c5cb6 6045 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6046
34f80b04
EG		 6047 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6048 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6049 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6050 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6051
619c5cb6 6052 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6053
f85582f8 6054
523224a3
DK		 6055 /* QM queues pointers table */
6056 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6057
34f80b04
EG		 6058 /* soft reset pulse */
6059 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6060 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6061
37b091ba 6062#ifdef BCM_CNIC
619c5cb6 6063 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6064#endif
a2fbb9ea 6065
619c5cb6 6066 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6067 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6068 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6069 /* enable hw interrupt from doorbell Q */
6070 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6071
619c5cb6 6072 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6073
619c5cb6 6074 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6075 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6076
f2e0899f 6077 if (!CHIP_IS_E1(bp))
619c5cb6 6078 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6079
619c5cb6
VZ		 6080 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6081 /* Bit-map indicating which L2 hdrs may appear
6082 * after the basic Ethernet header
6083 */
6084 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6085 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 6086
619c5cb6
VZ		 6087 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6088 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6089 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6090 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6091
619c5cb6
VZ		 6092 if (!CHIP_IS_E1x(bp)) {
6093 /* reset VFC memories */
6094 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6095 VFC_MEMORIES_RST_REG_CAM_RST |
6096 VFC_MEMORIES_RST_REG_RAM_RST);
6097 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6098 VFC_MEMORIES_RST_REG_CAM_RST |
6099 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6100
619c5cb6
VZ		 6101 msleep(20);
6102 }
a2fbb9ea 6103
619c5cb6
VZ		 6104 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6105 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6106 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6107 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6108
34f80b04
EG		 6109 /* sync semi rtc */
6110 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6111 0x80000000);
6112 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6113 0x80000000);
a2fbb9ea 6114
619c5cb6
VZ		 6115 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6116 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6117 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6118
619c5cb6
VZ		 6119 if (!CHIP_IS_E1x(bp))
6120 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6121 bp->path_has_ovlan ? 7 : 6);
f2e0899f 6122
34f80b04 6123 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6124
619c5cb6
VZ		 6125 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6126
37b091ba
MC		 6127#ifdef BCM_CNIC
6128 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6129 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6130 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6131 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6132 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6133 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6134 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6135 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6136 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6137 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6138#endif
34f80b04 6139 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6140
34f80b04
EG		 6141 if (sizeof(union cdu_context) != 1024)
6142 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 6143 dev_alert(&bp->pdev->dev, "please adjust the size "
6144 "of cdu_context(%ld)\n",
7995c64e 6145 (long)sizeof(union cdu_context));
a2fbb9ea 6146
619c5cb6 6147 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6148 val = (4 << 24) + (0 << 12) + 1024;
6149 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6150
619c5cb6 6151 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6152 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6153 /* enable context validation interrupt from CFC */
6154 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6155
6156 /* set the thresholds to prevent CFC/CDU race */
6157 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6158
619c5cb6 6159 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6160
619c5cb6 6161 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6162 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6163
619c5cb6
VZ		 6164 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6165 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6166
34f80b04
EG		 6167 /* Reset PCIE errors for debug */
6168 REG_WR(bp, 0x2814, 0xffffffff);
6169 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6170
619c5cb6 6171 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6172 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6173 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6174 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6175 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6176 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6177 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6178 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6179 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6180 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6181 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6182 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6183 }
6184
619c5cb6 6185 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6186 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6187 /* in E3 this done in per-port section */
6188 if (!CHIP_IS_E3(bp))
6189 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6190 }
619c5cb6
VZ		 6191 if (CHIP_IS_E1H(bp))
6192 /* not applicable for E2 (and above ...) */
6193 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6194
6195 if (CHIP_REV_IS_SLOW(bp))
6196 msleep(200);
6197
6198 /* finish CFC init */
6199 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6200 if (val != 1) {
6201 BNX2X_ERR("CFC LL_INIT failed\n");
6202 return -EBUSY;
6203 }
6204 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6205 if (val != 1) {
6206 BNX2X_ERR("CFC AC_INIT failed\n");
6207 return -EBUSY;
6208 }
6209 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6210 if (val != 1) {
6211 BNX2X_ERR("CFC CAM_INIT failed\n");
6212 return -EBUSY;
6213 }
6214 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6215
f2e0899f
DK		 6216 if (CHIP_IS_E1(bp)) {
6217 /* read NIG statistic
6218 to see if this is our first up since powerup */
6219 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6220 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6221
f2e0899f
DK		 6222 /* do internal memory self test */
6223 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6224 BNX2X_ERR("internal mem self test failed\n");
6225 return -EBUSY;
6226 }
34f80b04
EG		 6227 }
6228
fd4ef40d
EG		 6229 bnx2x_setup_fan_failure_detection(bp);
6230
34f80b04
EG		 6231 /* clear PXP2 attentions */
6232 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6233
4a33bc03 6234 bnx2x_enable_blocks_attention(bp);
c9ee9206 6235 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6236
6bbca910 6237 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6238 if (CHIP_IS_E1x(bp))
6239 bnx2x__common_init_phy(bp);
6bbca910
YR		 6240 } else
6241 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6242
34f80b04
EG		 6243 return 0;
6244}
a2fbb9ea 6245
619c5cb6
VZ		 6246/**
6247 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6248 *
6249 * @bp: driver handle
6250 */
6251static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6252{
6253 int rc = bnx2x_init_hw_common(bp);
6254
6255 if (rc)
6256 return rc;
6257
6258 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6259 if (!BP_NOMCP(bp))
6260 bnx2x__common_init_phy(bp);
6261
6262 return 0;
6263}
6264
523224a3 6265static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6266{
6267 int port = BP_PORT(bp);
619c5cb6 6268 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6269 u32 low, high;
34f80b04 6270 u32 val;
a2fbb9ea 6271
619c5cb6
VZ		 6272 bnx2x__link_reset(bp);
6273
cdaa7cb8 6274 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 6275
6276 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6277
619c5cb6
VZ		 6278 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6279 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6280 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6281
f2e0899f
DK		 6282 /* Timers bug workaround: disables the pf_master bit in pglue at
6283 * common phase, we need to enable it here before any dmae access are
6284 * attempted. Therefore we manually added the enable-master to the
6285 * port phase (it also happens in the function phase)
6286 */
619c5cb6 6287 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6288 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6289
619c5cb6
VZ		 6290 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6291 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6292 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6293 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6294
6295 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6296 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6297 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6298 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6299
523224a3
DK		 6300 /* QM cid (connection) count */
6301 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6302
523224a3 6303#ifdef BCM_CNIC
619c5cb6 6304 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 6305 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6306 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 6307#endif
cdaa7cb8 6308
619c5cb6 6309 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 6310
6311 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6312 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6313
6314 if (IS_MF(bp))
6315 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6316 else if (bp->dev->mtu > 4096) {
6317 if (bp->flags & ONE_PORT_FLAG)
6318 low = 160;
6319 else {
6320 val = bp->dev->mtu;
6321 /* (24*1024 + val*4)/256 */
6322 low = 96 + (val/64) +
6323 ((val % 64) ? 1 : 0);
6324 }
6325 } else
6326 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6327 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6328 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6329 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6330 }
1c06328c 6331
619c5cb6
VZ		 6332 if (CHIP_MODE_IS_4_PORT(bp))
6333 REG_WR(bp, (BP_PORT(bp) ?
6334 BRB1_REG_MAC_GUARANTIED_1 :
6335 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6336
ca00392c 6337
619c5cb6
VZ		 6338 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6339 if (CHIP_IS_E3B0(bp))
6340 /* Ovlan exists only if we are in multi-function +
6341 * switch-dependent mode, in switch-independent there
6342 * is no ovlan headers
6343 */
6344 REG_WR(bp, BP_PORT(bp) ?
6345 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6346 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6347 (bp->path_has_ovlan ? 7 : 6));
356e2385 6348
619c5cb6
VZ		 6349 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6350 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6351 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6352 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 6353
619c5cb6
VZ		 6354 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6355 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6356 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6357 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 6358
619c5cb6
VZ		 6359 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6360 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 6361
619c5cb6
VZ		 6362 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6363
6364 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6365 /* configure PBF to work without PAUSE mtu 9000 */
6366 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 6367
f2e0899f
DK		 6368 /* update threshold */
6369 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6370 /* update init credit */
6371 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 6372
f2e0899f
DK		 6373 /* probe changes */
6374 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6375 udelay(50);
6376 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6377 }
a2fbb9ea 6378
37b091ba 6379#ifdef BCM_CNIC
619c5cb6 6380 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 6381#endif
619c5cb6
VZ		 6382 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6383 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 6384
6385 if (CHIP_IS_E1(bp)) {
6386 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6387 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6388 }
619c5cb6 6389 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 6390
619c5cb6 6391 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6392
619c5cb6 6393 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 6394 /* init aeu_mask_attn_func_0/1:
6395 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6396 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6397 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 6398 val = IS_MF(bp) ? 0xF7 : 0x7;
6399 /* Enable DCBX attention for all but E1 */
6400 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6401 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 6402
619c5cb6
VZ		 6403 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6404
6405 if (!CHIP_IS_E1x(bp)) {
6406 /* Bit-map indicating which L2 hdrs may appear after the
6407 * basic Ethernet header
6408 */
6409 REG_WR(bp, BP_PORT(bp) ?
6410 NIG_REG_P1_HDRS_AFTER_BASIC :
6411 NIG_REG_P0_HDRS_AFTER_BASIC,
6412 IS_MF_SD(bp) ? 7 : 6);
6413
6414 if (CHIP_IS_E3(bp))
6415 REG_WR(bp, BP_PORT(bp) ?
6416 NIG_REG_LLH1_MF_MODE :
6417 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6418 }
6419 if (!CHIP_IS_E3(bp))
6420 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 6421
f2e0899f 6422 if (!CHIP_IS_E1(bp)) {
fb3bff17 6423 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 6424 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 6425 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 6426
619c5cb6 6427 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6428 val = 0;
6429 switch (bp->mf_mode) {
6430 case MULTI_FUNCTION_SD:
6431 val = 1;
6432 break;
6433 case MULTI_FUNCTION_SI:
6434 val = 2;
6435 break;
6436 }
6437
6438 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6439 NIG_REG_LLH0_CLS_TYPE), val);
6440 }
1c06328c
EG		 6441 {
6442 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6443 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6444 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6445 }
34f80b04
EG		 6446 }
6447
619c5cb6
VZ		 6448
6449 /* If SPIO5 is set to generate interrupts, enable it for this port */
6450 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6451 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 6452 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6453 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6454 val = REG_RD(bp, reg_addr);
f1410647 6455 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 6456 REG_WR(bp, reg_addr, val);
f1410647 6457 }
a2fbb9ea 6458
34f80b04
EG		 6459 return 0;
6460}
6461
34f80b04
EG		 6462static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6463{
6464 int reg;
6465
f2e0899f 6466 if (CHIP_IS_E1(bp))
34f80b04 6467 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 6468 else
6469 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 6470
6471 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6472}
6473
f2e0899f
DK		 6474static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6475{
619c5cb6 6476 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 6477}
6478
6479static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6480{
6481 u32 i, base = FUNC_ILT_BASE(func);
6482 for (i = base; i < base + ILT_PER_FUNC; i++)
6483 bnx2x_ilt_wr(bp, i, 0);
6484}
6485
523224a3 6486static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 6487{
6488 int port = BP_PORT(bp);
6489 int func = BP_FUNC(bp);
619c5cb6 6490 int init_phase = PHASE_PF0 + func;
523224a3
DK		 6491 struct bnx2x_ilt *ilt = BP_ILT(bp);
6492 u16 cdu_ilt_start;
8badd27a 6493 u32 addr, val;
f4a66897
VZ		 6494 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6495 int i, main_mem_width;
34f80b04 6496
cdaa7cb8 6497 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 6498
619c5cb6
VZ		 6499 /* FLR cleanup - hmmm */
6500 if (!CHIP_IS_E1x(bp))
6501 bnx2x_pf_flr_clnup(bp);
6502
8badd27a 6503 /* set MSI reconfigure capability */
f2e0899f
DK		 6504 if (bp->common.int_block == INT_BLOCK_HC) {
6505 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6506 val = REG_RD(bp, addr);
6507 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6508 REG_WR(bp, addr, val);
6509 }
8badd27a 6510
619c5cb6
VZ		 6511 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6512 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6513
523224a3
DK		 6514 ilt = BP_ILT(bp);
6515 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6516
523224a3
DK		 6517 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6518 ilt->lines[cdu_ilt_start + i].page =
6519 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6520 ilt->lines[cdu_ilt_start + i].page_mapping =
6521 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6522 /* cdu ilt pages are allocated manually so there's no need to
6523 set the size */
37b091ba 6524 }
523224a3 6525 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6526
523224a3
DK		 6527#ifdef BCM_CNIC
6528 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6529
523224a3
DK		 6530 /* T1 hash bits value determines the T1 number of entries */
6531 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6532#endif
37b091ba 6533
523224a3
DK		 6534#ifndef BCM_CNIC
6535 /* set NIC mode */
6536 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6537#endif /* BCM_CNIC */
37b091ba 6538
619c5cb6 6539 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6540 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6541
6542 /* Turn on a single ISR mode in IGU if driver is going to use
6543 * INT#x or MSI
6544 */
6545 if (!(bp->flags & USING_MSIX_FLAG))
6546 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6547 /*
6548 * Timers workaround bug: function init part.
6549 * Need to wait 20msec after initializing ILT,
6550 * needed to make sure there are no requests in
6551 * one of the PXP internal queues with "old" ILT addresses
6552 */
6553 msleep(20);
6554 /*
6555 * Master enable - Due to WB DMAE writes performed before this
6556 * register is re-initialized as part of the regular function
6557 * init
6558 */
6559 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6560 /* Enable the function in IGU */
6561 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6562 }
6563
523224a3 6564 bp->dmae_ready = 1;
34f80b04 6565
619c5cb6 6566 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6567
619c5cb6 6568 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6569 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6570
619c5cb6
VZ		 6571 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6572 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6573 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6574 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6575 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6576 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6577 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6578 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6579 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6580 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6581 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6582 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6583 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6584
6585 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6586 REG_WR(bp, QM_REG_PF_EN, 1);
6587
619c5cb6
VZ		 6588 if (!CHIP_IS_E1x(bp)) {
6589 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6590 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6591 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6592 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6593 }
6594 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6595
6596 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6597 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6598 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6599 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6600 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6601 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6602 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6603 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6604 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6605 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6606 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6607 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6608 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6609
619c5cb6 6610 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6611
619c5cb6 6612 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6613
619c5cb6 6614 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6615 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6616
fb3bff17 6617 if (IS_MF(bp)) {
34f80b04 6618 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6619 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6620 }
6621
619c5cb6 6622 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6623
34f80b04 6624 /* HC init per function */
f2e0899f
DK		 6625 if (bp->common.int_block == INT_BLOCK_HC) {
6626 if (CHIP_IS_E1H(bp)) {
6627 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6628
6629 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6630 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6631 }
619c5cb6 6632 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6633
6634 } else {
6635 int num_segs, sb_idx, prod_offset;
6636
34f80b04
EG		 6637 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6638
619c5cb6 6639 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6640 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6641 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6642 }
6643
619c5cb6 6644 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6645
619c5cb6 6646 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6647 int dsb_idx = 0;
6648 /**
6649 * Producer memory:
6650 * E2 mode: address 0-135 match to the mapping memory;
6651 * 136 - PF0 default prod; 137 - PF1 default prod;
6652 * 138 - PF2 default prod; 139 - PF3 default prod;
6653 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6654 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6655 * 144-147 reserved.
6656 *
6657 * E1.5 mode - In backward compatible mode;
6658 * for non default SB; each even line in the memory
6659 * holds the U producer and each odd line hold
6660 * the C producer. The first 128 producers are for
6661 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6662 * producers are for the DSB for each PF.
6663 * Each PF has five segments: (the order inside each
6664 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6665 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6666 * 144-147 attn prods;
6667 */
6668 /* non-default-status-blocks */
6669 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6670 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6671 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6672 prod_offset = (bp->igu_base_sb + sb_idx) *
6673 num_segs;
6674
6675 for (i = 0; i < num_segs; i++) {
6676 addr = IGU_REG_PROD_CONS_MEMORY +
6677 (prod_offset + i) * 4;
6678 REG_WR(bp, addr, 0);
6679 }
6680 /* send consumer update with value 0 */
6681 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6682 USTORM_ID, 0, IGU_INT_NOP, 1);
6683 bnx2x_igu_clear_sb(bp,
6684 bp->igu_base_sb + sb_idx);
6685 }
6686
6687 /* default-status-blocks */
6688 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6689 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6690
6691 if (CHIP_MODE_IS_4_PORT(bp))
6692 dsb_idx = BP_FUNC(bp);
6693 else
3395a033 6694 dsb_idx = BP_VN(bp);
f2e0899f
DK		 6695
6696 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6697 IGU_BC_BASE_DSB_PROD + dsb_idx :
6698 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6699
3395a033
DK		 6700 /*
6701 * igu prods come in chunks of E1HVN_MAX (4) -
6702 * does not matters what is the current chip mode
6703 */
f2e0899f
DK		 6704 for (i = 0; i < (num_segs * E1HVN_MAX);
6705 i += E1HVN_MAX) {
6706 addr = IGU_REG_PROD_CONS_MEMORY +
6707 (prod_offset + i)*4;
6708 REG_WR(bp, addr, 0);
6709 }
6710 /* send consumer update with 0 */
6711 if (CHIP_INT_MODE_IS_BC(bp)) {
6712 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6713 USTORM_ID, 0, IGU_INT_NOP, 1);
6714 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6715 CSTORM_ID, 0, IGU_INT_NOP, 1);
6716 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6717 XSTORM_ID, 0, IGU_INT_NOP, 1);
6718 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6719 TSTORM_ID, 0, IGU_INT_NOP, 1);
6720 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6721 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6722 } else {
6723 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6724 USTORM_ID, 0, IGU_INT_NOP, 1);
6725 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6726 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6727 }
6728 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6729
6730 /* !!! these should become driver const once
6731 rf-tool supports split-68 const */
6732 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6733 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6734 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6735 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6736 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6737 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6738 }
34f80b04 6739 }
34f80b04 6740
c14423fe 6741 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6742 REG_WR(bp, 0x2114, 0xffffffff);
6743 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6744
f4a66897
VZ		 6745 if (CHIP_IS_E1x(bp)) {
6746 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6747 main_mem_base = HC_REG_MAIN_MEMORY +
6748 BP_PORT(bp) * (main_mem_size * 4);
6749 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6750 main_mem_width = 8;
6751
6752 val = REG_RD(bp, main_mem_prty_clr);
6753 if (val)
6754 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6755 "block during "
6756 "function init (0x%x)!\n", val);
6757
6758 /* Clear "false" parity errors in MSI-X table */
6759 for (i = main_mem_base;
6760 i < main_mem_base + main_mem_size * 4;
6761 i += main_mem_width) {
6762 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6763 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6764 i, main_mem_width / 4);
6765 }
6766 /* Clear HC parity attention */
6767 REG_RD(bp, main_mem_prty_clr);
6768 }
6769
619c5cb6
VZ		 6770#ifdef BNX2X_STOP_ON_ERROR
6771 /* Enable STORMs SP logging */
6772 REG_WR8(bp, BAR_USTRORM_INTMEM +
6773 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6774 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6775 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6776 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6777 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6778 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6779 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6780#endif
6781
b7737c9b 6782 bnx2x_phy_probe(&bp->link_params);
f85582f8 6783
34f80b04
EG		 6784 return 0;
6785}
6786
a2fbb9ea 6787
9f6c9258 6788void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 6789{
a2fbb9ea 6790 /* fastpath */
b3b83c3f 6791 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 6792 /* end of fastpath */
6793
6794 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 6795 sizeof(struct host_sp_status_block));
a2fbb9ea 6796
619c5cb6
VZ		 6797 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6798 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6799
a2fbb9ea 6800 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 6801 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6802
523224a3
DK		 6803 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6804 bp->context.size);
6805
6806 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6807
6808 BNX2X_FREE(bp->ilt->lines);
f85582f8 6809
37b091ba 6810#ifdef BCM_CNIC
619c5cb6 6811 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6812 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6813 sizeof(struct host_hc_status_block_e2));
6814 else
6815 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6816 sizeof(struct host_hc_status_block_e1x));
f85582f8 6817
523224a3 6818 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 6819#endif
f85582f8 6820
7a9b2557 6821 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 6822
523224a3
DK		 6823 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6824 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 6825}
6826
6827static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6828{
6829 int num_groups;
6830
6831 /* number of eth_queues */
6832 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6833
6834 /* Total number of FW statistics requests =
6835 * 1 for port stats + 1 for PF stats + num_eth_queues */
6836 bp->fw_stats_num = 2 + num_queue_stats;
523224a3 6837
619c5cb6
VZ		 6838
6839 /* Request is built from stats_query_header and an array of
6840 * stats_query_cmd_group each of which contains
6841 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6842 * configured in the stats_query_header.
6843 */
6844 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6845 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6846
6847 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6848 num_groups * sizeof(struct stats_query_cmd_group);
6849
6850 /* Data for statistics requests + stats_conter
6851 *
6852 * stats_counter holds per-STORM counters that are incremented
6853 * when STORM has finished with the current request.
6854 */
6855 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6856 sizeof(struct per_pf_stats) +
6857 sizeof(struct per_queue_stats) * num_queue_stats +
6858 sizeof(struct stats_counter);
6859
6860 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6861 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6862
6863 /* Set shortcuts */
6864 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6865 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6866
6867 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6868 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6869
6870 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6871 bp->fw_stats_req_sz;
6872 return 0;
6873
6874alloc_mem_err:
6875 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6876 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6877 return -ENOMEM;
a2fbb9ea
ET		 6878}
6879
f2e0899f 6880
9f6c9258 6881int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6882{
523224a3 6883#ifdef BCM_CNIC
619c5cb6
VZ		 6884 if (!CHIP_IS_E1x(bp))
6885 /* size = the status block + ramrod buffers */
f2e0899f
DK		 6886 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6887 sizeof(struct host_hc_status_block_e2));
6888 else
6889 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6890 sizeof(struct host_hc_status_block_e1x));
8badd27a 6891
523224a3
DK		 6892 /* allocate searcher T2 table */
6893 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6894#endif
a2fbb9ea 6895
8badd27a 6896
523224a3
DK		 6897 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6898 sizeof(struct host_sp_status_block));
a2fbb9ea 6899
523224a3
DK		 6900 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6901 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6902
619c5cb6
VZ		 6903 /* Allocated memory for FW statistics */
6904 if (bnx2x_alloc_fw_stats_mem(bp))
6905 goto alloc_mem_err;
6906
6383c0b3 6907 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
f85582f8 6908
523224a3
DK		 6909 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6910 bp->context.size);
65abd74d 6911
523224a3 6912 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6913
523224a3
DK		 6914 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6915 goto alloc_mem_err;
65abd74d 6916
9f6c9258
DK		 6917 /* Slow path ring */
6918 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6919
523224a3
DK		 6920 /* EQ */
6921 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6922 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 6923
b3b83c3f
DK		 6924
6925 /* fastpath */
6926 /* need to be done at the end, since it's self adjusting to amount
6927 * of memory available for RSS queues
6928 */
6929 if (bnx2x_alloc_fp_mem(bp))
6930 goto alloc_mem_err;
9f6c9258 6931 return 0;
e1510706 6932
9f6c9258
DK		 6933alloc_mem_err:
6934 bnx2x_free_mem(bp);
6935 return -ENOMEM;
65abd74d
YG		 6936}
6937
a2fbb9ea
ET		 6938/*
6939 * Init service functions
6940 */
a2fbb9ea 6941
619c5cb6
VZ		 6942int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6943 struct bnx2x_vlan_mac_obj *obj, bool set,
6944 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 6945{
619c5cb6
VZ		 6946 int rc;
6947 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 6948
619c5cb6 6949 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 6950
619c5cb6
VZ		 6951 /* Fill general parameters */
6952 ramrod_param.vlan_mac_obj = obj;
6953 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 6954
619c5cb6
VZ		 6955 /* Fill a user request section if needed */
6956 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6957 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 6958
619c5cb6 6959 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 6960
619c5cb6
VZ		 6961 /* Set the command: ADD or DEL */
6962 if (set)
6963 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6964 else
6965 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 6966 }
6967
619c5cb6
VZ		 6968 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6969 if (rc < 0)
6970 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6971 return rc;
a2fbb9ea
ET		 6972}
6973
619c5cb6
VZ		 6974int bnx2x_del_all_macs(struct bnx2x *bp,
6975 struct bnx2x_vlan_mac_obj *mac_obj,
6976 int mac_type, bool wait_for_comp)
e665bfda 6977{
619c5cb6
VZ		 6978 int rc;
6979 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 6980
619c5cb6
VZ		 6981 /* Wait for completion of requested */
6982 if (wait_for_comp)
6983 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 6984
619c5cb6
VZ		 6985 /* Set the mac type of addresses we want to clear */
6986 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 6987
619c5cb6
VZ		 6988 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6989 if (rc < 0)
6990 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 6991
619c5cb6 6992 return rc;
0793f83f
DK		 6993}
6994
619c5cb6 6995int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 6996{
619c5cb6 6997 unsigned long ramrod_flags = 0;
e665bfda 6998
619c5cb6 6999 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 7000
619c5cb6
VZ		 7001 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7002 /* Eth MAC is set on RSS leading client (fp[0]) */
7003 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7004 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 7005}
6e30dd4e 7006
619c5cb6 7007int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 7008{
619c5cb6 7009 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 7010}
a2fbb9ea 7011
d6214d7a 7012/**
e8920674 7013 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 7014 *
e8920674 7015 * @bp: driver handle
d6214d7a 7016 *
e8920674 7017 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 7018 */
9ee3d37b 7019static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 7020{
9ee3d37b 7021 switch (int_mode) {
d6214d7a
DK		 7022 case INT_MODE_MSI:
7023 bnx2x_enable_msi(bp);
7024 /* falling through... */
7025 case INT_MODE_INTx:
6383c0b3 7026 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7027 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 7028 break;
d6214d7a
DK		 7029 default:
7030 /* Set number of queues according to bp->multi_mode value */
7031 bnx2x_set_num_queues(bp);
ca00392c 7032
d6214d7a
DK		 7033 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7034 bp->num_queues);
ca00392c 7035
d6214d7a
DK		 7036 /* if we can't use MSI-X we only need one fp,
7037 * so try to enable MSI-X with the requested number of fp's
7038 * and fallback to MSI or legacy INTx with one fp
7039 */
9ee3d37b 7040 if (bnx2x_enable_msix(bp)) {
d6214d7a
DK		 7041 /* failed to enable MSI-X */
7042 if (bp->multi_mode)
7043 DP(NETIF_MSG_IFUP,
7044 "Multi requested but failed to "
7045 "enable MSI-X (%d), "
7046 "set number of queues to %d\n",
7047 bp->num_queues,
6383c0b3
AE		 7048 1 + NON_ETH_CONTEXT_USE);
7049 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7050
9ee3d37b 7051 /* Try to enable MSI */
d6214d7a
DK		 7052 if (!(bp->flags & DISABLE_MSI_FLAG))
7053 bnx2x_enable_msi(bp);
7054 }
9f6c9258
DK		 7055 break;
7056 }
a2fbb9ea
ET		 7057}
7058
c2bff63f
DK		 7059/* must be called prioir to any HW initializations */
7060static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7061{
7062 return L2_ILT_LINES(bp);
7063}
7064
523224a3
DK		 7065void bnx2x_ilt_set_info(struct bnx2x *bp)
7066{
7067 struct ilt_client_info *ilt_client;
7068 struct bnx2x_ilt *ilt = BP_ILT(bp);
7069 u16 line = 0;
7070
7071 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7072 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7073
7074 /* CDU */
7075 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7076 ilt_client->client_num = ILT_CLIENT_CDU;
7077 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7078 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7079 ilt_client->start = line;
619c5cb6 7080 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 7081#ifdef BCM_CNIC
7082 line += CNIC_ILT_LINES;
7083#endif
7084 ilt_client->end = line - 1;
7085
7086 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7087 "flags 0x%x, hw psz %d\n",
7088 ilt_client->start,
7089 ilt_client->end,
7090 ilt_client->page_size,
7091 ilt_client->flags,
7092 ilog2(ilt_client->page_size >> 12));
7093
7094 /* QM */
7095 if (QM_INIT(bp->qm_cid_count)) {
7096 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7097 ilt_client->client_num = ILT_CLIENT_QM;
7098 ilt_client->page_size = QM_ILT_PAGE_SZ;
7099 ilt_client->flags = 0;
7100 ilt_client->start = line;
7101
7102 /* 4 bytes for each cid */
7103 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7104 QM_ILT_PAGE_SZ);
7105
7106 ilt_client->end = line - 1;
7107
7108 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7109 "flags 0x%x, hw psz %d\n",
7110 ilt_client->start,
7111 ilt_client->end,
7112 ilt_client->page_size,
7113 ilt_client->flags,
7114 ilog2(ilt_client->page_size >> 12));
7115
7116 }
7117 /* SRC */
7118 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7119#ifdef BCM_CNIC
7120 ilt_client->client_num = ILT_CLIENT_SRC;
7121 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7122 ilt_client->flags = 0;
7123 ilt_client->start = line;
7124 line += SRC_ILT_LINES;
7125 ilt_client->end = line - 1;
7126
7127 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7128 "flags 0x%x, hw psz %d\n",
7129 ilt_client->start,
7130 ilt_client->end,
7131 ilt_client->page_size,
7132 ilt_client->flags,
7133 ilog2(ilt_client->page_size >> 12));
7134
7135#else
7136 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7137#endif
9f6c9258 7138
523224a3
DK		 7139 /* TM */
7140 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7141#ifdef BCM_CNIC
7142 ilt_client->client_num = ILT_CLIENT_TM;
7143 ilt_client->page_size = TM_ILT_PAGE_SZ;
7144 ilt_client->flags = 0;
7145 ilt_client->start = line;
7146 line += TM_ILT_LINES;
7147 ilt_client->end = line - 1;
7148
7149 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7150 "flags 0x%x, hw psz %d\n",
7151 ilt_client->start,
7152 ilt_client->end,
7153 ilt_client->page_size,
7154 ilt_client->flags,
7155 ilog2(ilt_client->page_size >> 12));
9f6c9258 7156
523224a3
DK		 7157#else
7158 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7159#endif
619c5cb6 7160 BUG_ON(line > ILT_MAX_LINES);
523224a3 7161}
f85582f8 7162
619c5cb6
VZ		 7163/**
7164 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7165 *
7166 * @bp: driver handle
7167 * @fp: pointer to fastpath
7168 * @init_params: pointer to parameters structure
7169 *
7170 * parameters configured:
7171 * - HC configuration
7172 * - Queue's CDU context
7173 */
7174static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7175 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 7176{
6383c0b3
AE		 7177
7178 u8 cos;
619c5cb6
VZ		 7179 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7180 if (!IS_FCOE_FP(fp)) {
7181 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7182 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7183
7184 /* If HC is supporterd, enable host coalescing in the transition
7185 * to INIT state.
7186 */
7187 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7188 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7189
7190 /* HC rate */
7191 init_params->rx.hc_rate = bp->rx_ticks ?
7192 (1000000 / bp->rx_ticks) : 0;
7193 init_params->tx.hc_rate = bp->tx_ticks ?
7194 (1000000 / bp->tx_ticks) : 0;
7195
7196 /* FW SB ID */
7197 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7198 fp->fw_sb_id;
7199
7200 /*
7201 * CQ index among the SB indices: FCoE clients uses the default
7202 * SB, therefore it's different.
7203 */
6383c0b3
AE		 7204 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7205 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 7206 }
7207
6383c0b3
AE		 7208 /* set maximum number of COSs supported by this queue */
7209 init_params->max_cos = fp->max_cos;
7210
7211 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7212 fp->index, init_params->max_cos);
7213
7214 /* set the context pointers queue object */
7215 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7216 init_params->cxts[cos] =
7217 &bp->context.vcxt[fp->txdata[cos].cid].eth;
619c5cb6
VZ		 7218}
7219
6383c0b3
AE		 7220int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7221 struct bnx2x_queue_state_params *q_params,
7222 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7223 int tx_index, bool leading)
7224{
7225 memset(tx_only_params, 0, sizeof(*tx_only_params));
7226
7227 /* Set the command */
7228 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7229
7230 /* Set tx-only QUEUE flags: don't zero statistics */
7231 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7232
7233 /* choose the index of the cid to send the slow path on */
7234 tx_only_params->cid_index = tx_index;
7235
7236 /* Set general TX_ONLY_SETUP parameters */
7237 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7238
7239 /* Set Tx TX_ONLY_SETUP parameters */
7240 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7241
7242 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7243 "cos %d, primary cid %d, cid %d, "
7244 "client id %d, sp-client id %d, flags %lx",
7245 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7246 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7247 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7248
7249 /* send the ramrod */
7250 return bnx2x_queue_state_change(bp, q_params);
7251}
7252
7253
619c5cb6
VZ		 7254/**
7255 * bnx2x_setup_queue - setup queue
7256 *
7257 * @bp: driver handle
7258 * @fp: pointer to fastpath
7259 * @leading: is leading
7260 *
7261 * This function performs 2 steps in a Queue state machine
7262 * actually: 1) RESET->INIT 2) INIT->SETUP
7263 */
7264
7265int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7266 bool leading)
7267{
7268 struct bnx2x_queue_state_params q_params = {0};
7269 struct bnx2x_queue_setup_params *setup_params =
7270 &q_params.params.setup;
6383c0b3
AE		 7271 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7272 &q_params.params.tx_only;
a2fbb9ea 7273 int rc;
6383c0b3
AE		 7274 u8 tx_index;
7275
7276 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
a2fbb9ea 7277
ec6ba945
VZ		 7278 /* reset IGU state skip FCoE L2 queue */
7279 if (!IS_FCOE_FP(fp))
7280 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 7281 IGU_INT_ENABLE, 0);
a2fbb9ea 7282
619c5cb6
VZ		 7283 q_params.q_obj = &fp->q_obj;
7284 /* We want to wait for completion in this context */
7285 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7286
619c5cb6
VZ		 7287 /* Prepare the INIT parameters */
7288 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 7289
619c5cb6
VZ		 7290 /* Set the command */
7291 q_params.cmd = BNX2X_Q_CMD_INIT;
7292
7293 /* Change the state to INIT */
7294 rc = bnx2x_queue_state_change(bp, &q_params);
7295 if (rc) {
6383c0b3 7296 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 7297 return rc;
7298 }
ec6ba945 7299
6383c0b3
AE		 7300 DP(BNX2X_MSG_SP, "init complete");
7301
7302
619c5cb6
VZ		 7303 /* Now move the Queue to the SETUP state... */
7304 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 7305
619c5cb6
VZ		 7306 /* Set QUEUE flags */
7307 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 7308
619c5cb6 7309 /* Set general SETUP parameters */
6383c0b3
AE		 7310 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7311 FIRST_TX_COS_INDEX);
619c5cb6 7312
6383c0b3 7313 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 7314 &setup_params->rxq_params);
7315
6383c0b3
AE		 7316 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7317 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 7318
7319 /* Set the command */
7320 q_params.cmd = BNX2X_Q_CMD_SETUP;
7321
7322 /* Change the state to SETUP */
7323 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 7324 if (rc) {
7325 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7326 return rc;
7327 }
7328
7329 /* loop through the relevant tx-only indices */
7330 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7331 tx_index < fp->max_cos;
7332 tx_index++) {
7333
7334 /* prepare and send tx-only ramrod*/
7335 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7336 tx_only_params, tx_index, leading);
7337 if (rc) {
7338 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7339 fp->index, tx_index);
7340 return rc;
7341 }
7342 }
523224a3 7343
34f80b04 7344 return rc;
a2fbb9ea
ET		 7345}
7346
619c5cb6 7347static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 7348{
619c5cb6 7349 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 7350 struct bnx2x_fp_txdata *txdata;
619c5cb6 7351 struct bnx2x_queue_state_params q_params = {0};
6383c0b3
AE		 7352 int rc, tx_index;
7353
7354 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
a2fbb9ea 7355
619c5cb6
VZ		 7356 q_params.q_obj = &fp->q_obj;
7357 /* We want to wait for completion in this context */
7358 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7359
6383c0b3
AE		 7360
7361 /* close tx-only connections */
7362 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7363 tx_index < fp->max_cos;
7364 tx_index++){
7365
7366 /* ascertain this is a normal queue*/
7367 txdata = &fp->txdata[tx_index];
7368
7369 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7370 txdata->txq_index);
7371
7372 /* send halt terminate on tx-only connection */
7373 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7374 memset(&q_params.params.terminate, 0,
7375 sizeof(q_params.params.terminate));
7376 q_params.params.terminate.cid_index = tx_index;
7377
7378 rc = bnx2x_queue_state_change(bp, &q_params);
7379 if (rc)
7380 return rc;
7381
7382 /* send halt terminate on tx-only connection */
7383 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7384 memset(&q_params.params.cfc_del, 0,
7385 sizeof(q_params.params.cfc_del));
7386 q_params.params.cfc_del.cid_index = tx_index;
7387 rc = bnx2x_queue_state_change(bp, &q_params);
7388 if (rc)
7389 return rc;
7390 }
7391 /* Stop the primary connection: */
7392 /* ...halt the connection */
619c5cb6
VZ		 7393 q_params.cmd = BNX2X_Q_CMD_HALT;
7394 rc = bnx2x_queue_state_change(bp, &q_params);
7395 if (rc)
da5a662a 7396 return rc;
a2fbb9ea 7397
6383c0b3 7398 /* ...terminate the connection */
619c5cb6 7399 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 7400 memset(&q_params.params.terminate, 0,
7401 sizeof(q_params.params.terminate));
7402 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 7403 rc = bnx2x_queue_state_change(bp, &q_params);
7404 if (rc)
523224a3 7405 return rc;
6383c0b3 7406 /* ...delete cfc entry */
619c5cb6 7407 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 7408 memset(&q_params.params.cfc_del, 0,
7409 sizeof(q_params.params.cfc_del));
7410 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 7411 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 7412}
7413
7414
34f80b04
EG		 7415static void bnx2x_reset_func(struct bnx2x *bp)
7416{
7417 int port = BP_PORT(bp);
7418 int func = BP_FUNC(bp);
f2e0899f 7419 int i;
523224a3
DK		 7420
7421 /* Disable the function in the FW */
7422 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7423 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7424 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7425 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7426
7427 /* FP SBs */
ec6ba945 7428 for_each_eth_queue(bp, i) {
523224a3 7429 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 7430 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7431 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7432 SB_DISABLED);
523224a3
DK		 7433 }
7434
619c5cb6
VZ		 7435#ifdef BCM_CNIC
7436 /* CNIC SB */
7437 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7438 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7439 SB_DISABLED);
7440#endif
523224a3 7441 /* SP SB */
619c5cb6 7442 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7443 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7444 SB_DISABLED);
523224a3
DK		 7445
7446 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7447 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7448 0);
34f80b04
EG		 7449
7450 /* Configure IGU */
f2e0899f
DK		 7451 if (bp->common.int_block == INT_BLOCK_HC) {
7452 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7453 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7454 } else {
7455 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7456 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7457 }
34f80b04 7458
37b091ba
MC		 7459#ifdef BCM_CNIC
7460 /* Disable Timer scan */
7461 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7462 /*
7463 * Wait for at least 10ms and up to 2 second for the timers scan to
7464 * complete
7465 */
7466 for (i = 0; i < 200; i++) {
7467 msleep(10);
7468 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7469 break;
7470 }
7471#endif
34f80b04 7472 /* Clear ILT */
f2e0899f
DK		 7473 bnx2x_clear_func_ilt(bp, func);
7474
7475 /* Timers workaround bug for E2: if this is vnic-3,
7476 * we need to set the entire ilt range for this timers.
7477 */
619c5cb6 7478 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 7479 struct ilt_client_info ilt_cli;
7480 /* use dummy TM client */
7481 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7482 ilt_cli.start = 0;
7483 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7484 ilt_cli.client_num = ILT_CLIENT_TM;
7485
7486 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7487 }
7488
7489 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 7490 if (!CHIP_IS_E1x(bp))
f2e0899f 7491 bnx2x_pf_disable(bp);
523224a3
DK		 7492
7493 bp->dmae_ready = 0;
34f80b04
EG		 7494}
7495
7496static void bnx2x_reset_port(struct bnx2x *bp)
7497{
7498 int port = BP_PORT(bp);
7499 u32 val;
7500
619c5cb6
VZ		 7501 /* Reset physical Link */
7502 bnx2x__link_reset(bp);
7503
34f80b04
EG		 7504 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7505
7506 /* Do not rcv packets to BRB */
7507 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7508 /* Do not direct rcv packets that are not for MCP to the BRB */
7509 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7510 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7511
7512 /* Configure AEU */
7513 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7514
7515 msleep(100);
7516 /* Check for BRB port occupancy */
7517 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7518 if (val)
7519 DP(NETIF_MSG_IFDOWN,
33471629 7520 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7521
7522 /* TODO: Close Doorbell port? */
7523}
7524
619c5cb6 7525static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 7526{
619c5cb6 7527 struct bnx2x_func_state_params func_params = {0};
34f80b04 7528
619c5cb6
VZ		 7529 /* Prepare parameters for function state transitions */
7530 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 7531
619c5cb6
VZ		 7532 func_params.f_obj = &bp->func_obj;
7533 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 7534
619c5cb6 7535 func_params.params.hw_init.load_phase = load_code;
49d66772 7536
619c5cb6 7537 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 7538}
7539
619c5cb6 7540static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 7541{
619c5cb6
VZ		 7542 struct bnx2x_func_state_params func_params = {0};
7543 int rc;
228241eb 7544
619c5cb6
VZ		 7545 /* Prepare parameters for function state transitions */
7546 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7547 func_params.f_obj = &bp->func_obj;
7548 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 7549
619c5cb6
VZ		 7550 /*
7551 * Try to stop the function the 'good way'. If fails (in case
7552 * of a parity error during bnx2x_chip_cleanup()) and we are
7553 * not in a debug mode, perform a state transaction in order to
7554 * enable further HW_RESET transaction.
7555 */
7556 rc = bnx2x_func_state_change(bp, &func_params);
7557 if (rc) {
34f80b04 7558#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 7559 return rc;
34f80b04 7560#else
619c5cb6
VZ		 7561 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7562 "transaction\n");
7563 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7564 return bnx2x_func_state_change(bp, &func_params);
34f80b04 7565#endif
228241eb 7566 }
a2fbb9ea 7567
619c5cb6
VZ		 7568 return 0;
7569}
523224a3 7570
619c5cb6
VZ		 7571/**
7572 * bnx2x_send_unload_req - request unload mode from the MCP.
7573 *
7574 * @bp: driver handle
7575 * @unload_mode: requested function's unload mode
7576 *
7577 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7578 */
7579u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7580{
7581 u32 reset_code = 0;
7582 int port = BP_PORT(bp);
3101c2bc 7583
619c5cb6 7584 /* Select the UNLOAD request mode */
65abd74d
YG		 7585 if (unload_mode == UNLOAD_NORMAL)
7586 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7587
7d0446c2 7588 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7589 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7590
7d0446c2 7591 else if (bp->wol) {
65abd74d
YG		 7592 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7593 u8 *mac_addr = bp->dev->dev_addr;
7594 u32 val;
7595 /* The mac address is written to entries 1-4 to
7596 preserve entry 0 which is used by the PMF */
3395a033 7597 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 7598
7599 val = (mac_addr[0] << 8) | mac_addr[1];
7600 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7601
7602 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7603 (mac_addr[4] << 8) | mac_addr[5];
7604 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7605
7606 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7607
7608 } else
7609 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7610
619c5cb6
VZ		 7611 /* Send the request to the MCP */
7612 if (!BP_NOMCP(bp))
7613 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7614 else {
7615 int path = BP_PATH(bp);
7616
7617 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7618 "%d, %d, %d\n",
7619 path, load_count[path][0], load_count[path][1],
7620 load_count[path][2]);
7621 load_count[path][0]--;
7622 load_count[path][1 + port]--;
7623 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7624 "%d, %d, %d\n",
7625 path, load_count[path][0], load_count[path][1],
7626 load_count[path][2]);
7627 if (load_count[path][0] == 0)
7628 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7629 else if (load_count[path][1 + port] == 0)
7630 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7631 else
7632 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7633 }
7634
7635 return reset_code;
7636}
7637
7638/**
7639 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7640 *
7641 * @bp: driver handle
7642 */
7643void bnx2x_send_unload_done(struct bnx2x *bp)
7644{
7645 /* Report UNLOAD_DONE to MCP */
7646 if (!BP_NOMCP(bp))
7647 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7648}
7649
6debea87
DK		 7650static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7651{
7652 int tout = 50;
7653 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7654
7655 if (!bp->port.pmf)
7656 return 0;
7657
7658 /*
7659 * (assumption: No Attention from MCP at this stage)
7660 * PMF probably in the middle of TXdisable/enable transaction
7661 * 1. Sync IRS for default SB
7662 * 2. Sync SP queue - this guarantes us that attention handling started
7663 * 3. Wait, that TXdisable/enable transaction completes
7664 *
7665 * 1+2 guranty that if DCBx attention was scheduled it already changed
7666 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7667 * received complettion for the transaction the state is TX_STOPPED.
7668 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7669 * transaction.
7670 */
7671
7672 /* make sure default SB ISR is done */
7673 if (msix)
7674 synchronize_irq(bp->msix_table[0].vector);
7675 else
7676 synchronize_irq(bp->pdev->irq);
7677
7678 flush_workqueue(bnx2x_wq);
7679
7680 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7681 BNX2X_F_STATE_STARTED && tout--)
7682 msleep(20);
7683
7684 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7685 BNX2X_F_STATE_STARTED) {
7686#ifdef BNX2X_STOP_ON_ERROR
7687 return -EBUSY;
7688#else
7689 /*
7690 * Failed to complete the transaction in a "good way"
7691 * Force both transactions with CLR bit
7692 */
7693 struct bnx2x_func_state_params func_params = {0};
7694
7695 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7696 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7697
7698 func_params.f_obj = &bp->func_obj;
7699 __set_bit(RAMROD_DRV_CLR_ONLY,
7700 &func_params.ramrod_flags);
7701
7702 /* STARTED-->TX_ST0PPED */
7703 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7704 bnx2x_func_state_change(bp, &func_params);
7705
7706 /* TX_ST0PPED-->STARTED */
7707 func_params.cmd = BNX2X_F_CMD_TX_START;
7708 return bnx2x_func_state_change(bp, &func_params);
7709#endif
7710 }
7711
7712 return 0;
7713}
7714
619c5cb6
VZ		 7715void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7716{
7717 int port = BP_PORT(bp);
6383c0b3
AE		 7718 int i, rc = 0;
7719 u8 cos;
619c5cb6
VZ		 7720 struct bnx2x_mcast_ramrod_params rparam = {0};
7721 u32 reset_code;
7722
7723 /* Wait until tx fastpath tasks complete */
7724 for_each_tx_queue(bp, i) {
7725 struct bnx2x_fastpath *fp = &bp->fp[i];
7726
6383c0b3
AE		 7727 for_each_cos_in_tx_queue(fp, cos)
7728 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
619c5cb6
VZ		 7729#ifdef BNX2X_STOP_ON_ERROR
7730 if (rc)
7731 return;
7732#endif
7733 }
7734
7735 /* Give HW time to discard old tx messages */
7736 usleep_range(1000, 1000);
7737
7738 /* Clean all ETH MACs */
7739 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7740 if (rc < 0)
7741 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7742
7743 /* Clean up UC list */
7744 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7745 true);
7746 if (rc < 0)
7747 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7748 "%d\n", rc);
7749
7750 /* Disable LLH */
7751 if (!CHIP_IS_E1(bp))
7752 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7753
7754 /* Set "drop all" (stop Rx).
7755 * We need to take a netif_addr_lock() here in order to prevent
7756 * a race between the completion code and this code.
7757 */
7758 netif_addr_lock_bh(bp->dev);
7759 /* Schedule the rx_mode command */
7760 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7761 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7762 else
7763 bnx2x_set_storm_rx_mode(bp);
7764
7765 /* Cleanup multicast configuration */
7766 rparam.mcast_obj = &bp->mcast_obj;
7767 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7768 if (rc < 0)
7769 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7770
7771 netif_addr_unlock_bh(bp->dev);
7772
7773
6debea87
DK		 7774
7775 /*
7776 * Send the UNLOAD_REQUEST to the MCP. This will return if
7777 * this function should perform FUNC, PORT or COMMON HW
7778 * reset.
7779 */
7780 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7781
7782 /*
7783 * (assumption: No Attention from MCP at this stage)
7784 * PMF probably in the middle of TXdisable/enable transaction
7785 */
7786 rc = bnx2x_func_wait_started(bp);
7787 if (rc) {
7788 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7789#ifdef BNX2X_STOP_ON_ERROR
7790 return;
7791#endif
7792 }
7793
34f80b04 7794 /* Close multi and leading connections
619c5cb6
VZ		 7795 * Completions for ramrods are collected in a synchronous way
7796 */
523224a3 7797 for_each_queue(bp, i)
619c5cb6 7798 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 7799#ifdef BNX2X_STOP_ON_ERROR
7800 return;
7801#else
228241eb 7802 goto unload_error;
523224a3 7803#endif
619c5cb6
VZ		 7804 /* If SP settings didn't get completed so far - something
7805 * very wrong has happen.
7806 */
7807 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7808 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 7809
619c5cb6
VZ		 7810#ifndef BNX2X_STOP_ON_ERROR
7811unload_error:
7812#endif
523224a3 7813 rc = bnx2x_func_stop(bp);
da5a662a 7814 if (rc) {
523224a3 7815 BNX2X_ERR("Function stop failed!\n");
da5a662a 7816#ifdef BNX2X_STOP_ON_ERROR
523224a3 7817 return;
523224a3 7818#endif
34f80b04 7819 }
a2fbb9ea 7820
523224a3
DK		 7821 /* Disable HW interrupts, NAPI */
7822 bnx2x_netif_stop(bp, 1);
7823
7824 /* Release IRQs */
d6214d7a 7825 bnx2x_free_irq(bp);
523224a3 7826
a2fbb9ea 7827 /* Reset the chip */
619c5cb6
VZ		 7828 rc = bnx2x_reset_hw(bp, reset_code);
7829 if (rc)
7830 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 7831
356e2385 7832
619c5cb6
VZ		 7833 /* Report UNLOAD_DONE to MCP */
7834 bnx2x_send_unload_done(bp);
72fd0718
VZ		 7835}
7836
9f6c9258 7837void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7838{
7839 u32 val;
7840
7841 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7842
7843 if (CHIP_IS_E1(bp)) {
7844 int port = BP_PORT(bp);
7845 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7846 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7847
7848 val = REG_RD(bp, addr);
7849 val &= ~(0x300);
7850 REG_WR(bp, addr, val);
619c5cb6 7851 } else {
72fd0718
VZ		 7852 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7853 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7854 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7855 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7856 }
7857}
7858
72fd0718
VZ		 7859/* Close gates #2, #3 and #4: */
7860static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7861{
c9ee9206 7862 u32 val;
72fd0718
VZ		 7863
7864 /* Gates #2 and #4a are closed/opened for "not E1" only */
7865 if (!CHIP_IS_E1(bp)) {
7866 /* #4 */
c9ee9206 7867 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 7868 /* #2 */
c9ee9206 7869 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 7870 }
7871
7872 /* #3 */
c9ee9206
VZ		 7873 if (CHIP_IS_E1x(bp)) {
7874 /* Prevent interrupts from HC on both ports */
7875 val = REG_RD(bp, HC_REG_CONFIG_1);
7876 REG_WR(bp, HC_REG_CONFIG_1,
7877 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7878 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7879
7880 val = REG_RD(bp, HC_REG_CONFIG_0);
7881 REG_WR(bp, HC_REG_CONFIG_0,
7882 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7883 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7884 } else {
7885 /* Prevent incomming interrupts in IGU */
7886 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7887
7888 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7889 (!close) ?
7890 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7891 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7892 }
72fd0718
VZ		 7893
7894 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7895 close ? "closing" : "opening");
7896 mmiowb();
7897}
7898
7899#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7900
7901static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7902{
7903 /* Do some magic... */
7904 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7905 *magic_val = val & SHARED_MF_CLP_MAGIC;
7906 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7907}
7908
e8920674
DK		 7909/**
7910 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7911 *
e8920674
DK		 7912 * @bp: driver handle
7913 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7914 */
7915static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7916{
7917 /* Restore the `magic' bit value... */
72fd0718
VZ		 7918 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7919 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7920 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7921}
7922
f85582f8 7923/**
e8920674 7924 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7925 *
e8920674
DK		 7926 * @bp: driver handle
7927 * @magic_val: old value of 'magic' bit.
7928 *
7929 * Takes care of CLP configurations.
72fd0718
VZ		 7930 */
7931static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7932{
7933 u32 shmem;
7934 u32 validity_offset;
7935
7936 DP(NETIF_MSG_HW, "Starting\n");
7937
7938 /* Set `magic' bit in order to save MF config */
7939 if (!CHIP_IS_E1(bp))
7940 bnx2x_clp_reset_prep(bp, magic_val);
7941
7942 /* Get shmem offset */
7943 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7944 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7945
7946 /* Clear validity map flags */
7947 if (shmem > 0)
7948 REG_WR(bp, shmem + validity_offset, 0);
7949}
7950
7951#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7952#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7953
e8920674
DK		 7954/**
7955 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7956 *
e8920674 7957 * @bp: driver handle
72fd0718
VZ		 7958 */
7959static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7960{
7961 /* special handling for emulation and FPGA,
7962 wait 10 times longer */
7963 if (CHIP_REV_IS_SLOW(bp))
7964 msleep(MCP_ONE_TIMEOUT*10);
7965 else
7966 msleep(MCP_ONE_TIMEOUT);
7967}
7968
1b6e2ceb
DK		 7969/*
7970 * initializes bp->common.shmem_base and waits for validity signature to appear
7971 */
7972static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 7973{
1b6e2ceb
DK		 7974 int cnt = 0;
7975 u32 val = 0;
72fd0718 7976
1b6e2ceb
DK		 7977 do {
7978 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7979 if (bp->common.shmem_base) {
7980 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7981 if (val & SHR_MEM_VALIDITY_MB)
7982 return 0;
7983 }
72fd0718 7984
1b6e2ceb 7985 bnx2x_mcp_wait_one(bp);
72fd0718 7986
1b6e2ceb 7987 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 7988
1b6e2ceb 7989 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 7990
1b6e2ceb
DK		 7991 return -ENODEV;
7992}
72fd0718 7993
1b6e2ceb
DK		 7994static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7995{
7996 int rc = bnx2x_init_shmem(bp);
72fd0718 7997
72fd0718
VZ		 7998 /* Restore the `magic' bit value */
7999 if (!CHIP_IS_E1(bp))
8000 bnx2x_clp_reset_done(bp, magic_val);
8001
8002 return rc;
8003}
8004
8005static void bnx2x_pxp_prep(struct bnx2x *bp)
8006{
8007 if (!CHIP_IS_E1(bp)) {
8008 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8009 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 8010 mmiowb();
8011 }
8012}
8013
8014/*
8015 * Reset the whole chip except for:
8016 * - PCIE core
8017 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8018 * one reset bit)
8019 * - IGU
8020 * - MISC (including AEU)
8021 * - GRC
8022 * - RBCN, RBCP
8023 */
c9ee9206 8024static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 8025{
8026 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 8027 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 8028
8029 /*
8030 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8031 * (per chip) blocks.
8032 */
8033 global_bits2 =
8034 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8035 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 8036
8736c826 8037 /* Don't reset the following blocks */
72fd0718
VZ		 8038 not_reset_mask1 =
8039 MISC_REGISTERS_RESET_REG_1_RST_HC |
8040 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8041 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8042
8043 not_reset_mask2 =
c9ee9206 8044 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8045 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8046 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8047 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8048 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8049 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8050 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8051 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8052 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8053 MISC_REGISTERS_RESET_REG_2_PGLC;
72fd0718 8054
8736c826
VZ		 8055 /*
8056 * Keep the following blocks in reset:
8057 * - all xxMACs are handled by the bnx2x_link code.
8058 */
8059 stay_reset2 =
8060 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8061 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8062 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8063 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8064 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8065 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8066 MISC_REGISTERS_RESET_REG_2_XMAC |
8067 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8068
8069 /* Full reset masks according to the chip */
72fd0718
VZ		 8070 reset_mask1 = 0xffffffff;
8071
8072 if (CHIP_IS_E1(bp))
8073 reset_mask2 = 0xffff;
8736c826 8074 else if (CHIP_IS_E1H(bp))
72fd0718 8075 reset_mask2 = 0x1ffff;
8736c826
VZ		 8076 else if (CHIP_IS_E2(bp))
8077 reset_mask2 = 0xfffff;
8078 else /* CHIP_IS_E3 */
8079 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 8080
8081 /* Don't reset global blocks unless we need to */
8082 if (!global)
8083 reset_mask2 &= ~global_bits2;
8084
8085 /*
8086 * In case of attention in the QM, we need to reset PXP
8087 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8088 * because otherwise QM reset would release 'close the gates' shortly
8089 * before resetting the PXP, then the PSWRQ would send a write
8090 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8091 * read the payload data from PSWWR, but PSWWR would not
8092 * respond. The write queue in PGLUE would stuck, dmae commands
8093 * would not return. Therefore it's important to reset the second
8094 * reset register (containing the
8095 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8096 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8097 * bit).
8098 */
72fd0718
VZ		 8099 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8100 reset_mask2 & (~not_reset_mask2));
8101
c9ee9206
VZ		 8102 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8103 reset_mask1 & (~not_reset_mask1));
8104
72fd0718
VZ		 8105 barrier();
8106 mmiowb();
8107
8736c826
VZ		 8108 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8109 reset_mask2 & (~stay_reset2));
8110
8111 barrier();
8112 mmiowb();
8113
c9ee9206 8114 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 8115 mmiowb();
8116}
8117
c9ee9206
VZ		 8118/**
8119 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8120 * It should get cleared in no more than 1s.
8121 *
8122 * @bp: driver handle
8123 *
8124 * It should get cleared in no more than 1s. Returns 0 if
8125 * pending writes bit gets cleared.
8126 */
8127static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8128{
8129 u32 cnt = 1000;
8130 u32 pend_bits = 0;
8131
8132 do {
8133 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8134
8135 if (pend_bits == 0)
8136 break;
8137
8138 usleep_range(1000, 1000);
8139 } while (cnt-- > 0);
8140
8141 if (cnt <= 0) {
8142 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8143 pend_bits);
8144 return -EBUSY;
8145 }
8146
8147 return 0;
8148}
8149
8150static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 8151{
8152 int cnt = 1000;
8153 u32 val = 0;
8154 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8155
8156
8157 /* Empty the Tetris buffer, wait for 1s */
8158 do {
8159 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8160 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8161 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8162 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8163 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8164 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8165 ((port_is_idle_0 & 0x1) == 0x1) &&
8166 ((port_is_idle_1 & 0x1) == 0x1) &&
8167 (pgl_exp_rom2 == 0xffffffff))
8168 break;
c9ee9206 8169 usleep_range(1000, 1000);
72fd0718
VZ		 8170 } while (cnt-- > 0);
8171
8172 if (cnt <= 0) {
8173 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8174 " are still"
8175 " outstanding read requests after 1s!\n");
8176 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8177 " port_is_idle_0=0x%08x,"
8178 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8179 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8180 pgl_exp_rom2);
8181 return -EAGAIN;
8182 }
8183
8184 barrier();
8185
8186 /* Close gates #2, #3 and #4 */
8187 bnx2x_set_234_gates(bp, true);
8188
c9ee9206
VZ		 8189 /* Poll for IGU VQs for 57712 and newer chips */
8190 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8191 return -EAGAIN;
8192
8193
72fd0718
VZ		 8194 /* TBD: Indicate that "process kill" is in progress to MCP */
8195
8196 /* Clear "unprepared" bit */
8197 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8198 barrier();
8199
8200 /* Make sure all is written to the chip before the reset */
8201 mmiowb();
8202
8203 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8204 * PSWHST, GRC and PSWRD Tetris buffer.
8205 */
c9ee9206 8206 usleep_range(1000, 1000);
72fd0718
VZ		 8207
8208 /* Prepare to chip reset: */
8209 /* MCP */
c9ee9206
VZ		 8210 if (global)
8211 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 8212
8213 /* PXP */
8214 bnx2x_pxp_prep(bp);
8215 barrier();
8216
8217 /* reset the chip */
c9ee9206 8218 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 8219 barrier();
8220
8221 /* Recover after reset: */
8222 /* MCP */
c9ee9206 8223 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 8224 return -EAGAIN;
8225
c9ee9206
VZ		 8226 /* TBD: Add resetting the NO_MCP mode DB here */
8227
72fd0718
VZ		 8228 /* PXP */
8229 bnx2x_pxp_prep(bp);
8230
8231 /* Open the gates #2, #3 and #4 */
8232 bnx2x_set_234_gates(bp, false);
8233
8234 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8235 * reset state, re-enable attentions. */
8236
a2fbb9ea
ET		 8237 return 0;
8238}
8239
c9ee9206 8240int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 8241{
8242 int rc = 0;
c9ee9206
VZ		 8243 bool global = bnx2x_reset_is_global(bp);
8244
72fd0718 8245 /* Try to recover after the failure */
c9ee9206
VZ		 8246 if (bnx2x_process_kill(bp, global)) {
8247 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8248 "Aii!\n", BP_PATH(bp));
72fd0718
VZ		 8249 rc = -EAGAIN;
8250 goto exit_leader_reset;
8251 }
8252
c9ee9206
VZ		 8253 /*
8254 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8255 * state.
8256 */
72fd0718 8257 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 8258 if (global)
8259 bnx2x_clear_reset_global(bp);
72fd0718
VZ		 8260
8261exit_leader_reset:
8262 bp->is_leader = 0;
c9ee9206
VZ		 8263 bnx2x_release_leader_lock(bp);
8264 smp_mb();
72fd0718
VZ		 8265 return rc;
8266}
8267
c9ee9206
VZ		 8268static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8269{
8270 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8271
8272 /* Disconnect this device */
8273 netif_device_detach(bp->dev);
8274
8275 /*
8276 * Block ifup for all function on this engine until "process kill"
8277 * or power cycle.
8278 */
8279 bnx2x_set_reset_in_progress(bp);
8280
8281 /* Shut down the power */
8282 bnx2x_set_power_state(bp, PCI_D3hot);
8283
8284 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8285
8286 smp_mb();
8287}
8288
8289/*
8290 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 8291 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 8292 * will never be called when netif_running(bp->dev) is false.
8293 */
8294static void bnx2x_parity_recover(struct bnx2x *bp)
8295{
c9ee9206
VZ		 8296 bool global = false;
8297
72fd0718
VZ		 8298 DP(NETIF_MSG_HW, "Handling parity\n");
8299 while (1) {
8300 switch (bp->recovery_state) {
8301 case BNX2X_RECOVERY_INIT:
8302 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
c9ee9206
VZ		 8303 bnx2x_chk_parity_attn(bp, &global, false);
8304
72fd0718 8305 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 8306 if (bnx2x_trylock_leader_lock(bp)) {
8307 bnx2x_set_reset_in_progress(bp);
8308 /*
8309 * Check if there is a global attention and if
8310 * there was a global attention, set the global
8311 * reset bit.
8312 */
8313
8314 if (global)
8315 bnx2x_set_reset_global(bp);
8316
72fd0718 8317 bp->is_leader = 1;
c9ee9206 8318 }
72fd0718
VZ		 8319
8320 /* Stop the driver */
8321 /* If interface has been removed - break */
8322 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8323 return;
8324
8325 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206
VZ		 8326
8327 /*
8328 * Reset MCP command sequence number and MCP mail box
8329 * sequence as we are going to reset the MCP.
8330 */
8331 if (global) {
8332 bp->fw_seq = 0;
8333 bp->fw_drv_pulse_wr_seq = 0;
8334 }
8335
8336 /* Ensure "is_leader", MCP command sequence and
8337 * "recovery_state" update values are seen on other
8338 * CPUs.
72fd0718 8339 */
c9ee9206 8340 smp_mb();
72fd0718
VZ		 8341 break;
8342
8343 case BNX2X_RECOVERY_WAIT:
8344 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8345 if (bp->is_leader) {
c9ee9206
VZ		 8346 int other_engine = BP_PATH(bp) ? 0 : 1;
8347 u32 other_load_counter =
8348 bnx2x_get_load_cnt(bp, other_engine);
8349 u32 load_counter =
8350 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8351 global = bnx2x_reset_is_global(bp);
8352
8353 /*
8354 * In case of a parity in a global block, let
8355 * the first leader that performs a
8356 * leader_reset() reset the global blocks in
8357 * order to clear global attentions. Otherwise
8358 * the the gates will remain closed for that
8359 * engine.
8360 */
8361 if (load_counter ||
8362 (global && other_load_counter)) {
72fd0718
VZ		 8363 /* Wait until all other functions get
8364 * down.
8365 */
7be08a72 8366 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8367 HZ/10);
8368 return;
8369 } else {
8370 /* If all other functions got down -
8371 * try to bring the chip back to
8372 * normal. In any case it's an exit
8373 * point for a leader.
8374 */
c9ee9206
VZ		 8375 if (bnx2x_leader_reset(bp)) {
8376 bnx2x_recovery_failed(bp);
72fd0718
VZ		 8377 return;
8378 }
8379
c9ee9206
VZ		 8380 /* If we are here, means that the
8381 * leader has succeeded and doesn't
8382 * want to be a leader any more. Try
8383 * to continue as a none-leader.
8384 */
8385 break;
72fd0718
VZ		 8386 }
8387 } else { /* non-leader */
c9ee9206 8388 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 8389 /* Try to get a LEADER_LOCK HW lock as
8390 * long as a former leader may have
8391 * been unloaded by the user or
8392 * released a leadership by another
8393 * reason.
8394 */
c9ee9206 8395 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 8396 /* I'm a leader now! Restart a
8397 * switch case.
8398 */
8399 bp->is_leader = 1;
8400 break;
8401 }
8402
7be08a72 8403 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8404 HZ/10);
8405 return;
8406
c9ee9206
VZ		 8407 } else {
8408 /*
8409 * If there was a global attention, wait
8410 * for it to be cleared.
8411 */
8412 if (bnx2x_reset_is_global(bp)) {
8413 schedule_delayed_work(
7be08a72
AE		 8414 &bp->sp_rtnl_task,
8415 HZ/10);
c9ee9206
VZ		 8416 return;
8417 }
8418
8419 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8420 bnx2x_recovery_failed(bp);
8421 else {
8422 bp->recovery_state =
8423 BNX2X_RECOVERY_DONE;
8424 smp_mb();
8425 }
8426
72fd0718
VZ		 8427 return;
8428 }
8429 }
8430 default:
8431 return;
8432 }
8433 }
8434}
8435
8436/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8437 * scheduled on a general queue in order to prevent a dead lock.
8438 */
7be08a72 8439static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 8440{
7be08a72 8441 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 8442
8443 rtnl_lock();
8444
8445 if (!netif_running(bp->dev))
7be08a72
AE		 8446 goto sp_rtnl_exit;
8447
8448 /* if stop on error is defined no recovery flows should be executed */
8449#ifdef BNX2X_STOP_ON_ERROR
8450 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8451 "so reset not done to allow debug dump,\n"
8452 "you will need to reboot when done\n");
b1fb8740 8453 goto sp_rtnl_not_reset;
7be08a72 8454#endif
34f80b04 8455
7be08a72
AE		 8456 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8457 /*
b1fb8740
VZ		 8458 * Clear all pending SP commands as we are going to reset the
8459 * function anyway.
7be08a72 8460 */
b1fb8740
VZ		 8461 bp->sp_rtnl_state = 0;
8462 smp_mb();
8463
72fd0718 8464 bnx2x_parity_recover(bp);
b1fb8740
VZ		 8465
8466 goto sp_rtnl_exit;
8467 }
8468
8469 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8470 /*
8471 * Clear all pending SP commands as we are going to reset the
8472 * function anyway.
8473 */
8474 bp->sp_rtnl_state = 0;
8475 smp_mb();
8476
72fd0718
VZ		 8477 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8478 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740
VZ		 8479
8480 goto sp_rtnl_exit;
72fd0718 8481 }
b1fb8740
VZ		 8482#ifdef BNX2X_STOP_ON_ERROR
8483sp_rtnl_not_reset:
8484#endif
8485 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8486 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
34f80b04 8487
7be08a72 8488sp_rtnl_exit:
34f80b04
EG		 8489 rtnl_unlock();
8490}
8491
a2fbb9ea
ET		 8492/* end of nic load/unload */
8493
3deb8167
YR		 8494static void bnx2x_period_task(struct work_struct *work)
8495{
8496 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8497
8498 if (!netif_running(bp->dev))
8499 goto period_task_exit;
8500
8501 if (CHIP_REV_IS_SLOW(bp)) {
8502 BNX2X_ERR("period task called on emulation, ignoring\n");
8503 goto period_task_exit;
8504 }
8505
8506 bnx2x_acquire_phy_lock(bp);
8507 /*
8508 * The barrier is needed to ensure the ordering between the writing to
8509 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8510 * the reading here.
8511 */
8512 smp_mb();
8513 if (bp->port.pmf) {
8514 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8515
8516 /* Re-queue task in 1 sec */
8517 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8518 }
8519
8520 bnx2x_release_phy_lock(bp);
8521period_task_exit:
8522 return;
8523}
8524
a2fbb9ea
ET		 8525/*
8526 * Init service functions
8527 */
8528
8d96286a 8529static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 8530{
8531 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8532 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8533 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 8534}
8535
f2e0899f 8536static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 8537{
f2e0899f 8538 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 8539
8540 /* Flush all outstanding writes */
8541 mmiowb();
8542
8543 /* Pretend to be function 0 */
8544 REG_WR(bp, reg, 0);
f2e0899f 8545 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 8546
8547 /* From now we are in the "like-E1" mode */
8548 bnx2x_int_disable(bp);
8549
8550 /* Flush all outstanding writes */
8551 mmiowb();
8552
f2e0899f
DK		 8553 /* Restore the original function */
8554 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8555 REG_RD(bp, reg);
f1ef27ef
EG		 8556}
8557
f2e0899f 8558static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 8559{
f2e0899f 8560 if (CHIP_IS_E1(bp))
f1ef27ef 8561 bnx2x_int_disable(bp);
f2e0899f
DK		 8562 else
8563 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 8564}
8565
34f80b04
EG		 8566static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8567{
8568 u32 val;
8569
8570 /* Check if there is any driver already loaded */
8571 val = REG_RD(bp, MISC_REG_UNPREPARED);
8572 if (val == 0x1) {
7a06a122
DK		 8573
8574 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8575 /*
8576 * Check if it is the UNDI driver
34f80b04
EG		 8577 * UNDI driver initializes CID offset for normal bell to 0x7
8578 */
8579 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8580 if (val == 0x7) {
8581 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 8582 /* save our pf_num */
8583 int orig_pf_num = bp->pf_num;
619c5cb6
VZ		 8584 int port;
8585 u32 swap_en, swap_val, value;
34f80b04 8586
b4661739
EG		 8587 /* clear the UNDI indication */
8588 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8589
34f80b04
EG		 8590 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8591
8592 /* try unload UNDI on port 0 */
f2e0899f 8593 bp->pf_num = 0;
da5a662a 8594 bp->fw_seq =
f2e0899f 8595 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8596 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 8597 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8598
8599 /* if UNDI is loaded on the other port */
8600 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8601
da5a662a 8602 /* send "DONE" for previous unload */
a22f0788
YR		 8603 bnx2x_fw_command(bp,
8604 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8605
8606 /* unload UNDI on port 1 */
f2e0899f 8607 bp->pf_num = 1;
da5a662a 8608 bp->fw_seq =
f2e0899f 8609 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 8610 DRV_MSG_SEQ_NUMBER_MASK);
8611 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8612
a22f0788 8613 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8614 }
8615
f2e0899f 8616 bnx2x_undi_int_disable(bp);
619c5cb6 8617 port = BP_PORT(bp);
da5a662a
VZ		 8618
8619 /* close input traffic and wait for it */
8620 /* Do not rcv packets to BRB */
619c5cb6
VZ		 8621 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8622 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
da5a662a
VZ		 8623 /* Do not direct rcv packets that are not for MCP to
8624 * the BRB */
619c5cb6
VZ		 8625 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8626 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
da5a662a 8627 /* clear AEU */
619c5cb6
VZ		 8628 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8629 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
da5a662a
VZ		 8630 msleep(10);
8631
8632 /* save NIG port swap info */
8633 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8634 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 8635 /* reset device */
8636 REG_WR(bp,
8637 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 8638 0xd3ffffff);
619c5cb6
VZ		 8639
8640 value = 0x1400;
8641 if (CHIP_IS_E3(bp)) {
8642 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8643 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8644 }
8645
34f80b04
EG		 8646 REG_WR(bp,
8647 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
619c5cb6
VZ		 8648 value);
8649
da5a662a
VZ		 8650 /* take the NIG out of reset and restore swap values */
8651 REG_WR(bp,
8652 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8653 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8654 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8655 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8656
8657 /* send unload done to the MCP */
a22f0788 8658 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8659
8660 /* restore our func and fw_seq */
f2e0899f 8661 bp->pf_num = orig_pf_num;
da5a662a 8662 bp->fw_seq =
f2e0899f 8663 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8664 DRV_MSG_SEQ_NUMBER_MASK);
7a06a122
DK		 8665 }
8666
8667 /* now it's safe to release the lock */
8668 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
34f80b04
EG		 8669 }
8670}
8671
8672static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8673{
8674 u32 val, val2, val3, val4, id;
72ce58c3 8675 u16 pmc;
34f80b04
EG		 8676
8677 /* Get the chip revision id and number. */
8678 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8679 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8680 id = ((val & 0xffff) << 16);
8681 val = REG_RD(bp, MISC_REG_CHIP_REV);
8682 id |= ((val & 0xf) << 12);
8683 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8684 id |= ((val & 0xff) << 4);
5a40e08e 8685 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 8686 id |= (val & 0xf);
8687 bp->common.chip_id = id;
523224a3
DK		 8688
8689 /* Set doorbell size */
8690 bp->db_size = (1 << BNX2X_DB_SHIFT);
8691
619c5cb6 8692 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8693 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8694 if ((val & 1) == 0)
8695 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8696 else
8697 val = (val >> 1) & 1;
8698 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8699 "2_PORT_MODE");
8700 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8701 CHIP_2_PORT_MODE;
8702
8703 if (CHIP_MODE_IS_4_PORT(bp))
8704 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8705 else
8706 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8707 } else {
8708 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8709 bp->pfid = bp->pf_num; /* 0..7 */
8710 }
8711
f2e0899f
DK		 8712 bp->link_params.chip_id = bp->common.chip_id;
8713 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 8714
1c06328c
EG		 8715 val = (REG_RD(bp, 0x2874) & 0x55);
8716 if ((bp->common.chip_id & 0x1) ||
8717 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8718 bp->flags |= ONE_PORT_FLAG;
8719 BNX2X_DEV_INFO("single port device\n");
8720 }
8721
34f80b04 8722 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 8723 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 8724 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8725 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8726 bp->common.flash_size, bp->common.flash_size);
8727
1b6e2ceb
DK		 8728 bnx2x_init_shmem(bp);
8729
619c5cb6
VZ		 8730
8731
f2e0899f
DK		 8732 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8733 MISC_REG_GENERIC_CR_1 :
8734 MISC_REG_GENERIC_CR_0));
1b6e2ceb 8735
34f80b04 8736 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 8737 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 8738 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8739 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 8740
f2e0899f 8741 if (!bp->common.shmem_base) {
34f80b04
EG		 8742 BNX2X_DEV_INFO("MCP not active\n");
8743 bp->flags |= NO_MCP_FLAG;
8744 return;
8745 }
8746
34f80b04 8747 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 8748 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 8749
8750 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8751 SHARED_HW_CFG_LED_MODE_MASK) >>
8752 SHARED_HW_CFG_LED_MODE_SHIFT);
8753
c2c8b03e
EG		 8754 bp->link_params.feature_config_flags = 0;
8755 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8756 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8757 bp->link_params.feature_config_flags |=
8758 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8759 else
8760 bp->link_params.feature_config_flags &=
8761 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8762
34f80b04
EG		 8763 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8764 bp->common.bc_ver = val;
8765 BNX2X_DEV_INFO("bc_ver %X\n", val);
8766 if (val < BNX2X_BC_VER) {
8767 /* for now only warn
8768 * later we might need to enforce this */
f2e0899f
DK		 8769 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8770 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 8771 }
4d295db0 8772 bp->link_params.feature_config_flags |=
a22f0788 8773 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 8774 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8775
a22f0788
YR		 8776 bp->link_params.feature_config_flags |=
8777 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8778 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 8779
85242eea
YR		 8780 bp->link_params.feature_config_flags |=
8781 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8782 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8783
f9a3ebbe
DK		 8784 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8785 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8786
72ce58c3 8787 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 8788 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 8789
8790 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8791 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8792 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8793 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8794
cdaa7cb8
VZ		 8795 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8796 val, val2, val3, val4);
34f80b04
EG		 8797}
8798
f2e0899f
DK		 8799#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8800#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8801
8802static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8803{
8804 int pfid = BP_FUNC(bp);
f2e0899f
DK		 8805 int igu_sb_id;
8806 u32 val;
6383c0b3 8807 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 8808
8809 bp->igu_base_sb = 0xff;
f2e0899f 8810 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 8811 int vn = BP_VN(bp);
6383c0b3 8812 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 8813 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8814 FP_SB_MAX_E1x;
8815
8816 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8817 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8818
8819 return;
8820 }
8821
8822 /* IGU in normal mode - read CAM */
8823 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8824 igu_sb_id++) {
8825 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8826 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8827 continue;
8828 fid = IGU_FID(val);
8829 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8830 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8831 continue;
8832 if (IGU_VEC(val) == 0)
8833 /* default status block */
8834 bp->igu_dsb_id = igu_sb_id;
8835 else {
8836 if (bp->igu_base_sb == 0xff)
8837 bp->igu_base_sb = igu_sb_id;
6383c0b3 8838 igu_sb_cnt++;
f2e0899f
DK		 8839 }
8840 }
8841 }
619c5cb6 8842
6383c0b3
AE		 8843#ifdef CONFIG_PCI_MSI
8844 /*
8845 * It's expected that number of CAM entries for this functions is equal
8846 * to the number evaluated based on the MSI-X table size. We want a
8847 * harsh warning if these values are different!
619c5cb6 8848 */
6383c0b3
AE		 8849 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8850#endif
619c5cb6 8851
6383c0b3 8852 if (igu_sb_cnt == 0)
f2e0899f
DK		 8853 BNX2X_ERR("CAM configuration error\n");
8854}
8855
34f80b04
EG		 8856static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8857 u32 switch_cfg)
a2fbb9ea 8858{
a22f0788
YR		 8859 int cfg_size = 0, idx, port = BP_PORT(bp);
8860
8861 /* Aggregation of supported attributes of all external phys */
8862 bp->port.supported[0] = 0;
8863 bp->port.supported[1] = 0;
b7737c9b
YR		 8864 switch (bp->link_params.num_phys) {
8865 case 1:
a22f0788
YR		 8866 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8867 cfg_size = 1;
8868 break;
b7737c9b 8869 case 2:
a22f0788
YR		 8870 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8871 cfg_size = 1;
8872 break;
8873 case 3:
8874 if (bp->link_params.multi_phy_config &
8875 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8876 bp->port.supported[1] =
8877 bp->link_params.phy[EXT_PHY1].supported;
8878 bp->port.supported[0] =
8879 bp->link_params.phy[EXT_PHY2].supported;
8880 } else {
8881 bp->port.supported[0] =
8882 bp->link_params.phy[EXT_PHY1].supported;
8883 bp->port.supported[1] =
8884 bp->link_params.phy[EXT_PHY2].supported;
8885 }
8886 cfg_size = 2;
8887 break;
b7737c9b 8888 }
a2fbb9ea 8889
a22f0788 8890 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8891 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8892 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8893 SHMEM_RD(bp,
a22f0788
YR		 8894 dev_info.port_hw_config[port].external_phy_config),
8895 SHMEM_RD(bp,
8896 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8897 return;
f85582f8 8898 }
a2fbb9ea 8899
619c5cb6
VZ		 8900 if (CHIP_IS_E3(bp))
8901 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8902 else {
8903 switch (switch_cfg) {
8904 case SWITCH_CFG_1G:
8905 bp->port.phy_addr = REG_RD(
8906 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8907 break;
8908 case SWITCH_CFG_10G:
8909 bp->port.phy_addr = REG_RD(
8910 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8911 break;
8912 default:
8913 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8914 bp->port.link_config[0]);
8915 return;
8916 }
a2fbb9ea 8917 }
619c5cb6 8918 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 8919 /* mask what we support according to speed_cap_mask per configuration */
8920 for (idx = 0; idx < cfg_size; idx++) {
8921 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8922 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8923 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8924
a22f0788 8925 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8926 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8927 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8928
a22f0788 8929 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8930 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8931 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8932
a22f0788 8933 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8934 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8935 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8936
a22f0788 8937 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8938 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8939 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8940 SUPPORTED_1000baseT_Full);
a2fbb9ea 8941
a22f0788 8942 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8943 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8944 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8945
a22f0788 8946 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8947 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8948 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8949
8950 }
a2fbb9ea 8951
a22f0788
YR		 8952 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8953 bp->port.supported[1]);
a2fbb9ea
ET		 8954}
8955
34f80b04 8956static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8957{
a22f0788
YR		 8958 u32 link_config, idx, cfg_size = 0;
8959 bp->port.advertising[0] = 0;
8960 bp->port.advertising[1] = 0;
8961 switch (bp->link_params.num_phys) {
8962 case 1:
8963 case 2:
8964 cfg_size = 1;
8965 break;
8966 case 3:
8967 cfg_size = 2;
8968 break;
8969 }
8970 for (idx = 0; idx < cfg_size; idx++) {
8971 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8972 link_config = bp->port.link_config[idx];
8973 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8974 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8975 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8976 bp->link_params.req_line_speed[idx] =
8977 SPEED_AUTO_NEG;
8978 bp->port.advertising[idx] |=
8979 bp->port.supported[idx];
f85582f8
DK		 8980 } else {
8981 /* force 10G, no AN */
a22f0788
YR		 8982 bp->link_params.req_line_speed[idx] =
8983 SPEED_10000;
8984 bp->port.advertising[idx] |=
8985 (ADVERTISED_10000baseT_Full |
f85582f8 8986 ADVERTISED_FIBRE);
a22f0788 8987 continue;
f85582f8
DK		 8988 }
8989 break;
a2fbb9ea 8990
f85582f8 8991 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8992 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8993 bp->link_params.req_line_speed[idx] =
8994 SPEED_10;
8995 bp->port.advertising[idx] |=
8996 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8997 ADVERTISED_TP);
8998 } else {
754a2f52 8999 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9000 "Invalid link_config 0x%x"
9001 " speed_cap_mask 0x%x\n",
9002 link_config,
a22f0788 9003 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9004 return;
9005 }
9006 break;
a2fbb9ea 9007
f85582f8 9008 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 9009 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9010 bp->link_params.req_line_speed[idx] =
9011 SPEED_10;
9012 bp->link_params.req_duplex[idx] =
9013 DUPLEX_HALF;
9014 bp->port.advertising[idx] |=
9015 (ADVERTISED_10baseT_Half |
f85582f8
DK		 9016 ADVERTISED_TP);
9017 } else {
754a2f52 9018 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9019 "Invalid link_config 0x%x"
9020 " speed_cap_mask 0x%x\n",
9021 link_config,
9022 bp->link_params.speed_cap_mask[idx]);
9023 return;
9024 }
9025 break;
a2fbb9ea 9026
f85582f8
DK		 9027 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9028 if (bp->port.supported[idx] &
9029 SUPPORTED_100baseT_Full) {
a22f0788
YR		 9030 bp->link_params.req_line_speed[idx] =
9031 SPEED_100;
9032 bp->port.advertising[idx] |=
9033 (ADVERTISED_100baseT_Full |
f85582f8
DK		 9034 ADVERTISED_TP);
9035 } else {
754a2f52 9036 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9037 "Invalid link_config 0x%x"
9038 " speed_cap_mask 0x%x\n",
9039 link_config,
9040 bp->link_params.speed_cap_mask[idx]);
9041 return;
9042 }
9043 break;
a2fbb9ea 9044
f85582f8
DK		 9045 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9046 if (bp->port.supported[idx] &
9047 SUPPORTED_100baseT_Half) {
9048 bp->link_params.req_line_speed[idx] =
9049 SPEED_100;
9050 bp->link_params.req_duplex[idx] =
9051 DUPLEX_HALF;
a22f0788
YR		 9052 bp->port.advertising[idx] |=
9053 (ADVERTISED_100baseT_Half |
f85582f8
DK		 9054 ADVERTISED_TP);
9055 } else {
754a2f52 9056 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9057 "Invalid link_config 0x%x"
9058 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9059 link_config,
9060 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9061 return;
9062 }
9063 break;
a2fbb9ea 9064
f85582f8 9065 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 9066 if (bp->port.supported[idx] &
9067 SUPPORTED_1000baseT_Full) {
9068 bp->link_params.req_line_speed[idx] =
9069 SPEED_1000;
9070 bp->port.advertising[idx] |=
9071 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 9072 ADVERTISED_TP);
9073 } else {
754a2f52 9074 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9075 "Invalid link_config 0x%x"
9076 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9077 link_config,
9078 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9079 return;
9080 }
9081 break;
a2fbb9ea 9082
f85582f8 9083 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 9084 if (bp->port.supported[idx] &
9085 SUPPORTED_2500baseX_Full) {
9086 bp->link_params.req_line_speed[idx] =
9087 SPEED_2500;
9088 bp->port.advertising[idx] |=
9089 (ADVERTISED_2500baseX_Full |
34f80b04 9090 ADVERTISED_TP);
f85582f8 9091 } else {
754a2f52 9092 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9093 "Invalid link_config 0x%x"
9094 " speed_cap_mask 0x%x\n",
a22f0788 9095 link_config,
f85582f8
DK		 9096 bp->link_params.speed_cap_mask[idx]);
9097 return;
9098 }
9099 break;
a2fbb9ea 9100
f85582f8 9101 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 9102 if (bp->port.supported[idx] &
9103 SUPPORTED_10000baseT_Full) {
9104 bp->link_params.req_line_speed[idx] =
9105 SPEED_10000;
9106 bp->port.advertising[idx] |=
9107 (ADVERTISED_10000baseT_Full |
34f80b04 9108 ADVERTISED_FIBRE);
f85582f8 9109 } else {
754a2f52 9110 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9111 "Invalid link_config 0x%x"
9112 " speed_cap_mask 0x%x\n",
a22f0788 9113 link_config,
f85582f8
DK		 9114 bp->link_params.speed_cap_mask[idx]);
9115 return;
9116 }
9117 break;
3c9ada22
YR		 9118 case PORT_FEATURE_LINK_SPEED_20G:
9119 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 9120
3c9ada22 9121 break;
f85582f8 9122 default:
754a2f52
DK		 9123 BNX2X_ERR("NVRAM config error. "
9124 "BAD link speed link_config 0x%x\n",
9125 link_config);
f85582f8
DK		 9126 bp->link_params.req_line_speed[idx] =
9127 SPEED_AUTO_NEG;
9128 bp->port.advertising[idx] =
9129 bp->port.supported[idx];
9130 break;
9131 }
a2fbb9ea 9132
a22f0788 9133 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 9134 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 9135 if ((bp->link_params.req_flow_ctrl[idx] ==
9136 BNX2X_FLOW_CTRL_AUTO) &&
9137 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9138 bp->link_params.req_flow_ctrl[idx] =
9139 BNX2X_FLOW_CTRL_NONE;
9140 }
a2fbb9ea 9141
a22f0788
YR		 9142 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9143 " 0x%x advertising 0x%x\n",
9144 bp->link_params.req_line_speed[idx],
9145 bp->link_params.req_duplex[idx],
9146 bp->link_params.req_flow_ctrl[idx],
9147 bp->port.advertising[idx]);
9148 }
a2fbb9ea
ET		 9149}
9150
e665bfda
MC		 9151static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9152{
9153 mac_hi = cpu_to_be16(mac_hi);
9154 mac_lo = cpu_to_be32(mac_lo);
9155 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9156 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9157}
9158
34f80b04 9159static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 9160{
34f80b04 9161 int port = BP_PORT(bp);
589abe3a 9162 u32 config;
6f38ad93 9163 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 9164
c18487ee 9165 bp->link_params.bp = bp;
34f80b04 9166 bp->link_params.port = port;
c18487ee 9167
c18487ee 9168 bp->link_params.lane_config =
a2fbb9ea 9169 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 9170
a22f0788 9171 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 9172 SHMEM_RD(bp,
9173 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 9174 bp->link_params.speed_cap_mask[1] =
9175 SHMEM_RD(bp,
9176 dev_info.port_hw_config[port].speed_capability_mask2);
9177 bp->port.link_config[0] =
a2fbb9ea
ET		 9178 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9179
a22f0788
YR		 9180 bp->port.link_config[1] =
9181 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 9182
a22f0788
YR		 9183 bp->link_params.multi_phy_config =
9184 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 9185 /* If the device is capable of WoL, set the default state according
9186 * to the HW
9187 */
4d295db0 9188 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 9189 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9190 (config & PORT_FEATURE_WOL_ENABLED));
9191
f85582f8 9192 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 9193 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 9194 bp->link_params.lane_config,
a22f0788
YR		 9195 bp->link_params.speed_cap_mask[0],
9196 bp->port.link_config[0]);
a2fbb9ea 9197
a22f0788 9198 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 9199 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 9200 bnx2x_phy_probe(&bp->link_params);
c18487ee 9201 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 9202
9203 bnx2x_link_settings_requested(bp);
9204
01cd4528
EG		 9205 /*
9206 * If connected directly, work with the internal PHY, otherwise, work
9207 * with the external PHY
9208 */
b7737c9b
YR		 9209 ext_phy_config =
9210 SHMEM_RD(bp,
9211 dev_info.port_hw_config[port].external_phy_config);
9212 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 9213 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 9214 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 9215
9216 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9217 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9218 bp->mdio.prtad =
b7737c9b 9219 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 9220
9221 /*
9222 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9223 * In MF mode, it is set to cover self test cases
9224 */
9225 if (IS_MF(bp))
9226 bp->port.need_hw_lock = 1;
9227 else
9228 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9229 bp->common.shmem_base,
9230 bp->common.shmem2_base);
0793f83f 9231}
01cd4528 9232
2ba45142
VZ		 9233#ifdef BCM_CNIC
9234static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9235{
bf61ee14
VZ		 9236 int port = BP_PORT(bp);
9237 int func = BP_ABS_FUNC(bp);
9238
2ba45142 9239 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9240 drv_lic_key[port].max_iscsi_conn);
2ba45142 9241 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9242 drv_lic_key[port].max_fcoe_conn);
2ba45142
VZ		 9243
9244 /* Get the number of maximum allowed iSCSI and FCoE connections */
9245 bp->cnic_eth_dev.max_iscsi_conn =
9246 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9247 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9248
9249 bp->cnic_eth_dev.max_fcoe_conn =
9250 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9251 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9252
bf61ee14
VZ		 9253 /* Read the WWN: */
9254 if (!IS_MF(bp)) {
9255 /* Port info */
9256 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9257 SHMEM_RD(bp,
9258 dev_info.port_hw_config[port].
9259 fcoe_wwn_port_name_upper);
9260 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9261 SHMEM_RD(bp,
9262 dev_info.port_hw_config[port].
9263 fcoe_wwn_port_name_lower);
9264
9265 /* Node info */
9266 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9267 SHMEM_RD(bp,
9268 dev_info.port_hw_config[port].
9269 fcoe_wwn_node_name_upper);
9270 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9271 SHMEM_RD(bp,
9272 dev_info.port_hw_config[port].
9273 fcoe_wwn_node_name_lower);
9274 } else if (!IS_MF_SD(bp)) {
9275 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9276
9277 /*
9278 * Read the WWN info only if the FCoE feature is enabled for
9279 * this function.
9280 */
9281 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9282 /* Port info */
9283 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9284 MF_CFG_RD(bp, func_ext_config[func].
9285 fcoe_wwn_port_name_upper);
9286 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9287 MF_CFG_RD(bp, func_ext_config[func].
9288 fcoe_wwn_port_name_lower);
9289
9290 /* Node info */
9291 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9292 MF_CFG_RD(bp, func_ext_config[func].
9293 fcoe_wwn_node_name_upper);
9294 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9295 MF_CFG_RD(bp, func_ext_config[func].
9296 fcoe_wwn_node_name_lower);
9297 }
9298 }
9299
2ba45142
VZ		 9300 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9301 bp->cnic_eth_dev.max_iscsi_conn,
9302 bp->cnic_eth_dev.max_fcoe_conn);
9303
bf61ee14
VZ		 9304 /*
9305 * If maximum allowed number of connections is zero -
2ba45142
VZ		 9306 * disable the feature.
9307 */
9308 if (!bp->cnic_eth_dev.max_iscsi_conn)
9309 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9310
9311 if (!bp->cnic_eth_dev.max_fcoe_conn)
9312 bp->flags |= NO_FCOE_FLAG;
9313}
9314#endif
9315
0793f83f
DK		 9316static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9317{
9318 u32 val, val2;
9319 int func = BP_ABS_FUNC(bp);
9320 int port = BP_PORT(bp);
2ba45142
VZ		 9321#ifdef BCM_CNIC
9322 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9323 u8 *fip_mac = bp->fip_mac;
9324#endif
0793f83f 9325
619c5cb6
VZ		 9326 /* Zero primary MAC configuration */
9327 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9328
0793f83f
DK		 9329 if (BP_NOMCP(bp)) {
9330 BNX2X_ERROR("warning: random MAC workaround active\n");
9331 random_ether_addr(bp->dev->dev_addr);
9332 } else if (IS_MF(bp)) {
9333 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9334 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9335 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9336 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9337 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 9338
9339#ifdef BCM_CNIC
2ba45142
VZ		 9340 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9341 * FCoE MAC then the appropriate feature should be disabled.
9342 */
0793f83f
DK		 9343 if (IS_MF_SI(bp)) {
9344 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9345 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9346 val2 = MF_CFG_RD(bp, func_ext_config[func].
9347 iscsi_mac_addr_upper);
9348 val = MF_CFG_RD(bp, func_ext_config[func].
9349 iscsi_mac_addr_lower);
2ba45142 9350 bnx2x_set_mac_buf(iscsi_mac, val, val2);
619c5cb6
VZ		 9351 BNX2X_DEV_INFO("Read iSCSI MAC: "
9352 BNX2X_MAC_FMT"\n",
9353 BNX2X_MAC_PRN_LIST(iscsi_mac));
2ba45142
VZ		 9354 } else
9355 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9356
9357 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9358 val2 = MF_CFG_RD(bp, func_ext_config[func].
9359 fcoe_mac_addr_upper);
9360 val = MF_CFG_RD(bp, func_ext_config[func].
9361 fcoe_mac_addr_lower);
2ba45142 9362 bnx2x_set_mac_buf(fip_mac, val, val2);
619c5cb6
VZ		 9363 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9364 BNX2X_MAC_FMT"\n",
9365 BNX2X_MAC_PRN_LIST(fip_mac));
2ba45142 9366
2ba45142
VZ		 9367 } else
9368 bp->flags |= NO_FCOE_FLAG;
0793f83f 9369 }
37b091ba 9370#endif
0793f83f
DK		 9371 } else {
9372 /* in SF read MACs from port configuration */
9373 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9374 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9375 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9376
9377#ifdef BCM_CNIC
9378 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9379 iscsi_mac_upper);
9380 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9381 iscsi_mac_lower);
2ba45142 9382 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 9383
9384 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9385 fcoe_fip_mac_upper);
9386 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9387 fcoe_fip_mac_lower);
9388 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 9389#endif
9390 }
9391
9392 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9393 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9394
ec6ba945 9395#ifdef BCM_CNIC
c03bd39c
VZ		 9396 /* Set the FCoE MAC in MF_SD mode */
9397 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9398 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
426b9241
DK		 9399
9400 /* Disable iSCSI if MAC configuration is
9401 * invalid.
9402 */
9403 if (!is_valid_ether_addr(iscsi_mac)) {
9404 bp->flags |= NO_ISCSI_FLAG;
9405 memset(iscsi_mac, 0, ETH_ALEN);
9406 }
9407
9408 /* Disable FCoE if MAC configuration is
9409 * invalid.
9410 */
9411 if (!is_valid_ether_addr(fip_mac)) {
9412 bp->flags |= NO_FCOE_FLAG;
9413 memset(bp->fip_mac, 0, ETH_ALEN);
9414 }
ec6ba945 9415#endif
619c5cb6
VZ		 9416
9417 if (!is_valid_ether_addr(bp->dev->dev_addr))
9418 dev_err(&bp->pdev->dev,
9419 "bad Ethernet MAC address configuration: "
9420 BNX2X_MAC_FMT", change it manually before bringing up "
9421 "the appropriate network interface\n",
9422 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
34f80b04
EG		 9423}
9424
9425static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9426{
0793f83f 9427 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 9428 int vn;
0793f83f 9429 u32 val = 0;
34f80b04 9430 int rc = 0;
a2fbb9ea 9431
34f80b04 9432 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 9433
6383c0b3
AE		 9434 /*
9435 * initialize IGU parameters
9436 */
f2e0899f
DK		 9437 if (CHIP_IS_E1x(bp)) {
9438 bp->common.int_block = INT_BLOCK_HC;
9439
9440 bp->igu_dsb_id = DEF_SB_IGU_ID;
9441 bp->igu_base_sb = 0;
f2e0899f
DK		 9442 } else {
9443 bp->common.int_block = INT_BLOCK_IGU;
7a06a122
DK		 9444
9445 /* do not allow device reset during IGU info preocessing */
9446 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9447
f2e0899f 9448 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 9449
9450 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9451 int tout = 5000;
9452
9453 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9454
9455 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9456 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9457 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9458
9459 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9460 tout--;
9461 usleep_range(1000, 1000);
9462 }
9463
9464 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9465 dev_err(&bp->pdev->dev,
9466 "FORCING Normal Mode failed!!!\n");
9467 return -EPERM;
9468 }
9469 }
9470
f2e0899f 9471 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 9472 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 9473 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9474 } else
619c5cb6 9475 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 9476
f2e0899f
DK		 9477 bnx2x_get_igu_cam_info(bp);
9478
7a06a122 9479 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
f2e0899f 9480 }
619c5cb6
VZ		 9481
9482 /*
9483 * set base FW non-default (fast path) status block id, this value is
9484 * used to initialize the fw_sb_id saved on the fp/queue structure to
9485 * determine the id used by the FW.
9486 */
9487 if (CHIP_IS_E1x(bp))
9488 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9489 else /*
9490 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9491 * the same queue are indicated on the same IGU SB). So we prefer
9492 * FW and IGU SBs to be the same value.
9493 */
9494 bp->base_fw_ndsb = bp->igu_base_sb;
9495
9496 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9497 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9498 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 9499
9500 /*
9501 * Initialize MF configuration
9502 */
523224a3 9503
fb3bff17
DK		 9504 bp->mf_ov = 0;
9505 bp->mf_mode = 0;
3395a033 9506 vn = BP_VN(bp);
0793f83f 9507
f2e0899f 9508 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 9509 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9510 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9511 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9512
f2e0899f
DK		 9513 if (SHMEM2_HAS(bp, mf_cfg_addr))
9514 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9515 else
9516 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 9517 offsetof(struct shmem_region, func_mb) +
9518 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 9519 /*
9520 * get mf configuration:
25985edc 9521 * 1. existence of MF configuration
0793f83f
DK		 9522 * 2. MAC address must be legal (check only upper bytes)
9523 * for Switch-Independent mode;
9524 * OVLAN must be legal for Switch-Dependent mode
9525 * 3. SF_MODE configures specific MF mode
9526 */
9527 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9528 /* get mf configuration */
9529 val = SHMEM_RD(bp,
9530 dev_info.shared_feature_config.config);
9531 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9532
9533 switch (val) {
9534 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9535 val = MF_CFG_RD(bp, func_mf_config[func].
9536 mac_upper);
9537 /* check for legal mac (upper bytes)*/
9538 if (val != 0xffff) {
9539 bp->mf_mode = MULTI_FUNCTION_SI;
9540 bp->mf_config[vn] = MF_CFG_RD(bp,
9541 func_mf_config[func].config);
9542 } else
619c5cb6
VZ		 9543 BNX2X_DEV_INFO("illegal MAC address "
9544 "for SI\n");
0793f83f
DK		 9545 break;
9546 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9547 /* get OV configuration */
9548 val = MF_CFG_RD(bp,
9549 func_mf_config[FUNC_0].e1hov_tag);
9550 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9551
9552 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9553 bp->mf_mode = MULTI_FUNCTION_SD;
9554 bp->mf_config[vn] = MF_CFG_RD(bp,
9555 func_mf_config[func].config);
9556 } else
754a2f52 9557 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 9558 break;
9559 default:
9560 /* Unknown configuration: reset mf_config */
9561 bp->mf_config[vn] = 0;
754a2f52 9562 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
0793f83f
DK		 9563 }
9564 }
a2fbb9ea 9565
2691d51d 9566 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 9567 IS_MF(bp) ? "multi" : "single");
2691d51d 9568
0793f83f
DK		 9569 switch (bp->mf_mode) {
9570 case MULTI_FUNCTION_SD:
9571 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9572 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 9573 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 9574 bp->mf_ov = val;
619c5cb6
VZ		 9575 bp->path_has_ovlan = true;
9576
9577 BNX2X_DEV_INFO("MF OV for func %d is %d "
9578 "(0x%04x)\n", func, bp->mf_ov,
9579 bp->mf_ov);
2691d51d 9580 } else {
619c5cb6
VZ		 9581 dev_err(&bp->pdev->dev,
9582 "No valid MF OV for func %d, "
9583 "aborting\n", func);
9584 return -EPERM;
34f80b04 9585 }
0793f83f
DK		 9586 break;
9587 case MULTI_FUNCTION_SI:
9588 BNX2X_DEV_INFO("func %d is in MF "
9589 "switch-independent mode\n", func);
9590 break;
9591 default:
9592 if (vn) {
619c5cb6
VZ		 9593 dev_err(&bp->pdev->dev,
9594 "VN %d is in a single function mode, "
9595 "aborting\n", vn);
9596 return -EPERM;
2691d51d 9597 }
0793f83f 9598 break;
34f80b04 9599 }
0793f83f 9600
619c5cb6
VZ		 9601 /* check if other port on the path needs ovlan:
9602 * Since MF configuration is shared between ports
9603 * Possible mixed modes are only
9604 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9605 */
9606 if (CHIP_MODE_IS_4_PORT(bp) &&
9607 !bp->path_has_ovlan &&
9608 !IS_MF(bp) &&
9609 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9610 u8 other_port = !BP_PORT(bp);
9611 u8 other_func = BP_PATH(bp) + 2*other_port;
9612 val = MF_CFG_RD(bp,
9613 func_mf_config[other_func].e1hov_tag);
9614 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9615 bp->path_has_ovlan = true;
9616 }
34f80b04 9617 }
a2fbb9ea 9618
f2e0899f
DK		 9619 /* adjust igu_sb_cnt to MF for E1x */
9620 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 9621 bp->igu_sb_cnt /= E1HVN_MAX;
9622
619c5cb6
VZ		 9623 /* port info */
9624 bnx2x_get_port_hwinfo(bp);
f2e0899f 9625
0793f83f
DK		 9626 /* Get MAC addresses */
9627 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 9628
2ba45142
VZ		 9629#ifdef BCM_CNIC
9630 bnx2x_get_cnic_info(bp);
9631#endif
9632
619c5cb6
VZ		 9633 /* Get current FW pulse sequence */
9634 if (!BP_NOMCP(bp)) {
9635 int mb_idx = BP_FW_MB_IDX(bp);
9636
9637 bp->fw_drv_pulse_wr_seq =
9638 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9639 DRV_PULSE_SEQ_MASK);
9640 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9641 }
9642
34f80b04
EG		 9643 return rc;
9644}
9645
34f24c7f
VZ		 9646static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9647{
9648 int cnt, i, block_end, rodi;
9649 char vpd_data[BNX2X_VPD_LEN+1];
9650 char str_id_reg[VENDOR_ID_LEN+1];
9651 char str_id_cap[VENDOR_ID_LEN+1];
9652 u8 len;
9653
9654 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9655 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9656
9657 if (cnt < BNX2X_VPD_LEN)
9658 goto out_not_found;
9659
9660 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9661 PCI_VPD_LRDT_RO_DATA);
9662 if (i < 0)
9663 goto out_not_found;
9664
9665
9666 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9667 pci_vpd_lrdt_size(&vpd_data[i]);
9668
9669 i += PCI_VPD_LRDT_TAG_SIZE;
9670
9671 if (block_end > BNX2X_VPD_LEN)
9672 goto out_not_found;
9673
9674 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9675 PCI_VPD_RO_KEYWORD_MFR_ID);
9676 if (rodi < 0)
9677 goto out_not_found;
9678
9679 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9680
9681 if (len != VENDOR_ID_LEN)
9682 goto out_not_found;
9683
9684 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9685
9686 /* vendor specific info */
9687 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9688 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9689 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9690 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9691
9692 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9693 PCI_VPD_RO_KEYWORD_VENDOR0);
9694 if (rodi >= 0) {
9695 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9696
9697 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9698
9699 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9700 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9701 bp->fw_ver[len] = ' ';
9702 }
9703 }
9704 return;
9705 }
9706out_not_found:
9707 return;
9708}
9709
619c5cb6
VZ		 9710static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9711{
9712 u32 flags = 0;
9713
9714 if (CHIP_REV_IS_FPGA(bp))
9715 SET_FLAGS(flags, MODE_FPGA);
9716 else if (CHIP_REV_IS_EMUL(bp))
9717 SET_FLAGS(flags, MODE_EMUL);
9718 else
9719 SET_FLAGS(flags, MODE_ASIC);
9720
9721 if (CHIP_MODE_IS_4_PORT(bp))
9722 SET_FLAGS(flags, MODE_PORT4);
9723 else
9724 SET_FLAGS(flags, MODE_PORT2);
9725
9726 if (CHIP_IS_E2(bp))
9727 SET_FLAGS(flags, MODE_E2);
9728 else if (CHIP_IS_E3(bp)) {
9729 SET_FLAGS(flags, MODE_E3);
9730 if (CHIP_REV(bp) == CHIP_REV_Ax)
9731 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 9732 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9733 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 9734 }
9735
9736 if (IS_MF(bp)) {
9737 SET_FLAGS(flags, MODE_MF);
9738 switch (bp->mf_mode) {
9739 case MULTI_FUNCTION_SD:
9740 SET_FLAGS(flags, MODE_MF_SD);
9741 break;
9742 case MULTI_FUNCTION_SI:
9743 SET_FLAGS(flags, MODE_MF_SI);
9744 break;
9745 }
9746 } else
9747 SET_FLAGS(flags, MODE_SF);
9748
9749#if defined(__LITTLE_ENDIAN)
9750 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9751#else /*(__BIG_ENDIAN)*/
9752 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9753#endif
9754 INIT_MODE_FLAGS(bp) = flags;
9755}
9756
34f80b04
EG		 9757static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9758{
f2e0899f 9759 int func;
87942b46 9760 int timer_interval;
34f80b04
EG		 9761 int rc;
9762
34f80b04 9763 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 9764 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 9765 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 9766#ifdef BCM_CNIC
9767 mutex_init(&bp->cnic_mutex);
9768#endif
a2fbb9ea 9769
1cf167f2 9770 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 9771 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 9772 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
34f80b04 9773 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 9774 if (rc)
9775 return rc;
34f80b04 9776
619c5cb6
VZ		 9777 bnx2x_set_modes_bitmap(bp);
9778
9779 rc = bnx2x_alloc_mem_bp(bp);
9780 if (rc)
9781 return rc;
523224a3 9782
34f24c7f 9783 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 9784
9785 func = BP_FUNC(bp);
9786
34f80b04
EG		 9787 /* need to reset chip if undi was active */
9788 if (!BP_NOMCP(bp))
9789 bnx2x_undi_unload(bp);
9790
0735f2fc
DK		 9791 /* init fw_seq after undi_unload! */
9792 if (!BP_NOMCP(bp)) {
9793 bp->fw_seq =
9794 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9795 DRV_MSG_SEQ_NUMBER_MASK);
9796 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9797 }
9798
34f80b04 9799 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 9800 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 9801
9802 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 9803 dev_err(&bp->pdev->dev, "MCP disabled, "
9804 "must load devices in order!\n");
34f80b04 9805
555f6c78 9806 bp->multi_mode = multi_mode;
555f6c78 9807
7a9b2557
VZ		 9808 /* Set TPA flags */
9809 if (disable_tpa) {
9810 bp->flags &= ~TPA_ENABLE_FLAG;
9811 bp->dev->features &= ~NETIF_F_LRO;
9812 } else {
9813 bp->flags |= TPA_ENABLE_FLAG;
9814 bp->dev->features |= NETIF_F_LRO;
9815 }
5d7cd496 9816 bp->disable_tpa = disable_tpa;
7a9b2557 9817
a18f5128
EG		 9818 if (CHIP_IS_E1(bp))
9819 bp->dropless_fc = 0;
9820 else
9821 bp->dropless_fc = dropless_fc;
9822
8d5726c4 9823 bp->mrrs = mrrs;
7a9b2557 9824
34f80b04 9825 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 9826
7d323bfd 9827 /* make sure that the numbers are in the right granularity */
523224a3
DK		 9828 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9829 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 9830
87942b46
EG		 9831 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9832 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 9833
9834 init_timer(&bp->timer);
9835 bp->timer.expires = jiffies + bp->current_interval;
9836 bp->timer.data = (unsigned long) bp;
9837 bp->timer.function = bnx2x_timer;
9838
785b9b1a 9839 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 9840 bnx2x_dcbx_init_params(bp);
9841
619c5cb6
VZ		 9842#ifdef BCM_CNIC
9843 if (CHIP_IS_E1x(bp))
9844 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9845 else
9846 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9847#endif
9848
6383c0b3
AE		 9849 /* multiple tx priority */
9850 if (CHIP_IS_E1x(bp))
9851 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9852 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9853 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9854 if (CHIP_IS_E3B0(bp))
9855 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9856
34f80b04 9857 return rc;
a2fbb9ea
ET		 9858}
9859
a2fbb9ea 9860
de0c62db
DK		 9861/****************************************************************************
9862* General service functions
9863****************************************************************************/
a2fbb9ea 9864
619c5cb6
VZ		 9865/*
9866 * net_device service functions
9867 */
9868
bb2a0f7a 9869/* called with rtnl_lock */
a2fbb9ea
ET		 9870static int bnx2x_open(struct net_device *dev)
9871{
9872 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 9873 bool global = false;
9874 int other_engine = BP_PATH(bp) ? 0 : 1;
9875 u32 other_load_counter, load_counter;
a2fbb9ea 9876
6eccabb3
EG		 9877 netif_carrier_off(dev);
9878
a2fbb9ea
ET		 9879 bnx2x_set_power_state(bp, PCI_D0);
9880
c9ee9206
VZ		 9881 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9882 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9883
9884 /*
9885 * If parity had happen during the unload, then attentions
9886 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9887 * want the first function loaded on the current engine to
9888 * complete the recovery.
9889 */
9890 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9891 bnx2x_chk_parity_attn(bp, &global, true))
72fd0718 9892 do {
c9ee9206
VZ		 9893 /*
9894 * If there are attentions and they are in a global
9895 * blocks, set the GLOBAL_RESET bit regardless whether
9896 * it will be this function that will complete the
9897 * recovery or not.
72fd0718 9898 */
c9ee9206
VZ		 9899 if (global)
9900 bnx2x_set_reset_global(bp);
72fd0718 9901
c9ee9206
VZ		 9902 /*
9903 * Only the first function on the current engine should
9904 * try to recover in open. In case of attentions in
9905 * global blocks only the first in the chip should try
9906 * to recover.
72fd0718 9907 */
c9ee9206
VZ		 9908 if ((!load_counter &&
9909 (!global || !other_load_counter)) &&
9910 bnx2x_trylock_leader_lock(bp) &&
9911 !bnx2x_leader_reset(bp)) {
9912 netdev_info(bp->dev, "Recovered in open\n");
72fd0718
VZ		 9913 break;
9914 }
9915
c9ee9206 9916 /* recovery has failed... */
72fd0718 9917 bnx2x_set_power_state(bp, PCI_D3hot);
c9ee9206 9918 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 9919
c9ee9206 9920 netdev_err(bp->dev, "Recovery flow hasn't been properly"
72fd0718
VZ		 9921 " completed yet. Try again later. If u still see this"
9922 " message after a few retries then power cycle is"
c9ee9206 9923 " required.\n");
72fd0718
VZ		 9924
9925 return -EAGAIN;
9926 } while (0);
72fd0718
VZ		 9927
9928 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 9929 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 9930}
9931
bb2a0f7a 9932/* called with rtnl_lock */
a2fbb9ea
ET		 9933static int bnx2x_close(struct net_device *dev)
9934{
a2fbb9ea
ET		 9935 struct bnx2x *bp = netdev_priv(dev);
9936
9937 /* Unload the driver, release IRQs */
bb2a0f7a 9938 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
c9ee9206
VZ		 9939
9940 /* Power off */
d3dbfee0 9941 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 9942
9943 return 0;
9944}
9945
619c5cb6
VZ		 9946static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9947 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 9948{
619c5cb6
VZ		 9949 int mc_count = netdev_mc_count(bp->dev);
9950 struct bnx2x_mcast_list_elem *mc_mac =
9951 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9952 struct netdev_hw_addr *ha;
6e30dd4e 9953
619c5cb6
VZ		 9954 if (!mc_mac)
9955 return -ENOMEM;
6e30dd4e 9956
619c5cb6 9957 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 9958
619c5cb6
VZ		 9959 netdev_for_each_mc_addr(ha, bp->dev) {
9960 mc_mac->mac = bnx2x_mc_addr(ha);
9961 list_add_tail(&mc_mac->link, &p->mcast_list);
9962 mc_mac++;
6e30dd4e 9963 }
619c5cb6
VZ		 9964
9965 p->mcast_list_len = mc_count;
9966
9967 return 0;
6e30dd4e
VZ		 9968}
9969
619c5cb6
VZ		 9970static inline void bnx2x_free_mcast_macs_list(
9971 struct bnx2x_mcast_ramrod_params *p)
9972{
9973 struct bnx2x_mcast_list_elem *mc_mac =
9974 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9975 link);
9976
9977 WARN_ON(!mc_mac);
9978 kfree(mc_mac);
9979}
9980
9981/**
9982 * bnx2x_set_uc_list - configure a new unicast MACs list.
9983 *
9984 * @bp: driver handle
6e30dd4e 9985 *
619c5cb6 9986 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 9987 */
619c5cb6 9988static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 9989{
619c5cb6 9990 int rc;
6e30dd4e 9991 struct net_device *dev = bp->dev;
6e30dd4e 9992 struct netdev_hw_addr *ha;
619c5cb6
VZ		 9993 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9994 unsigned long ramrod_flags = 0;
6e30dd4e 9995
619c5cb6
VZ		 9996 /* First schedule a cleanup up of old configuration */
9997 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9998 if (rc < 0) {
9999 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10000 return rc;
10001 }
6e30dd4e
VZ		 10002
10003 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 10004 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10005 BNX2X_UC_LIST_MAC, &ramrod_flags);
10006 if (rc < 0) {
10007 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10008 rc);
10009 return rc;
6e30dd4e
VZ		 10010 }
10011 }
10012
619c5cb6
VZ		 10013 /* Execute the pending commands */
10014 __set_bit(RAMROD_CONT, &ramrod_flags);
10015 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10016 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 10017}
10018
619c5cb6 10019static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 10020{
619c5cb6
VZ		 10021 struct net_device *dev = bp->dev;
10022 struct bnx2x_mcast_ramrod_params rparam = {0};
10023 int rc = 0;
6e30dd4e 10024
619c5cb6 10025 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 10026
619c5cb6
VZ		 10027 /* first, clear all configured multicast MACs */
10028 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10029 if (rc < 0) {
10030 BNX2X_ERR("Failed to clear multicast "
10031 "configuration: %d\n", rc);
10032 return rc;
10033 }
6e30dd4e 10034
619c5cb6
VZ		 10035 /* then, configure a new MACs list */
10036 if (netdev_mc_count(dev)) {
10037 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10038 if (rc) {
10039 BNX2X_ERR("Failed to create multicast MACs "
10040 "list: %d\n", rc);
10041 return rc;
10042 }
6e30dd4e 10043
619c5cb6
VZ		 10044 /* Now add the new MACs */
10045 rc = bnx2x_config_mcast(bp, &rparam,
10046 BNX2X_MCAST_CMD_ADD);
10047 if (rc < 0)
10048 BNX2X_ERR("Failed to set a new multicast "
10049 "configuration: %d\n", rc);
6e30dd4e 10050
619c5cb6
VZ		 10051 bnx2x_free_mcast_macs_list(&rparam);
10052 }
6e30dd4e 10053
619c5cb6 10054 return rc;
6e30dd4e
VZ		 10055}
10056
6e30dd4e 10057
619c5cb6 10058/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 10059void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 10060{
10061 struct bnx2x *bp = netdev_priv(dev);
10062 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 10063
10064 if (bp->state != BNX2X_STATE_OPEN) {
10065 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10066 return;
10067 }
10068
619c5cb6 10069 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 10070
10071 if (dev->flags & IFF_PROMISC)
10072 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 10073 else if ((dev->flags & IFF_ALLMULTI) ||
10074 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10075 CHIP_IS_E1(bp)))
34f80b04 10076 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 10077 else {
10078 /* some multicasts */
619c5cb6 10079 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 10080 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 10081
619c5cb6 10082 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 10083 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 10084 }
10085
10086 bp->rx_mode = rx_mode;
619c5cb6
VZ		 10087
10088 /* Schedule the rx_mode command */
10089 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10090 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10091 return;
10092 }
10093
34f80b04
EG		 10094 bnx2x_set_storm_rx_mode(bp);
10095}
10096
c18487ee 10097/* called with rtnl_lock */
01cd4528
EG		 10098static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10099 int devad, u16 addr)
a2fbb9ea 10100{
01cd4528
EG		 10101 struct bnx2x *bp = netdev_priv(netdev);
10102 u16 value;
10103 int rc;
a2fbb9ea 10104
01cd4528
EG		 10105 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10106 prtad, devad, addr);
a2fbb9ea 10107
01cd4528
EG		 10108 /* The HW expects different devad if CL22 is used */
10109 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 10110
01cd4528 10111 bnx2x_acquire_phy_lock(bp);
e10bc84d 10112 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 10113 bnx2x_release_phy_lock(bp);
10114 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 10115
01cd4528
EG		 10116 if (!rc)
10117 rc = value;
10118 return rc;
10119}
a2fbb9ea 10120
01cd4528
EG		 10121/* called with rtnl_lock */
10122static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10123 u16 addr, u16 value)
10124{
10125 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 10126 int rc;
10127
10128 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10129 " value 0x%x\n", prtad, devad, addr, value);
10130
01cd4528
EG		 10131 /* The HW expects different devad if CL22 is used */
10132 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 10133
01cd4528 10134 bnx2x_acquire_phy_lock(bp);
e10bc84d 10135 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 10136 bnx2x_release_phy_lock(bp);
10137 return rc;
10138}
c18487ee 10139
01cd4528
EG		 10140/* called with rtnl_lock */
10141static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10142{
10143 struct bnx2x *bp = netdev_priv(dev);
10144 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 10145
01cd4528
EG		 10146 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10147 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 10148
01cd4528
EG		 10149 if (!netif_running(dev))
10150 return -EAGAIN;
10151
10152 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 10153}
10154
257ddbda 10155#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 10156static void poll_bnx2x(struct net_device *dev)
10157{
10158 struct bnx2x *bp = netdev_priv(dev);
10159
10160 disable_irq(bp->pdev->irq);
10161 bnx2x_interrupt(bp->pdev->irq, dev);
10162 enable_irq(bp->pdev->irq);
10163}
10164#endif
10165
c64213cd
SH		 10166static const struct net_device_ops bnx2x_netdev_ops = {
10167 .ndo_open = bnx2x_open,
10168 .ndo_stop = bnx2x_close,
10169 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 10170 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 10171 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd
SH		 10172 .ndo_set_mac_address = bnx2x_change_mac_addr,
10173 .ndo_validate_addr = eth_validate_addr,
10174 .ndo_do_ioctl = bnx2x_ioctl,
10175 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 10176 .ndo_fix_features = bnx2x_fix_features,
10177 .ndo_set_features = bnx2x_set_features,
c64213cd 10178 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 10179#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 10180 .ndo_poll_controller = poll_bnx2x,
10181#endif
6383c0b3
AE		 10182 .ndo_setup_tc = bnx2x_setup_tc,
10183
bf61ee14
VZ		 10184#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10185 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10186#endif
c64213cd
SH		 10187};
10188
619c5cb6
VZ		 10189static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10190{
10191 struct device *dev = &bp->pdev->dev;
10192
10193 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10194 bp->flags |= USING_DAC_FLAG;
10195 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10196 dev_err(dev, "dma_set_coherent_mask failed, "
10197 "aborting\n");
10198 return -EIO;
10199 }
10200 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10201 dev_err(dev, "System does not support DMA, aborting\n");
10202 return -EIO;
10203 }
10204
10205 return 0;
10206}
10207
34f80b04 10208static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 10209 struct net_device *dev,
10210 unsigned long board_type)
a2fbb9ea
ET		 10211{
10212 struct bnx2x *bp;
10213 int rc;
10214
10215 SET_NETDEV_DEV(dev, &pdev->dev);
10216 bp = netdev_priv(dev);
10217
34f80b04
EG		 10218 bp->dev = dev;
10219 bp->pdev = pdev;
a2fbb9ea 10220 bp->flags = 0;
f2e0899f 10221 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 10222
10223 rc = pci_enable_device(pdev);
10224 if (rc) {
cdaa7cb8
VZ		 10225 dev_err(&bp->pdev->dev,
10226 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 10227 goto err_out;
10228 }
10229
10230 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10231 dev_err(&bp->pdev->dev,
10232 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 10233 rc = -ENODEV;
10234 goto err_out_disable;
10235 }
10236
10237 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10238 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10239 " base address, aborting\n");
a2fbb9ea
ET		 10240 rc = -ENODEV;
10241 goto err_out_disable;
10242 }
10243
34f80b04
EG		 10244 if (atomic_read(&pdev->enable_cnt) == 1) {
10245 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10246 if (rc) {
cdaa7cb8
VZ		 10247 dev_err(&bp->pdev->dev,
10248 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 10249 goto err_out_disable;
10250 }
a2fbb9ea 10251
34f80b04
EG		 10252 pci_set_master(pdev);
10253 pci_save_state(pdev);
10254 }
a2fbb9ea
ET		 10255
10256 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10257 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 10258 dev_err(&bp->pdev->dev,
10259 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 10260 rc = -EIO;
10261 goto err_out_release;
10262 }
10263
77c98e6a
JM		 10264 if (!pci_is_pcie(pdev)) {
10265 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 10266 rc = -EIO;
10267 goto err_out_release;
10268 }
10269
619c5cb6
VZ		 10270 rc = bnx2x_set_coherency_mask(bp);
10271 if (rc)
a2fbb9ea 10272 goto err_out_release;
a2fbb9ea 10273
34f80b04
EG		 10274 dev->mem_start = pci_resource_start(pdev, 0);
10275 dev->base_addr = dev->mem_start;
10276 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 10277
10278 dev->irq = pdev->irq;
10279
275f165f 10280 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 10281 if (!bp->regview) {
cdaa7cb8
VZ		 10282 dev_err(&bp->pdev->dev,
10283 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 10284 rc = -ENOMEM;
10285 goto err_out_release;
10286 }
10287
a2fbb9ea
ET		 10288 bnx2x_set_power_state(bp, PCI_D0);
10289
34f80b04
EG		 10290 /* clean indirect addresses */
10291 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10292 PCICFG_VENDOR_ID_OFFSET);
9f0096a1
DK		 10293 /* Clean the following indirect addresses for all functions since it
10294 * is not used by the driver.
10295 */
10296 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10297 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10298 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10299 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10300 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10301 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10302 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10303 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
a2fbb9ea 10304
2189400b 10305 /*
619c5cb6 10306 * Enable internal target-read (in case we are probed after PF FLR).
2189400b 10307 * Must be done prior to any BAR read access. Only for 57712 and up
619c5cb6 10308 */
2189400b
SR		 10309 if (board_type != BCM57710 &&
10310 board_type != BCM57711 &&
10311 board_type != BCM57711E)
10312 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
619c5cb6 10313
72fd0718
VZ		 10314 /* Reset the load counter */
10315 bnx2x_clear_load_cnt(bp);
10316
34f80b04 10317 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 10318
c64213cd 10319 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 10320 bnx2x_set_ethtool_ops(dev);
5316bc0b 10321
66371c44
MM		 10322 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10323 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10324 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10325
10326 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10327 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10328
10329 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 10330 if (bp->flags & USING_DAC_FLAG)
66371c44 10331 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 10332
538dd2e3
MB		 10333 /* Add Loopback capability to the device */
10334 dev->hw_features |= NETIF_F_LOOPBACK;
10335
98507672 10336#ifdef BCM_DCBNL
785b9b1a
SR		 10337 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10338#endif
10339
01cd4528
EG		 10340 /* get_port_hwinfo() will set prtad and mmds properly */
10341 bp->mdio.prtad = MDIO_PRTAD_NONE;
10342 bp->mdio.mmds = 0;
10343 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10344 bp->mdio.dev = dev;
10345 bp->mdio.mdio_read = bnx2x_mdio_read;
10346 bp->mdio.mdio_write = bnx2x_mdio_write;
10347
a2fbb9ea
ET		 10348 return 0;
10349
a2fbb9ea 10350err_out_release:
34f80b04
EG		 10351 if (atomic_read(&pdev->enable_cnt) == 1)
10352 pci_release_regions(pdev);
a2fbb9ea
ET		 10353
10354err_out_disable:
10355 pci_disable_device(pdev);
10356 pci_set_drvdata(pdev, NULL);
10357
10358err_out:
10359 return rc;
10360}
10361
37f9ce62
EG		 10362static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10363 int *width, int *speed)
25047950
ET		 10364{
10365 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10366
37f9ce62 10367 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 10368
37f9ce62
EG		 10369 /* return value of 1=2.5GHz 2=5GHz */
10370 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 10371}
37f9ce62 10372
6891dd25 10373static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 10374{
37f9ce62 10375 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 10376 struct bnx2x_fw_file_hdr *fw_hdr;
10377 struct bnx2x_fw_file_section *sections;
94a78b79 10378 u32 offset, len, num_ops;
37f9ce62 10379 u16 *ops_offsets;
94a78b79 10380 int i;
37f9ce62 10381 const u8 *fw_ver;
94a78b79
VZ		 10382
10383 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10384 return -EINVAL;
10385
10386 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10387 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10388
10389 /* Make sure none of the offsets and sizes make us read beyond
10390 * the end of the firmware data */
10391 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10392 offset = be32_to_cpu(sections[i].offset);
10393 len = be32_to_cpu(sections[i].len);
10394 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 10395 dev_err(&bp->pdev->dev,
10396 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 10397 return -EINVAL;
10398 }
10399 }
10400
10401 /* Likewise for the init_ops offsets */
10402 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10403 ops_offsets = (u16 *)(firmware->data + offset);
10404 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10405
10406 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10407 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 10408 dev_err(&bp->pdev->dev,
10409 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 10410 return -EINVAL;
10411 }
10412 }
10413
10414 /* Check FW version */
10415 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10416 fw_ver = firmware->data + offset;
10417 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10418 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10419 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10420 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 10421 dev_err(&bp->pdev->dev,
10422 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 10423 fw_ver[0], fw_ver[1], fw_ver[2],
10424 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10425 BCM_5710_FW_MINOR_VERSION,
10426 BCM_5710_FW_REVISION_VERSION,
10427 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 10428 return -EINVAL;
94a78b79
VZ		 10429 }
10430
10431 return 0;
10432}
10433
ab6ad5a4 10434static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10435{
ab6ad5a4
EG		 10436 const __be32 *source = (const __be32 *)_source;
10437 u32 *target = (u32 *)_target;
94a78b79 10438 u32 i;
94a78b79
VZ		 10439
10440 for (i = 0; i < n/4; i++)
10441 target[i] = be32_to_cpu(source[i]);
10442}
10443
10444/*
10445 Ops array is stored in the following format:
10446 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10447 */
ab6ad5a4 10448static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 10449{
ab6ad5a4
EG		 10450 const __be32 *source = (const __be32 *)_source;
10451 struct raw_op *target = (struct raw_op *)_target;
94a78b79 10452 u32 i, j, tmp;
94a78b79 10453
ab6ad5a4 10454 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 10455 tmp = be32_to_cpu(source[j]);
10456 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 10457 target[i].offset = tmp & 0xffffff;
10458 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 10459 }
10460}
ab6ad5a4 10461
523224a3
DK		 10462/**
10463 * IRO array is stored in the following format:
10464 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10465 */
10466static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10467{
10468 const __be32 *source = (const __be32 *)_source;
10469 struct iro *target = (struct iro *)_target;
10470 u32 i, j, tmp;
10471
10472 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10473 target[i].base = be32_to_cpu(source[j]);
10474 j++;
10475 tmp = be32_to_cpu(source[j]);
10476 target[i].m1 = (tmp >> 16) & 0xffff;
10477 target[i].m2 = tmp & 0xffff;
10478 j++;
10479 tmp = be32_to_cpu(source[j]);
10480 target[i].m3 = (tmp >> 16) & 0xffff;
10481 target[i].size = tmp & 0xffff;
10482 j++;
10483 }
10484}
10485
ab6ad5a4 10486static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10487{
ab6ad5a4
EG		 10488 const __be16 *source = (const __be16 *)_source;
10489 u16 *target = (u16 *)_target;
94a78b79 10490 u32 i;
94a78b79
VZ		 10491
10492 for (i = 0; i < n/2; i++)
10493 target[i] = be16_to_cpu(source[i]);
10494}
10495
7995c64e
JP		 10496#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10497do { \
10498 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10499 bp->arr = kmalloc(len, GFP_KERNEL); \
10500 if (!bp->arr) { \
10501 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10502 goto lbl; \
10503 } \
10504 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10505 (u8 *)bp->arr, len); \
10506} while (0)
94a78b79 10507
6891dd25 10508int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 10509{
45229b42 10510 const char *fw_file_name;
94a78b79 10511 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 10512 int rc;
94a78b79 10513
94a78b79 10514 if (CHIP_IS_E1(bp))
45229b42 10515 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 10516 else if (CHIP_IS_E1H(bp))
45229b42 10517 fw_file_name = FW_FILE_NAME_E1H;
619c5cb6 10518 else if (!CHIP_IS_E1x(bp))
f2e0899f 10519 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 10520 else {
6891dd25 10521 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 10522 return -EINVAL;
10523 }
94a78b79 10524
6891dd25 10525 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 10526
6891dd25 10527 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 10528 if (rc) {
6891dd25 10529 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 10530 goto request_firmware_exit;
10531 }
10532
10533 rc = bnx2x_check_firmware(bp);
10534 if (rc) {
6891dd25 10535 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 10536 goto request_firmware_exit;
10537 }
10538
10539 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10540
10541 /* Initialize the pointers to the init arrays */
10542 /* Blob */
10543 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10544
10545 /* Opcodes */
10546 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10547
10548 /* Offsets */
ab6ad5a4
EG		 10549 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10550 be16_to_cpu_n);
94a78b79
VZ		 10551
10552 /* STORMs firmware */
573f2035
EG		 10553 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10554 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10555 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10556 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10557 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10558 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10559 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10560 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10561 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10562 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10563 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10564 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10565 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10566 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10567 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10568 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 10569 /* IRO */
10570 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 10571
10572 return 0;
ab6ad5a4 10573
523224a3
DK		 10574iro_alloc_err:
10575 kfree(bp->init_ops_offsets);
94a78b79
VZ		 10576init_offsets_alloc_err:
10577 kfree(bp->init_ops);
10578init_ops_alloc_err:
10579 kfree(bp->init_data);
10580request_firmware_exit:
10581 release_firmware(bp->firmware);
10582
10583 return rc;
10584}
10585
619c5cb6
VZ		 10586static void bnx2x_release_firmware(struct bnx2x *bp)
10587{
10588 kfree(bp->init_ops_offsets);
10589 kfree(bp->init_ops);
10590 kfree(bp->init_data);
10591 release_firmware(bp->firmware);
10592}
10593
10594
10595static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10596 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10597 .init_hw_cmn = bnx2x_init_hw_common,
10598 .init_hw_port = bnx2x_init_hw_port,
10599 .init_hw_func = bnx2x_init_hw_func,
10600
10601 .reset_hw_cmn = bnx2x_reset_common,
10602 .reset_hw_port = bnx2x_reset_port,
10603 .reset_hw_func = bnx2x_reset_func,
10604
10605 .gunzip_init = bnx2x_gunzip_init,
10606 .gunzip_end = bnx2x_gunzip_end,
10607
10608 .init_fw = bnx2x_init_firmware,
10609 .release_fw = bnx2x_release_firmware,
10610};
10611
10612void bnx2x__init_func_obj(struct bnx2x *bp)
10613{
10614 /* Prepare DMAE related driver resources */
10615 bnx2x_setup_dmae(bp);
10616
10617 bnx2x_init_func_obj(bp, &bp->func_obj,
10618 bnx2x_sp(bp, func_rdata),
10619 bnx2x_sp_mapping(bp, func_rdata),
10620 &bnx2x_func_sp_drv);
10621}
10622
10623/* must be called after sriov-enable */
6383c0b3 10624static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 10625{
6383c0b3 10626 int cid_count = BNX2X_L2_CID_COUNT(bp);
94a78b79 10627
523224a3
DK		 10628#ifdef BCM_CNIC
10629 cid_count += CNIC_CID_MAX;
10630#endif
10631 return roundup(cid_count, QM_CID_ROUND);
10632}
f85582f8 10633
619c5cb6 10634/**
6383c0b3 10635 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 10636 *
10637 * @dev: pci device
10638 *
10639 */
6383c0b3 10640static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
619c5cb6
VZ		 10641{
10642 int pos;
10643 u16 control;
10644
10645 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 10646
10647 /*
10648 * If MSI-X is not supported - return number of SBs needed to support
10649 * one fast path queue: one FP queue + SB for CNIC
10650 */
619c5cb6 10651 if (!pos)
6383c0b3 10652 return 1 + CNIC_PRESENT;
619c5cb6 10653
6383c0b3
AE		 10654 /*
10655 * The value in the PCI configuration space is the index of the last
10656 * entry, namely one less than the actual size of the table, which is
10657 * exactly what we want to return from this function: number of all SBs
10658 * without the default SB.
10659 */
619c5cb6 10660 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
6383c0b3 10661 return control & PCI_MSIX_FLAGS_QSIZE;
619c5cb6
VZ		 10662}
10663
a2fbb9ea
ET		 10664static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10665 const struct pci_device_id *ent)
10666{
a2fbb9ea
ET		 10667 struct net_device *dev = NULL;
10668 struct bnx2x *bp;
37f9ce62 10669 int pcie_width, pcie_speed;
6383c0b3
AE		 10670 int rc, max_non_def_sbs;
10671 int rx_count, tx_count, rss_count;
10672 /*
10673 * An estimated maximum supported CoS number according to the chip
10674 * version.
10675 * We will try to roughly estimate the maximum number of CoSes this chip
10676 * may support in order to minimize the memory allocated for Tx
10677 * netdev_queue's. This number will be accurately calculated during the
10678 * initialization of bp->max_cos based on the chip versions AND chip
10679 * revision in the bnx2x_init_bp().
10680 */
10681 u8 max_cos_est = 0;
523224a3 10682
f2e0899f
DK		 10683 switch (ent->driver_data) {
10684 case BCM57710:
10685 case BCM57711:
10686 case BCM57711E:
6383c0b3
AE		 10687 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10688 break;
10689
f2e0899f 10690 case BCM57712:
619c5cb6 10691 case BCM57712_MF:
6383c0b3
AE		 10692 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10693 break;
10694
619c5cb6
VZ		 10695 case BCM57800:
10696 case BCM57800_MF:
10697 case BCM57810:
10698 case BCM57810_MF:
10699 case BCM57840:
10700 case BCM57840_MF:
6383c0b3 10701 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
f2e0899f 10702 break;
a2fbb9ea 10703
f2e0899f
DK		 10704 default:
10705 pr_err("Unknown board_type (%ld), aborting\n",
10706 ent->driver_data);
870634b0 10707 return -ENODEV;
f2e0899f
DK		 10708 }
10709
6383c0b3
AE		 10710 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10711
10712 /* !!! FIXME !!!
10713 * Do not allow the maximum SB count to grow above 16
10714 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10715 * We will use the FP_SB_MAX_E1x macro for this matter.
10716 */
10717 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10718
10719 WARN_ON(!max_non_def_sbs);
10720
10721 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10722 rss_count = max_non_def_sbs - CNIC_PRESENT;
10723
10724 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10725 rx_count = rss_count + FCOE_PRESENT;
10726
10727 /*
10728 * Maximum number of netdev Tx queues:
10729 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10730 */
10731 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
f85582f8 10732
a2fbb9ea 10733 /* dev zeroed in init_etherdev */
6383c0b3 10734 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
34f80b04 10735 if (!dev) {
cdaa7cb8 10736 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 10737 return -ENOMEM;
34f80b04 10738 }
a2fbb9ea 10739
a2fbb9ea 10740 bp = netdev_priv(dev);
a2fbb9ea 10741
6383c0b3
AE		 10742 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10743 tx_count, rx_count);
df4770de 10744
6383c0b3
AE		 10745 bp->igu_sb_cnt = max_non_def_sbs;
10746 bp->msg_enable = debug;
10747 pci_set_drvdata(pdev, dev);
523224a3 10748
619c5cb6 10749 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 10750 if (rc < 0) {
10751 free_netdev(dev);
10752 return rc;
10753 }
10754
6383c0b3 10755 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
619c5cb6 10756
34f80b04 10757 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 10758 if (rc)
10759 goto init_one_exit;
10760
6383c0b3
AE		 10761 /*
10762 * Map doorbels here as we need the real value of bp->max_cos which
10763 * is initialized in bnx2x_init_bp().
10764 */
10765 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10766 min_t(u64, BNX2X_DB_SIZE(bp),
10767 pci_resource_len(pdev, 2)));
10768 if (!bp->doorbells) {
10769 dev_err(&bp->pdev->dev,
10770 "Cannot map doorbell space, aborting\n");
10771 rc = -ENOMEM;
10772 goto init_one_exit;
10773 }
10774
523224a3 10775 /* calc qm_cid_count */
6383c0b3 10776 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
523224a3 10777
ec6ba945 10778#ifdef BCM_CNIC
928ad22a
DK		 10779 /* disable FCOE L2 queue for E1x and E3*/
10780 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
ec6ba945
VZ		 10781 bp->flags |= NO_FCOE_FLAG;
10782
10783#endif
10784
25985edc 10785 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 10786 * needed, set bp->num_queues appropriately.
10787 */
10788 bnx2x_set_int_mode(bp);
10789
10790 /* Add all NAPI objects */
10791 bnx2x_add_all_napi(bp);
10792
b340007f
VZ		 10793 rc = register_netdev(dev);
10794 if (rc) {
10795 dev_err(&pdev->dev, "Cannot register net device\n");
10796 goto init_one_exit;
10797 }
10798
ec6ba945
VZ		 10799#ifdef BCM_CNIC
10800 if (!NO_FCOE(bp)) {
10801 /* Add storage MAC address */
10802 rtnl_lock();
10803 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10804 rtnl_unlock();
10805 }
10806#endif
10807
37f9ce62 10808 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 10809
cdaa7cb8
VZ		 10810 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10811 " IRQ %d, ", board_info[ent->driver_data].name,
10812 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 10813 pcie_width,
10814 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10815 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10816 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 10817 dev->base_addr, bp->pdev->irq);
10818 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 10819
a2fbb9ea 10820 return 0;
34f80b04
EG		 10821
10822init_one_exit:
10823 if (bp->regview)
10824 iounmap(bp->regview);
10825
10826 if (bp->doorbells)
10827 iounmap(bp->doorbells);
10828
10829 free_netdev(dev);
10830
10831 if (atomic_read(&pdev->enable_cnt) == 1)
10832 pci_release_regions(pdev);
10833
10834 pci_disable_device(pdev);
10835 pci_set_drvdata(pdev, NULL);
10836
10837 return rc;
a2fbb9ea
ET		 10838}
10839
10840static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10841{
10842 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 10843 struct bnx2x *bp;
10844
10845 if (!dev) {
cdaa7cb8 10846 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 10847 return;
10848 }
228241eb 10849 bp = netdev_priv(dev);
a2fbb9ea 10850
ec6ba945
VZ		 10851#ifdef BCM_CNIC
10852 /* Delete storage MAC address */
10853 if (!NO_FCOE(bp)) {
10854 rtnl_lock();
10855 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10856 rtnl_unlock();
10857 }
10858#endif
10859
98507672
SR		 10860#ifdef BCM_DCBNL
10861 /* Delete app tlvs from dcbnl */
10862 bnx2x_dcbnl_update_applist(bp, true);
10863#endif
10864
a2fbb9ea
ET		 10865 unregister_netdev(dev);
10866
d6214d7a
DK		 10867 /* Delete all NAPI objects */
10868 bnx2x_del_all_napi(bp);
10869
084d6cbb
VZ		 10870 /* Power on: we can't let PCI layer write to us while we are in D3 */
10871 bnx2x_set_power_state(bp, PCI_D0);
10872
d6214d7a
DK		 10873 /* Disable MSI/MSI-X */
10874 bnx2x_disable_msi(bp);
f85582f8 10875
084d6cbb
VZ		 10876 /* Power off */
10877 bnx2x_set_power_state(bp, PCI_D3hot);
10878
72fd0718 10879 /* Make sure RESET task is not scheduled before continuing */
7be08a72 10880 cancel_delayed_work_sync(&bp->sp_rtnl_task);
72fd0718 10881
a2fbb9ea
ET		 10882 if (bp->regview)
10883 iounmap(bp->regview);
10884
10885 if (bp->doorbells)
10886 iounmap(bp->doorbells);
10887
523224a3
DK		 10888 bnx2x_free_mem_bp(bp);
10889
a2fbb9ea 10890 free_netdev(dev);
34f80b04
EG		 10891
10892 if (atomic_read(&pdev->enable_cnt) == 1)
10893 pci_release_regions(pdev);
10894
a2fbb9ea
ET		 10895 pci_disable_device(pdev);
10896 pci_set_drvdata(pdev, NULL);
10897}
10898
f8ef6e44
YG		 10899static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10900{
10901 int i;
10902
10903 bp->state = BNX2X_STATE_ERROR;
10904
10905 bp->rx_mode = BNX2X_RX_MODE_NONE;
10906
619c5cb6
VZ		 10907#ifdef BCM_CNIC
10908 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10909#endif
10910 /* Stop Tx */
10911 bnx2x_tx_disable(bp);
10912
f8ef6e44
YG		 10913 bnx2x_netif_stop(bp, 0);
10914
10915 del_timer_sync(&bp->timer);
619c5cb6
VZ		 10916
10917 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 10918
10919 /* Release IRQs */
d6214d7a 10920 bnx2x_free_irq(bp);
f8ef6e44 10921
f8ef6e44
YG		 10922 /* Free SKBs, SGEs, TPA pool and driver internals */
10923 bnx2x_free_skbs(bp);
523224a3 10924
ec6ba945 10925 for_each_rx_queue(bp, i)
f8ef6e44 10926 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 10927
f8ef6e44
YG		 10928 bnx2x_free_mem(bp);
10929
10930 bp->state = BNX2X_STATE_CLOSED;
10931
619c5cb6
VZ		 10932 netif_carrier_off(bp->dev);
10933
f8ef6e44
YG		 10934 return 0;
10935}
10936
10937static void bnx2x_eeh_recover(struct bnx2x *bp)
10938{
10939 u32 val;
10940
10941 mutex_init(&bp->port.phy_mutex);
10942
10943 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10944 bp->link_params.shmem_base = bp->common.shmem_base;
10945 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10946
10947 if (!bp->common.shmem_base ||
10948 (bp->common.shmem_base < 0xA0000) ||
10949 (bp->common.shmem_base >= 0xC0000)) {
10950 BNX2X_DEV_INFO("MCP not active\n");
10951 bp->flags |= NO_MCP_FLAG;
10952 return;
10953 }
10954
10955 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10956 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10957 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10958 BNX2X_ERR("BAD MCP validity signature\n");
10959
10960 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 10961 bp->fw_seq =
10962 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10963 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 10964 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10965 }
10966}
10967
493adb1f
WX		 10968/**
10969 * bnx2x_io_error_detected - called when PCI error is detected
10970 * @pdev: Pointer to PCI device
10971 * @state: The current pci connection state
10972 *
10973 * This function is called after a PCI bus error affecting
10974 * this device has been detected.
10975 */
10976static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10977 pci_channel_state_t state)
10978{
10979 struct net_device *dev = pci_get_drvdata(pdev);
10980 struct bnx2x *bp = netdev_priv(dev);
10981
10982 rtnl_lock();
10983
10984 netif_device_detach(dev);
10985
07ce50e4
DN		 10986 if (state == pci_channel_io_perm_failure) {
10987 rtnl_unlock();
10988 return PCI_ERS_RESULT_DISCONNECT;
10989 }
10990
493adb1f 10991 if (netif_running(dev))
f8ef6e44 10992 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 10993
10994 pci_disable_device(pdev);
10995
10996 rtnl_unlock();
10997
10998 /* Request a slot reset */
10999 return PCI_ERS_RESULT_NEED_RESET;
11000}
11001
11002/**
11003 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11004 * @pdev: Pointer to PCI device
11005 *
11006 * Restart the card from scratch, as if from a cold-boot.
11007 */
11008static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11009{
11010 struct net_device *dev = pci_get_drvdata(pdev);
11011 struct bnx2x *bp = netdev_priv(dev);
11012
11013 rtnl_lock();
11014
11015 if (pci_enable_device(pdev)) {
11016 dev_err(&pdev->dev,
11017 "Cannot re-enable PCI device after reset\n");
11018 rtnl_unlock();
11019 return PCI_ERS_RESULT_DISCONNECT;
11020 }
11021
11022 pci_set_master(pdev);
11023 pci_restore_state(pdev);
11024
11025 if (netif_running(dev))
11026 bnx2x_set_power_state(bp, PCI_D0);
11027
11028 rtnl_unlock();
11029
11030 return PCI_ERS_RESULT_RECOVERED;
11031}
11032
11033/**
11034 * bnx2x_io_resume - called when traffic can start flowing again
11035 * @pdev: Pointer to PCI device
11036 *
11037 * This callback is called when the error recovery driver tells us that
11038 * its OK to resume normal operation.
11039 */
11040static void bnx2x_io_resume(struct pci_dev *pdev)
11041{
11042 struct net_device *dev = pci_get_drvdata(pdev);
11043 struct bnx2x *bp = netdev_priv(dev);
11044
72fd0718 11045 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
754a2f52
DK		 11046 netdev_err(bp->dev, "Handling parity error recovery. "
11047 "Try again later\n");
72fd0718
VZ		 11048 return;
11049 }
11050
493adb1f
WX		 11051 rtnl_lock();
11052
f8ef6e44
YG		 11053 bnx2x_eeh_recover(bp);
11054
493adb1f 11055 if (netif_running(dev))
f8ef6e44 11056 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 11057
11058 netif_device_attach(dev);
11059
11060 rtnl_unlock();
11061}
11062
11063static struct pci_error_handlers bnx2x_err_handler = {
11064 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 11065 .slot_reset = bnx2x_io_slot_reset,
11066 .resume = bnx2x_io_resume,
493adb1f
WX		 11067};
11068
a2fbb9ea 11069static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 11070 .name = DRV_MODULE_NAME,
11071 .id_table = bnx2x_pci_tbl,
11072 .probe = bnx2x_init_one,
11073 .remove = __devexit_p(bnx2x_remove_one),
11074 .suspend = bnx2x_suspend,
11075 .resume = bnx2x_resume,
11076 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 11077};
11078
11079static int __init bnx2x_init(void)
11080{
dd21ca6d
SG		 11081 int ret;
11082
7995c64e 11083 pr_info("%s", version);
938cf541 11084
1cf167f2
EG		 11085 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11086 if (bnx2x_wq == NULL) {
7995c64e 11087 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 11088 return -ENOMEM;
11089 }
11090
dd21ca6d
SG		 11091 ret = pci_register_driver(&bnx2x_pci_driver);
11092 if (ret) {
7995c64e 11093 pr_err("Cannot register driver\n");
dd21ca6d
SG		 11094 destroy_workqueue(bnx2x_wq);
11095 }
11096 return ret;
a2fbb9ea
ET		 11097}
11098
11099static void __exit bnx2x_cleanup(void)
11100{
11101 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 11102
11103 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 11104}
11105
3deb8167
YR		 11106void bnx2x_notify_link_changed(struct bnx2x *bp)
11107{
11108 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11109}
11110
a2fbb9ea
ET		 11111module_init(bnx2x_init);
11112module_exit(bnx2x_cleanup);
11113
993ac7b5 11114#ifdef BCM_CNIC
619c5cb6
VZ		 11115/**
11116 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11117 *
11118 * @bp: driver handle
11119 * @set: set or clear the CAM entry
11120 *
11121 * This function will wait until the ramdord completion returns.
11122 * Return 0 if success, -ENODEV if ramrod doesn't return.
11123 */
11124static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11125{
11126 unsigned long ramrod_flags = 0;
11127
11128 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11129 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11130 &bp->iscsi_l2_mac_obj, true,
11131 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11132}
993ac7b5
MC		 11133
11134/* count denotes the number of new completions we have seen */
11135static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11136{
11137 struct eth_spe *spe;
11138
11139#ifdef BNX2X_STOP_ON_ERROR
11140 if (unlikely(bp->panic))
11141 return;
11142#endif
11143
11144 spin_lock_bh(&bp->spq_lock);
c2bff63f 11145 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 11146 bp->cnic_spq_pending -= count;
11147
993ac7b5 11148
c2bff63f
DK		 11149 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11150 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11151 & SPE_HDR_CONN_TYPE) >>
11152 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 11153 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11154 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 11155
11156 /* Set validation for iSCSI L2 client before sending SETUP
11157 * ramrod
11158 */
11159 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 11160 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 11161 bnx2x_set_ctx_validation(bp, &bp->context.
11162 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11163 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 11164 }
11165
619c5cb6
VZ		 11166 /*
11167 * There may be not more than 8 L2, not more than 8 L5 SPEs
11168 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 11169 * COMMON ramrods is not more than the EQ and SPQ can
11170 * accommodate.
c2bff63f 11171 */
6e30dd4e
VZ		 11172 if (type == ETH_CONNECTION_TYPE) {
11173 if (!atomic_read(&bp->cq_spq_left))
11174 break;
11175 else
11176 atomic_dec(&bp->cq_spq_left);
11177 } else if (type == NONE_CONNECTION_TYPE) {
11178 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 11179 break;
11180 else
6e30dd4e 11181 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 11182 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11183 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 11184 if (bp->cnic_spq_pending >=
11185 bp->cnic_eth_dev.max_kwqe_pending)
11186 break;
11187 else
11188 bp->cnic_spq_pending++;
11189 } else {
11190 BNX2X_ERR("Unknown SPE type: %d\n", type);
11191 bnx2x_panic();
993ac7b5 11192 break;
c2bff63f 11193 }
993ac7b5
MC		 11194
11195 spe = bnx2x_sp_get_next(bp);
11196 *spe = *bp->cnic_kwq_cons;
11197
993ac7b5
MC		 11198 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11199 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11200
11201 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11202 bp->cnic_kwq_cons = bp->cnic_kwq;
11203 else
11204 bp->cnic_kwq_cons++;
11205 }
11206 bnx2x_sp_prod_update(bp);
11207 spin_unlock_bh(&bp->spq_lock);
11208}
11209
11210static int bnx2x_cnic_sp_queue(struct net_device *dev,
11211 struct kwqe_16 *kwqes[], u32 count)
11212{
11213 struct bnx2x *bp = netdev_priv(dev);
11214 int i;
11215
11216#ifdef BNX2X_STOP_ON_ERROR
11217 if (unlikely(bp->panic))
11218 return -EIO;
11219#endif
11220
11221 spin_lock_bh(&bp->spq_lock);
11222
11223 for (i = 0; i < count; i++) {
11224 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11225
11226 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11227 break;
11228
11229 *bp->cnic_kwq_prod = *spe;
11230
11231 bp->cnic_kwq_pending++;
11232
11233 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11234 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 11235 spe->data.update_data_addr.hi,
11236 spe->data.update_data_addr.lo,
993ac7b5
MC		 11237 bp->cnic_kwq_pending);
11238
11239 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11240 bp->cnic_kwq_prod = bp->cnic_kwq;
11241 else
11242 bp->cnic_kwq_prod++;
11243 }
11244
11245 spin_unlock_bh(&bp->spq_lock);
11246
11247 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11248 bnx2x_cnic_sp_post(bp, 0);
11249
11250 return i;
11251}
11252
11253static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11254{
11255 struct cnic_ops *c_ops;
11256 int rc = 0;
11257
11258 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 11259 c_ops = rcu_dereference_protected(bp->cnic_ops,
11260 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 11261 if (c_ops)
11262 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11263 mutex_unlock(&bp->cnic_mutex);
11264
11265 return rc;
11266}
11267
11268static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11269{
11270 struct cnic_ops *c_ops;
11271 int rc = 0;
11272
11273 rcu_read_lock();
11274 c_ops = rcu_dereference(bp->cnic_ops);
11275 if (c_ops)
11276 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11277 rcu_read_unlock();
11278
11279 return rc;
11280}
11281
11282/*
11283 * for commands that have no data
11284 */
9f6c9258 11285int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 11286{
11287 struct cnic_ctl_info ctl = {0};
11288
11289 ctl.cmd = cmd;
11290
11291 return bnx2x_cnic_ctl_send(bp, &ctl);
11292}
11293
619c5cb6 11294static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 11295{
619c5cb6 11296 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 11297
11298 /* first we tell CNIC and only then we count this as a completion */
11299 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11300 ctl.data.comp.cid = cid;
619c5cb6 11301 ctl.data.comp.error = err;
993ac7b5
MC		 11302
11303 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 11304 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 11305}
11306
619c5cb6
VZ		 11307
11308/* Called with netif_addr_lock_bh() taken.
11309 * Sets an rx_mode config for an iSCSI ETH client.
11310 * Doesn't block.
11311 * Completion should be checked outside.
11312 */
11313static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11314{
11315 unsigned long accept_flags = 0, ramrod_flags = 0;
11316 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11317 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11318
11319 if (start) {
11320 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11321 * because it's the only way for UIO Queue to accept
11322 * multicasts (in non-promiscuous mode only one Queue per
11323 * function will receive multicast packets (leading in our
11324 * case).
11325 */
11326 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11327 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11328 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11329 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11330
11331 /* Clear STOP_PENDING bit if START is requested */
11332 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11333
11334 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11335 } else
11336 /* Clear START_PENDING bit if STOP is requested */
11337 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11338
11339 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11340 set_bit(sched_state, &bp->sp_state);
11341 else {
11342 __set_bit(RAMROD_RX, &ramrod_flags);
11343 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11344 ramrod_flags);
11345 }
11346}
11347
11348
993ac7b5
MC		 11349static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11350{
11351 struct bnx2x *bp = netdev_priv(dev);
11352 int rc = 0;
11353
11354 switch (ctl->cmd) {
11355 case DRV_CTL_CTXTBL_WR_CMD: {
11356 u32 index = ctl->data.io.offset;
11357 dma_addr_t addr = ctl->data.io.dma_addr;
11358
11359 bnx2x_ilt_wr(bp, index, addr);
11360 break;
11361 }
11362
c2bff63f
DK		 11363 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11364 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 11365
11366 bnx2x_cnic_sp_post(bp, count);
11367 break;
11368 }
11369
11370 /* rtnl_lock is held. */
11371 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 11372 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11373 unsigned long sp_bits = 0;
11374
11375 /* Configure the iSCSI classification object */
11376 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11377 cp->iscsi_l2_client_id,
11378 cp->iscsi_l2_cid, BP_FUNC(bp),
11379 bnx2x_sp(bp, mac_rdata),
11380 bnx2x_sp_mapping(bp, mac_rdata),
11381 BNX2X_FILTER_MAC_PENDING,
11382 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11383 &bp->macs_pool);
ec6ba945 11384
523224a3 11385 /* Set iSCSI MAC address */
619c5cb6
VZ		 11386 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11387 if (rc)
11388 break;
523224a3
DK		 11389
11390 mmiowb();
11391 barrier();
11392
619c5cb6
VZ		 11393 /* Start accepting on iSCSI L2 ring */
11394
11395 netif_addr_lock_bh(dev);
11396 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11397 netif_addr_unlock_bh(dev);
11398
11399 /* bits to wait on */
11400 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11401 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11402
11403 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11404 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 11405
993ac7b5
MC		 11406 break;
11407 }
11408
11409 /* rtnl_lock is held. */
11410 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 11411 unsigned long sp_bits = 0;
993ac7b5 11412
523224a3 11413 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 11414 netif_addr_lock_bh(dev);
11415 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11416 netif_addr_unlock_bh(dev);
11417
11418 /* bits to wait on */
11419 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11420 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11421
11422 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11423 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 11424
11425 mmiowb();
11426 barrier();
11427
11428 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 11429 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11430 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 11431 break;
11432 }
c2bff63f
DK		 11433 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11434 int count = ctl->data.credit.credit_count;
11435
11436 smp_mb__before_atomic_inc();
6e30dd4e 11437 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 11438 smp_mb__after_atomic_inc();
11439 break;
11440 }
993ac7b5
MC		 11441
11442 default:
11443 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11444 rc = -EINVAL;
11445 }
11446
11447 return rc;
11448}
11449
9f6c9258 11450void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 11451{
11452 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11453
11454 if (bp->flags & USING_MSIX_FLAG) {
11455 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11456 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11457 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11458 } else {
11459 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11460 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11461 }
619c5cb6 11462 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 11463 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11464 else
11465 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11466
619c5cb6
VZ		 11467 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11468 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 11469 cp->irq_arr[1].status_blk = bp->def_status_blk;
11470 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 11471 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 11472
11473 cp->num_irq = 2;
11474}
11475
11476static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11477 void *data)
11478{
11479 struct bnx2x *bp = netdev_priv(dev);
11480 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11481
11482 if (ops == NULL)
11483 return -EINVAL;
11484
993ac7b5
MC		 11485 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11486 if (!bp->cnic_kwq)
11487 return -ENOMEM;
11488
11489 bp->cnic_kwq_cons = bp->cnic_kwq;
11490 bp->cnic_kwq_prod = bp->cnic_kwq;
11491 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11492
11493 bp->cnic_spq_pending = 0;
11494 bp->cnic_kwq_pending = 0;
11495
11496 bp->cnic_data = data;
11497
11498 cp->num_irq = 0;
619c5cb6 11499 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 11500 cp->iro_arr = bp->iro_arr;
993ac7b5 11501
993ac7b5 11502 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 11503
993ac7b5
MC		 11504 rcu_assign_pointer(bp->cnic_ops, ops);
11505
11506 return 0;
11507}
11508
11509static int bnx2x_unregister_cnic(struct net_device *dev)
11510{
11511 struct bnx2x *bp = netdev_priv(dev);
11512 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11513
11514 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 11515 cp->drv_state = 0;
11516 rcu_assign_pointer(bp->cnic_ops, NULL);
11517 mutex_unlock(&bp->cnic_mutex);
11518 synchronize_rcu();
11519 kfree(bp->cnic_kwq);
11520 bp->cnic_kwq = NULL;
11521
11522 return 0;
11523}
11524
11525struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11526{
11527 struct bnx2x *bp = netdev_priv(dev);
11528 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11529
2ba45142
VZ		 11530 /* If both iSCSI and FCoE are disabled - return NULL in
11531 * order to indicate CNIC that it should not try to work
11532 * with this device.
11533 */
11534 if (NO_ISCSI(bp) && NO_FCOE(bp))
11535 return NULL;
11536
993ac7b5
MC		 11537 cp->drv_owner = THIS_MODULE;
11538 cp->chip_id = CHIP_ID(bp);
11539 cp->pdev = bp->pdev;
11540 cp->io_base = bp->regview;
11541 cp->io_base2 = bp->doorbells;
11542 cp->max_kwqe_pending = 8;
523224a3 11543 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 11544 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11545 bnx2x_cid_ilt_lines(bp);
993ac7b5 11546 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 11547 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 11548 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11549 cp->drv_ctl = bnx2x_drv_ctl;
11550 cp->drv_register_cnic = bnx2x_register_cnic;
11551 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 11552 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 11553 cp->iscsi_l2_client_id =
11554 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 11555 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11556
2ba45142
VZ		 11557 if (NO_ISCSI_OOO(bp))
11558 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11559
11560 if (NO_ISCSI(bp))
11561 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11562
11563 if (NO_FCOE(bp))
11564 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11565
c2bff63f
DK		 11566 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11567 "starting cid %d\n",
11568 cp->ctx_blk_size,
11569 cp->ctx_tbl_offset,
11570 cp->ctx_tbl_len,
11571 cp->starting_cid);
993ac7b5
MC		 11572 return cp;
11573}
11574EXPORT_SYMBOL(bnx2x_cnic_probe);
11575
11576#endif /* BCM_CNIC */
94a78b79 11577
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