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bnx2x: dcb - send all unmapped priorities to same COS as L2
[thirdparty/linux.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea 41#include <net/ip.h>
619c5cb6 42#include <net/ipv6.h>
a2fbb9ea
ET		 43#include <net/tcp.h>
44#include <net/checksum.h>
34f80b04 45#include <net/ip6_checksum.h>
a2fbb9ea
ET		 46#include <linux/workqueue.h>
47#include <linux/crc32.h>
34f80b04 48#include <linux/crc32c.h>
a2fbb9ea
ET		 49#include <linux/prefetch.h>
50#include <linux/zlib.h>
a2fbb9ea 51#include <linux/io.h>
45229b42 52#include <linux/stringify.h>
7ab24bfd 53#include <linux/vmalloc.h>
a2fbb9ea 54
a2fbb9ea
ET		 55#include "bnx2x.h"
56#include "bnx2x_init.h"
94a78b79 57#include "bnx2x_init_ops.h"
9f6c9258 58#include "bnx2x_cmn.h"
e4901dde 59#include "bnx2x_dcb.h"
042181f5 60#include "bnx2x_sp.h"
a2fbb9ea 61
94a78b79
VZ		 62#include <linux/firmware.h>
63#include "bnx2x_fw_file_hdr.h"
64/* FW files */
45229b42
BH		 65#define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 70#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 72#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 73
34f80b04
EG		 74/* Time in jiffies before concluding the transmitter is hung */
75#define TX_TIMEOUT (5*HZ)
a2fbb9ea 76
53a10565 77static char version[] __devinitdata =
619c5cb6 78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80
24e3fcef 81MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 82MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
a2fbb9ea
ET		 86MODULE_LICENSE("GPL");
87MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 88MODULE_FIRMWARE(FW_FILE_NAME_E1);
89MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 90MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 91
555f6c78
EG		 92static int multi_mode = 1;
93module_param(multi_mode, int, 0);
ca00392c
EG		 94MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
96
d6214d7a 97int num_queues;
54b9ddaa
VZ		 98module_param(num_queues, int, 0);
99MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
19680c48 103module_param(disable_tpa, int, 0);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
9ee3d37b
DK		 106#define INT_MODE_INTx 1
107#define INT_MODE_MSI 2
8badd27a
EG		 108static int int_mode;
109module_param(int_mode, int, 0);
619c5cb6 110MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 111 "(1 INT#x; 2 MSI)");
8badd27a 112
a18f5128
EG		 113static int dropless_fc;
114module_param(dropless_fc, int, 0);
115MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
9898f86d 117static int poll;
a2fbb9ea 118module_param(poll, int, 0);
9898f86d 119MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 120
121static int mrrs = -1;
122module_param(mrrs, int, 0);
123MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
124
9898f86d 125static int debug;
a2fbb9ea 126module_param(debug, int, 0);
9898f86d
EG		 127MODULE_PARM_DESC(debug, " Default debug msglevel");
128
a2fbb9ea 129
619c5cb6
VZ		 130
131struct workqueue_struct *bnx2x_wq;
ec6ba945 132
a2fbb9ea
ET		 133enum bnx2x_board_type {
134 BCM57710 = 0,
619c5cb6
VZ		 135 BCM57711,
136 BCM57711E,
137 BCM57712,
138 BCM57712_MF,
139 BCM57800,
140 BCM57800_MF,
141 BCM57810,
142 BCM57810_MF,
143 BCM57840,
144 BCM57840_MF
a2fbb9ea
ET		 145};
146
34f80b04 147/* indexed by board_type, above */
53a10565 148static struct {
a2fbb9ea
ET		 149 char *name;
150} board_info[] __devinitdata = {
619c5cb6
VZ		 151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
a2fbb9ea
ET		 163};
164
619c5cb6
VZ		 165#ifndef PCI_DEVICE_ID_NX2_57710
166#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
167#endif
168#ifndef PCI_DEVICE_ID_NX2_57711
169#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
170#endif
171#ifndef PCI_DEVICE_ID_NX2_57711E
172#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
173#endif
174#ifndef PCI_DEVICE_ID_NX2_57712
175#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
176#endif
177#ifndef PCI_DEVICE_ID_NX2_57712_MF
178#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
179#endif
180#ifndef PCI_DEVICE_ID_NX2_57800
181#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
182#endif
183#ifndef PCI_DEVICE_ID_NX2_57800_MF
184#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57810
187#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57810_MF
190#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57840
193#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57840_MF
196#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
197#endif
a3aa1884 198static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
a2fbb9ea
ET		 210 { 0 }
211};
212
213MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
214
215/****************************************************************************
216* General service functions
217****************************************************************************/
218
619c5cb6
VZ		 219static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
221{
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
224}
225
226static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
228{
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
231
232 __storm_memset_dma_mapping(bp, addr, mapping);
233}
234
235static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
236 u16 pf_id)
523224a3 237{
619c5cb6
VZ		 238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
239 pf_id);
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
241 pf_id);
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
243 pf_id);
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
245 pf_id);
523224a3
DK		 246}
247
619c5cb6
VZ		 248static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
249 u8 enable)
250{
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
252 enable);
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
254 enable);
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
256 enable);
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
258 enable);
259}
523224a3
DK		 260
261static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
263 u16 pfid)
264{
265 size_t size = sizeof(struct event_ring_data);
266
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
268
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
270}
271
272static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
273 u16 pfid)
274{
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
277}
278
a2fbb9ea
ET		 279/* used only at init
280 * locking is done by mcp
281 */
8d96286a 282static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 283{
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
288}
289
a2fbb9ea
ET		 290static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
291{
292 u32 val;
293
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
298
299 return val;
300}
a2fbb9ea 301
f2e0899f
DK		 302#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306#define DMAE_DP_DST_NONE "dst_addr [none]"
307
8d96286a 308static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
309 int msglvl)
f2e0899f
DK		 310{
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
312
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
322 dmae->comp_val);
323 else
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
330 dmae->comp_val);
331 break;
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
340 dmae->comp_val);
341 else
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
348 dmae->comp_val);
349 break;
350 default:
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
354 "dst_addr [none]\n"
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
358 dmae->comp_val);
359 else
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
362 "dst_addr [none]\n"
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
366 dmae->comp_val);
367 break;
368 }
369
370}
371
a2fbb9ea 372/* copy command into DMAE command memory and set DMAE command go */
6c719d00 373void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 374{
375 u32 cmd_offset;
376 int i;
377
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
381
ad8d3948
EG		 382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 384 }
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
386}
387
f2e0899f 388u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 389{
f2e0899f
DK		 390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
391 DMAE_CMD_C_ENABLE);
392}
ad8d3948 393
f2e0899f
DK		 394u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
395{
396 return opcode & ~DMAE_CMD_SRC_RESET;
397}
ad8d3948 398
f2e0899f
DK		 399u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
401{
402 u32 opcode = 0;
403
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 406
f2e0899f
DK		 407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 413
a2fbb9ea 414#ifdef __BIG_ENDIAN
f2e0899f 415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 416#else
f2e0899f 417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 418#endif
f2e0899f
DK		 419 if (with_comp)
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
421 return opcode;
422}
423
8d96286a 424static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
f2e0899f
DK		 427{
428 memset(dmae, 0, sizeof(struct dmae_command));
429
430 /* set the opcode */
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
433
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
438}
439
440/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 441static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
f2e0899f
DK		 443{
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 446 int rc = 0;
447
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 451
619c5cb6
VZ		 452 /*
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
456 */
6e30dd4e 457 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 458
f2e0899f 459 /* reset completion */
a2fbb9ea
ET		 460 *wb_comp = 0;
461
f2e0899f
DK		 462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 464
f2e0899f 465 /* wait for completion */
a2fbb9ea 466 udelay(5);
f2e0899f 467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
469
ad8d3948 470 if (!cnt) {
c3eefaf6 471 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 472 rc = DMAE_TIMEOUT;
473 goto unlock;
a2fbb9ea 474 }
ad8d3948 475 cnt--;
f2e0899f 476 udelay(50);
a2fbb9ea 477 }
f2e0899f
DK		 478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
480 rc = DMAE_PCI_ERROR;
481 }
482
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 486
f2e0899f 487unlock:
6e30dd4e 488 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 489 return rc;
490}
491
492void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
493 u32 len32)
494{
495 struct dmae_command dmae;
496
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
499
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
503 return;
504 }
505
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
508
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
514 dmae.len = len32;
515
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
517
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 520}
521
c18487ee 522void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 523{
5ff7b6d4 524 struct dmae_command dmae;
ad8d3948
EG		 525
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
528 int i;
529
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
534 return;
535 }
536
f2e0899f
DK		 537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 539
f2e0899f 540 /* fill in addresses and len */
5ff7b6d4
EG		 541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
545 dmae.len = len32;
ad8d3948 546
f2e0899f 547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 548
f2e0899f
DK		 549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 551}
552
8d96286a 553static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
554 u32 addr, u32 len)
573f2035 555{
02e3c6cb 556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 557 int offset = 0;
558
02e3c6cb 559 while (len > dmae_wr_max) {
573f2035 560 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
563 len -= dmae_wr_max;
573f2035
EG		 564 }
565
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
567}
568
ad8d3948
EG		 569/* used only for slowpath so not inlined */
570static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
571{
572 u32 wb_write[2];
573
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 577}
a2fbb9ea 578
ad8d3948
EG		 579#ifdef USE_WB_RD
580static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
581{
582 u32 wb_data[2];
583
584 REG_RD_DMAE(bp, reg, wb_data, 2);
585
586 return HILO_U64(wb_data[0], wb_data[1]);
587}
588#endif
589
a2fbb9ea
ET		 590static int bnx2x_mc_assert(struct bnx2x *bp)
591{
a2fbb9ea 592 char last_idx;
34f80b04
EG		 593 int i, rc = 0;
594 u32 row0, row1, row2, row3;
595
596 /* XSTORM */
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
599 if (last_idx)
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
601
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
604
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
613
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
618 rc++;
619 } else {
620 break;
621 }
622 }
623
624 /* TSTORM */
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
627 if (last_idx)
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
629
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
632
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
641
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
646 rc++;
647 } else {
648 break;
649 }
650 }
651
652 /* CSTORM */
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
655 if (last_idx)
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
657
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
660
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
669
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
674 rc++;
675 } else {
676 break;
677 }
678 }
679
680 /* USTORM */
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
683 if (last_idx)
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
685
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
688
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
697
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
a2fbb9ea
ET		 705 }
706 }
34f80b04 707
a2fbb9ea
ET		 708 return rc;
709}
c14423fe 710
7a25cc73 711void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 712{
7a25cc73 713 u32 addr, val;
a2fbb9ea 714 u32 mark, offset;
4781bfad 715 __be32 data[9];
a2fbb9ea 716 int word;
f2e0899f 717 u32 trace_shmem_base;
2145a920
VZ		 718 if (BP_NOMCP(bp)) {
719 BNX2X_ERR("NO MCP - can not dump\n");
720 return;
721 }
7a25cc73
DK		 722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
726
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 730
f2e0899f
DK		 731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
733 else
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 736 mark = REG_RD(bp, addr);
f2e0899f
DK		 737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 740
7a25cc73 741 printk("%s", lvl);
f2e0899f 742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 743 for (word = 0; word < 8; word++)
cdaa7cb8 744 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 745 data[8] = 0x0;
7995c64e 746 pr_cont("%s", (char *)data);
a2fbb9ea 747 }
cdaa7cb8 748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 749 for (word = 0; word < 8; word++)
cdaa7cb8 750 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 751 data[8] = 0x0;
7995c64e 752 pr_cont("%s", (char *)data);
a2fbb9ea 753 }
7a25cc73
DK		 754 printk("%s" "end of fw dump\n", lvl);
755}
756
757static inline void bnx2x_fw_dump(struct bnx2x *bp)
758{
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 760}
761
6c719d00 762void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 763{
764 int i;
523224a3
DK		 765 u16 j;
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768#ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
6383c0b3 770 u8 cos;
523224a3 771#endif
a2fbb9ea 772
66e855f3
YG		 773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
775
a2fbb9ea
ET		 776 BNX2X_ERR("begin crash dump -----------------\n");
777
8440d2b6
EG		 778 /* Indices */
779 /* Common */
523224a3 780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
619c5cb6
VZ		 781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
789 BNX2X_ERR(" def (");
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
791 pr_cont("0x%x%s",
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
794
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
798 i*sizeof(u32));
799
619c5cb6 800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
523224a3 801 "pf_id(0x%x) vnic_id(0x%x) "
619c5cb6
VZ		 802 "vf_id(0x%x) vf_valid (0x%x) "
803 "state(0x%x)\n",
523224a3
DK		 804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 809 sp_sb_data.p_func.vf_valid,
810 sp_sb_data.state);
523224a3 811
8440d2b6 812
ec6ba945 813 for_each_eth_queue(bp, i) {
a2fbb9ea 814 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 815 int loop;
f2e0899f 816 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 819 CHIP_IS_E1x(bp) ?
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
523224a3 822 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 823 CHIP_IS_E1x(bp) ?
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
6383c0b3 826 u8 data_size, cos;
523224a3 827 u32 *sb_data_p;
6383c0b3 828 struct bnx2x_fp_txdata txdata;
523224a3
DK		 829
830 /* Rx */
cdaa7cb8 831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 832 " rx_comp_prod(0x%x)"
cdaa7cb8 833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 834 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 835 fp->rx_comp_prod,
66e855f3 836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 838 " fp_hc_idx(0x%x)\n",
8440d2b6 839 fp->rx_sge_prod, fp->last_max_sge,
523224a3 840 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 841
523224a3 842 /* Tx */
6383c0b3
AE		 843 for_each_cos_in_tx_queue(fp, cos)
844 {
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
851 txdata.tx_bd_cons,
852 le16_to_cpu(*txdata.tx_cons_sb));
853 }
523224a3 854
619c5cb6
VZ		 855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 857
858 /* host sb data */
859
ec6ba945
VZ		 860#ifdef BCM_CNIC
861 if (IS_FCOE_FP(fp))
862 continue;
863#endif
523224a3
DK		 864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
866 pr_cont("0x%x%s",
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
869
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
872 pr_cont("0x%x%s",
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
875 /* fw sb data */
619c5cb6
VZ		 876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
523224a3 879 data_size /= sizeof(u32);
619c5cb6
VZ		 880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
882 (u32 *)&sb_data_e2;
523224a3
DK		 883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
887 j * sizeof(u32));
888
619c5cb6
VZ		 889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
892 "state(0x%x)\n",
f2e0899f
DK		 893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
f2e0899f 899 } else {
619c5cb6
VZ		 900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
902 "state(0x%x)\n",
f2e0899f
DK		 903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
f2e0899f 909 }
523224a3
DK		 910
911 /* SB_SMs data */
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
917 hc_sm_p[j].__flags,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
922 }
923
924 /* Indecies data */
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
928 hc_index_p[j].flags,
929 hc_index_p[j].timeout);
930 }
8440d2b6 931 }
a2fbb9ea 932
523224a3 933#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 934 /* Rings */
935 /* Rx */
ec6ba945 936 for_each_rx_queue(bp, i) {
8440d2b6 937 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 938
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 941 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
944
c3eefaf6
EG		 945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 947 }
948
3196a88a
EG		 949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
8440d2b6 951 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
954
c3eefaf6
EG		 955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 957 }
958
a2fbb9ea
ET		 959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
963
c3eefaf6
EG		 964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 966 }
967 }
968
8440d2b6 969 /* Tx */
ec6ba945 970 for_each_tx_queue(bp, i) {
8440d2b6 971 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3
AE		 972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
974
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
980
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
984 sw_bd->first_bd);
985 }
8440d2b6 986
6383c0b3
AE		 987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 991
6383c0b3
AE		 992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
993 "[%x:%x:%x:%x]\n",
994 i, cos, j, tx_bd[0], tx_bd[1],
995 tx_bd[2], tx_bd[3]);
996 }
8440d2b6
EG		 997 }
998 }
523224a3 999#endif
34f80b04 1000 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1003}
1004
619c5cb6
VZ		 1005/*
1006 * FLR Support for E2
1007 *
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1009 * initialization.
1010 */
1011#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012#define FLR_WAIT_INTERAVAL 50 /* usec */
1013#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1014
1015struct pbf_pN_buf_regs {
1016 int pN;
1017 u32 init_crd;
1018 u32 crd;
1019 u32 crd_freed;
1020};
1021
1022struct pbf_pN_cmd_regs {
1023 int pN;
1024 u32 lines_occup;
1025 u32 lines_freed;
1026};
1027
1028static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1030 u32 poll_count)
1031{
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1034
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1038
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1042
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1045 if (cur_cnt--) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1049 } else {
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1051 regs->pN);
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1053 regs->pN, crd);
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1056 break;
1057 }
1058 }
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1061}
1062
1063static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1065 u32 poll_count)
1066{
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1069
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1072
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1075
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1077 if (cur_cnt--) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1081 } else {
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1083 regs->pN);
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1085 regs->pN, occup);
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1087 regs->pN, freed);
1088 break;
1089 }
1090 }
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1093}
1094
1095static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1097{
1098 u32 cur_cnt = poll_count;
1099 u32 val;
1100
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1103
1104 return val;
1105}
1106
1107static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1109{
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1111 if (val != 0) {
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1113 return 1;
1114 }
1115 return 0;
1116}
1117
1118static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1119{
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1123
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1126
1127 return FLR_POLL_CNT;
1128}
1129
1130static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1131{
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1151 };
1152
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1158 PBF_REG_CREDIT_Q0 :
1159 PBF_REG_P0_CREDIT,
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1167 PBF_REG_CREDIT_Q1 :
1168 PBF_REG_P1_CREDIT,
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1177 PBF_REG_P4_CREDIT,
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1181 };
1182
1183 int i;
1184
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1188
1189
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1193}
1194
1195#define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1197
1198#define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1200
1201#define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1203
1204
1205static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1206 u32 poll_cnt)
1207{
1208 struct sdm_op_gen op_gen = {0};
1209
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1212 int ret = 0;
1213
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1216 return 1;
1217 }
1218
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1223
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1226
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1229 ret = 1;
1230 }
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1233
1234 return ret;
1235}
1236
1237static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1238{
1239 int pos;
1240 u16 status;
1241
77c98e6a 1242 pos = pci_pcie_cap(dev);
619c5cb6
VZ		 1243 if (!pos)
1244 return false;
1245
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1248}
1249
1250/* PF FLR specific routines
1251*/
1252static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1253{
1254
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1259 poll_cnt))
1260 return 1;
1261
1262
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1267 poll_cnt))
1268 return 1;
1269
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1274 poll_cnt))
1275 return 1;
1276
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1281 poll_cnt))
1282 return 1;
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1286 poll_cnt))
1287 return 1;
1288
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1293 poll_cnt))
1294 return 1;
1295
1296 return 0;
1297}
1298
1299static void bnx2x_hw_enable_status(struct bnx2x *bp)
1300{
1301 u32 val;
1302
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1305
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1308
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1311
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1314
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1317
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1320
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1323
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1326 val);
1327}
1328
1329static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1330{
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1332
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1334
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1337
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1340 return -EBUSY;
1341
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1343
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1346 return -EBUSY;
1347
1348 /* ATC cleanup */
1349
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1352
1353 /* Wait 100ms (not adjusted according to platform) */
1354 msleep(100);
1355
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1359
1360 /* Debug */
1361 bnx2x_hw_enable_status(bp);
1362
1363 /*
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1366 */
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1368
1369 return 0;
1370}
1371
f2e0899f 1372static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1373{
34f80b04 1374 int port = BP_PORT(bp);
a2fbb9ea
ET		 1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1379
1380 if (msix) {
8badd27a
EG		 1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1385 } else if (msi) {
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1390 } else {
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1395
a0fd065c
DK		 1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1398 val, port, addr);
615f8fd9 1399
a0fd065c 1400 REG_WR(bp, addr, val);
615f8fd9 1401
a0fd065c
DK		 1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1403 }
a2fbb9ea
ET		 1404 }
1405
a0fd065c
DK		 1406 if (CHIP_IS_E1(bp))
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1408
8badd27a
EG		 1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1411
1412 REG_WR(bp, addr, val);
37dbbf32
EG		 1413 /*
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1415 */
1416 mmiowb();
1417 barrier();
34f80b04 1418
f2e0899f 1419 if (!CHIP_IS_E1(bp)) {
34f80b04 1420 /* init leading/trailing edge */
fb3bff17 1421 if (IS_MF(bp)) {
8badd27a 1422 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1423 if (bp->port.pmf)
4acac6a5
EG		 1424 /* enable nig and gpio3 attention */
1425 val |= 0x1100;
34f80b04
EG		 1426 } else
1427 val = 0xffff;
1428
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1431 }
37dbbf32
EG		 1432
1433 /* Make sure that interrupts are indeed enabled from here on */
1434 mmiowb();
a2fbb9ea
ET		 1435}
1436
f2e0899f
DK		 1437static void bnx2x_igu_int_enable(struct bnx2x *bp)
1438{
1439 u32 val;
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1442
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1444
1445 if (msix) {
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1451 } else if (msi) {
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1457 } else {
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1463 }
1464
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1467
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1469
1470 barrier();
1471
1472 /* init leading/trailing edge */
1473 if (IS_MF(bp)) {
1474 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1475 if (bp->port.pmf)
1476 /* enable nig and gpio3 attention */
1477 val |= 0x1100;
1478 } else
1479 val = 0xffff;
1480
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1483
1484 /* Make sure that interrupts are indeed enabled from here on */
1485 mmiowb();
1486}
1487
1488void bnx2x_int_enable(struct bnx2x *bp)
1489{
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1492 else
1493 bnx2x_igu_int_enable(bp);
1494}
1495
1496static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1497{
34f80b04 1498 int port = BP_PORT(bp);
a2fbb9ea
ET		 1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1501
a0fd065c
DK		 1502 /*
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1506 */
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1511 */
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1513
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517 } else
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1522
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1524 val, port, addr);
1525
8badd27a
EG		 1526 /* flush all outstanding writes */
1527 mmiowb();
1528
a2fbb9ea
ET		 1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1532}
1533
f2e0899f
DK		 1534static void bnx2x_igu_int_disable(struct bnx2x *bp)
1535{
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1537
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1541
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1543
1544 /* flush all outstanding writes */
1545 mmiowb();
1546
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1550}
1551
6383c0b3 1552void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1553{
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1556 else
1557 bnx2x_igu_int_disable(bp);
1558}
1559
9f6c9258 1560void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1561{
a2fbb9ea 1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1563 int i, offset;
a2fbb9ea 1564
f8ef6e44
YG		 1565 if (disable_hw)
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1568
1569 /* make sure all ISRs are done */
1570 if (msix) {
8badd27a
EG		 1571 synchronize_irq(bp->msix_table[0].vector);
1572 offset = 1;
37b091ba
MC		 1573#ifdef BCM_CNIC
1574 offset++;
1575#endif
ec6ba945 1576 for_each_eth_queue(bp, i)
754a2f52 1577 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1578 } else
1579 synchronize_irq(bp->pdev->irq);
1580
1581 /* make sure sp_task is not running */
1cf167f2 1582 cancel_delayed_work(&bp->sp_task);
3deb8167 1583 cancel_delayed_work(&bp->period_task);
1cf167f2 1584 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1585}
1586
34f80b04 1587/* fast path */
a2fbb9ea
ET		 1588
1589/*
34f80b04 1590 * General service functions
a2fbb9ea
ET		 1591 */
1592
72fd0718
VZ		 1593/* Return true if succeeded to acquire the lock */
1594static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1595{
1596 u32 lock_status;
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1600
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1602
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1605 DP(NETIF_MSG_HW,
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1608 return false;
72fd0718
VZ		 1609 }
1610
1611 if (func <= 5)
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1613 else
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1616
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1621 return true;
1622
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1624 return false;
1625}
1626
c9ee9206
VZ		 1627/**
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1629 *
1630 * @bp: driver handle
1631 *
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1634 */
1635static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1636{
1637 if (BP_PATH(bp))
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1639 else
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1641}
1642
1643/**
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1645 *
1646 * @bp: driver handle
1647 *
1648 * Tries to aquire a leader lock for cuurent engine.
1649 */
1650static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1651{
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1653}
1654
993ac7b5 1655#ifdef BCM_CNIC
619c5cb6 1656static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1657#endif
3196a88a 1658
619c5cb6 1659void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1660{
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1666
34f80b04 1667 DP(BNX2X_MSG_SP,
a2fbb9ea 1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1669 fp->index, cid, command, bp->state,
34f80b04 1670 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1671
619c5cb6
VZ		 1672 switch (command) {
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1674 DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid);
1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1676 break;
1677 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
523224a3 1678 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1679 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1680 break;
1681
6383c0b3
AE		 1682 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1683 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1684 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1685 break;
1686
619c5cb6 1687 case (RAMROD_CMD_ID_ETH_HALT):
523224a3 1688 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1689 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1690 break;
1691
619c5cb6 1692 case (RAMROD_CMD_ID_ETH_TERMINATE):
523224a3 1693 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1694 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1695 break;
1696
619c5cb6
VZ		 1697 case (RAMROD_CMD_ID_ETH_EMPTY):
1698 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid);
1699 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1700 break;
619c5cb6
VZ		 1701
1702 default:
1703 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1704 command, fp->index);
1705 return;
523224a3 1706 }
3196a88a 1707
619c5cb6
VZ		 1708 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1709 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1710 /* q_obj->complete_cmd() failure means that this was
1711 * an unexpected completion.
1712 *
1713 * In this case we don't want to increase the bp->spq_left
1714 * because apparently we haven't sent this command the first
1715 * place.
1716 */
1717#ifdef BNX2X_STOP_ON_ERROR
1718 bnx2x_panic();
1719#else
1720 return;
1721#endif
1722
8fe23fbd 1723 smp_mb__before_atomic_inc();
6e30dd4e 1724 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1725 /* push the change in bp->spq_left and towards the memory */
1726 smp_mb__after_atomic_inc();
49d66772 1727
523224a3 1728 return;
a2fbb9ea
ET		 1729}
1730
619c5cb6
VZ		 1731void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1732 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1733{
1734 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1735
1736 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1737 start);
1738}
1739
9f6c9258 1740irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1741{
555f6c78 1742 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1743 u16 status = bnx2x_ack_int(bp);
34f80b04 1744 u16 mask;
ca00392c 1745 int i;
6383c0b3 1746 u8 cos;
a2fbb9ea 1747
34f80b04 1748 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1749 if (unlikely(status == 0)) {
1750 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1751 return IRQ_NONE;
1752 }
f5372251 1753 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1754
3196a88a
EG		 1755#ifdef BNX2X_STOP_ON_ERROR
1756 if (unlikely(bp->panic))
1757 return IRQ_HANDLED;
1758#endif
1759
ec6ba945 1760 for_each_eth_queue(bp, i) {
ca00392c 1761 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1762
6383c0b3 1763 mask = 0x2 << (fp->index + CNIC_PRESENT);
ca00392c 1764 if (status & mask) {
619c5cb6 1765 /* Handle Rx or Tx according to SB id */
54b9ddaa 1766 prefetch(fp->rx_cons_sb);
6383c0b3
AE		 1767 for_each_cos_in_tx_queue(fp, cos)
1768 prefetch(fp->txdata[cos].tx_cons_sb);
523224a3 1769 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1770 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1771 status &= ~mask;
1772 }
a2fbb9ea
ET		 1773 }
1774
993ac7b5 1775#ifdef BCM_CNIC
523224a3 1776 mask = 0x2;
993ac7b5
MC		 1777 if (status & (mask | 0x1)) {
1778 struct cnic_ops *c_ops = NULL;
1779
619c5cb6
VZ		 1780 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1781 rcu_read_lock();
1782 c_ops = rcu_dereference(bp->cnic_ops);
1783 if (c_ops)
1784 c_ops->cnic_handler(bp->cnic_data, NULL);
1785 rcu_read_unlock();
1786 }
993ac7b5
MC		 1787
1788 status &= ~mask;
1789 }
1790#endif
a2fbb9ea 1791
34f80b04 1792 if (unlikely(status & 0x1)) {
1cf167f2 1793 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1794
1795 status &= ~0x1;
1796 if (!status)
1797 return IRQ_HANDLED;
1798 }
1799
cdaa7cb8
VZ		 1800 if (unlikely(status))
1801 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1802 status);
a2fbb9ea 1803
c18487ee 1804 return IRQ_HANDLED;
a2fbb9ea
ET		 1805}
1806
c18487ee
YR		 1807/* Link */
1808
1809/*
1810 * General service functions
1811 */
a2fbb9ea 1812
9f6c9258 1813int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1814{
1815 u32 lock_status;
1816 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1817 int func = BP_FUNC(bp);
1818 u32 hw_lock_control_reg;
c18487ee 1819 int cnt;
a2fbb9ea 1820
c18487ee
YR		 1821 /* Validating that the resource is within range */
1822 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1823 DP(NETIF_MSG_HW,
1824 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1825 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1826 return -EINVAL;
1827 }
a2fbb9ea 1828
4a37fb66
YG		 1829 if (func <= 5) {
1830 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1831 } else {
1832 hw_lock_control_reg =
1833 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1834 }
1835
c18487ee 1836 /* Validating that the resource is not already taken */
4a37fb66 1837 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1838 if (lock_status & resource_bit) {
1839 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1840 lock_status, resource_bit);
1841 return -EEXIST;
1842 }
a2fbb9ea 1843
46230476
EG		 1844 /* Try for 5 second every 5ms */
1845 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1846 /* Try to acquire the lock */
4a37fb66
YG		 1847 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1848 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1849 if (lock_status & resource_bit)
1850 return 0;
a2fbb9ea 1851
c18487ee 1852 msleep(5);
a2fbb9ea 1853 }
c18487ee
YR		 1854 DP(NETIF_MSG_HW, "Timeout\n");
1855 return -EAGAIN;
1856}
a2fbb9ea 1857
c9ee9206
VZ		 1858int bnx2x_release_leader_lock(struct bnx2x *bp)
1859{
1860 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1861}
1862
9f6c9258 1863int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1864{
1865 u32 lock_status;
1866 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1867 int func = BP_FUNC(bp);
1868 u32 hw_lock_control_reg;
a2fbb9ea 1869
72fd0718
VZ		 1870 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1871
c18487ee
YR		 1872 /* Validating that the resource is within range */
1873 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1874 DP(NETIF_MSG_HW,
1875 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1876 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1877 return -EINVAL;
1878 }
1879
4a37fb66
YG		 1880 if (func <= 5) {
1881 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1882 } else {
1883 hw_lock_control_reg =
1884 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1885 }
1886
c18487ee 1887 /* Validating that the resource is currently taken */
4a37fb66 1888 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1889 if (!(lock_status & resource_bit)) {
1890 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1891 lock_status, resource_bit);
1892 return -EFAULT;
a2fbb9ea
ET		 1893 }
1894
9f6c9258
DK		 1895 REG_WR(bp, hw_lock_control_reg, resource_bit);
1896 return 0;
c18487ee 1897}
a2fbb9ea 1898
9f6c9258 1899
4acac6a5
EG		 1900int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1901{
1902 /* The GPIO should be swapped if swap register is set and active */
1903 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1904 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1905 int gpio_shift = gpio_num +
1906 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1907 u32 gpio_mask = (1 << gpio_shift);
1908 u32 gpio_reg;
1909 int value;
1910
1911 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1912 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1913 return -EINVAL;
1914 }
1915
1916 /* read GPIO value */
1917 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1918
1919 /* get the requested pin value */
1920 if ((gpio_reg & gpio_mask) == gpio_mask)
1921 value = 1;
1922 else
1923 value = 0;
1924
1925 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1926
1927 return value;
1928}
1929
17de50b7 1930int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1931{
1932 /* The GPIO should be swapped if swap register is set and active */
1933 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1934 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1935 int gpio_shift = gpio_num +
1936 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1937 u32 gpio_mask = (1 << gpio_shift);
1938 u32 gpio_reg;
a2fbb9ea 1939
c18487ee
YR		 1940 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1941 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1942 return -EINVAL;
1943 }
a2fbb9ea 1944
4a37fb66 1945 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1946 /* read GPIO and mask except the float bits */
1947 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1948
c18487ee
YR		 1949 switch (mode) {
1950 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1951 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1952 gpio_num, gpio_shift);
1953 /* clear FLOAT and set CLR */
1954 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1955 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1956 break;
a2fbb9ea 1957
c18487ee
YR		 1958 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1959 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1960 gpio_num, gpio_shift);
1961 /* clear FLOAT and set SET */
1962 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1963 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1964 break;
a2fbb9ea 1965
17de50b7 1966 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1967 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1968 gpio_num, gpio_shift);
1969 /* set FLOAT */
1970 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1971 break;
a2fbb9ea 1972
c18487ee
YR		 1973 default:
1974 break;
a2fbb9ea
ET		 1975 }
1976
c18487ee 1977 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1978 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1979
c18487ee 1980 return 0;
a2fbb9ea
ET		 1981}
1982
0d40f0d4
YR		 1983int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1984{
1985 u32 gpio_reg = 0;
1986 int rc = 0;
1987
1988 /* Any port swapping should be handled by caller. */
1989
1990 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1991 /* read GPIO and mask except the float bits */
1992 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1993 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1996
1997 switch (mode) {
1998 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1999 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2000 /* set CLR */
2001 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2002 break;
2003
2004 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2005 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2006 /* set SET */
2007 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2008 break;
2009
2010 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2011 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2012 /* set FLOAT */
2013 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2014 break;
2015
2016 default:
2017 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2018 rc = -EINVAL;
2019 break;
2020 }
2021
2022 if (rc == 0)
2023 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2024
2025 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2026
2027 return rc;
2028}
2029
4acac6a5
EG		 2030int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2031{
2032 /* The GPIO should be swapped if swap register is set and active */
2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035 int gpio_shift = gpio_num +
2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037 u32 gpio_mask = (1 << gpio_shift);
2038 u32 gpio_reg;
2039
2040 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2042 return -EINVAL;
2043 }
2044
2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2046 /* read GPIO int */
2047 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2048
2049 switch (mode) {
2050 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2051 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2052 "output low\n", gpio_num, gpio_shift);
2053 /* clear SET and set CLR */
2054 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2055 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2056 break;
2057
2058 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2059 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2060 "output high\n", gpio_num, gpio_shift);
2061 /* clear CLR and set SET */
2062 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2063 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2064 break;
2065
2066 default:
2067 break;
2068 }
2069
2070 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2071 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2072
2073 return 0;
2074}
2075
c18487ee 2076static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 2077{
c18487ee
YR		 2078 u32 spio_mask = (1 << spio_num);
2079 u32 spio_reg;
a2fbb9ea 2080
c18487ee
YR		 2081 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2082 (spio_num > MISC_REGISTERS_SPIO_7)) {
2083 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2084 return -EINVAL;
a2fbb9ea
ET		 2085 }
2086
4a37fb66 2087 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 2088 /* read SPIO and mask except the float bits */
2089 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 2090
c18487ee 2091 switch (mode) {
6378c025 2092 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 2093 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2094 /* clear FLOAT and set CLR */
2095 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2096 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2097 break;
a2fbb9ea 2098
6378c025 2099 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 2100 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2101 /* clear FLOAT and set SET */
2102 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2103 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2104 break;
a2fbb9ea 2105
c18487ee
YR		 2106 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2107 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2108 /* set FLOAT */
2109 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2110 break;
a2fbb9ea 2111
c18487ee
YR		 2112 default:
2113 break;
a2fbb9ea
ET		 2114 }
2115
c18487ee 2116 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2117 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2118
a2fbb9ea
ET		 2119 return 0;
2120}
2121
9f6c9258 2122void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2123{
a22f0788 2124 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2125 switch (bp->link_vars.ieee_fc &
2126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2127 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2128 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2129 ADVERTISED_Pause);
c18487ee 2130 break;
356e2385 2131
c18487ee 2132 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2133 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2134 ADVERTISED_Pause);
c18487ee 2135 break;
356e2385 2136
c18487ee 2137 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2138 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2139 break;
356e2385 2140
c18487ee 2141 default:
a22f0788 2142 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2143 ADVERTISED_Pause);
c18487ee
YR		 2144 break;
2145 }
2146}
f1410647 2147
9f6c9258 2148u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2149{
19680c48
EG		 2150 if (!BP_NOMCP(bp)) {
2151 u8 rc;
a22f0788
YR		 2152 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2153 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
19680c48 2154 /* Initialize link parameters structure variables */
8c99e7b0
YR		 2155 /* It is recommended to turn off RX FC for jumbo frames
2156 for better performance */
f2e0899f 2157 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
c0700f90 2158 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2159 else
c0700f90 2160 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2161
4a37fb66 2162 bnx2x_acquire_phy_lock(bp);
b5bf9068 2163
a22f0788 2164 if (load_mode == LOAD_DIAG) {
de6eae1f 2165 bp->link_params.loopback_mode = LOOPBACK_XGXS;
a22f0788
YR		 2166 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
2167 }
b5bf9068 2168
19680c48 2169 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2170
4a37fb66 2171 bnx2x_release_phy_lock(bp);
a2fbb9ea 2172
3c96c68b
EG		 2173 bnx2x_calc_fc_adv(bp);
2174
b5bf9068
EG		 2175 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2176 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2177 bnx2x_link_report(bp);
3deb8167
YR		 2178 } else
2179 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2180 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2181 return rc;
2182 }
f5372251 2183 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2184 return -EINVAL;
a2fbb9ea
ET		 2185}
2186
9f6c9258 2187void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2188{
19680c48 2189 if (!BP_NOMCP(bp)) {
4a37fb66 2190 bnx2x_acquire_phy_lock(bp);
54c2fb78 2191 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2192 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2193 bnx2x_release_phy_lock(bp);
a2fbb9ea 2194
19680c48
EG		 2195 bnx2x_calc_fc_adv(bp);
2196 } else
f5372251 2197 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2198}
a2fbb9ea 2199
c18487ee
YR		 2200static void bnx2x__link_reset(struct bnx2x *bp)
2201{
19680c48 2202 if (!BP_NOMCP(bp)) {
4a37fb66 2203 bnx2x_acquire_phy_lock(bp);
589abe3a 2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2205 bnx2x_release_phy_lock(bp);
19680c48 2206 } else
f5372251 2207 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2208}
a2fbb9ea 2209
a22f0788 2210u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2211{
2145a920 2212 u8 rc = 0;
a2fbb9ea 2213
2145a920
VZ		 2214 if (!BP_NOMCP(bp)) {
2215 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2216 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2217 is_serdes);
2145a920
VZ		 2218 bnx2x_release_phy_lock(bp);
2219 } else
2220 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2221
c18487ee
YR		 2222 return rc;
2223}
a2fbb9ea 2224
8a1c38d1 2225static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 2226{
8a1c38d1
EG		 2227 u32 r_param = bp->link_vars.line_speed / 8;
2228 u32 fair_periodic_timeout_usec;
2229 u32 t_fair;
34f80b04 2230
8a1c38d1
EG		 2231 memset(&(bp->cmng.rs_vars), 0,
2232 sizeof(struct rate_shaping_vars_per_port));
2233 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 2234
8a1c38d1
EG		 2235 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2236 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 2237
8a1c38d1
EG		 2238 /* this is the threshold below which no timer arming will occur
2239 1.25 coefficient is for the threshold to be a little bigger
2240 than the real time, to compensate for timer in-accuracy */
2241 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 2242 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2243
8a1c38d1
EG		 2244 /* resolution of fairness timer */
2245 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2246 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2247 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 2248
8a1c38d1
EG		 2249 /* this is the threshold below which we won't arm the timer anymore */
2250 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 2251
8a1c38d1
EG		 2252 /* we multiply by 1e3/8 to get bytes/msec.
2253 We don't want the credits to pass a credit
2254 of the t_fair*FAIR_MEM (algorithm resolution) */
2255 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2256 /* since each tick is 4 usec */
2257 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 2258}
2259
2691d51d
EG		 2260/* Calculates the sum of vn_min_rates.
2261 It's needed for further normalizing of the min_rates.
2262 Returns:
2263 sum of vn_min_rates.
2264 or
2265 0 - if all the min_rates are 0.
2266 In the later case fainess algorithm should be deactivated.
2267 If not all min_rates are zero then those that are zeroes will be set to 1.
2268 */
2269static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2270{
2271 int all_zero = 1;
2691d51d
EG		 2272 int vn;
2273
2274 bp->vn_weight_sum = 0;
2275 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 2276 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2277 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2278 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2279
2280 /* Skip hidden vns */
2281 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2282 continue;
2283
2284 /* If min rate is zero - set it to 1 */
2285 if (!vn_min_rate)
2286 vn_min_rate = DEF_MIN_RATE;
2287 else
2288 all_zero = 0;
2289
2290 bp->vn_weight_sum += vn_min_rate;
2291 }
2292
30ae438b
DK		 2293 /* if ETS or all min rates are zeros - disable fairness */
2294 if (BNX2X_IS_ETS_ENABLED(bp)) {
2295 bp->cmng.flags.cmng_enables &=
2296 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2297 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2298 } else if (all_zero) {
b015e3d1
EG		 2299 bp->cmng.flags.cmng_enables &=
2300 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2301 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2302 " fairness will be disabled\n");
2303 } else
2304 bp->cmng.flags.cmng_enables |=
2305 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2306}
2307
f2e0899f 2308static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 2309{
2310 struct rate_shaping_vars_per_vn m_rs_vn;
2311 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 2312 u32 vn_cfg = bp->mf_config[vn];
2313 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 2314 u16 vn_min_rate, vn_max_rate;
2315 int i;
2316
2317 /* If function is hidden - set min and max to zeroes */
2318 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2319 vn_min_rate = 0;
2320 vn_max_rate = 0;
2321
2322 } else {
faa6fcbb
DK		 2323 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2324
34f80b04
EG		 2325 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2326 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 2327 /* If fairness is enabled (not all min rates are zeroes) and
2328 if current min rate is zero - set it to 1.
2329 This is a requirement of the algorithm. */
f2e0899f 2330 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 2331 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 2332
2333 if (IS_MF_SI(bp))
2334 /* maxCfg in percents of linkspeed */
2335 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2336 else
2337 /* maxCfg is absolute in 100Mb units */
2338 vn_max_rate = maxCfg * 100;
34f80b04 2339 }
f85582f8 2340
8a1c38d1 2341 DP(NETIF_MSG_IFUP,
b015e3d1 2342 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 2343 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 2344
2345 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2346 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2347
2348 /* global vn counter - maximal Mbps for this vn */
2349 m_rs_vn.vn_counter.rate = vn_max_rate;
2350
2351 /* quota - number of bytes transmitted in this period */
2352 m_rs_vn.vn_counter.quota =
2353 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2354
8a1c38d1 2355 if (bp->vn_weight_sum) {
34f80b04
EG		 2356 /* credit for each period of the fairness algorithm:
2357 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2358 vn_weight_sum should not be larger than 10000, thus
2359 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2360 than zero */
34f80b04 2361 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2362 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2363 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2364 (bp->cmng.fair_vars.fair_threshold +
2365 MIN_ABOVE_THRESH));
cdaa7cb8 2366 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2367 m_fair_vn.vn_credit_delta);
2368 }
2369
34f80b04
EG		 2370 /* Store it to internal memory */
2371 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2372 REG_WR(bp, BAR_XSTRORM_INTMEM +
2373 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2374 ((u32 *)(&m_rs_vn))[i]);
2375
2376 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2377 REG_WR(bp, BAR_XSTRORM_INTMEM +
2378 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2379 ((u32 *)(&m_fair_vn))[i]);
2380}
f85582f8 2381
523224a3
DK		 2382static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2383{
2384 if (CHIP_REV_IS_SLOW(bp))
2385 return CMNG_FNS_NONE;
fb3bff17 2386 if (IS_MF(bp))
523224a3
DK		 2387 return CMNG_FNS_MINMAX;
2388
2389 return CMNG_FNS_NONE;
2390}
2391
2ae17f66 2392void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2393{
0793f83f 2394 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2395
2396 if (BP_NOMCP(bp))
2397 return; /* what should be the default bvalue in this case */
2398
0793f83f
DK		 2399 /* For 2 port configuration the absolute function number formula
2400 * is:
2401 * abs_func = 2 * vn + BP_PORT + BP_PATH
2402 *
2403 * and there are 4 functions per port
2404 *
2405 * For 4 port configuration it is
2406 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2407 *
2408 * and there are 2 functions per port
2409 */
523224a3 2410 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2411 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2412
2413 if (func >= E1H_FUNC_MAX)
2414 break;
2415
f2e0899f 2416 bp->mf_config[vn] =
523224a3
DK		 2417 MF_CFG_RD(bp, func_mf_config[func].config);
2418 }
2419}
2420
2421static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2422{
2423
2424 if (cmng_type == CMNG_FNS_MINMAX) {
2425 int vn;
2426
2427 /* clear cmng_enables */
2428 bp->cmng.flags.cmng_enables = 0;
2429
2430 /* read mf conf from shmem */
2431 if (read_cfg)
2432 bnx2x_read_mf_cfg(bp);
2433
2434 /* Init rate shaping and fairness contexts */
2435 bnx2x_init_port_minmax(bp);
2436
2437 /* vn_weight_sum and enable fairness if not 0 */
2438 bnx2x_calc_vn_weight_sum(bp);
2439
2440 /* calculate and set min-max rate for each vn */
c4154f25
DK		 2441 if (bp->port.pmf)
2442 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2443 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2444
2445 /* always enable rate shaping and fairness */
2446 bp->cmng.flags.cmng_enables |=
2447 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2448 if (!bp->vn_weight_sum)
2449 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2450 " fairness will be disabled\n");
2451 return;
2452 }
2453
2454 /* rate shaping and fairness are disabled */
2455 DP(NETIF_MSG_IFUP,
2456 "rate shaping and fairness are disabled\n");
2457}
34f80b04 2458
523224a3
DK		 2459static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2460{
2461 int port = BP_PORT(bp);
2462 int func;
2463 int vn;
2464
2465 /* Set the attention towards other drivers on the same port */
2466 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2467 if (vn == BP_E1HVN(bp))
2468 continue;
2469
2470 func = ((vn << 1) | port);
2471 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2472 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2473 }
2474}
8a1c38d1 2475
c18487ee
YR		 2476/* This function is called upon link interrupt */
2477static void bnx2x_link_attn(struct bnx2x *bp)
2478{
bb2a0f7a
YG		 2479 /* Make sure that we are synced with the current statistics */
2480 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2481
c18487ee 2482 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2483
bb2a0f7a
YG		 2484 if (bp->link_vars.link_up) {
2485
1c06328c 2486 /* dropless flow control */
f2e0899f 2487 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2488 int port = BP_PORT(bp);
2489 u32 pause_enabled = 0;
2490
2491 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2492 pause_enabled = 1;
2493
2494 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2495 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2496 pause_enabled);
2497 }
2498
619c5cb6 2499 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2500 struct host_port_stats *pstats;
2501
2502 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2503 /* reset old mac stats */
bb2a0f7a
YG		 2504 memset(&(pstats->mac_stx[0]), 0,
2505 sizeof(struct mac_stx));
2506 }
f34d28ea 2507 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2508 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2509 }
2510
f2e0899f
DK		 2511 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2512 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2513
f2e0899f
DK		 2514 if (cmng_fns != CMNG_FNS_NONE) {
2515 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2516 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2517 } else
2518 /* rate shaping and fairness are disabled */
2519 DP(NETIF_MSG_IFUP,
2520 "single function mode without fairness\n");
34f80b04 2521 }
9fdc3e95 2522
2ae17f66
VZ		 2523 __bnx2x_link_report(bp);
2524
9fdc3e95
DK		 2525 if (IS_MF(bp))
2526 bnx2x_link_sync_notify(bp);
c18487ee 2527}
a2fbb9ea 2528
9f6c9258 2529void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2530{
2ae17f66 2531 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2532 return;
a2fbb9ea 2533
c18487ee 2534 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2535
bb2a0f7a
YG		 2536 if (bp->link_vars.link_up)
2537 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2538 else
2539 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2540
c18487ee
YR		 2541 /* indicate link status */
2542 bnx2x_link_report(bp);
a2fbb9ea 2543}
a2fbb9ea 2544
34f80b04
EG		 2545static void bnx2x_pmf_update(struct bnx2x *bp)
2546{
2547 int port = BP_PORT(bp);
2548 u32 val;
2549
2550 bp->port.pmf = 1;
2551 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2552
3deb8167
YR		 2553 /*
2554 * We need the mb() to ensure the ordering between the writing to
2555 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2556 */
2557 smp_mb();
2558
2559 /* queue a periodic task */
2560 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2561
ef01854e
DK		 2562 bnx2x_dcbx_pmf_update(bp);
2563
34f80b04
EG		 2564 /* enable nig attention */
2565 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2566 if (bp->common.int_block == INT_BLOCK_HC) {
2567 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2568 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2569 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2570 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2571 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2572 }
bb2a0f7a
YG		 2573
2574 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2575}
2576
c18487ee 2577/* end of Link */
a2fbb9ea
ET		 2578
2579/* slow path */
2580
2581/*
2582 * General service functions
2583 */
2584
2691d51d 2585/* send the MCP a request, block until there is a reply */
a22f0788 2586u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2587{
f2e0899f 2588 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2589 u32 seq;
2691d51d
EG		 2590 u32 rc = 0;
2591 u32 cnt = 1;
2592 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2593
c4ff7cbf 2594 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2595 seq = ++bp->fw_seq;
f2e0899f
DK		 2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2597 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2598
754a2f52
DK		 2599 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2600 (command | seq), param);
2691d51d
EG		 2601
2602 do {
2603 /* let the FW do it's magic ... */
2604 msleep(delay);
2605
f2e0899f 2606 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2607
c4ff7cbf
EG		 2608 /* Give the FW up to 5 second (500*10ms) */
2609 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2610
2611 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2612 cnt*delay, rc, seq);
2613
2614 /* is this a reply to our command? */
2615 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2616 rc &= FW_MSG_CODE_MASK;
2617 else {
2618 /* FW BUG! */
2619 BNX2X_ERR("FW failed to respond!\n");
2620 bnx2x_fw_dump(bp);
2621 rc = 0;
2622 }
c4ff7cbf 2623 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2624
2625 return rc;
2626}
2627
ec6ba945
VZ		 2628static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2629{
2630#ifdef BCM_CNIC
619c5cb6
VZ		 2631 /* Statistics are not supported for CNIC Clients at the moment */
2632 if (IS_FCOE_FP(fp))
ec6ba945
VZ		 2633 return false;
2634#endif
2635 return true;
2636}
2637
619c5cb6
VZ		 2638void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2639{
2640 if (CHIP_IS_E1x(bp)) {
2641 struct tstorm_eth_function_common_config tcfg = {0};
2642
2643 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2644 }
2645
2646 /* Enable the function in the FW */
2647 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2648 storm_memset_func_en(bp, p->func_id, 1);
2649
2650 /* spq */
2651 if (p->func_flgs & FUNC_FLG_SPQ) {
2652 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2653 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2654 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2655 }
2656}
2657
6383c0b3
AE		 2658/**
2659 * bnx2x_get_tx_only_flags - Return common flags
2660 *
2661 * @bp device handle
2662 * @fp queue handle
2663 * @zero_stats TRUE if statistics zeroing is needed
2664 *
2665 * Return the flags that are common for the Tx-only and not normal connections.
2666 */
2667static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2668 struct bnx2x_fastpath *fp,
2669 bool zero_stats)
28912902 2670{
619c5cb6
VZ		 2671 unsigned long flags = 0;
2672
2673 /* PF driver will always initialize the Queue to an ACTIVE state */
2674 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2675
6383c0b3
AE		 2676 /* tx only connections collect statistics (on the same index as the
2677 * parent connection). The statistics are zeroed when the parent
2678 * connection is initialized.
2679 */
2680 if (stat_counter_valid(bp, fp)) {
2681 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2682 if (zero_stats)
2683 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2684 }
2685
2686 return flags;
2687}
2688
2689static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2690 struct bnx2x_fastpath *fp,
2691 bool leading)
2692{
2693 unsigned long flags = 0;
2694
619c5cb6
VZ		 2695 /* calculate other queue flags */
2696 if (IS_MF_SD(bp))
2697 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2698
619c5cb6
VZ		 2699 if (IS_FCOE_FP(fp))
2700 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3 2701
f5219d8e 2702 if (!fp->disable_tpa) {
619c5cb6 2703 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e
VZ		 2704 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2705 }
619c5cb6 2706
619c5cb6
VZ		 2707 if (leading) {
2708 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2709 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2710 }
523224a3 2711
619c5cb6
VZ		 2712 /* Always set HW VLAN stripping */
2713 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2714
6383c0b3
AE		 2715
2716 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2717}
2718
619c5cb6 2719static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2720 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2721 u8 cos)
619c5cb6
VZ		 2722{
2723 gen_init->stat_id = bnx2x_stats_id(fp);
2724 gen_init->spcl_id = fp->cl_id;
2725
2726 /* Always use mini-jumbo MTU for FCoE L2 ring */
2727 if (IS_FCOE_FP(fp))
2728 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2729 else
2730 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2731
2732 gen_init->cos = cos;
619c5cb6
VZ		 2733}
2734
2735static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2736 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2737 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2738{
619c5cb6 2739 u8 max_sge = 0;
523224a3
DK		 2740 u16 sge_sz = 0;
2741 u16 tpa_agg_size = 0;
2742
523224a3
DK		 2743 if (!fp->disable_tpa) {
2744 pause->sge_th_hi = 250;
2745 pause->sge_th_lo = 150;
2746 tpa_agg_size = min_t(u32,
2747 (min_t(u32, 8, MAX_SKB_FRAGS) *
2748 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2749 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2750 SGE_PAGE_SHIFT;
2751 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2752 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2753 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2754 0xffff);
2755 }
2756
2757 /* pause - not for e1 */
2758 if (!CHIP_IS_E1(bp)) {
2759 pause->bd_th_hi = 350;
2760 pause->bd_th_lo = 250;
2761 pause->rcq_th_hi = 350;
2762 pause->rcq_th_lo = 250;
619c5cb6 2763
523224a3
DK		 2764 pause->pri_map = 1;
2765 }
2766
2767 /* rxq setup */
523224a3
DK		 2768 rxq_init->dscr_map = fp->rx_desc_mapping;
2769 rxq_init->sge_map = fp->rx_sge_mapping;
2770 rxq_init->rcq_map = fp->rx_comp_mapping;
2771 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2772
619c5cb6
VZ		 2773 /* This should be a maximum number of data bytes that may be
2774 * placed on the BD (not including paddings).
2775 */
2776 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2777 IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2778
523224a3 2779 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2780 rxq_init->tpa_agg_sz = tpa_agg_size;
2781 rxq_init->sge_buf_sz = sge_sz;
2782 rxq_init->max_sges_pkt = max_sge;
619c5cb6
VZ		 2783 rxq_init->rss_engine_id = BP_FUNC(bp);
2784
2785 /* Maximum number or simultaneous TPA aggregation for this Queue.
2786 *
2787 * For PF Clients it should be the maximum avaliable number.
2788 * VF driver(s) may want to define it to a smaller value.
2789 */
2790 rxq_init->max_tpa_queues =
2791 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2792 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2793
523224a3
DK		 2794 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2795 rxq_init->fw_sb_id = fp->fw_sb_id;
2796
ec6ba945
VZ		 2797 if (IS_FCOE_FP(fp))
2798 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2799 else
6383c0b3 2800 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
523224a3
DK		 2801}
2802
619c5cb6 2803static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 2804 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2805 u8 cos)
523224a3 2806{
6383c0b3
AE		 2807 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2808 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 2809 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2810 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2811
619c5cb6
VZ		 2812 /*
2813 * set the tss leading client id for TX classfication ==
2814 * leading RSS client id
2815 */
2816 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2817
ec6ba945
VZ		 2818 if (IS_FCOE_FP(fp)) {
2819 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2820 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2821 }
523224a3
DK		 2822}
2823
8d96286a 2824static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2825{
2826 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2827 struct event_ring_data eq_data = { {0} };
2828 u16 flags;
2829
619c5cb6 2830 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2831 /* reset IGU PF statistics: MSIX + ATTN */
2832 /* PF */
2833 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2834 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2835 (CHIP_MODE_IS_4_PORT(bp) ?
2836 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2837 /* ATTN */
2838 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2839 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2840 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2841 (CHIP_MODE_IS_4_PORT(bp) ?
2842 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2843 }
2844
523224a3
DK		 2845 /* function setup flags */
2846 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2847
619c5cb6
VZ		 2848 /* This flag is relevant for E1x only.
2849 * E2 doesn't have a TPA configuration in a function level.
523224a3 2850 */
619c5cb6 2851 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2852
2853 func_init.func_flgs = flags;
2854 func_init.pf_id = BP_FUNC(bp);
2855 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2856 func_init.spq_map = bp->spq_mapping;
2857 func_init.spq_prod = bp->spq_prod_idx;
2858
2859 bnx2x_func_init(bp, &func_init);
2860
2861 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2862
2863 /*
619c5cb6
VZ		 2864 * Congestion management values depend on the link rate
2865 * There is no active link so initial link rate is set to 10 Gbps.
2866 * When the link comes up The congestion management values are
2867 * re-calculated according to the actual link rate.
2868 */
523224a3
DK		 2869 bp->link_vars.line_speed = SPEED_10000;
2870 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2871
2872 /* Only the PMF sets the HW */
2873 if (bp->port.pmf)
2874 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2875
523224a3
DK		 2876 /* init Event Queue */
2877 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2878 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2879 eq_data.producer = bp->eq_prod;
2880 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2881 eq_data.sb_id = DEF_SB_ID;
2882 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2883}
2884
2885
2886static void bnx2x_e1h_disable(struct bnx2x *bp)
2887{
2888 int port = BP_PORT(bp);
2889
619c5cb6 2890 bnx2x_tx_disable(bp);
523224a3
DK		 2891
2892 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2893}
2894
2895static void bnx2x_e1h_enable(struct bnx2x *bp)
2896{
2897 int port = BP_PORT(bp);
2898
2899 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2900
2901 /* Tx queue should be only reenabled */
2902 netif_tx_wake_all_queues(bp->dev);
2903
2904 /*
2905 * Should not call netif_carrier_on since it will be called if the link
2906 * is up when checking for link state
2907 */
2908}
2909
0793f83f
DK		 2910/* called due to MCP event (on pmf):
2911 * reread new bandwidth configuration
2912 * configure FW
2913 * notify others function about the change
2914 */
2915static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2916{
2917 if (bp->link_vars.link_up) {
2918 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2919 bnx2x_link_sync_notify(bp);
2920 }
2921 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2922}
2923
2924static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2925{
2926 bnx2x_config_mf_bw(bp);
2927 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2928}
2929
523224a3
DK		 2930static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2931{
2932 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2933
2934 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2935
2936 /*
2937 * This is the only place besides the function initialization
2938 * where the bp->flags can change so it is done without any
2939 * locks
2940 */
f2e0899f 2941 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2942 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2943 bp->flags |= MF_FUNC_DIS;
2944
2945 bnx2x_e1h_disable(bp);
2946 } else {
2947 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2948 bp->flags &= ~MF_FUNC_DIS;
2949
2950 bnx2x_e1h_enable(bp);
2951 }
2952 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2953 }
2954 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2955 bnx2x_config_mf_bw(bp);
523224a3
DK		 2956 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2957 }
2958
2959 /* Report results to MCP */
2960 if (dcc_event)
2961 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2962 else
2963 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2964}
2965
2966/* must be called under the spq lock */
2967static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2968{
2969 struct eth_spe *next_spe = bp->spq_prod_bd;
2970
2971 if (bp->spq_prod_bd == bp->spq_last_bd) {
2972 bp->spq_prod_bd = bp->spq;
2973 bp->spq_prod_idx = 0;
2974 DP(NETIF_MSG_TIMER, "end of spq\n");
2975 } else {
2976 bp->spq_prod_bd++;
2977 bp->spq_prod_idx++;
2978 }
2979 return next_spe;
2980}
2981
2982/* must be called under the spq lock */
28912902
MC		 2983static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2984{
2985 int func = BP_FUNC(bp);
2986
53e51e2f
VZ		 2987 /*
2988 * Make sure that BD data is updated before writing the producer:
2989 * BD data is written to the memory, the producer is read from the
2990 * memory, thus we need a full memory barrier to ensure the ordering.
2991 */
2992 mb();
28912902 2993
523224a3 2994 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 2995 bp->spq_prod_idx);
28912902
MC		 2996 mmiowb();
2997}
2998
619c5cb6
VZ		 2999/**
3000 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3001 *
3002 * @cmd: command to check
3003 * @cmd_type: command type
3004 */
3005static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3006{
3007 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3008 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3009 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3010 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3011 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3012 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3013 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3014 return true;
3015 else
3016 return false;
3017
3018}
3019
3020
3021/**
3022 * bnx2x_sp_post - place a single command on an SP ring
3023 *
3024 * @bp: driver handle
3025 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3026 * @cid: SW CID the command is related to
3027 * @data_hi: command private data address (high 32 bits)
3028 * @data_lo: command private data address (low 32 bits)
3029 * @cmd_type: command type (e.g. NONE, ETH)
3030 *
3031 * SP data is handled as if it's always an address pair, thus data fields are
3032 * not swapped to little endian in upper functions. Instead this function swaps
3033 * data as if it's two u32 fields.
3034 */
9f6c9258 3035int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3036 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3037{
28912902 3038 struct eth_spe *spe;
523224a3 3039 u16 type;
619c5cb6 3040 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3041
a2fbb9ea
ET		 3042#ifdef BNX2X_STOP_ON_ERROR
3043 if (unlikely(bp->panic))
3044 return -EIO;
3045#endif
3046
34f80b04 3047 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3048
6e30dd4e
VZ		 3049 if (common) {
3050 if (!atomic_read(&bp->eq_spq_left)) {
3051 BNX2X_ERR("BUG! EQ ring full!\n");
3052 spin_unlock_bh(&bp->spq_lock);
3053 bnx2x_panic();
3054 return -EBUSY;
3055 }
3056 } else if (!atomic_read(&bp->cq_spq_left)) {
3057 BNX2X_ERR("BUG! SPQ ring full!\n");
3058 spin_unlock_bh(&bp->spq_lock);
3059 bnx2x_panic();
3060 return -EBUSY;
a2fbb9ea 3061 }
f1410647 3062
28912902
MC		 3063 spe = bnx2x_sp_get_next(bp);
3064
a2fbb9ea 3065 /* CID needs port number to be encoded int it */
28912902 3066 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3067 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3068 HW_CID(bp, cid));
523224a3 3069
619c5cb6 3070 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3071
523224a3
DK		 3072 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3073 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3074
523224a3
DK		 3075 spe->hdr.type = cpu_to_le16(type);
3076
3077 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3078 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3079
3080 /* stats ramrod has it's own slot on the spq */
6e30dd4e 3081 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
619c5cb6
VZ		 3082 /*
3083 * It's ok if the actual decrement is issued towards the memory
523224a3
DK		 3084 * somewhere between the spin_lock and spin_unlock. Thus no
3085 * more explict memory barrier is needed.
3086 */
6e30dd4e
VZ		 3087 if (common)
3088 atomic_dec(&bp->eq_spq_left);
3089 else
3090 atomic_dec(&bp->cq_spq_left);
3091 }
3092
a2fbb9ea 3093
cdaa7cb8 3094 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
523224a3 3095 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
6e30dd4e 3096 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
cdaa7cb8
VZ		 3097 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3098 (u32)(U64_LO(bp->spq_mapping) +
3099 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
6e30dd4e
VZ		 3100 HW_CID(bp, cid), data_hi, data_lo, type,
3101 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3102
28912902 3103 bnx2x_sp_prod_update(bp);
34f80b04 3104 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3105 return 0;
3106}
3107
3108/* acquire split MCP access lock register */
4a37fb66 3109static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3110{
72fd0718 3111 u32 j, val;
34f80b04 3112 int rc = 0;
a2fbb9ea
ET		 3113
3114 might_sleep();
72fd0718 3115 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3116 val = (1UL << 31);
3117 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3118 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3119 if (val & (1L << 31))
3120 break;
3121
3122 msleep(5);
3123 }
a2fbb9ea 3124 if (!(val & (1L << 31))) {
19680c48 3125 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3126 rc = -EBUSY;
3127 }
3128
3129 return rc;
3130}
3131
4a37fb66
YG		 3132/* release split MCP access lock register */
3133static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3134{
72fd0718 3135 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3136}
3137
523224a3
DK		 3138#define BNX2X_DEF_SB_ATT_IDX 0x0001
3139#define BNX2X_DEF_SB_IDX 0x0002
3140
a2fbb9ea
ET		 3141static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3142{
523224a3 3143 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3144 u16 rc = 0;
3145
3146 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3147 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3148 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3149 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3150 }
523224a3
DK		 3151
3152 if (bp->def_idx != def_sb->sp_sb.running_index) {
3153 bp->def_idx = def_sb->sp_sb.running_index;
3154 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3155 }
523224a3
DK		 3156
3157 /* Do not reorder: indecies reading should complete before handling */
3158 barrier();
a2fbb9ea
ET		 3159 return rc;
3160}
3161
3162/*
3163 * slow path service functions
3164 */
3165
3166static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3167{
34f80b04 3168 int port = BP_PORT(bp);
a2fbb9ea
ET		 3169 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3170 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3171 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3172 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3173 u32 aeu_mask;
87942b46 3174 u32 nig_mask = 0;
f2e0899f 3175 u32 reg_addr;
a2fbb9ea 3176
a2fbb9ea
ET		 3177 if (bp->attn_state & asserted)
3178 BNX2X_ERR("IGU ERROR\n");
3179
3fcaf2e5
EG		 3180 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3181 aeu_mask = REG_RD(bp, aeu_addr);
3182
a2fbb9ea 3183 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3184 aeu_mask, asserted);
72fd0718 3185 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3186 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3187
3fcaf2e5
EG		 3188 REG_WR(bp, aeu_addr, aeu_mask);
3189 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3190
3fcaf2e5 3191 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3192 bp->attn_state |= asserted;
3fcaf2e5 3193 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3194
3195 if (asserted & ATTN_HARD_WIRED_MASK) {
3196 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3197
a5e9a7cf
EG		 3198 bnx2x_acquire_phy_lock(bp);
3199
877e9aa4 3200 /* save nig interrupt mask */
87942b46 3201 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3202
361c391e
YR		 3203 /* If nig_mask is not set, no need to call the update
3204 * function.
3205 */
3206 if (nig_mask) {
3207 REG_WR(bp, nig_int_mask_addr, 0);
3208
3209 bnx2x_link_attn(bp);
3210 }
a2fbb9ea
ET		 3211
3212 /* handle unicore attn? */
3213 }
3214 if (asserted & ATTN_SW_TIMER_4_FUNC)
3215 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3216
3217 if (asserted & GPIO_2_FUNC)
3218 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3219
3220 if (asserted & GPIO_3_FUNC)
3221 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3222
3223 if (asserted & GPIO_4_FUNC)
3224 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3225
3226 if (port == 0) {
3227 if (asserted & ATTN_GENERAL_ATTN_1) {
3228 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3229 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3230 }
3231 if (asserted & ATTN_GENERAL_ATTN_2) {
3232 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3233 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3234 }
3235 if (asserted & ATTN_GENERAL_ATTN_3) {
3236 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3237 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3238 }
3239 } else {
3240 if (asserted & ATTN_GENERAL_ATTN_4) {
3241 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3242 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3243 }
3244 if (asserted & ATTN_GENERAL_ATTN_5) {
3245 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3246 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3247 }
3248 if (asserted & ATTN_GENERAL_ATTN_6) {
3249 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3250 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3251 }
3252 }
3253
3254 } /* if hardwired */
3255
f2e0899f
DK		 3256 if (bp->common.int_block == INT_BLOCK_HC)
3257 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3258 COMMAND_REG_ATTN_BITS_SET);
3259 else
3260 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3261
3262 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3263 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3264 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3265
3266 /* now set back the mask */
a5e9a7cf 3267 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3268 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3269 bnx2x_release_phy_lock(bp);
3270 }
a2fbb9ea
ET		 3271}
3272
fd4ef40d
EG		 3273static inline void bnx2x_fan_failure(struct bnx2x *bp)
3274{
3275 int port = BP_PORT(bp);
b7737c9b 3276 u32 ext_phy_config;
fd4ef40d 3277 /* mark the failure */
b7737c9b
YR		 3278 ext_phy_config =
3279 SHMEM_RD(bp,
3280 dev_info.port_hw_config[port].external_phy_config);
3281
3282 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3283 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3284 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3285 ext_phy_config);
fd4ef40d
EG		 3286
3287 /* log the failure */
cdaa7cb8
VZ		 3288 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3289 " the driver to shutdown the card to prevent permanent"
3290 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 3291}
ab6ad5a4 3292
877e9aa4 3293static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3294{
34f80b04 3295 int port = BP_PORT(bp);
877e9aa4 3296 int reg_offset;
d90d96ba 3297 u32 val;
877e9aa4 3298
34f80b04
EG		 3299 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3300 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3301
34f80b04 3302 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3303
3304 val = REG_RD(bp, reg_offset);
3305 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3306 REG_WR(bp, reg_offset, val);
3307
3308 BNX2X_ERR("SPIO5 hw attention\n");
3309
fd4ef40d 3310 /* Fan failure attention */
d90d96ba 3311 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3312 bnx2x_fan_failure(bp);
877e9aa4 3313 }
34f80b04 3314
3deb8167 3315 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3316 bnx2x_acquire_phy_lock(bp);
3317 bnx2x_handle_module_detect_int(&bp->link_params);
3318 bnx2x_release_phy_lock(bp);
3319 }
3320
34f80b04
EG		 3321 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3322
3323 val = REG_RD(bp, reg_offset);
3324 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3325 REG_WR(bp, reg_offset, val);
3326
3327 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3328 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3329 bnx2x_panic();
3330 }
877e9aa4
ET		 3331}
3332
3333static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3334{
3335 u32 val;
3336
0626b899 3337 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3338
3339 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3340 BNX2X_ERR("DB hw attention 0x%x\n", val);
3341 /* DORQ discard attention */
3342 if (val & 0x2)
3343 BNX2X_ERR("FATAL error from DORQ\n");
3344 }
34f80b04
EG		 3345
3346 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3347
3348 int port = BP_PORT(bp);
3349 int reg_offset;
3350
3351 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3352 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3353
3354 val = REG_RD(bp, reg_offset);
3355 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3356 REG_WR(bp, reg_offset, val);
3357
3358 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3359 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3360 bnx2x_panic();
3361 }
877e9aa4
ET		 3362}
3363
3364static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3365{
3366 u32 val;
3367
3368 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3369
3370 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3371 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3372 /* CFC error attention */
3373 if (val & 0x2)
3374 BNX2X_ERR("FATAL error from CFC\n");
3375 }
3376
3377 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3378 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3379 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3380 /* RQ_USDMDP_FIFO_OVERFLOW */
3381 if (val & 0x18000)
3382 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3383
3384 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3385 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3386 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3387 }
877e9aa4 3388 }
34f80b04
EG		 3389
3390 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3391
3392 int port = BP_PORT(bp);
3393 int reg_offset;
3394
3395 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3396 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3397
3398 val = REG_RD(bp, reg_offset);
3399 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3400 REG_WR(bp, reg_offset, val);
3401
3402 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3403 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3404 bnx2x_panic();
3405 }
877e9aa4
ET		 3406}
3407
3408static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3409{
34f80b04
EG		 3410 u32 val;
3411
877e9aa4
ET		 3412 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3413
34f80b04
EG		 3414 if (attn & BNX2X_PMF_LINK_ASSERT) {
3415 int func = BP_FUNC(bp);
3416
3417 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3418 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3419 func_mf_config[BP_ABS_FUNC(bp)].config);
3420 val = SHMEM_RD(bp,
3421 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3422 if (val & DRV_STATUS_DCC_EVENT_MASK)
3423 bnx2x_dcc_event(bp,
3424 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3425
3426 if (val & DRV_STATUS_SET_MF_BW)
3427 bnx2x_set_mf_bw(bp);
3428
2691d51d 3429 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3430 bnx2x_pmf_update(bp);
3431
e4901dde 3432 if (bp->port.pmf &&
785b9b1a
SR		 3433 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3434 bp->dcbx_enabled > 0)
e4901dde
VZ		 3435 /* start dcbx state machine */
3436 bnx2x_dcbx_set_params(bp,
3437 BNX2X_DCBX_STATE_NEG_RECEIVED);
3deb8167
YR		 3438 if (bp->link_vars.periodic_flags &
3439 PERIODIC_FLAGS_LINK_EVENT) {
3440 /* sync with link */
3441 bnx2x_acquire_phy_lock(bp);
3442 bp->link_vars.periodic_flags &=
3443 ~PERIODIC_FLAGS_LINK_EVENT;
3444 bnx2x_release_phy_lock(bp);
3445 if (IS_MF(bp))
3446 bnx2x_link_sync_notify(bp);
3447 bnx2x_link_report(bp);
3448 }
3449 /* Always call it here: bnx2x_link_report() will
3450 * prevent the link indication duplication.
3451 */
3452 bnx2x__link_status_update(bp);
34f80b04 3453 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3454
3455 BNX2X_ERR("MC assert!\n");
3456 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3457 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3458 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3459 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3460 bnx2x_panic();
3461
3462 } else if (attn & BNX2X_MCP_ASSERT) {
3463
3464 BNX2X_ERR("MCP assert!\n");
3465 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3466 bnx2x_fw_dump(bp);
877e9aa4
ET		 3467
3468 } else
3469 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3470 }
3471
3472 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3473 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3474 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3475 val = CHIP_IS_E1(bp) ? 0 :
3476 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3477 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3478 }
3479 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3480 val = CHIP_IS_E1(bp) ? 0 :
3481 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3482 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3483 }
877e9aa4 3484 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3485 }
3486}
3487
c9ee9206
VZ		 3488/*
3489 * Bits map:
3490 * 0-7 - Engine0 load counter.
3491 * 8-15 - Engine1 load counter.
3492 * 16 - Engine0 RESET_IN_PROGRESS bit.
3493 * 17 - Engine1 RESET_IN_PROGRESS bit.
3494 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3495 * on the engine
3496 * 19 - Engine1 ONE_IS_LOADED.
3497 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3498 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3499 * just the one belonging to its engine).
3500 *
3501 */
3502#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3503
3504#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3505#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3506#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3507#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3508#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3509#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3510#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3511
3512/*
3513 * Set the GLOBAL_RESET bit.
3514 *
3515 * Should be run under rtnl lock
3516 */
3517void bnx2x_set_reset_global(struct bnx2x *bp)
3518{
3519 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3520
3521 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3522 barrier();
3523 mmiowb();
3524}
3525
3526/*
3527 * Clear the GLOBAL_RESET bit.
3528 *
3529 * Should be run under rtnl lock
3530 */
3531static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3532{
3533 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3534
3535 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3536 barrier();
3537 mmiowb();
3538}
f85582f8 3539
72fd0718 3540/*
c9ee9206
VZ		 3541 * Checks the GLOBAL_RESET bit.
3542 *
72fd0718
VZ		 3543 * should be run under rtnl lock
3544 */
c9ee9206
VZ		 3545static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3546{
3547 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3548
3549 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3550 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3551}
3552
3553/*
3554 * Clear RESET_IN_PROGRESS bit for the current engine.
3555 *
3556 * Should be run under rtnl lock
3557 */
72fd0718
VZ		 3558static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3559{
c9ee9206
VZ		 3560 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3561 u32 bit = BP_PATH(bp) ?
3562 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3563
3564 /* Clear the bit */
3565 val &= ~bit;
3566 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3567 barrier();
3568 mmiowb();
3569}
3570
3571/*
c9ee9206
VZ		 3572 * Set RESET_IN_PROGRESS for the current engine.
3573 *
72fd0718
VZ		 3574 * should be run under rtnl lock
3575 */
c9ee9206 3576void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 3577{
c9ee9206
VZ		 3578 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3579 u32 bit = BP_PATH(bp) ?
3580 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3581
3582 /* Set the bit */
3583 val |= bit;
3584 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3585 barrier();
3586 mmiowb();
3587}
3588
3589/*
c9ee9206 3590 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 3591 * should be run under rtnl lock
3592 */
c9ee9206 3593bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 3594{
c9ee9206
VZ		 3595 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3596 u32 bit = engine ?
3597 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3598
3599 /* return false if bit is set */
3600 return (val & bit) ? false : true;
72fd0718
VZ		 3601}
3602
3603/*
c9ee9206
VZ		 3604 * Increment the load counter for the current engine.
3605 *
72fd0718
VZ		 3606 * should be run under rtnl lock
3607 */
c9ee9206 3608void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718 3609{
c9ee9206
VZ		 3610 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3611 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3612 BNX2X_PATH0_LOAD_CNT_MASK;
3613 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3614 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3615
3616 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3617
c9ee9206
VZ		 3618 /* get the current counter value */
3619 val1 = (val & mask) >> shift;
3620
3621 /* increment... */
3622 val1++;
3623
3624 /* clear the old value */
3625 val &= ~mask;
3626
3627 /* set the new one */
3628 val |= ((val1 << shift) & mask);
3629
3630 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3631 barrier();
3632 mmiowb();
3633}
3634
c9ee9206
VZ		 3635/**
3636 * bnx2x_dec_load_cnt - decrement the load counter
3637 *
3638 * @bp: driver handle
3639 *
3640 * Should be run under rtnl lock.
3641 * Decrements the load counter for the current engine. Returns
3642 * the new counter value.
72fd0718 3643 */
9f6c9258 3644u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718 3645{
c9ee9206
VZ		 3646 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3647 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3648 BNX2X_PATH0_LOAD_CNT_MASK;
3649 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3650 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3651
3652 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3653
c9ee9206
VZ		 3654 /* get the current counter value */
3655 val1 = (val & mask) >> shift;
3656
3657 /* decrement... */
3658 val1--;
3659
3660 /* clear the old value */
3661 val &= ~mask;
3662
3663 /* set the new one */
3664 val |= ((val1 << shift) & mask);
3665
3666 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3667 barrier();
3668 mmiowb();
3669
3670 return val1;
3671}
3672
3673/*
c9ee9206
VZ		 3674 * Read the load counter for the current engine.
3675 *
72fd0718
VZ		 3676 * should be run under rtnl lock
3677 */
c9ee9206 3678static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
72fd0718 3679{
c9ee9206
VZ		 3680 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3681 BNX2X_PATH0_LOAD_CNT_MASK);
3682 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3683 BNX2X_PATH0_LOAD_CNT_SHIFT);
3684 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3685
3686 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3687
3688 val = (val & mask) >> shift;
3689
3690 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3691
3692 return val;
72fd0718
VZ		 3693}
3694
c9ee9206
VZ		 3695/*
3696 * Reset the load counter for the current engine.
3697 *
3698 * should be run under rtnl lock
3699 */
72fd0718
VZ		 3700static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3701{
c9ee9206
VZ		 3702 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3703 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3704 BNX2X_PATH0_LOAD_CNT_MASK);
3705
3706 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
72fd0718
VZ		 3707}
3708
3709static inline void _print_next_block(int idx, const char *blk)
3710{
3711 if (idx)
3712 pr_cont(", ");
3713 pr_cont("%s", blk);
3714}
3715
c9ee9206
VZ		 3716static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3717 bool print)
72fd0718
VZ		 3718{
3719 int i = 0;
3720 u32 cur_bit = 0;
3721 for (i = 0; sig; i++) {
3722 cur_bit = ((u32)0x1 << i);
3723 if (sig & cur_bit) {
3724 switch (cur_bit) {
3725 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 3726 if (print)
3727 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 3728 break;
3729 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 3730 if (print)
3731 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 3732 break;
3733 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 3734 if (print)
3735 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 3736 break;
3737 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 3738 if (print)
3739 _print_next_block(par_num++,
3740 "SEARCHER");
3741 break;
3742 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3743 if (print)
3744 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 3745 break;
3746 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 3747 if (print)
3748 _print_next_block(par_num++, "TSEMI");
3749 break;
3750 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3751 if (print)
3752 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 3753 break;
3754 }
3755
3756 /* Clear the bit */
3757 sig &= ~cur_bit;
3758 }
3759 }
3760
3761 return par_num;
3762}
3763
c9ee9206
VZ		 3764static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3765 bool *global, bool print)
72fd0718
VZ		 3766{
3767 int i = 0;
3768 u32 cur_bit = 0;
3769 for (i = 0; sig; i++) {
3770 cur_bit = ((u32)0x1 << i);
3771 if (sig & cur_bit) {
3772 switch (cur_bit) {
c9ee9206
VZ		 3773 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3774 if (print)
3775 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 3776 break;
3777 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 3778 if (print)
3779 _print_next_block(par_num++, "QM");
3780 break;
3781 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3782 if (print)
3783 _print_next_block(par_num++, "TM");
72fd0718
VZ		 3784 break;
3785 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 3786 if (print)
3787 _print_next_block(par_num++, "XSDM");
3788 break;
3789 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3790 if (print)
3791 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 3792 break;
3793 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 3794 if (print)
3795 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 3796 break;
3797 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 3798 if (print)
3799 _print_next_block(par_num++,
3800 "DOORBELLQ");
3801 break;
3802 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3803 if (print)
3804 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 3805 break;
3806 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 3807 if (print)
3808 _print_next_block(par_num++,
3809 "VAUX PCI CORE");
3810 *global = true;
72fd0718
VZ		 3811 break;
3812 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 3813 if (print)
3814 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 3815 break;
3816 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 3817 if (print)
3818 _print_next_block(par_num++, "USDM");
72fd0718 3819 break;
8736c826
VZ		 3820 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3821 if (print)
3822 _print_next_block(par_num++, "UCM");
3823 break;
72fd0718 3824 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 3825 if (print)
3826 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 3827 break;
3828 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 3829 if (print)
3830 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 3831 break;
3832 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 3833 if (print)
3834 _print_next_block(par_num++, "CSDM");
72fd0718 3835 break;
8736c826
VZ		 3836 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3837 if (print)
3838 _print_next_block(par_num++, "CCM");
3839 break;
72fd0718
VZ		 3840 }
3841
3842 /* Clear the bit */
3843 sig &= ~cur_bit;
3844 }
3845 }
3846
3847 return par_num;
3848}
3849
c9ee9206
VZ		 3850static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3851 bool print)
72fd0718
VZ		 3852{
3853 int i = 0;
3854 u32 cur_bit = 0;
3855 for (i = 0; sig; i++) {
3856 cur_bit = ((u32)0x1 << i);
3857 if (sig & cur_bit) {
3858 switch (cur_bit) {
3859 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 3860 if (print)
3861 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 3862 break;
3863 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 3864 if (print)
3865 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 3866 break;
3867 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 3868 if (print)
3869 _print_next_block(par_num++,
72fd0718
VZ		 3870 "PXPPCICLOCKCLIENT");
3871 break;
3872 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 3873 if (print)
3874 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 3875 break;
3876 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 3877 if (print)
3878 _print_next_block(par_num++, "CDU");
3879 break;
3880 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3881 if (print)
3882 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 3883 break;
3884 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 3885 if (print)
3886 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 3887 break;
3888 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 3889 if (print)
3890 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 3891 break;
3892 }
3893
3894 /* Clear the bit */
3895 sig &= ~cur_bit;
3896 }
3897 }
3898
3899 return par_num;
3900}
3901
c9ee9206
VZ		 3902static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3903 bool *global, bool print)
72fd0718
VZ		 3904{
3905 int i = 0;
3906 u32 cur_bit = 0;
3907 for (i = 0; sig; i++) {
3908 cur_bit = ((u32)0x1 << i);
3909 if (sig & cur_bit) {
3910 switch (cur_bit) {
3911 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 3912 if (print)
3913 _print_next_block(par_num++, "MCP ROM");
3914 *global = true;
72fd0718
VZ		 3915 break;
3916 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 3917 if (print)
3918 _print_next_block(par_num++,
3919 "MCP UMP RX");
3920 *global = true;
72fd0718
VZ		 3921 break;
3922 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 3923 if (print)
3924 _print_next_block(par_num++,
3925 "MCP UMP TX");
3926 *global = true;
72fd0718
VZ		 3927 break;
3928 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 3929 if (print)
3930 _print_next_block(par_num++,
3931 "MCP SCPAD");
3932 *global = true;
72fd0718
VZ		 3933 break;
3934 }
3935
3936 /* Clear the bit */
3937 sig &= ~cur_bit;
3938 }
3939 }
3940
3941 return par_num;
3942}
3943
8736c826
VZ		 3944static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3945 bool print)
3946{
3947 int i = 0;
3948 u32 cur_bit = 0;
3949 for (i = 0; sig; i++) {
3950 cur_bit = ((u32)0x1 << i);
3951 if (sig & cur_bit) {
3952 switch (cur_bit) {
3953 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3954 if (print)
3955 _print_next_block(par_num++, "PGLUE_B");
3956 break;
3957 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3958 if (print)
3959 _print_next_block(par_num++, "ATC");
3960 break;
3961 }
3962
3963 /* Clear the bit */
3964 sig &= ~cur_bit;
3965 }
3966 }
3967
3968 return par_num;
3969}
3970
c9ee9206 3971static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
8736c826 3972 u32 *sig)
72fd0718 3973{
8736c826
VZ		 3974 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3975 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3976 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3977 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3978 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718
VZ		 3979 int par_num = 0;
3980 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
8736c826
VZ		 3981 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
3982 "[4]:0x%08x\n",
3983 sig[0] & HW_PRTY_ASSERT_SET_0,
3984 sig[1] & HW_PRTY_ASSERT_SET_1,
3985 sig[2] & HW_PRTY_ASSERT_SET_2,
3986 sig[3] & HW_PRTY_ASSERT_SET_3,
3987 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 3988 if (print)
3989 netdev_err(bp->dev,
3990 "Parity errors detected in blocks: ");
3991 par_num = bnx2x_check_blocks_with_parity0(
8736c826 3992 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 3993 par_num = bnx2x_check_blocks_with_parity1(
8736c826 3994 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 3995 par_num = bnx2x_check_blocks_with_parity2(
8736c826 3996 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 3997 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 3998 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
3999 par_num = bnx2x_check_blocks_with_parity4(
4000 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4001
c9ee9206
VZ		 4002 if (print)
4003 pr_cont("\n");
8736c826 4004
72fd0718
VZ		 4005 return true;
4006 } else
4007 return false;
4008}
4009
c9ee9206
VZ		 4010/**
4011 * bnx2x_chk_parity_attn - checks for parity attentions.
4012 *
4013 * @bp: driver handle
4014 * @global: true if there was a global attention
4015 * @print: show parity attention in syslog
4016 */
4017bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4018{
8736c826 4019 struct attn_route attn = { {0} };
72fd0718
VZ		 4020 int port = BP_PORT(bp);
4021
4022 attn.sig[0] = REG_RD(bp,
4023 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4024 port*4);
4025 attn.sig[1] = REG_RD(bp,
4026 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4027 port*4);
4028 attn.sig[2] = REG_RD(bp,
4029 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4030 port*4);
4031 attn.sig[3] = REG_RD(bp,
4032 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4033 port*4);
4034
8736c826
VZ		 4035 if (!CHIP_IS_E1x(bp))
4036 attn.sig[4] = REG_RD(bp,
4037 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4038 port*4);
4039
4040 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4041}
4042
f2e0899f
DK		 4043
4044static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4045{
4046 u32 val;
4047 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4048
4049 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4050 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4051 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4052 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4053 "ADDRESS_ERROR\n");
4054 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4055 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4056 "INCORRECT_RCV_BEHAVIOR\n");
4057 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4058 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4059 "WAS_ERROR_ATTN\n");
4060 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4061 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4062 "VF_LENGTH_VIOLATION_ATTN\n");
4063 if (val &
4064 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4065 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4066 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4067 if (val &
4068 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4069 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4070 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4071 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4072 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4073 "TCPL_ERROR_ATTN\n");
4074 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4075 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4076 "TCPL_IN_TWO_RCBS_ATTN\n");
4077 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4078 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4079 "CSSNOOP_FIFO_OVERFLOW\n");
4080 }
4081 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4082 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4083 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4084 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4085 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4086 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4087 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4088 "_ATC_TCPL_TO_NOT_PEND\n");
4089 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4090 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4091 "ATC_GPA_MULTIPLE_HITS\n");
4092 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4093 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4094 "ATC_RCPL_TO_EMPTY_CNT\n");
4095 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4096 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4097 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4098 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4099 "ATC_IREQ_LESS_THAN_STU\n");
4100 }
4101
4102 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4103 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4104 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4105 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4106 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4107 }
4108
4109}
4110
72fd0718
VZ		 4111static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4112{
4113 struct attn_route attn, *group_mask;
34f80b04 4114 int port = BP_PORT(bp);
877e9aa4 4115 int index;
a2fbb9ea
ET		 4116 u32 reg_addr;
4117 u32 val;
3fcaf2e5 4118 u32 aeu_mask;
c9ee9206 4119 bool global = false;
a2fbb9ea
ET		 4120
4121 /* need to take HW lock because MCP or other port might also
4122 try to handle this event */
4a37fb66 4123 bnx2x_acquire_alr(bp);
a2fbb9ea 4124
c9ee9206
VZ		 4125 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4126#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4127 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4128 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4129 /* Disable HW interrupts */
4130 bnx2x_int_disable(bp);
72fd0718
VZ		 4131 /* In case of parity errors don't handle attentions so that
4132 * other function would "see" parity errors.
4133 */
c9ee9206
VZ		 4134#else
4135 bnx2x_panic();
4136#endif
4137 bnx2x_release_alr(bp);
72fd0718
VZ		 4138 return;
4139 }
4140
a2fbb9ea
ET		 4141 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4142 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4143 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4144 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4145 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4146 attn.sig[4] =
4147 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4148 else
4149 attn.sig[4] = 0;
4150
4151 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4152 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4153
4154 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4155 if (deasserted & (1 << index)) {
72fd0718 4156 group_mask = &bp->attn_group[index];
a2fbb9ea 4157
f2e0899f
DK		 4158 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4159 "%08x %08x %08x\n",
4160 index,
4161 group_mask->sig[0], group_mask->sig[1],
4162 group_mask->sig[2], group_mask->sig[3],
4163 group_mask->sig[4]);
a2fbb9ea 4164
f2e0899f
DK		 4165 bnx2x_attn_int_deasserted4(bp,
4166 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4167 bnx2x_attn_int_deasserted3(bp,
72fd0718 4168 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4169 bnx2x_attn_int_deasserted1(bp,
72fd0718 4170 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4171 bnx2x_attn_int_deasserted2(bp,
72fd0718 4172 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4173 bnx2x_attn_int_deasserted0(bp,
72fd0718 4174 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4175 }
4176 }
4177
4a37fb66 4178 bnx2x_release_alr(bp);
a2fbb9ea 4179
f2e0899f
DK		 4180 if (bp->common.int_block == INT_BLOCK_HC)
4181 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4182 COMMAND_REG_ATTN_BITS_CLR);
4183 else
4184 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4185
4186 val = ~deasserted;
f2e0899f
DK		 4187 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4188 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4189 REG_WR(bp, reg_addr, val);
a2fbb9ea 4190
a2fbb9ea 4191 if (~bp->attn_state & deasserted)
3fcaf2e5 4192 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4193
4194 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4195 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4196
3fcaf2e5
EG		 4197 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4198 aeu_mask = REG_RD(bp, reg_addr);
4199
4200 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4201 aeu_mask, deasserted);
72fd0718 4202 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4203 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4204
3fcaf2e5
EG		 4205 REG_WR(bp, reg_addr, aeu_mask);
4206 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4207
4208 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4209 bp->attn_state &= ~deasserted;
4210 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4211}
4212
4213static void bnx2x_attn_int(struct bnx2x *bp)
4214{
4215 /* read local copy of bits */
68d59484
EG		 4216 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4217 attn_bits);
4218 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4219 attn_bits_ack);
a2fbb9ea
ET		 4220 u32 attn_state = bp->attn_state;
4221
4222 /* look for changed bits */
4223 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4224 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4225
4226 DP(NETIF_MSG_HW,
4227 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4228 attn_bits, attn_ack, asserted, deasserted);
4229
4230 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4231 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4232
4233 /* handle bits that were raised */
4234 if (asserted)
4235 bnx2x_attn_int_asserted(bp, asserted);
4236
4237 if (deasserted)
4238 bnx2x_attn_int_deasserted(bp, deasserted);
4239}
4240
619c5cb6
VZ		 4241void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4242 u16 index, u8 op, u8 update)
4243{
4244 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4245
4246 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4247 igu_addr);
4248}
4249
523224a3
DK		 4250static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4251{
4252 /* No memory barriers */
4253 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4254 mmiowb(); /* keep prod updates ordered */
4255}
4256
4257#ifdef BCM_CNIC
4258static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4259 union event_ring_elem *elem)
4260{
619c5cb6
VZ		 4261 u8 err = elem->message.error;
4262
523224a3 4263 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4264 (cid < bp->cnic_eth_dev.starting_cid &&
4265 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4266 return 1;
4267
4268 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4269
619c5cb6
VZ		 4270 if (unlikely(err)) {
4271
523224a3
DK		 4272 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4273 cid);
4274 bnx2x_panic_dump(bp);
4275 }
619c5cb6 4276 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4277 return 0;
4278}
4279#endif
4280
619c5cb6
VZ		 4281static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4282{
4283 struct bnx2x_mcast_ramrod_params rparam;
4284 int rc;
4285
4286 memset(&rparam, 0, sizeof(rparam));
4287
4288 rparam.mcast_obj = &bp->mcast_obj;
4289
4290 netif_addr_lock_bh(bp->dev);
4291
4292 /* Clear pending state for the last command */
4293 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4294
4295 /* If there are pending mcast commands - send them */
4296 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4297 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4298 if (rc < 0)
4299 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4300 rc);
4301 }
4302
4303 netif_addr_unlock_bh(bp->dev);
4304}
4305
4306static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4307 union event_ring_elem *elem)
4308{
4309 unsigned long ramrod_flags = 0;
4310 int rc = 0;
4311 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4312 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4313
4314 /* Always push next commands out, don't wait here */
4315 __set_bit(RAMROD_CONT, &ramrod_flags);
4316
4317 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4318 case BNX2X_FILTER_MAC_PENDING:
4319#ifdef BCM_CNIC
4320 if (cid == BNX2X_ISCSI_ETH_CID)
4321 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4322 else
4323#endif
4324 vlan_mac_obj = &bp->fp[cid].mac_obj;
4325
4326 break;
4327 vlan_mac_obj = &bp->fp[cid].mac_obj;
4328
4329 case BNX2X_FILTER_MCAST_PENDING:
4330 /* This is only relevant for 57710 where multicast MACs are
4331 * configured as unicast MACs using the same ramrod.
4332 */
4333 bnx2x_handle_mcast_eqe(bp);
4334 return;
4335 default:
4336 BNX2X_ERR("Unsupported classification command: %d\n",
4337 elem->message.data.eth_event.echo);
4338 return;
4339 }
4340
4341 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4342
4343 if (rc < 0)
4344 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4345 else if (rc > 0)
4346 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4347
4348}
4349
4350#ifdef BCM_CNIC
4351static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4352#endif
4353
4354static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4355{
4356 netif_addr_lock_bh(bp->dev);
4357
4358 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4359
4360 /* Send rx_mode command again if was requested */
4361 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4362 bnx2x_set_storm_rx_mode(bp);
4363#ifdef BCM_CNIC
4364 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4365 &bp->sp_state))
4366 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4367 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4368 &bp->sp_state))
4369 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4370#endif
4371
4372 netif_addr_unlock_bh(bp->dev);
4373}
4374
4375static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4376 struct bnx2x *bp, u32 cid)
4377{
6383c0b3 4378 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
619c5cb6
VZ		 4379#ifdef BCM_CNIC
4380 if (cid == BNX2X_FCOE_ETH_CID)
4381 return &bnx2x_fcoe(bp, q_obj);
4382 else
4383#endif
6383c0b3 4384 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
619c5cb6
VZ		 4385}
4386
523224a3
DK		 4387static void bnx2x_eq_int(struct bnx2x *bp)
4388{
4389 u16 hw_cons, sw_cons, sw_prod;
4390 union event_ring_elem *elem;
4391 u32 cid;
4392 u8 opcode;
4393 int spqe_cnt = 0;
619c5cb6
VZ		 4394 struct bnx2x_queue_sp_obj *q_obj;
4395 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4396 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4397
4398 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4399
4400 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4401 * when we get the the next-page we nned to adjust so the loop
4402 * condition below will be met. The next element is the size of a
4403 * regular element and hence incrementing by 1
4404 */
4405 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4406 hw_cons++;
4407
25985edc 4408 /* This function may never run in parallel with itself for a
523224a3
DK		 4409 * specific bp, thus there is no need in "paired" read memory
4410 * barrier here.
4411 */
4412 sw_cons = bp->eq_cons;
4413 sw_prod = bp->eq_prod;
4414
6e30dd4e
VZ		 4415 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
4416 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4417
4418 for (; sw_cons != hw_cons;
4419 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4420
4421
4422 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4423
4424 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4425 opcode = elem->message.opcode;
4426
4427
4428 /* handle eq element */
4429 switch (opcode) {
4430 case EVENT_RING_OPCODE_STAT_QUERY:
619c5cb6
VZ		 4431 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4432 bp->stats_comp++);
523224a3
DK		 4433 /* nothing to do with stats comp */
4434 continue;
4435
4436 case EVENT_RING_OPCODE_CFC_DEL:
4437 /* handle according to cid range */
4438 /*
4439 * we may want to verify here that the bp state is
4440 * HALTING
4441 */
4442 DP(NETIF_MSG_IFDOWN,
4443 "got delete ramrod for MULTI[%d]\n", cid);
4444#ifdef BCM_CNIC
4445 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4446 goto next_spqe;
4447#endif
619c5cb6
VZ		 4448 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4449
4450 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4451 break;
4452
4453
523224a3
DK		 4454
4455 goto next_spqe;
e4901dde
VZ		 4456
4457 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4458 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
6debea87
DK		 4459 if (f_obj->complete_cmd(bp, f_obj,
4460 BNX2X_F_CMD_TX_STOP))
4461 break;
e4901dde
VZ		 4462 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4463 goto next_spqe;
619c5cb6 4464
e4901dde
VZ		 4465 case EVENT_RING_OPCODE_START_TRAFFIC:
4466 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
6debea87
DK		 4467 if (f_obj->complete_cmd(bp, f_obj,
4468 BNX2X_F_CMD_TX_START))
4469 break;
e4901dde
VZ		 4470 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4471 goto next_spqe;
619c5cb6
VZ		 4472 case EVENT_RING_OPCODE_FUNCTION_START:
4473 DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n");
4474 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4475 break;
4476
4477 goto next_spqe;
4478
4479 case EVENT_RING_OPCODE_FUNCTION_STOP:
4480 DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n");
4481 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4482 break;
4483
4484 goto next_spqe;
523224a3
DK		 4485 }
4486
4487 switch (opcode | bp->state) {
619c5cb6
VZ		 4488 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4489 BNX2X_STATE_OPEN):
4490 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4491 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4492 cid = elem->message.data.eth_event.echo &
4493 BNX2X_SWCID_MASK;
4494 DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n",
4495 cid);
4496 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4497 break;
4498
619c5cb6
VZ		 4499 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4500 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4501 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4502 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4503 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4504 BNX2X_STATE_OPEN):
4505 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4506 BNX2X_STATE_DIAG):
4507 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4508 BNX2X_STATE_CLOSING_WAIT4_HALT):
4509 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
4510 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4511 break;
4512
619c5cb6
VZ		 4513 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4514 BNX2X_STATE_OPEN):
4515 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4516 BNX2X_STATE_DIAG):
4517 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4518 BNX2X_STATE_CLOSING_WAIT4_HALT):
4519 DP(NETIF_MSG_IFUP, "got mcast ramrod\n");
4520 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4521 break;
4522
619c5cb6
VZ		 4523 case (EVENT_RING_OPCODE_FILTERS_RULES |
4524 BNX2X_STATE_OPEN):
4525 case (EVENT_RING_OPCODE_FILTERS_RULES |
4526 BNX2X_STATE_DIAG):
4527 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4528 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4529 DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n");
4530 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4531 break;
4532 default:
4533 /* unknown event log error and continue */
619c5cb6
VZ		 4534 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4535 elem->message.opcode, bp->state);
523224a3
DK		 4536 }
4537next_spqe:
4538 spqe_cnt++;
4539 } /* for */
4540
8fe23fbd 4541 smp_mb__before_atomic_inc();
6e30dd4e 4542 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4543
4544 bp->eq_cons = sw_cons;
4545 bp->eq_prod = sw_prod;
4546 /* Make sure that above mem writes were issued towards the memory */
4547 smp_wmb();
4548
4549 /* update producer */
4550 bnx2x_update_eq_prod(bp, bp->eq_prod);
4551}
4552
a2fbb9ea
ET		 4553static void bnx2x_sp_task(struct work_struct *work)
4554{
1cf167f2 4555 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4556 u16 status;
4557
a2fbb9ea 4558 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4559/* if (status == 0) */
4560/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4561
cdaa7cb8 4562 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4563
877e9aa4 4564 /* HW attentions */
523224a3 4565 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4566 bnx2x_attn_int(bp);
523224a3 4567 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4568 }
4569
523224a3
DK		 4570 /* SP events: STAT_QUERY and others */
4571 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4572#ifdef BCM_CNIC
4573 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4574
ec6ba945 4575 if ((!NO_FCOE(bp)) &&
019dbb4c
VZ		 4576 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4577 /*
4578 * Prevent local bottom-halves from running as
4579 * we are going to change the local NAPI list.
4580 */
4581 local_bh_disable();
ec6ba945 4582 napi_schedule(&bnx2x_fcoe(bp, napi));
019dbb4c
VZ		 4583 local_bh_enable();
4584 }
ec6ba945 4585#endif
523224a3
DK		 4586 /* Handle EQ completions */
4587 bnx2x_eq_int(bp);
4588
4589 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4590 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4591
4592 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4593 }
4594
4595 if (unlikely(status))
4596 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4597 status);
a2fbb9ea 4598
523224a3
DK		 4599 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4600 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4601}
4602
9f6c9258 4603irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4604{
4605 struct net_device *dev = dev_instance;
4606 struct bnx2x *bp = netdev_priv(dev);
4607
523224a3
DK		 4608 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4609 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4610
4611#ifdef BNX2X_STOP_ON_ERROR
4612 if (unlikely(bp->panic))
4613 return IRQ_HANDLED;
4614#endif
4615
993ac7b5
MC		 4616#ifdef BCM_CNIC
4617 {
4618 struct cnic_ops *c_ops;
4619
4620 rcu_read_lock();
4621 c_ops = rcu_dereference(bp->cnic_ops);
4622 if (c_ops)
4623 c_ops->cnic_handler(bp->cnic_data, NULL);
4624 rcu_read_unlock();
4625 }
4626#endif
1cf167f2 4627 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4628
4629 return IRQ_HANDLED;
4630}
4631
4632/* end of slow path */
4633
619c5cb6
VZ		 4634
4635void bnx2x_drv_pulse(struct bnx2x *bp)
4636{
4637 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4638 bp->fw_drv_pulse_wr_seq);
4639}
4640
4641
a2fbb9ea
ET		 4642static void bnx2x_timer(unsigned long data)
4643{
6383c0b3 4644 u8 cos;
a2fbb9ea
ET		 4645 struct bnx2x *bp = (struct bnx2x *) data;
4646
4647 if (!netif_running(bp->dev))
4648 return;
4649
a2fbb9ea
ET		 4650 if (poll) {
4651 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 4652
6383c0b3
AE		 4653 for_each_cos_in_tx_queue(fp, cos)
4654 bnx2x_tx_int(bp, &fp->txdata[cos]);
b8ee8328 4655 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 4656 }
4657
34f80b04 4658 if (!BP_NOMCP(bp)) {
f2e0899f 4659 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4660 u32 drv_pulse;
4661 u32 mcp_pulse;
4662
4663 ++bp->fw_drv_pulse_wr_seq;
4664 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4665 /* TBD - add SYSTEM_TIME */
4666 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4667 bnx2x_drv_pulse(bp);
a2fbb9ea 4668
f2e0899f 4669 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4670 MCP_PULSE_SEQ_MASK);
4671 /* The delta between driver pulse and mcp response
4672 * should be 1 (before mcp response) or 0 (after mcp response)
4673 */
4674 if ((drv_pulse != mcp_pulse) &&
4675 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4676 /* someone lost a heartbeat... */
4677 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4678 drv_pulse, mcp_pulse);
4679 }
4680 }
4681
f34d28ea 4682 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4683 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4684
a2fbb9ea
ET		 4685 mod_timer(&bp->timer, jiffies + bp->current_interval);
4686}
4687
4688/* end of Statistics */
4689
4690/* nic init */
4691
4692/*
4693 * nic init service functions
4694 */
4695
523224a3 4696static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4697{
523224a3
DK		 4698 u32 i;
4699 if (!(len%4) && !(addr%4))
4700 for (i = 0; i < len; i += 4)
4701 REG_WR(bp, addr + i, fill);
4702 else
4703 for (i = 0; i < len; i++)
4704 REG_WR8(bp, addr + i, fill);
34f80b04 4705
34f80b04
EG		 4706}
4707
523224a3
DK		 4708/* helper: writes FP SP data to FW - data_size in dwords */
4709static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4710 int fw_sb_id,
4711 u32 *sb_data_p,
4712 u32 data_size)
34f80b04 4713{
a2fbb9ea 4714 int index;
523224a3
DK		 4715 for (index = 0; index < data_size; index++)
4716 REG_WR(bp, BAR_CSTRORM_INTMEM +
4717 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4718 sizeof(u32)*index,
4719 *(sb_data_p + index));
4720}
a2fbb9ea 4721
523224a3
DK		 4722static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4723{
4724 u32 *sb_data_p;
4725 u32 data_size = 0;
f2e0899f 4726 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4727 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4728
523224a3 4729 /* disable the function first */
619c5cb6 4730 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4731 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4732 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4733 sb_data_e2.common.p_func.vf_valid = false;
4734 sb_data_p = (u32 *)&sb_data_e2;
4735 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4736 } else {
4737 memset(&sb_data_e1x, 0,
4738 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4739 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4740 sb_data_e1x.common.p_func.vf_valid = false;
4741 sb_data_p = (u32 *)&sb_data_e1x;
4742 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4743 }
523224a3 4744 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4745
523224a3
DK		 4746 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4747 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4748 CSTORM_STATUS_BLOCK_SIZE);
4749 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4750 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4751 CSTORM_SYNC_BLOCK_SIZE);
4752}
34f80b04 4753
523224a3
DK		 4754/* helper: writes SP SB data to FW */
4755static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4756 struct hc_sp_status_block_data *sp_sb_data)
4757{
4758 int func = BP_FUNC(bp);
4759 int i;
4760 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4761 REG_WR(bp, BAR_CSTRORM_INTMEM +
4762 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4763 i*sizeof(u32),
4764 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4765}
4766
523224a3 4767static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4768{
4769 int func = BP_FUNC(bp);
523224a3
DK		 4770 struct hc_sp_status_block_data sp_sb_data;
4771 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4772
619c5cb6 4773 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4774 sp_sb_data.p_func.vf_valid = false;
4775
4776 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4777
4778 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4779 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4780 CSTORM_SP_STATUS_BLOCK_SIZE);
4781 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4782 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4783 CSTORM_SP_SYNC_BLOCK_SIZE);
4784
4785}
4786
4787
4788static inline
4789void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4790 int igu_sb_id, int igu_seg_id)
4791{
4792 hc_sm->igu_sb_id = igu_sb_id;
4793 hc_sm->igu_seg_id = igu_seg_id;
4794 hc_sm->timer_value = 0xFF;
4795 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4796}
4797
8d96286a 4798static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4799 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4800{
523224a3
DK		 4801 int igu_seg_id;
4802
f2e0899f 4803 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4804 struct hc_status_block_data_e1x sb_data_e1x;
4805 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4806 int data_size;
4807 u32 *sb_data_p;
4808
f2e0899f
DK		 4809 if (CHIP_INT_MODE_IS_BC(bp))
4810 igu_seg_id = HC_SEG_ACCESS_NORM;
4811 else
4812 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4813
4814 bnx2x_zero_fp_sb(bp, fw_sb_id);
4815
619c5cb6 4816 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4817 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4818 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 4819 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4820 sb_data_e2.common.p_func.vf_id = vfid;
4821 sb_data_e2.common.p_func.vf_valid = vf_valid;
4822 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4823 sb_data_e2.common.same_igu_sb_1b = true;
4824 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4825 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4826 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4827 sb_data_p = (u32 *)&sb_data_e2;
4828 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4829 } else {
4830 memset(&sb_data_e1x, 0,
4831 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4832 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 4833 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4834 sb_data_e1x.common.p_func.vf_id = 0xff;
4835 sb_data_e1x.common.p_func.vf_valid = false;
4836 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4837 sb_data_e1x.common.same_igu_sb_1b = true;
4838 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4839 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4840 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4841 sb_data_p = (u32 *)&sb_data_e1x;
4842 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4843 }
523224a3
DK		 4844
4845 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4846 igu_sb_id, igu_seg_id);
4847 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4848 igu_sb_id, igu_seg_id);
4849
4850 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4851
4852 /* write indecies to HW */
4853 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4854}
4855
619c5cb6 4856static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 4857 u16 tx_usec, u16 rx_usec)
4858{
6383c0b3 4859 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 4860 false, rx_usec);
6383c0b3
AE		 4861 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4862 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4863 tx_usec);
4864 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4865 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4866 tx_usec);
4867 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4868 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4869 tx_usec);
523224a3 4870}
f2e0899f 4871
523224a3
DK		 4872static void bnx2x_init_def_sb(struct bnx2x *bp)
4873{
4874 struct host_sp_status_block *def_sb = bp->def_status_blk;
4875 dma_addr_t mapping = bp->def_status_blk_mapping;
4876 int igu_sp_sb_index;
4877 int igu_seg_id;
34f80b04
EG		 4878 int port = BP_PORT(bp);
4879 int func = BP_FUNC(bp);
523224a3 4880 int reg_offset;
a2fbb9ea 4881 u64 section;
523224a3
DK		 4882 int index;
4883 struct hc_sp_status_block_data sp_sb_data;
4884 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4885
f2e0899f
DK		 4886 if (CHIP_INT_MODE_IS_BC(bp)) {
4887 igu_sp_sb_index = DEF_SB_IGU_ID;
4888 igu_seg_id = HC_SEG_ACCESS_DEF;
4889 } else {
4890 igu_sp_sb_index = bp->igu_dsb_id;
4891 igu_seg_id = IGU_SEG_ACCESS_DEF;
4892 }
a2fbb9ea
ET		 4893
4894 /* ATTN */
523224a3 4895 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4896 atten_status_block);
523224a3 4897 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4898
49d66772
ET		 4899 bp->attn_state = 0;
4900
a2fbb9ea
ET		 4901 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4902 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4903 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4904 int sindex;
4905 /* take care of sig[0]..sig[4] */
4906 for (sindex = 0; sindex < 4; sindex++)
4907 bp->attn_group[index].sig[sindex] =
4908 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 4909
619c5cb6 4910 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4911 /*
4912 * enable5 is separate from the rest of the registers,
4913 * and therefore the address skip is 4
4914 * and not 16 between the different groups
4915 */
4916 bp->attn_group[index].sig[4] = REG_RD(bp,
4917 reg_offset + 0x10 + 0x4*index);
4918 else
4919 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4920 }
4921
f2e0899f
DK		 4922 if (bp->common.int_block == INT_BLOCK_HC) {
4923 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4924 HC_REG_ATTN_MSG0_ADDR_L);
4925
4926 REG_WR(bp, reg_offset, U64_LO(section));
4927 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 4928 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4929 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4930 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4931 }
a2fbb9ea 4932
523224a3
DK		 4933 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4934 sp_sb);
a2fbb9ea 4935
523224a3 4936 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4937
619c5cb6 4938 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 4939 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4940 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4941 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4942 sp_sb_data.igu_seg_id = igu_seg_id;
4943 sp_sb_data.p_func.pf_id = func;
f2e0899f 4944 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4945 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4946
523224a3 4947 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4948
523224a3 4949 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4950}
4951
9f6c9258 4952void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4953{
a2fbb9ea
ET		 4954 int i;
4955
ec6ba945 4956 for_each_eth_queue(bp, i)
523224a3 4957 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 4958 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 4959}
4960
a2fbb9ea
ET		 4961static void bnx2x_init_sp_ring(struct bnx2x *bp)
4962{
a2fbb9ea 4963 spin_lock_init(&bp->spq_lock);
6e30dd4e 4964 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4965
a2fbb9ea 4966 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4967 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4968 bp->spq_prod_bd = bp->spq;
4969 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4970}
4971
523224a3 4972static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4973{
4974 int i;
523224a3
DK		 4975 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4976 union event_ring_elem *elem =
4977 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4978
523224a3
DK		 4979 elem->next_page.addr.hi =
4980 cpu_to_le32(U64_HI(bp->eq_mapping +
4981 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4982 elem->next_page.addr.lo =
4983 cpu_to_le32(U64_LO(bp->eq_mapping +
4984 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4985 }
523224a3
DK		 4986 bp->eq_cons = 0;
4987 bp->eq_prod = NUM_EQ_DESC;
4988 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 4989 /* we want a warning message before it gets rought... */
4990 atomic_set(&bp->eq_spq_left,
4991 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 4992}
4993
619c5cb6
VZ		 4994
4995/* called with netif_addr_lock_bh() */
4996void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
4997 unsigned long rx_mode_flags,
4998 unsigned long rx_accept_flags,
4999 unsigned long tx_accept_flags,
5000 unsigned long ramrod_flags)
ab532cf3 5001{
619c5cb6
VZ		 5002 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5003 int rc;
5004
5005 memset(&ramrod_param, 0, sizeof(ramrod_param));
5006
5007 /* Prepare ramrod parameters */
5008 ramrod_param.cid = 0;
5009 ramrod_param.cl_id = cl_id;
5010 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5011 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5012
619c5cb6
VZ		 5013 ramrod_param.pstate = &bp->sp_state;
5014 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5015
619c5cb6
VZ		 5016 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5017 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5018
5019 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5020
5021 ramrod_param.ramrod_flags = ramrod_flags;
5022 ramrod_param.rx_mode_flags = rx_mode_flags;
5023
5024 ramrod_param.rx_accept_flags = rx_accept_flags;
5025 ramrod_param.tx_accept_flags = tx_accept_flags;
5026
5027 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5028 if (rc < 0) {
5029 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5030 return;
5031 }
a2fbb9ea
ET		 5032}
5033
619c5cb6
VZ		 5034/* called with netif_addr_lock_bh() */
5035void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5036{
619c5cb6
VZ		 5037 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5038 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5039
619c5cb6
VZ		 5040#ifdef BCM_CNIC
5041 if (!NO_FCOE(bp))
5042
5043 /* Configure rx_mode of FCoE Queue */
5044 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5045#endif
5046
5047 switch (bp->rx_mode) {
5048 case BNX2X_RX_MODE_NONE:
5049 /*
5050 * 'drop all' supersedes any accept flags that may have been
5051 * passed to the function.
5052 */
5053 break;
5054 case BNX2X_RX_MODE_NORMAL:
5055 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5056 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5057 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5058
5059 /* internal switching mode */
5060 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5061 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5062 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5063
5064 break;
5065 case BNX2X_RX_MODE_ALLMULTI:
5066 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5067 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5068 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5069
5070 /* internal switching mode */
5071 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5072 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5073 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5074
5075 break;
5076 case BNX2X_RX_MODE_PROMISC:
5077 /* According to deffinition of SI mode, iface in promisc mode
5078 * should receive matched and unmatched (in resolution of port)
5079 * unicast packets.
5080 */
5081 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5082 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5083 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5084 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5085
5086 /* internal switching mode */
5087 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5088 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5089
5090 if (IS_MF_SI(bp))
5091 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5092 else
5093 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5094
5095 break;
5096 default:
5097 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5098 return;
5099 }
de832a55 5100
619c5cb6
VZ		 5101 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5102 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5103 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5104 }
5105
619c5cb6
VZ		 5106 __set_bit(RAMROD_RX, &ramrod_flags);
5107 __set_bit(RAMROD_TX, &ramrod_flags);
5108
5109 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5110 tx_accept_flags, ramrod_flags);
5111}
5112
5113static void bnx2x_init_internal_common(struct bnx2x *bp)
5114{
5115 int i;
5116
0793f83f
DK		 5117 if (IS_MF_SI(bp))
5118 /*
5119 * In switch independent mode, the TSTORM needs to accept
5120 * packets that failed classification, since approximate match
5121 * mac addresses aren't written to NIG LLH
5122 */
5123 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5124 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5125 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5126 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5127 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5128
523224a3
DK		 5129 /* Zero this manually as its initialization is
5130 currently missing in the initTool */
5131 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5132 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5133 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5134 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5135 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5136 CHIP_INT_MODE_IS_BC(bp) ?
5137 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5138 }
523224a3 5139}
8a1c38d1 5140
471de716
EG		 5141static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5142{
5143 switch (load_code) {
5144 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5145 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5146 bnx2x_init_internal_common(bp);
5147 /* no break */
5148
5149 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5150 /* nothing to do */
471de716
EG		 5151 /* no break */
5152
5153 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5154 /* internal memory per function is
5155 initialized inside bnx2x_pf_init */
471de716
EG		 5156 break;
5157
5158 default:
5159 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5160 break;
5161 }
5162}
5163
619c5cb6 5164static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5165{
6383c0b3 5166 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
619c5cb6 5167}
523224a3 5168
619c5cb6
VZ		 5169static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5170{
6383c0b3 5171 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
619c5cb6
VZ		 5172}
5173
5174static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5175{
5176 if (CHIP_IS_E1x(fp->bp))
5177 return BP_L_ID(fp->bp) + fp->index;
5178 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5179 return bnx2x_fp_igu_sb_id(fp);
5180}
5181
6383c0b3 5182static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5183{
5184 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5185 u8 cos;
619c5cb6 5186 unsigned long q_type = 0;
6383c0b3 5187 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
523224a3 5188
b3b83c3f 5189 fp->cid = fp_idx;
619c5cb6
VZ		 5190 fp->cl_id = bnx2x_fp_cl_id(fp);
5191 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5192 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5193 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5194 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5195
523224a3 5196 /* init shortcut */
619c5cb6 5197 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
523224a3
DK		 5198 /* Setup SB indicies */
5199 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5200
619c5cb6
VZ		 5201 /* Configure Queue State object */
5202 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5203 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5204
5205 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5206
5207 /* init tx data */
5208 for_each_cos_in_tx_queue(fp, cos) {
5209 bnx2x_init_txdata(bp, &fp->txdata[cos],
5210 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5211 FP_COS_TO_TXQ(fp, cos),
5212 BNX2X_TX_SB_INDEX_BASE + cos);
5213 cids[cos] = fp->txdata[cos].cid;
5214 }
5215
5216 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5217 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5218 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5219
5220 /**
5221 * Configure classification DBs: Always enable Tx switching
5222 */
5223 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5224
523224a3
DK		 5225 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5226 "cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 5227 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 5228 fp->igu_sb_id);
5229 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5230 fp->fw_sb_id, fp->igu_sb_id);
5231
5232 bnx2x_update_fpsb_idx(fp);
5233}
5234
9f6c9258 5235void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 5236{
5237 int i;
5238
ec6ba945 5239 for_each_eth_queue(bp, i)
6383c0b3 5240 bnx2x_init_eth_fp(bp, i);
37b091ba 5241#ifdef BCM_CNIC
ec6ba945
VZ		 5242 if (!NO_FCOE(bp))
5243 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5244
5245 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5246 BNX2X_VF_ID_INVALID, false,
619c5cb6 5247 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5248
37b091ba 5249#endif
a2fbb9ea 5250
020c7e3f
YR		 5251 /* Initialize MOD_ABS interrupts */
5252 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5253 bp->common.shmem_base, bp->common.shmem2_base,
5254 BP_PORT(bp));
16119785
EG		 5255 /* ensure status block indices were read */
5256 rmb();
5257
523224a3 5258 bnx2x_init_def_sb(bp);
5c862848 5259 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5260 bnx2x_init_rx_rings(bp);
523224a3 5261 bnx2x_init_tx_rings(bp);
a2fbb9ea 5262 bnx2x_init_sp_ring(bp);
523224a3 5263 bnx2x_init_eq_ring(bp);
471de716 5264 bnx2x_init_internal(bp, load_code);
523224a3 5265 bnx2x_pf_init(bp);
0ef00459
EG		 5266 bnx2x_stats_init(bp);
5267
0ef00459
EG		 5268 /* flush all before enabling interrupts */
5269 mb();
5270 mmiowb();
5271
615f8fd9 5272 bnx2x_int_enable(bp);
eb8da205
EG		 5273
5274 /* Check for SPIO5 */
5275 bnx2x_attn_int_deasserted0(bp,
5276 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5277 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5278}
5279
5280/* end of nic init */
5281
5282/*
5283 * gzip service functions
5284 */
5285
5286static int bnx2x_gunzip_init(struct bnx2x *bp)
5287{
1a983142
FT		 5288 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5289 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5290 if (bp->gunzip_buf == NULL)
5291 goto gunzip_nomem1;
5292
5293 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5294 if (bp->strm == NULL)
5295 goto gunzip_nomem2;
5296
7ab24bfd 5297 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5298 if (bp->strm->workspace == NULL)
5299 goto gunzip_nomem3;
5300
5301 return 0;
5302
5303gunzip_nomem3:
5304 kfree(bp->strm);
5305 bp->strm = NULL;
5306
5307gunzip_nomem2:
1a983142
FT		 5308 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5309 bp->gunzip_mapping);
a2fbb9ea
ET		 5310 bp->gunzip_buf = NULL;
5311
5312gunzip_nomem1:
cdaa7cb8
VZ		 5313 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5314 " un-compression\n");
a2fbb9ea
ET		 5315 return -ENOMEM;
5316}
5317
5318static void bnx2x_gunzip_end(struct bnx2x *bp)
5319{
b3b83c3f 5320 if (bp->strm) {
7ab24bfd 5321 vfree(bp->strm->workspace);
b3b83c3f
DK		 5322 kfree(bp->strm);
5323 bp->strm = NULL;
5324 }
a2fbb9ea
ET		 5325
5326 if (bp->gunzip_buf) {
1a983142
FT		 5327 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5328 bp->gunzip_mapping);
a2fbb9ea
ET		 5329 bp->gunzip_buf = NULL;
5330 }
5331}
5332
94a78b79 5333static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 5334{
5335 int n, rc;
5336
5337 /* check gzip header */
94a78b79
VZ		 5338 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5339 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 5340 return -EINVAL;
94a78b79 5341 }
a2fbb9ea
ET		 5342
5343 n = 10;
5344
34f80b04 5345#define FNAME 0x8
a2fbb9ea
ET		 5346
5347 if (zbuf[3] & FNAME)
5348 while ((zbuf[n++] != 0) && (n < len));
5349
94a78b79 5350 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 5351 bp->strm->avail_in = len - n;
5352 bp->strm->next_out = bp->gunzip_buf;
5353 bp->strm->avail_out = FW_BUF_SIZE;
5354
5355 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5356 if (rc != Z_OK)
5357 return rc;
5358
5359 rc = zlib_inflate(bp->strm, Z_FINISH);
5360 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 5361 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5362 bp->strm->msg);
a2fbb9ea
ET		 5363
5364 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5365 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 5366 netdev_err(bp->dev, "Firmware decompression error:"
5367 " gunzip_outlen (%d) not aligned\n",
5368 bp->gunzip_outlen);
a2fbb9ea
ET		 5369 bp->gunzip_outlen >>= 2;
5370
5371 zlib_inflateEnd(bp->strm);
5372
5373 if (rc == Z_STREAM_END)
5374 return 0;
5375
5376 return rc;
5377}
5378
5379/* nic load/unload */
5380
5381/*
34f80b04 5382 * General service functions
a2fbb9ea
ET		 5383 */
5384
5385/* send a NIG loopback debug packet */
5386static void bnx2x_lb_pckt(struct bnx2x *bp)
5387{
a2fbb9ea 5388 u32 wb_write[3];
a2fbb9ea
ET		 5389
5390 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 5391 wb_write[0] = 0x55555555;
5392 wb_write[1] = 0x55555555;
34f80b04 5393 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 5394 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5395
5396 /* NON-IP protocol */
a2fbb9ea
ET		 5397 wb_write[0] = 0x09000000;
5398 wb_write[1] = 0x55555555;
34f80b04 5399 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 5400 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5401}
5402
5403/* some of the internal memories
5404 * are not directly readable from the driver
5405 * to test them we send debug packets
5406 */
5407static int bnx2x_int_mem_test(struct bnx2x *bp)
5408{
5409 int factor;
5410 int count, i;
5411 u32 val = 0;
5412
ad8d3948 5413 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 5414 factor = 120;
ad8d3948
EG		 5415 else if (CHIP_REV_IS_EMUL(bp))
5416 factor = 200;
5417 else
a2fbb9ea 5418 factor = 1;
a2fbb9ea 5419
a2fbb9ea
ET		 5420 /* Disable inputs of parser neighbor blocks */
5421 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5422 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5423 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5424 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5425
5426 /* Write 0 to parser credits for CFC search request */
5427 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5428
5429 /* send Ethernet packet */
5430 bnx2x_lb_pckt(bp);
5431
5432 /* TODO do i reset NIG statistic? */
5433 /* Wait until NIG register shows 1 packet of size 0x10 */
5434 count = 1000 * factor;
5435 while (count) {
34f80b04 5436
a2fbb9ea
ET		 5437 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5438 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5439 if (val == 0x10)
5440 break;
5441
5442 msleep(10);
5443 count--;
5444 }
5445 if (val != 0x10) {
5446 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5447 return -1;
5448 }
5449
5450 /* Wait until PRS register shows 1 packet */
5451 count = 1000 * factor;
5452 while (count) {
5453 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 5454 if (val == 1)
5455 break;
5456
5457 msleep(10);
5458 count--;
5459 }
5460 if (val != 0x1) {
5461 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5462 return -2;
5463 }
5464
5465 /* Reset and init BRB, PRS */
34f80b04 5466 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5467 msleep(50);
34f80b04 5468 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5469 msleep(50);
619c5cb6
VZ		 5470 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5471 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5472
5473 DP(NETIF_MSG_HW, "part2\n");
5474
5475 /* Disable inputs of parser neighbor blocks */
5476 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5477 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5478 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5479 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5480
5481 /* Write 0 to parser credits for CFC search request */
5482 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5483
5484 /* send 10 Ethernet packets */
5485 for (i = 0; i < 10; i++)
5486 bnx2x_lb_pckt(bp);
5487
5488 /* Wait until NIG register shows 10 + 1
5489 packets of size 11*0x10 = 0xb0 */
5490 count = 1000 * factor;
5491 while (count) {
34f80b04 5492
a2fbb9ea
ET		 5493 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5494 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5495 if (val == 0xb0)
5496 break;
5497
5498 msleep(10);
5499 count--;
5500 }
5501 if (val != 0xb0) {
5502 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5503 return -3;
5504 }
5505
5506 /* Wait until PRS register shows 2 packets */
5507 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5508 if (val != 2)
5509 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5510
5511 /* Write 1 to parser credits for CFC search request */
5512 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5513
5514 /* Wait until PRS register shows 3 packets */
5515 msleep(10 * factor);
5516 /* Wait until NIG register shows 1 packet of size 0x10 */
5517 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5518 if (val != 3)
5519 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5520
5521 /* clear NIG EOP FIFO */
5522 for (i = 0; i < 11; i++)
5523 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5524 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5525 if (val != 1) {
5526 BNX2X_ERR("clear of NIG failed\n");
5527 return -4;
5528 }
5529
5530 /* Reset and init BRB, PRS, NIG */
5531 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5532 msleep(50);
5533 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5534 msleep(50);
619c5cb6
VZ		 5535 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5536 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5537#ifndef BCM_CNIC
a2fbb9ea
ET		 5538 /* set NIC mode */
5539 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5540#endif
5541
5542 /* Enable inputs of parser neighbor blocks */
5543 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5544 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5545 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5546 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5547
5548 DP(NETIF_MSG_HW, "done\n");
5549
5550 return 0; /* OK */
5551}
5552
4a33bc03 5553static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5554{
5555 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5556 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5557 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5558 else
5559 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5560 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5561 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5562 /*
5563 * mask read length error interrupts in brb for parser
5564 * (parsing unit and 'checksum and crc' unit)
5565 * these errors are legal (PU reads fixed length and CAC can cause
5566 * read length error on truncated packets)
5567 */
5568 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5569 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5570 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5571 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5572 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5573 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5574/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5575/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5576 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5577 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5578 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5579/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5580/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5581 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5582 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5583 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5584 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5585/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5586/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5587
34f80b04
EG		 5588 if (CHIP_REV_IS_FPGA(bp))
5589 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5590 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5591 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5592 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5593 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5594 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5595 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5596 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5597 else
5598 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5599 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5600 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5601 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5602/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5603
5604 if (!CHIP_IS_E1x(bp))
5605 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5606 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5607
a2fbb9ea
ET		 5608 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5609 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5610/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5611 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5612}
5613
81f75bbf
EG		 5614static void bnx2x_reset_common(struct bnx2x *bp)
5615{
619c5cb6
VZ		 5616 u32 val = 0x1400;
5617
81f75bbf
EG		 5618 /* reset_common */
5619 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5620 0xd3ffff7f);
619c5cb6
VZ		 5621
5622 if (CHIP_IS_E3(bp)) {
5623 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5624 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5625 }
5626
5627 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5628}
5629
5630static void bnx2x_setup_dmae(struct bnx2x *bp)
5631{
5632 bp->dmae_ready = 0;
5633 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5634}
5635
573f2035
EG		 5636static void bnx2x_init_pxp(struct bnx2x *bp)
5637{
5638 u16 devctl;
5639 int r_order, w_order;
5640
5641 pci_read_config_word(bp->pdev,
77c98e6a 5642 bp->pdev->pcie_cap + PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 5643 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5644 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5645 if (bp->mrrs == -1)
5646 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5647 else {
5648 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5649 r_order = bp->mrrs;
5650 }
5651
5652 bnx2x_init_pxp_arb(bp, r_order, w_order);
5653}
fd4ef40d
EG		 5654
5655static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5656{
2145a920 5657 int is_required;
fd4ef40d 5658 u32 val;
2145a920 5659 int port;
fd4ef40d 5660
2145a920
VZ		 5661 if (BP_NOMCP(bp))
5662 return;
5663
5664 is_required = 0;
fd4ef40d
EG		 5665 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5666 SHARED_HW_CFG_FAN_FAILURE_MASK;
5667
5668 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5669 is_required = 1;
5670
5671 /*
5672 * The fan failure mechanism is usually related to the PHY type since
5673 * the power consumption of the board is affected by the PHY. Currently,
5674 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5675 */
5676 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5677 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5678 is_required |=
d90d96ba
YR		 5679 bnx2x_fan_failure_det_req(
5680 bp,
5681 bp->common.shmem_base,
a22f0788 5682 bp->common.shmem2_base,
d90d96ba 5683 port);
fd4ef40d
EG		 5684 }
5685
5686 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5687
5688 if (is_required == 0)
5689 return;
5690
5691 /* Fan failure is indicated by SPIO 5 */
5692 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5693 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5694
5695 /* set to active low mode */
5696 val = REG_RD(bp, MISC_REG_SPIO_INT);
5697 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5698 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5699 REG_WR(bp, MISC_REG_SPIO_INT, val);
5700
5701 /* enable interrupt to signal the IGU */
5702 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5703 val |= (1 << MISC_REGISTERS_SPIO_5);
5704 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5705}
5706
f2e0899f
DK		 5707static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5708{
5709 u32 offset = 0;
5710
5711 if (CHIP_IS_E1(bp))
5712 return;
5713 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5714 return;
5715
5716 switch (BP_ABS_FUNC(bp)) {
5717 case 0:
5718 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5719 break;
5720 case 1:
5721 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5722 break;
5723 case 2:
5724 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5725 break;
5726 case 3:
5727 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5728 break;
5729 case 4:
5730 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5731 break;
5732 case 5:
5733 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5734 break;
5735 case 6:
5736 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5737 break;
5738 case 7:
5739 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5740 break;
5741 default:
5742 return;
5743 }
5744
5745 REG_WR(bp, offset, pretend_func_num);
5746 REG_RD(bp, offset);
5747 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5748}
5749
c9ee9206 5750void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 5751{
5752 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5753 val &= ~IGU_PF_CONF_FUNC_EN;
5754
5755 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5756 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5757 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5758}
5759
619c5cb6
VZ		 5760static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5761{
5762 u32 shmem_base[2], shmem2_base[2];
5763 shmem_base[0] = bp->common.shmem_base;
5764 shmem2_base[0] = bp->common.shmem2_base;
5765 if (!CHIP_IS_E1x(bp)) {
5766 shmem_base[1] =
5767 SHMEM2_RD(bp, other_shmem_base_addr);
5768 shmem2_base[1] =
5769 SHMEM2_RD(bp, other_shmem2_base_addr);
5770 }
5771 bnx2x_acquire_phy_lock(bp);
5772 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5773 bp->common.chip_id);
5774 bnx2x_release_phy_lock(bp);
5775}
5776
5777/**
5778 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5779 *
5780 * @bp: driver handle
5781 */
5782static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 5783{
619c5cb6 5784 u32 val;
a2fbb9ea 5785
f2e0899f 5786 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 5787
81f75bbf 5788 bnx2x_reset_common(bp);
34f80b04 5789 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 5790
619c5cb6
VZ		 5791 val = 0xfffc;
5792 if (CHIP_IS_E3(bp)) {
5793 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5794 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5795 }
5796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5797
5798 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 5799
619c5cb6
VZ		 5800 if (!CHIP_IS_E1x(bp)) {
5801 u8 abs_func_id;
f2e0899f
DK		 5802
5803 /**
5804 * 4-port mode or 2-port mode we need to turn of master-enable
5805 * for everyone, after that, turn it back on for self.
5806 * so, we disregard multi-function or not, and always disable
5807 * for all functions on the given path, this means 0,2,4,6 for
5808 * path 0 and 1,3,5,7 for path 1
5809 */
619c5cb6
VZ		 5810 for (abs_func_id = BP_PATH(bp);
5811 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5812 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 5813 REG_WR(bp,
5814 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5815 1);
5816 continue;
5817 }
5818
619c5cb6 5819 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 5820 /* clear pf enable */
5821 bnx2x_pf_disable(bp);
5822 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5823 }
5824 }
a2fbb9ea 5825
619c5cb6 5826 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 5827 if (CHIP_IS_E1(bp)) {
5828 /* enable HW interrupt from PXP on USDM overflow
5829 bit 16 on INT_MASK_0 */
5830 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5831 }
a2fbb9ea 5832
619c5cb6 5833 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 5834 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5835
5836#ifdef __BIG_ENDIAN
34f80b04
EG		 5837 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5838 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5839 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5840 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5841 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5842 /* make sure this value is 0 */
5843 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5844
5845/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5846 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5847 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5848 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5849 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5850#endif
5851
523224a3
DK		 5852 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5853
34f80b04
EG		 5854 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5855 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5856
34f80b04
EG		 5857 /* let the HW do it's magic ... */
5858 msleep(100);
5859 /* finish PXP init */
5860 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5861 if (val != 1) {
5862 BNX2X_ERR("PXP2 CFG failed\n");
5863 return -EBUSY;
5864 }
5865 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5866 if (val != 1) {
5867 BNX2X_ERR("PXP2 RD_INIT failed\n");
5868 return -EBUSY;
5869 }
a2fbb9ea 5870
f2e0899f
DK		 5871 /* Timers bug workaround E2 only. We need to set the entire ILT to
5872 * have entries with value "0" and valid bit on.
5873 * This needs to be done by the first PF that is loaded in a path
5874 * (i.e. common phase)
5875 */
619c5cb6
VZ		 5876 if (!CHIP_IS_E1x(bp)) {
5877/* In E2 there is a bug in the timers block that can cause function 6 / 7
5878 * (i.e. vnic3) to start even if it is marked as "scan-off".
5879 * This occurs when a different function (func2,3) is being marked
5880 * as "scan-off". Real-life scenario for example: if a driver is being
5881 * load-unloaded while func6,7 are down. This will cause the timer to access
5882 * the ilt, translate to a logical address and send a request to read/write.
5883 * Since the ilt for the function that is down is not valid, this will cause
5884 * a translation error which is unrecoverable.
5885 * The Workaround is intended to make sure that when this happens nothing fatal
5886 * will occur. The workaround:
5887 * 1. First PF driver which loads on a path will:
5888 * a. After taking the chip out of reset, by using pretend,
5889 * it will write "0" to the following registers of
5890 * the other vnics.
5891 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5892 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5893 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5894 * And for itself it will write '1' to
5895 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5896 * dmae-operations (writing to pram for example.)
5897 * note: can be done for only function 6,7 but cleaner this
5898 * way.
5899 * b. Write zero+valid to the entire ILT.
5900 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5901 * VNIC3 (of that port). The range allocated will be the
5902 * entire ILT. This is needed to prevent ILT range error.
5903 * 2. Any PF driver load flow:
5904 * a. ILT update with the physical addresses of the allocated
5905 * logical pages.
5906 * b. Wait 20msec. - note that this timeout is needed to make
5907 * sure there are no requests in one of the PXP internal
5908 * queues with "old" ILT addresses.
5909 * c. PF enable in the PGLC.
5910 * d. Clear the was_error of the PF in the PGLC. (could have
5911 * occured while driver was down)
5912 * e. PF enable in the CFC (WEAK + STRONG)
5913 * f. Timers scan enable
5914 * 3. PF driver unload flow:
5915 * a. Clear the Timers scan_en.
5916 * b. Polling for scan_on=0 for that PF.
5917 * c. Clear the PF enable bit in the PXP.
5918 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5919 * e. Write zero+valid to all ILT entries (The valid bit must
5920 * stay set)
5921 * f. If this is VNIC 3 of a port then also init
5922 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5923 * to the last enrty in the ILT.
5924 *
5925 * Notes:
5926 * Currently the PF error in the PGLC is non recoverable.
5927 * In the future the there will be a recovery routine for this error.
5928 * Currently attention is masked.
5929 * Having an MCP lock on the load/unload process does not guarantee that
5930 * there is no Timer disable during Func6/7 enable. This is because the
5931 * Timers scan is currently being cleared by the MCP on FLR.
5932 * Step 2.d can be done only for PF6/7 and the driver can also check if
5933 * there is error before clearing it. But the flow above is simpler and
5934 * more general.
5935 * All ILT entries are written by zero+valid and not just PF6/7
5936 * ILT entries since in the future the ILT entries allocation for
5937 * PF-s might be dynamic.
5938 */
f2e0899f
DK		 5939 struct ilt_client_info ilt_cli;
5940 struct bnx2x_ilt ilt;
5941 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5942 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5943
b595076a 5944 /* initialize dummy TM client */
f2e0899f
DK		 5945 ilt_cli.start = 0;
5946 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5947 ilt_cli.client_num = ILT_CLIENT_TM;
5948
5949 /* Step 1: set zeroes to all ilt page entries with valid bit on
5950 * Step 2: set the timers first/last ilt entry to point
5951 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 5952 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 5953 *
5954 * both steps performed by call to bnx2x_ilt_client_init_op()
5955 * with dummy TM client
5956 *
5957 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5958 * and his brother are split registers
5959 */
5960 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5961 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5962 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5963
5964 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5965 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5966 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5967 }
5968
5969
34f80b04
EG		 5970 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5971 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5972
619c5cb6 5973 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5974 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5975 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 5976 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 5977
619c5cb6 5978 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 5979
5980 /* let the HW do it's magic ... */
5981 do {
5982 msleep(200);
5983 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5984 } while (factor-- && (val != 1));
5985
5986 if (val != 1) {
5987 BNX2X_ERR("ATC_INIT failed\n");
5988 return -EBUSY;
5989 }
5990 }
5991
619c5cb6 5992 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 5993
34f80b04
EG		 5994 /* clean the DMAE memory */
5995 bp->dmae_ready = 1;
619c5cb6
VZ		 5996 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
5997
5998 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
5999
6000 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6001
6002 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6003
619c5cb6 6004 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6005
34f80b04
EG		 6006 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6007 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6008 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6009 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6010
619c5cb6 6011 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6012
f85582f8 6013
523224a3
DK		 6014 /* QM queues pointers table */
6015 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6016
34f80b04
EG		 6017 /* soft reset pulse */
6018 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6019 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6020
37b091ba 6021#ifdef BCM_CNIC
619c5cb6 6022 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6023#endif
a2fbb9ea 6024
619c5cb6 6025 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6026 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6027 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6028 /* enable hw interrupt from doorbell Q */
6029 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6030
619c5cb6 6031 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6032
619c5cb6 6033 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6034 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6035
f2e0899f 6036 if (!CHIP_IS_E1(bp))
619c5cb6 6037 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6038
619c5cb6
VZ		 6039 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6040 /* Bit-map indicating which L2 hdrs may appear
6041 * after the basic Ethernet header
6042 */
6043 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6044 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 6045
619c5cb6
VZ		 6046 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6047 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6048 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6049 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6050
619c5cb6
VZ		 6051 if (!CHIP_IS_E1x(bp)) {
6052 /* reset VFC memories */
6053 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6054 VFC_MEMORIES_RST_REG_CAM_RST |
6055 VFC_MEMORIES_RST_REG_RAM_RST);
6056 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6057 VFC_MEMORIES_RST_REG_CAM_RST |
6058 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6059
619c5cb6
VZ		 6060 msleep(20);
6061 }
a2fbb9ea 6062
619c5cb6
VZ		 6063 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6064 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6065 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6066 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6067
34f80b04
EG		 6068 /* sync semi rtc */
6069 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6070 0x80000000);
6071 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6072 0x80000000);
a2fbb9ea 6073
619c5cb6
VZ		 6074 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6075 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6076 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6077
619c5cb6
VZ		 6078 if (!CHIP_IS_E1x(bp))
6079 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6080 bp->path_has_ovlan ? 7 : 6);
f2e0899f 6081
34f80b04 6082 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6083
619c5cb6
VZ		 6084 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6085
37b091ba
MC		 6086#ifdef BCM_CNIC
6087 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6088 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6089 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6090 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6091 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6092 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6093 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6094 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6095 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6096 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6097#endif
34f80b04 6098 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6099
34f80b04
EG		 6100 if (sizeof(union cdu_context) != 1024)
6101 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 6102 dev_alert(&bp->pdev->dev, "please adjust the size "
6103 "of cdu_context(%ld)\n",
7995c64e 6104 (long)sizeof(union cdu_context));
a2fbb9ea 6105
619c5cb6 6106 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6107 val = (4 << 24) + (0 << 12) + 1024;
6108 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6109
619c5cb6 6110 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6111 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6112 /* enable context validation interrupt from CFC */
6113 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6114
6115 /* set the thresholds to prevent CFC/CDU race */
6116 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6117
619c5cb6 6118 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6119
619c5cb6 6120 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6121 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6122
619c5cb6
VZ		 6123 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6124 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6125
34f80b04
EG		 6126 /* Reset PCIE errors for debug */
6127 REG_WR(bp, 0x2814, 0xffffffff);
6128 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6129
619c5cb6 6130 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6131 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6132 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6133 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6134 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6135 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6136 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6137 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6138 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6139 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6140 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6141 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6142 }
6143
619c5cb6 6144 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6145 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6146 /* in E3 this done in per-port section */
6147 if (!CHIP_IS_E3(bp))
6148 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6149 }
619c5cb6
VZ		 6150 if (CHIP_IS_E1H(bp))
6151 /* not applicable for E2 (and above ...) */
6152 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6153
6154 if (CHIP_REV_IS_SLOW(bp))
6155 msleep(200);
6156
6157 /* finish CFC init */
6158 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6159 if (val != 1) {
6160 BNX2X_ERR("CFC LL_INIT failed\n");
6161 return -EBUSY;
6162 }
6163 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6164 if (val != 1) {
6165 BNX2X_ERR("CFC AC_INIT failed\n");
6166 return -EBUSY;
6167 }
6168 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6169 if (val != 1) {
6170 BNX2X_ERR("CFC CAM_INIT failed\n");
6171 return -EBUSY;
6172 }
6173 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6174
f2e0899f
DK		 6175 if (CHIP_IS_E1(bp)) {
6176 /* read NIG statistic
6177 to see if this is our first up since powerup */
6178 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6179 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6180
f2e0899f
DK		 6181 /* do internal memory self test */
6182 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6183 BNX2X_ERR("internal mem self test failed\n");
6184 return -EBUSY;
6185 }
34f80b04
EG		 6186 }
6187
fd4ef40d
EG		 6188 bnx2x_setup_fan_failure_detection(bp);
6189
34f80b04
EG		 6190 /* clear PXP2 attentions */
6191 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6192
4a33bc03 6193 bnx2x_enable_blocks_attention(bp);
c9ee9206 6194 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6195
6bbca910 6196 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6197 if (CHIP_IS_E1x(bp))
6198 bnx2x__common_init_phy(bp);
6bbca910
YR		 6199 } else
6200 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6201
34f80b04
EG		 6202 return 0;
6203}
a2fbb9ea 6204
619c5cb6
VZ		 6205/**
6206 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6207 *
6208 * @bp: driver handle
6209 */
6210static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6211{
6212 int rc = bnx2x_init_hw_common(bp);
6213
6214 if (rc)
6215 return rc;
6216
6217 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6218 if (!BP_NOMCP(bp))
6219 bnx2x__common_init_phy(bp);
6220
6221 return 0;
6222}
6223
523224a3 6224static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6225{
6226 int port = BP_PORT(bp);
619c5cb6 6227 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6228 u32 low, high;
34f80b04 6229 u32 val;
a2fbb9ea 6230
619c5cb6
VZ		 6231 bnx2x__link_reset(bp);
6232
cdaa7cb8 6233 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 6234
6235 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6236
619c5cb6
VZ		 6237 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6238 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6239 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6240
f2e0899f
DK		 6241 /* Timers bug workaround: disables the pf_master bit in pglue at
6242 * common phase, we need to enable it here before any dmae access are
6243 * attempted. Therefore we manually added the enable-master to the
6244 * port phase (it also happens in the function phase)
6245 */
619c5cb6 6246 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6247 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6248
619c5cb6
VZ		 6249 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6250 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6251 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6252 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6253
6254 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6255 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6256 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6257 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6258
523224a3
DK		 6259 /* QM cid (connection) count */
6260 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6261
523224a3 6262#ifdef BCM_CNIC
619c5cb6 6263 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 6264 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6265 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 6266#endif
cdaa7cb8 6267
619c5cb6 6268 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 6269
6270 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6271 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6272
6273 if (IS_MF(bp))
6274 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6275 else if (bp->dev->mtu > 4096) {
6276 if (bp->flags & ONE_PORT_FLAG)
6277 low = 160;
6278 else {
6279 val = bp->dev->mtu;
6280 /* (24*1024 + val*4)/256 */
6281 low = 96 + (val/64) +
6282 ((val % 64) ? 1 : 0);
6283 }
6284 } else
6285 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6286 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6287 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6288 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6289 }
1c06328c 6290
619c5cb6
VZ		 6291 if (CHIP_MODE_IS_4_PORT(bp))
6292 REG_WR(bp, (BP_PORT(bp) ?
6293 BRB1_REG_MAC_GUARANTIED_1 :
6294 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6295
ca00392c 6296
619c5cb6
VZ		 6297 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6298 if (CHIP_IS_E3B0(bp))
6299 /* Ovlan exists only if we are in multi-function +
6300 * switch-dependent mode, in switch-independent there
6301 * is no ovlan headers
6302 */
6303 REG_WR(bp, BP_PORT(bp) ?
6304 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6305 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6306 (bp->path_has_ovlan ? 7 : 6));
356e2385 6307
619c5cb6
VZ		 6308 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6309 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6310 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6311 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 6312
619c5cb6
VZ		 6313 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6314 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6315 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6316 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 6317
619c5cb6
VZ		 6318 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6319 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 6320
619c5cb6
VZ		 6321 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6322
6323 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6324 /* configure PBF to work without PAUSE mtu 9000 */
6325 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 6326
f2e0899f
DK		 6327 /* update threshold */
6328 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6329 /* update init credit */
6330 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 6331
f2e0899f
DK		 6332 /* probe changes */
6333 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6334 udelay(50);
6335 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6336 }
a2fbb9ea 6337
37b091ba 6338#ifdef BCM_CNIC
619c5cb6 6339 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 6340#endif
619c5cb6
VZ		 6341 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6342 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 6343
6344 if (CHIP_IS_E1(bp)) {
6345 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6346 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6347 }
619c5cb6 6348 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 6349
619c5cb6 6350 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6351
619c5cb6 6352 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 6353 /* init aeu_mask_attn_func_0/1:
6354 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6355 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6356 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 6357 val = IS_MF(bp) ? 0xF7 : 0x7;
6358 /* Enable DCBX attention for all but E1 */
6359 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6360 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 6361
619c5cb6
VZ		 6362 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6363
6364 if (!CHIP_IS_E1x(bp)) {
6365 /* Bit-map indicating which L2 hdrs may appear after the
6366 * basic Ethernet header
6367 */
6368 REG_WR(bp, BP_PORT(bp) ?
6369 NIG_REG_P1_HDRS_AFTER_BASIC :
6370 NIG_REG_P0_HDRS_AFTER_BASIC,
6371 IS_MF_SD(bp) ? 7 : 6);
6372
6373 if (CHIP_IS_E3(bp))
6374 REG_WR(bp, BP_PORT(bp) ?
6375 NIG_REG_LLH1_MF_MODE :
6376 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6377 }
6378 if (!CHIP_IS_E3(bp))
6379 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 6380
f2e0899f 6381 if (!CHIP_IS_E1(bp)) {
fb3bff17 6382 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 6383 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 6384 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 6385
619c5cb6 6386 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6387 val = 0;
6388 switch (bp->mf_mode) {
6389 case MULTI_FUNCTION_SD:
6390 val = 1;
6391 break;
6392 case MULTI_FUNCTION_SI:
6393 val = 2;
6394 break;
6395 }
6396
6397 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6398 NIG_REG_LLH0_CLS_TYPE), val);
6399 }
1c06328c
EG		 6400 {
6401 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6402 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6403 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6404 }
34f80b04
EG		 6405 }
6406
619c5cb6
VZ		 6407
6408 /* If SPIO5 is set to generate interrupts, enable it for this port */
6409 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6410 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 6411 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6412 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6413 val = REG_RD(bp, reg_addr);
f1410647 6414 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 6415 REG_WR(bp, reg_addr, val);
f1410647 6416 }
a2fbb9ea 6417
34f80b04
EG		 6418 return 0;
6419}
6420
34f80b04
EG		 6421static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6422{
6423 int reg;
6424
f2e0899f 6425 if (CHIP_IS_E1(bp))
34f80b04 6426 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 6427 else
6428 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 6429
6430 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6431}
6432
f2e0899f
DK		 6433static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6434{
619c5cb6 6435 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 6436}
6437
6438static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6439{
6440 u32 i, base = FUNC_ILT_BASE(func);
6441 for (i = base; i < base + ILT_PER_FUNC; i++)
6442 bnx2x_ilt_wr(bp, i, 0);
6443}
6444
523224a3 6445static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 6446{
6447 int port = BP_PORT(bp);
6448 int func = BP_FUNC(bp);
619c5cb6 6449 int init_phase = PHASE_PF0 + func;
523224a3
DK		 6450 struct bnx2x_ilt *ilt = BP_ILT(bp);
6451 u16 cdu_ilt_start;
8badd27a 6452 u32 addr, val;
f4a66897
VZ		 6453 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6454 int i, main_mem_width;
34f80b04 6455
cdaa7cb8 6456 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 6457
619c5cb6
VZ		 6458 /* FLR cleanup - hmmm */
6459 if (!CHIP_IS_E1x(bp))
6460 bnx2x_pf_flr_clnup(bp);
6461
8badd27a 6462 /* set MSI reconfigure capability */
f2e0899f
DK		 6463 if (bp->common.int_block == INT_BLOCK_HC) {
6464 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6465 val = REG_RD(bp, addr);
6466 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6467 REG_WR(bp, addr, val);
6468 }
8badd27a 6469
619c5cb6
VZ		 6470 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6471 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6472
523224a3
DK		 6473 ilt = BP_ILT(bp);
6474 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6475
523224a3
DK		 6476 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6477 ilt->lines[cdu_ilt_start + i].page =
6478 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6479 ilt->lines[cdu_ilt_start + i].page_mapping =
6480 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6481 /* cdu ilt pages are allocated manually so there's no need to
6482 set the size */
37b091ba 6483 }
523224a3 6484 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6485
523224a3
DK		 6486#ifdef BCM_CNIC
6487 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6488
523224a3
DK		 6489 /* T1 hash bits value determines the T1 number of entries */
6490 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6491#endif
37b091ba 6492
523224a3
DK		 6493#ifndef BCM_CNIC
6494 /* set NIC mode */
6495 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6496#endif /* BCM_CNIC */
37b091ba 6497
619c5cb6 6498 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6499 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6500
6501 /* Turn on a single ISR mode in IGU if driver is going to use
6502 * INT#x or MSI
6503 */
6504 if (!(bp->flags & USING_MSIX_FLAG))
6505 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6506 /*
6507 * Timers workaround bug: function init part.
6508 * Need to wait 20msec after initializing ILT,
6509 * needed to make sure there are no requests in
6510 * one of the PXP internal queues with "old" ILT addresses
6511 */
6512 msleep(20);
6513 /*
6514 * Master enable - Due to WB DMAE writes performed before this
6515 * register is re-initialized as part of the regular function
6516 * init
6517 */
6518 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6519 /* Enable the function in IGU */
6520 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6521 }
6522
523224a3 6523 bp->dmae_ready = 1;
34f80b04 6524
619c5cb6 6525 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6526
619c5cb6 6527 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6528 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6529
619c5cb6
VZ		 6530 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6531 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6532 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6533 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6534 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6535 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6536 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6537 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6538 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6539 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6540 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6541 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6542 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6543
6544 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6545 REG_WR(bp, QM_REG_PF_EN, 1);
6546
619c5cb6
VZ		 6547 if (!CHIP_IS_E1x(bp)) {
6548 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6549 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6550 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6551 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6552 }
6553 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6554
6555 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6556 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6557 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6558 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6559 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6560 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6561 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6562 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6563 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6564 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6565 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6566 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6567 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6568
619c5cb6 6569 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6570
619c5cb6 6571 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6572
619c5cb6 6573 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6574 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6575
fb3bff17 6576 if (IS_MF(bp)) {
34f80b04 6577 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6578 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6579 }
6580
619c5cb6 6581 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6582
34f80b04 6583 /* HC init per function */
f2e0899f
DK		 6584 if (bp->common.int_block == INT_BLOCK_HC) {
6585 if (CHIP_IS_E1H(bp)) {
6586 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6587
6588 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6589 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6590 }
619c5cb6 6591 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6592
6593 } else {
6594 int num_segs, sb_idx, prod_offset;
6595
34f80b04
EG		 6596 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6597
619c5cb6 6598 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6599 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6600 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6601 }
6602
619c5cb6 6603 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6604
619c5cb6 6605 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6606 int dsb_idx = 0;
6607 /**
6608 * Producer memory:
6609 * E2 mode: address 0-135 match to the mapping memory;
6610 * 136 - PF0 default prod; 137 - PF1 default prod;
6611 * 138 - PF2 default prod; 139 - PF3 default prod;
6612 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6613 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6614 * 144-147 reserved.
6615 *
6616 * E1.5 mode - In backward compatible mode;
6617 * for non default SB; each even line in the memory
6618 * holds the U producer and each odd line hold
6619 * the C producer. The first 128 producers are for
6620 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6621 * producers are for the DSB for each PF.
6622 * Each PF has five segments: (the order inside each
6623 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6624 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6625 * 144-147 attn prods;
6626 */
6627 /* non-default-status-blocks */
6628 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6629 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6630 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6631 prod_offset = (bp->igu_base_sb + sb_idx) *
6632 num_segs;
6633
6634 for (i = 0; i < num_segs; i++) {
6635 addr = IGU_REG_PROD_CONS_MEMORY +
6636 (prod_offset + i) * 4;
6637 REG_WR(bp, addr, 0);
6638 }
6639 /* send consumer update with value 0 */
6640 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6641 USTORM_ID, 0, IGU_INT_NOP, 1);
6642 bnx2x_igu_clear_sb(bp,
6643 bp->igu_base_sb + sb_idx);
6644 }
6645
6646 /* default-status-blocks */
6647 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6648 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6649
6650 if (CHIP_MODE_IS_4_PORT(bp))
6651 dsb_idx = BP_FUNC(bp);
6652 else
6653 dsb_idx = BP_E1HVN(bp);
6654
6655 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6656 IGU_BC_BASE_DSB_PROD + dsb_idx :
6657 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6658
6659 for (i = 0; i < (num_segs * E1HVN_MAX);
6660 i += E1HVN_MAX) {
6661 addr = IGU_REG_PROD_CONS_MEMORY +
6662 (prod_offset + i)*4;
6663 REG_WR(bp, addr, 0);
6664 }
6665 /* send consumer update with 0 */
6666 if (CHIP_INT_MODE_IS_BC(bp)) {
6667 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6668 USTORM_ID, 0, IGU_INT_NOP, 1);
6669 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6670 CSTORM_ID, 0, IGU_INT_NOP, 1);
6671 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6672 XSTORM_ID, 0, IGU_INT_NOP, 1);
6673 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6674 TSTORM_ID, 0, IGU_INT_NOP, 1);
6675 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6676 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6677 } else {
6678 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6679 USTORM_ID, 0, IGU_INT_NOP, 1);
6680 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6681 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6682 }
6683 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6684
6685 /* !!! these should become driver const once
6686 rf-tool supports split-68 const */
6687 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6688 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6689 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6690 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6691 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6692 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6693 }
34f80b04 6694 }
34f80b04 6695
c14423fe 6696 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6697 REG_WR(bp, 0x2114, 0xffffffff);
6698 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6699
f4a66897
VZ		 6700 if (CHIP_IS_E1x(bp)) {
6701 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6702 main_mem_base = HC_REG_MAIN_MEMORY +
6703 BP_PORT(bp) * (main_mem_size * 4);
6704 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6705 main_mem_width = 8;
6706
6707 val = REG_RD(bp, main_mem_prty_clr);
6708 if (val)
6709 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6710 "block during "
6711 "function init (0x%x)!\n", val);
6712
6713 /* Clear "false" parity errors in MSI-X table */
6714 for (i = main_mem_base;
6715 i < main_mem_base + main_mem_size * 4;
6716 i += main_mem_width) {
6717 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6718 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6719 i, main_mem_width / 4);
6720 }
6721 /* Clear HC parity attention */
6722 REG_RD(bp, main_mem_prty_clr);
6723 }
6724
619c5cb6
VZ		 6725#ifdef BNX2X_STOP_ON_ERROR
6726 /* Enable STORMs SP logging */
6727 REG_WR8(bp, BAR_USTRORM_INTMEM +
6728 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6729 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6730 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6731 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6732 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6733 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6734 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6735#endif
6736
b7737c9b 6737 bnx2x_phy_probe(&bp->link_params);
f85582f8 6738
34f80b04
EG		 6739 return 0;
6740}
6741
a2fbb9ea 6742
9f6c9258 6743void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 6744{
a2fbb9ea 6745 /* fastpath */
b3b83c3f 6746 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 6747 /* end of fastpath */
6748
6749 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 6750 sizeof(struct host_sp_status_block));
a2fbb9ea 6751
619c5cb6
VZ		 6752 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6753 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6754
a2fbb9ea 6755 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 6756 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6757
523224a3
DK		 6758 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6759 bp->context.size);
6760
6761 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6762
6763 BNX2X_FREE(bp->ilt->lines);
f85582f8 6764
37b091ba 6765#ifdef BCM_CNIC
619c5cb6 6766 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6767 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6768 sizeof(struct host_hc_status_block_e2));
6769 else
6770 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6771 sizeof(struct host_hc_status_block_e1x));
f85582f8 6772
523224a3 6773 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 6774#endif
f85582f8 6775
7a9b2557 6776 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 6777
523224a3
DK		 6778 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6779 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 6780}
6781
6782static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6783{
6784 int num_groups;
6785
6786 /* number of eth_queues */
6787 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6788
6789 /* Total number of FW statistics requests =
6790 * 1 for port stats + 1 for PF stats + num_eth_queues */
6791 bp->fw_stats_num = 2 + num_queue_stats;
523224a3 6792
619c5cb6
VZ		 6793
6794 /* Request is built from stats_query_header and an array of
6795 * stats_query_cmd_group each of which contains
6796 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6797 * configured in the stats_query_header.
6798 */
6799 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6800 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6801
6802 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6803 num_groups * sizeof(struct stats_query_cmd_group);
6804
6805 /* Data for statistics requests + stats_conter
6806 *
6807 * stats_counter holds per-STORM counters that are incremented
6808 * when STORM has finished with the current request.
6809 */
6810 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6811 sizeof(struct per_pf_stats) +
6812 sizeof(struct per_queue_stats) * num_queue_stats +
6813 sizeof(struct stats_counter);
6814
6815 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6816 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6817
6818 /* Set shortcuts */
6819 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6820 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6821
6822 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6823 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6824
6825 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6826 bp->fw_stats_req_sz;
6827 return 0;
6828
6829alloc_mem_err:
6830 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6831 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6832 return -ENOMEM;
a2fbb9ea
ET		 6833}
6834
f2e0899f 6835
9f6c9258 6836int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6837{
523224a3 6838#ifdef BCM_CNIC
619c5cb6
VZ		 6839 if (!CHIP_IS_E1x(bp))
6840 /* size = the status block + ramrod buffers */
f2e0899f
DK		 6841 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6842 sizeof(struct host_hc_status_block_e2));
6843 else
6844 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6845 sizeof(struct host_hc_status_block_e1x));
8badd27a 6846
523224a3
DK		 6847 /* allocate searcher T2 table */
6848 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6849#endif
a2fbb9ea 6850
8badd27a 6851
523224a3
DK		 6852 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6853 sizeof(struct host_sp_status_block));
a2fbb9ea 6854
523224a3
DK		 6855 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6856 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6857
619c5cb6
VZ		 6858 /* Allocated memory for FW statistics */
6859 if (bnx2x_alloc_fw_stats_mem(bp))
6860 goto alloc_mem_err;
6861
6383c0b3 6862 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
f85582f8 6863
523224a3
DK		 6864 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6865 bp->context.size);
65abd74d 6866
523224a3 6867 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6868
523224a3
DK		 6869 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6870 goto alloc_mem_err;
65abd74d 6871
9f6c9258
DK		 6872 /* Slow path ring */
6873 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6874
523224a3
DK		 6875 /* EQ */
6876 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6877 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 6878
b3b83c3f
DK		 6879
6880 /* fastpath */
6881 /* need to be done at the end, since it's self adjusting to amount
6882 * of memory available for RSS queues
6883 */
6884 if (bnx2x_alloc_fp_mem(bp))
6885 goto alloc_mem_err;
9f6c9258 6886 return 0;
e1510706 6887
9f6c9258
DK		 6888alloc_mem_err:
6889 bnx2x_free_mem(bp);
6890 return -ENOMEM;
65abd74d
YG		 6891}
6892
a2fbb9ea
ET		 6893/*
6894 * Init service functions
6895 */
a2fbb9ea 6896
619c5cb6
VZ		 6897int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6898 struct bnx2x_vlan_mac_obj *obj, bool set,
6899 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 6900{
619c5cb6
VZ		 6901 int rc;
6902 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 6903
619c5cb6 6904 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 6905
619c5cb6
VZ		 6906 /* Fill general parameters */
6907 ramrod_param.vlan_mac_obj = obj;
6908 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 6909
619c5cb6
VZ		 6910 /* Fill a user request section if needed */
6911 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6912 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 6913
619c5cb6 6914 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 6915
619c5cb6
VZ		 6916 /* Set the command: ADD or DEL */
6917 if (set)
6918 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6919 else
6920 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 6921 }
6922
619c5cb6
VZ		 6923 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6924 if (rc < 0)
6925 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6926 return rc;
a2fbb9ea
ET		 6927}
6928
619c5cb6
VZ		 6929int bnx2x_del_all_macs(struct bnx2x *bp,
6930 struct bnx2x_vlan_mac_obj *mac_obj,
6931 int mac_type, bool wait_for_comp)
e665bfda 6932{
619c5cb6
VZ		 6933 int rc;
6934 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 6935
619c5cb6
VZ		 6936 /* Wait for completion of requested */
6937 if (wait_for_comp)
6938 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 6939
619c5cb6
VZ		 6940 /* Set the mac type of addresses we want to clear */
6941 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 6942
619c5cb6
VZ		 6943 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6944 if (rc < 0)
6945 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 6946
619c5cb6 6947 return rc;
0793f83f
DK		 6948}
6949
619c5cb6 6950int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 6951{
619c5cb6 6952 unsigned long ramrod_flags = 0;
e665bfda 6953
619c5cb6 6954 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 6955
619c5cb6
VZ		 6956 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6957 /* Eth MAC is set on RSS leading client (fp[0]) */
6958 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6959 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 6960}
6e30dd4e 6961
619c5cb6 6962int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 6963{
619c5cb6 6964 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 6965}
a2fbb9ea 6966
d6214d7a 6967/**
e8920674 6968 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 6969 *
e8920674 6970 * @bp: driver handle
d6214d7a 6971 *
e8920674 6972 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 6973 */
9ee3d37b 6974static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6975{
9ee3d37b 6976 switch (int_mode) {
d6214d7a
DK		 6977 case INT_MODE_MSI:
6978 bnx2x_enable_msi(bp);
6979 /* falling through... */
6980 case INT_MODE_INTx:
6383c0b3 6981 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 6982 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 6983 break;
d6214d7a
DK		 6984 default:
6985 /* Set number of queues according to bp->multi_mode value */
6986 bnx2x_set_num_queues(bp);
ca00392c 6987
d6214d7a
DK		 6988 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6989 bp->num_queues);
ca00392c 6990
d6214d7a
DK		 6991 /* if we can't use MSI-X we only need one fp,
6992 * so try to enable MSI-X with the requested number of fp's
6993 * and fallback to MSI or legacy INTx with one fp
6994 */
9ee3d37b 6995 if (bnx2x_enable_msix(bp)) {
d6214d7a
DK		 6996 /* failed to enable MSI-X */
6997 if (bp->multi_mode)
6998 DP(NETIF_MSG_IFUP,
6999 "Multi requested but failed to "
7000 "enable MSI-X (%d), "
7001 "set number of queues to %d\n",
7002 bp->num_queues,
6383c0b3
AE		 7003 1 + NON_ETH_CONTEXT_USE);
7004 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7005
9ee3d37b 7006 /* Try to enable MSI */
d6214d7a
DK		 7007 if (!(bp->flags & DISABLE_MSI_FLAG))
7008 bnx2x_enable_msi(bp);
7009 }
9f6c9258
DK		 7010 break;
7011 }
a2fbb9ea
ET		 7012}
7013
c2bff63f
DK		 7014/* must be called prioir to any HW initializations */
7015static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7016{
7017 return L2_ILT_LINES(bp);
7018}
7019
523224a3
DK		 7020void bnx2x_ilt_set_info(struct bnx2x *bp)
7021{
7022 struct ilt_client_info *ilt_client;
7023 struct bnx2x_ilt *ilt = BP_ILT(bp);
7024 u16 line = 0;
7025
7026 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7027 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7028
7029 /* CDU */
7030 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7031 ilt_client->client_num = ILT_CLIENT_CDU;
7032 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7033 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7034 ilt_client->start = line;
619c5cb6 7035 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 7036#ifdef BCM_CNIC
7037 line += CNIC_ILT_LINES;
7038#endif
7039 ilt_client->end = line - 1;
7040
7041 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7042 "flags 0x%x, hw psz %d\n",
7043 ilt_client->start,
7044 ilt_client->end,
7045 ilt_client->page_size,
7046 ilt_client->flags,
7047 ilog2(ilt_client->page_size >> 12));
7048
7049 /* QM */
7050 if (QM_INIT(bp->qm_cid_count)) {
7051 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7052 ilt_client->client_num = ILT_CLIENT_QM;
7053 ilt_client->page_size = QM_ILT_PAGE_SZ;
7054 ilt_client->flags = 0;
7055 ilt_client->start = line;
7056
7057 /* 4 bytes for each cid */
7058 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7059 QM_ILT_PAGE_SZ);
7060
7061 ilt_client->end = line - 1;
7062
7063 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7064 "flags 0x%x, hw psz %d\n",
7065 ilt_client->start,
7066 ilt_client->end,
7067 ilt_client->page_size,
7068 ilt_client->flags,
7069 ilog2(ilt_client->page_size >> 12));
7070
7071 }
7072 /* SRC */
7073 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7074#ifdef BCM_CNIC
7075 ilt_client->client_num = ILT_CLIENT_SRC;
7076 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7077 ilt_client->flags = 0;
7078 ilt_client->start = line;
7079 line += SRC_ILT_LINES;
7080 ilt_client->end = line - 1;
7081
7082 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7083 "flags 0x%x, hw psz %d\n",
7084 ilt_client->start,
7085 ilt_client->end,
7086 ilt_client->page_size,
7087 ilt_client->flags,
7088 ilog2(ilt_client->page_size >> 12));
7089
7090#else
7091 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7092#endif
9f6c9258 7093
523224a3
DK		 7094 /* TM */
7095 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7096#ifdef BCM_CNIC
7097 ilt_client->client_num = ILT_CLIENT_TM;
7098 ilt_client->page_size = TM_ILT_PAGE_SZ;
7099 ilt_client->flags = 0;
7100 ilt_client->start = line;
7101 line += TM_ILT_LINES;
7102 ilt_client->end = line - 1;
7103
7104 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7105 "flags 0x%x, hw psz %d\n",
7106 ilt_client->start,
7107 ilt_client->end,
7108 ilt_client->page_size,
7109 ilt_client->flags,
7110 ilog2(ilt_client->page_size >> 12));
9f6c9258 7111
523224a3
DK		 7112#else
7113 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7114#endif
619c5cb6 7115 BUG_ON(line > ILT_MAX_LINES);
523224a3 7116}
f85582f8 7117
619c5cb6
VZ		 7118/**
7119 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7120 *
7121 * @bp: driver handle
7122 * @fp: pointer to fastpath
7123 * @init_params: pointer to parameters structure
7124 *
7125 * parameters configured:
7126 * - HC configuration
7127 * - Queue's CDU context
7128 */
7129static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7130 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 7131{
6383c0b3
AE		 7132
7133 u8 cos;
619c5cb6
VZ		 7134 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7135 if (!IS_FCOE_FP(fp)) {
7136 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7137 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7138
7139 /* If HC is supporterd, enable host coalescing in the transition
7140 * to INIT state.
7141 */
7142 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7143 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7144
7145 /* HC rate */
7146 init_params->rx.hc_rate = bp->rx_ticks ?
7147 (1000000 / bp->rx_ticks) : 0;
7148 init_params->tx.hc_rate = bp->tx_ticks ?
7149 (1000000 / bp->tx_ticks) : 0;
7150
7151 /* FW SB ID */
7152 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7153 fp->fw_sb_id;
7154
7155 /*
7156 * CQ index among the SB indices: FCoE clients uses the default
7157 * SB, therefore it's different.
7158 */
6383c0b3
AE		 7159 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7160 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 7161 }
7162
6383c0b3
AE		 7163 /* set maximum number of COSs supported by this queue */
7164 init_params->max_cos = fp->max_cos;
7165
7166 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7167 fp->index, init_params->max_cos);
7168
7169 /* set the context pointers queue object */
7170 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7171 init_params->cxts[cos] =
7172 &bp->context.vcxt[fp->txdata[cos].cid].eth;
619c5cb6
VZ		 7173}
7174
6383c0b3
AE		 7175int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7176 struct bnx2x_queue_state_params *q_params,
7177 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7178 int tx_index, bool leading)
7179{
7180 memset(tx_only_params, 0, sizeof(*tx_only_params));
7181
7182 /* Set the command */
7183 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7184
7185 /* Set tx-only QUEUE flags: don't zero statistics */
7186 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7187
7188 /* choose the index of the cid to send the slow path on */
7189 tx_only_params->cid_index = tx_index;
7190
7191 /* Set general TX_ONLY_SETUP parameters */
7192 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7193
7194 /* Set Tx TX_ONLY_SETUP parameters */
7195 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7196
7197 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7198 "cos %d, primary cid %d, cid %d, "
7199 "client id %d, sp-client id %d, flags %lx",
7200 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7201 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7202 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7203
7204 /* send the ramrod */
7205 return bnx2x_queue_state_change(bp, q_params);
7206}
7207
7208
619c5cb6
VZ		 7209/**
7210 * bnx2x_setup_queue - setup queue
7211 *
7212 * @bp: driver handle
7213 * @fp: pointer to fastpath
7214 * @leading: is leading
7215 *
7216 * This function performs 2 steps in a Queue state machine
7217 * actually: 1) RESET->INIT 2) INIT->SETUP
7218 */
7219
7220int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7221 bool leading)
7222{
7223 struct bnx2x_queue_state_params q_params = {0};
7224 struct bnx2x_queue_setup_params *setup_params =
7225 &q_params.params.setup;
6383c0b3
AE		 7226 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7227 &q_params.params.tx_only;
a2fbb9ea 7228 int rc;
6383c0b3
AE		 7229 u8 tx_index;
7230
7231 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
a2fbb9ea 7232
ec6ba945
VZ		 7233 /* reset IGU state skip FCoE L2 queue */
7234 if (!IS_FCOE_FP(fp))
7235 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 7236 IGU_INT_ENABLE, 0);
a2fbb9ea 7237
619c5cb6
VZ		 7238 q_params.q_obj = &fp->q_obj;
7239 /* We want to wait for completion in this context */
7240 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7241
619c5cb6
VZ		 7242 /* Prepare the INIT parameters */
7243 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 7244
619c5cb6
VZ		 7245 /* Set the command */
7246 q_params.cmd = BNX2X_Q_CMD_INIT;
7247
7248 /* Change the state to INIT */
7249 rc = bnx2x_queue_state_change(bp, &q_params);
7250 if (rc) {
6383c0b3 7251 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 7252 return rc;
7253 }
ec6ba945 7254
6383c0b3
AE		 7255 DP(BNX2X_MSG_SP, "init complete");
7256
7257
619c5cb6
VZ		 7258 /* Now move the Queue to the SETUP state... */
7259 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 7260
619c5cb6
VZ		 7261 /* Set QUEUE flags */
7262 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 7263
619c5cb6 7264 /* Set general SETUP parameters */
6383c0b3
AE		 7265 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7266 FIRST_TX_COS_INDEX);
619c5cb6 7267
6383c0b3 7268 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 7269 &setup_params->rxq_params);
7270
6383c0b3
AE		 7271 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7272 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 7273
7274 /* Set the command */
7275 q_params.cmd = BNX2X_Q_CMD_SETUP;
7276
7277 /* Change the state to SETUP */
7278 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 7279 if (rc) {
7280 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7281 return rc;
7282 }
7283
7284 /* loop through the relevant tx-only indices */
7285 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7286 tx_index < fp->max_cos;
7287 tx_index++) {
7288
7289 /* prepare and send tx-only ramrod*/
7290 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7291 tx_only_params, tx_index, leading);
7292 if (rc) {
7293 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7294 fp->index, tx_index);
7295 return rc;
7296 }
7297 }
523224a3 7298
34f80b04 7299 return rc;
a2fbb9ea
ET		 7300}
7301
619c5cb6 7302static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 7303{
619c5cb6 7304 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 7305 struct bnx2x_fp_txdata *txdata;
619c5cb6 7306 struct bnx2x_queue_state_params q_params = {0};
6383c0b3
AE		 7307 int rc, tx_index;
7308
7309 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
a2fbb9ea 7310
619c5cb6
VZ		 7311 q_params.q_obj = &fp->q_obj;
7312 /* We want to wait for completion in this context */
7313 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7314
6383c0b3
AE		 7315
7316 /* close tx-only connections */
7317 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7318 tx_index < fp->max_cos;
7319 tx_index++){
7320
7321 /* ascertain this is a normal queue*/
7322 txdata = &fp->txdata[tx_index];
7323
7324 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7325 txdata->txq_index);
7326
7327 /* send halt terminate on tx-only connection */
7328 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7329 memset(&q_params.params.terminate, 0,
7330 sizeof(q_params.params.terminate));
7331 q_params.params.terminate.cid_index = tx_index;
7332
7333 rc = bnx2x_queue_state_change(bp, &q_params);
7334 if (rc)
7335 return rc;
7336
7337 /* send halt terminate on tx-only connection */
7338 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7339 memset(&q_params.params.cfc_del, 0,
7340 sizeof(q_params.params.cfc_del));
7341 q_params.params.cfc_del.cid_index = tx_index;
7342 rc = bnx2x_queue_state_change(bp, &q_params);
7343 if (rc)
7344 return rc;
7345 }
7346 /* Stop the primary connection: */
7347 /* ...halt the connection */
619c5cb6
VZ		 7348 q_params.cmd = BNX2X_Q_CMD_HALT;
7349 rc = bnx2x_queue_state_change(bp, &q_params);
7350 if (rc)
da5a662a 7351 return rc;
a2fbb9ea 7352
6383c0b3 7353 /* ...terminate the connection */
619c5cb6 7354 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 7355 memset(&q_params.params.terminate, 0,
7356 sizeof(q_params.params.terminate));
7357 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 7358 rc = bnx2x_queue_state_change(bp, &q_params);
7359 if (rc)
523224a3 7360 return rc;
6383c0b3 7361 /* ...delete cfc entry */
619c5cb6 7362 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 7363 memset(&q_params.params.cfc_del, 0,
7364 sizeof(q_params.params.cfc_del));
7365 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 7366 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 7367}
7368
7369
34f80b04
EG		 7370static void bnx2x_reset_func(struct bnx2x *bp)
7371{
7372 int port = BP_PORT(bp);
7373 int func = BP_FUNC(bp);
f2e0899f 7374 int i;
523224a3
DK		 7375
7376 /* Disable the function in the FW */
7377 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7378 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7379 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7380 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7381
7382 /* FP SBs */
ec6ba945 7383 for_each_eth_queue(bp, i) {
523224a3 7384 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 7385 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7386 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7387 SB_DISABLED);
523224a3
DK		 7388 }
7389
619c5cb6
VZ		 7390#ifdef BCM_CNIC
7391 /* CNIC SB */
7392 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7393 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7394 SB_DISABLED);
7395#endif
523224a3 7396 /* SP SB */
619c5cb6 7397 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7398 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7399 SB_DISABLED);
523224a3
DK		 7400
7401 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7402 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7403 0);
34f80b04
EG		 7404
7405 /* Configure IGU */
f2e0899f
DK		 7406 if (bp->common.int_block == INT_BLOCK_HC) {
7407 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7408 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7409 } else {
7410 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7411 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7412 }
34f80b04 7413
37b091ba
MC		 7414#ifdef BCM_CNIC
7415 /* Disable Timer scan */
7416 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7417 /*
7418 * Wait for at least 10ms and up to 2 second for the timers scan to
7419 * complete
7420 */
7421 for (i = 0; i < 200; i++) {
7422 msleep(10);
7423 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7424 break;
7425 }
7426#endif
34f80b04 7427 /* Clear ILT */
f2e0899f
DK		 7428 bnx2x_clear_func_ilt(bp, func);
7429
7430 /* Timers workaround bug for E2: if this is vnic-3,
7431 * we need to set the entire ilt range for this timers.
7432 */
619c5cb6 7433 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 7434 struct ilt_client_info ilt_cli;
7435 /* use dummy TM client */
7436 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7437 ilt_cli.start = 0;
7438 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7439 ilt_cli.client_num = ILT_CLIENT_TM;
7440
7441 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7442 }
7443
7444 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 7445 if (!CHIP_IS_E1x(bp))
f2e0899f 7446 bnx2x_pf_disable(bp);
523224a3
DK		 7447
7448 bp->dmae_ready = 0;
34f80b04
EG		 7449}
7450
7451static void bnx2x_reset_port(struct bnx2x *bp)
7452{
7453 int port = BP_PORT(bp);
7454 u32 val;
7455
619c5cb6
VZ		 7456 /* Reset physical Link */
7457 bnx2x__link_reset(bp);
7458
34f80b04
EG		 7459 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7460
7461 /* Do not rcv packets to BRB */
7462 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7463 /* Do not direct rcv packets that are not for MCP to the BRB */
7464 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7465 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7466
7467 /* Configure AEU */
7468 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7469
7470 msleep(100);
7471 /* Check for BRB port occupancy */
7472 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7473 if (val)
7474 DP(NETIF_MSG_IFDOWN,
33471629 7475 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7476
7477 /* TODO: Close Doorbell port? */
7478}
7479
619c5cb6 7480static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 7481{
619c5cb6 7482 struct bnx2x_func_state_params func_params = {0};
34f80b04 7483
619c5cb6
VZ		 7484 /* Prepare parameters for function state transitions */
7485 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 7486
619c5cb6
VZ		 7487 func_params.f_obj = &bp->func_obj;
7488 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 7489
619c5cb6 7490 func_params.params.hw_init.load_phase = load_code;
49d66772 7491
619c5cb6 7492 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 7493}
7494
619c5cb6 7495static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 7496{
619c5cb6
VZ		 7497 struct bnx2x_func_state_params func_params = {0};
7498 int rc;
228241eb 7499
619c5cb6
VZ		 7500 /* Prepare parameters for function state transitions */
7501 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7502 func_params.f_obj = &bp->func_obj;
7503 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 7504
619c5cb6
VZ		 7505 /*
7506 * Try to stop the function the 'good way'. If fails (in case
7507 * of a parity error during bnx2x_chip_cleanup()) and we are
7508 * not in a debug mode, perform a state transaction in order to
7509 * enable further HW_RESET transaction.
7510 */
7511 rc = bnx2x_func_state_change(bp, &func_params);
7512 if (rc) {
34f80b04 7513#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 7514 return rc;
34f80b04 7515#else
619c5cb6
VZ		 7516 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7517 "transaction\n");
7518 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7519 return bnx2x_func_state_change(bp, &func_params);
34f80b04 7520#endif
228241eb 7521 }
a2fbb9ea 7522
619c5cb6
VZ		 7523 return 0;
7524}
523224a3 7525
619c5cb6
VZ		 7526/**
7527 * bnx2x_send_unload_req - request unload mode from the MCP.
7528 *
7529 * @bp: driver handle
7530 * @unload_mode: requested function's unload mode
7531 *
7532 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7533 */
7534u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7535{
7536 u32 reset_code = 0;
7537 int port = BP_PORT(bp);
3101c2bc 7538
619c5cb6 7539 /* Select the UNLOAD request mode */
65abd74d
YG		 7540 if (unload_mode == UNLOAD_NORMAL)
7541 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7542
7d0446c2 7543 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7544 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7545
7d0446c2 7546 else if (bp->wol) {
65abd74d
YG		 7547 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7548 u8 *mac_addr = bp->dev->dev_addr;
7549 u32 val;
7550 /* The mac address is written to entries 1-4 to
7551 preserve entry 0 which is used by the PMF */
7552 u8 entry = (BP_E1HVN(bp) + 1)*8;
7553
7554 val = (mac_addr[0] << 8) | mac_addr[1];
7555 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7556
7557 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7558 (mac_addr[4] << 8) | mac_addr[5];
7559 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7560
7561 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7562
7563 } else
7564 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7565
619c5cb6
VZ		 7566 /* Send the request to the MCP */
7567 if (!BP_NOMCP(bp))
7568 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7569 else {
7570 int path = BP_PATH(bp);
7571
7572 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7573 "%d, %d, %d\n",
7574 path, load_count[path][0], load_count[path][1],
7575 load_count[path][2]);
7576 load_count[path][0]--;
7577 load_count[path][1 + port]--;
7578 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7579 "%d, %d, %d\n",
7580 path, load_count[path][0], load_count[path][1],
7581 load_count[path][2]);
7582 if (load_count[path][0] == 0)
7583 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7584 else if (load_count[path][1 + port] == 0)
7585 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7586 else
7587 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7588 }
7589
7590 return reset_code;
7591}
7592
7593/**
7594 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7595 *
7596 * @bp: driver handle
7597 */
7598void bnx2x_send_unload_done(struct bnx2x *bp)
7599{
7600 /* Report UNLOAD_DONE to MCP */
7601 if (!BP_NOMCP(bp))
7602 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7603}
7604
6debea87
DK		 7605static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7606{
7607 int tout = 50;
7608 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7609
7610 if (!bp->port.pmf)
7611 return 0;
7612
7613 /*
7614 * (assumption: No Attention from MCP at this stage)
7615 * PMF probably in the middle of TXdisable/enable transaction
7616 * 1. Sync IRS for default SB
7617 * 2. Sync SP queue - this guarantes us that attention handling started
7618 * 3. Wait, that TXdisable/enable transaction completes
7619 *
7620 * 1+2 guranty that if DCBx attention was scheduled it already changed
7621 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7622 * received complettion for the transaction the state is TX_STOPPED.
7623 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7624 * transaction.
7625 */
7626
7627 /* make sure default SB ISR is done */
7628 if (msix)
7629 synchronize_irq(bp->msix_table[0].vector);
7630 else
7631 synchronize_irq(bp->pdev->irq);
7632
7633 flush_workqueue(bnx2x_wq);
7634
7635 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7636 BNX2X_F_STATE_STARTED && tout--)
7637 msleep(20);
7638
7639 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7640 BNX2X_F_STATE_STARTED) {
7641#ifdef BNX2X_STOP_ON_ERROR
7642 return -EBUSY;
7643#else
7644 /*
7645 * Failed to complete the transaction in a "good way"
7646 * Force both transactions with CLR bit
7647 */
7648 struct bnx2x_func_state_params func_params = {0};
7649
7650 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7651 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7652
7653 func_params.f_obj = &bp->func_obj;
7654 __set_bit(RAMROD_DRV_CLR_ONLY,
7655 &func_params.ramrod_flags);
7656
7657 /* STARTED-->TX_ST0PPED */
7658 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7659 bnx2x_func_state_change(bp, &func_params);
7660
7661 /* TX_ST0PPED-->STARTED */
7662 func_params.cmd = BNX2X_F_CMD_TX_START;
7663 return bnx2x_func_state_change(bp, &func_params);
7664#endif
7665 }
7666
7667 return 0;
7668}
7669
619c5cb6
VZ		 7670void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7671{
7672 int port = BP_PORT(bp);
6383c0b3
AE		 7673 int i, rc = 0;
7674 u8 cos;
619c5cb6
VZ		 7675 struct bnx2x_mcast_ramrod_params rparam = {0};
7676 u32 reset_code;
7677
7678 /* Wait until tx fastpath tasks complete */
7679 for_each_tx_queue(bp, i) {
7680 struct bnx2x_fastpath *fp = &bp->fp[i];
7681
6383c0b3
AE		 7682 for_each_cos_in_tx_queue(fp, cos)
7683 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
619c5cb6
VZ		 7684#ifdef BNX2X_STOP_ON_ERROR
7685 if (rc)
7686 return;
7687#endif
7688 }
7689
7690 /* Give HW time to discard old tx messages */
7691 usleep_range(1000, 1000);
7692
7693 /* Clean all ETH MACs */
7694 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7695 if (rc < 0)
7696 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7697
7698 /* Clean up UC list */
7699 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7700 true);
7701 if (rc < 0)
7702 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7703 "%d\n", rc);
7704
7705 /* Disable LLH */
7706 if (!CHIP_IS_E1(bp))
7707 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7708
7709 /* Set "drop all" (stop Rx).
7710 * We need to take a netif_addr_lock() here in order to prevent
7711 * a race between the completion code and this code.
7712 */
7713 netif_addr_lock_bh(bp->dev);
7714 /* Schedule the rx_mode command */
7715 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7716 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7717 else
7718 bnx2x_set_storm_rx_mode(bp);
7719
7720 /* Cleanup multicast configuration */
7721 rparam.mcast_obj = &bp->mcast_obj;
7722 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7723 if (rc < 0)
7724 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7725
7726 netif_addr_unlock_bh(bp->dev);
7727
7728
6debea87
DK		 7729
7730 /*
7731 * Send the UNLOAD_REQUEST to the MCP. This will return if
7732 * this function should perform FUNC, PORT or COMMON HW
7733 * reset.
7734 */
7735 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7736
7737 /*
7738 * (assumption: No Attention from MCP at this stage)
7739 * PMF probably in the middle of TXdisable/enable transaction
7740 */
7741 rc = bnx2x_func_wait_started(bp);
7742 if (rc) {
7743 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7744#ifdef BNX2X_STOP_ON_ERROR
7745 return;
7746#endif
7747 }
7748
34f80b04 7749 /* Close multi and leading connections
619c5cb6
VZ		 7750 * Completions for ramrods are collected in a synchronous way
7751 */
523224a3 7752 for_each_queue(bp, i)
619c5cb6 7753 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 7754#ifdef BNX2X_STOP_ON_ERROR
7755 return;
7756#else
228241eb 7757 goto unload_error;
523224a3 7758#endif
619c5cb6
VZ		 7759 /* If SP settings didn't get completed so far - something
7760 * very wrong has happen.
7761 */
7762 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7763 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 7764
619c5cb6
VZ		 7765#ifndef BNX2X_STOP_ON_ERROR
7766unload_error:
7767#endif
523224a3 7768 rc = bnx2x_func_stop(bp);
da5a662a 7769 if (rc) {
523224a3 7770 BNX2X_ERR("Function stop failed!\n");
da5a662a 7771#ifdef BNX2X_STOP_ON_ERROR
523224a3 7772 return;
523224a3 7773#endif
34f80b04 7774 }
a2fbb9ea 7775
523224a3
DK		 7776 /* Disable HW interrupts, NAPI */
7777 bnx2x_netif_stop(bp, 1);
7778
7779 /* Release IRQs */
d6214d7a 7780 bnx2x_free_irq(bp);
523224a3 7781
a2fbb9ea 7782 /* Reset the chip */
619c5cb6
VZ		 7783 rc = bnx2x_reset_hw(bp, reset_code);
7784 if (rc)
7785 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 7786
356e2385 7787
619c5cb6
VZ		 7788 /* Report UNLOAD_DONE to MCP */
7789 bnx2x_send_unload_done(bp);
72fd0718
VZ		 7790}
7791
9f6c9258 7792void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7793{
7794 u32 val;
7795
7796 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7797
7798 if (CHIP_IS_E1(bp)) {
7799 int port = BP_PORT(bp);
7800 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7801 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7802
7803 val = REG_RD(bp, addr);
7804 val &= ~(0x300);
7805 REG_WR(bp, addr, val);
619c5cb6 7806 } else {
72fd0718
VZ		 7807 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7808 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7809 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7810 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7811 }
7812}
7813
72fd0718
VZ		 7814/* Close gates #2, #3 and #4: */
7815static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7816{
c9ee9206 7817 u32 val;
72fd0718
VZ		 7818
7819 /* Gates #2 and #4a are closed/opened for "not E1" only */
7820 if (!CHIP_IS_E1(bp)) {
7821 /* #4 */
c9ee9206 7822 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 7823 /* #2 */
c9ee9206 7824 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 7825 }
7826
7827 /* #3 */
c9ee9206
VZ		 7828 if (CHIP_IS_E1x(bp)) {
7829 /* Prevent interrupts from HC on both ports */
7830 val = REG_RD(bp, HC_REG_CONFIG_1);
7831 REG_WR(bp, HC_REG_CONFIG_1,
7832 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7833 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7834
7835 val = REG_RD(bp, HC_REG_CONFIG_0);
7836 REG_WR(bp, HC_REG_CONFIG_0,
7837 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7838 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7839 } else {
7840 /* Prevent incomming interrupts in IGU */
7841 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7842
7843 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7844 (!close) ?
7845 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7846 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7847 }
72fd0718
VZ		 7848
7849 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7850 close ? "closing" : "opening");
7851 mmiowb();
7852}
7853
7854#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7855
7856static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7857{
7858 /* Do some magic... */
7859 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7860 *magic_val = val & SHARED_MF_CLP_MAGIC;
7861 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7862}
7863
e8920674
DK		 7864/**
7865 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7866 *
e8920674
DK		 7867 * @bp: driver handle
7868 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7869 */
7870static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7871{
7872 /* Restore the `magic' bit value... */
72fd0718
VZ		 7873 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7874 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7875 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7876}
7877
f85582f8 7878/**
e8920674 7879 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7880 *
e8920674
DK		 7881 * @bp: driver handle
7882 * @magic_val: old value of 'magic' bit.
7883 *
7884 * Takes care of CLP configurations.
72fd0718
VZ		 7885 */
7886static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7887{
7888 u32 shmem;
7889 u32 validity_offset;
7890
7891 DP(NETIF_MSG_HW, "Starting\n");
7892
7893 /* Set `magic' bit in order to save MF config */
7894 if (!CHIP_IS_E1(bp))
7895 bnx2x_clp_reset_prep(bp, magic_val);
7896
7897 /* Get shmem offset */
7898 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7899 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7900
7901 /* Clear validity map flags */
7902 if (shmem > 0)
7903 REG_WR(bp, shmem + validity_offset, 0);
7904}
7905
7906#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7907#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7908
e8920674
DK		 7909/**
7910 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7911 *
e8920674 7912 * @bp: driver handle
72fd0718
VZ		 7913 */
7914static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7915{
7916 /* special handling for emulation and FPGA,
7917 wait 10 times longer */
7918 if (CHIP_REV_IS_SLOW(bp))
7919 msleep(MCP_ONE_TIMEOUT*10);
7920 else
7921 msleep(MCP_ONE_TIMEOUT);
7922}
7923
1b6e2ceb
DK		 7924/*
7925 * initializes bp->common.shmem_base and waits for validity signature to appear
7926 */
7927static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 7928{
1b6e2ceb
DK		 7929 int cnt = 0;
7930 u32 val = 0;
72fd0718 7931
1b6e2ceb
DK		 7932 do {
7933 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7934 if (bp->common.shmem_base) {
7935 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7936 if (val & SHR_MEM_VALIDITY_MB)
7937 return 0;
7938 }
72fd0718 7939
1b6e2ceb 7940 bnx2x_mcp_wait_one(bp);
72fd0718 7941
1b6e2ceb 7942 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 7943
1b6e2ceb 7944 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 7945
1b6e2ceb
DK		 7946 return -ENODEV;
7947}
72fd0718 7948
1b6e2ceb
DK		 7949static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7950{
7951 int rc = bnx2x_init_shmem(bp);
72fd0718 7952
72fd0718
VZ		 7953 /* Restore the `magic' bit value */
7954 if (!CHIP_IS_E1(bp))
7955 bnx2x_clp_reset_done(bp, magic_val);
7956
7957 return rc;
7958}
7959
7960static void bnx2x_pxp_prep(struct bnx2x *bp)
7961{
7962 if (!CHIP_IS_E1(bp)) {
7963 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7964 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 7965 mmiowb();
7966 }
7967}
7968
7969/*
7970 * Reset the whole chip except for:
7971 * - PCIE core
7972 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7973 * one reset bit)
7974 * - IGU
7975 * - MISC (including AEU)
7976 * - GRC
7977 * - RBCN, RBCP
7978 */
c9ee9206 7979static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 7980{
7981 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 7982 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 7983
7984 /*
7985 * Bits that have to be set in reset_mask2 if we want to reset 'global'
7986 * (per chip) blocks.
7987 */
7988 global_bits2 =
7989 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
7990 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 7991
8736c826 7992 /* Don't reset the following blocks */
72fd0718
VZ		 7993 not_reset_mask1 =
7994 MISC_REGISTERS_RESET_REG_1_RST_HC |
7995 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7996 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7997
7998 not_reset_mask2 =
c9ee9206 7999 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8000 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8001 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8002 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8003 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8004 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8005 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8006 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8007 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8008 MISC_REGISTERS_RESET_REG_2_PGLC;
72fd0718 8009
8736c826
VZ		 8010 /*
8011 * Keep the following blocks in reset:
8012 * - all xxMACs are handled by the bnx2x_link code.
8013 */
8014 stay_reset2 =
8015 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8016 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8017 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8018 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8019 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8020 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8021 MISC_REGISTERS_RESET_REG_2_XMAC |
8022 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8023
8024 /* Full reset masks according to the chip */
72fd0718
VZ		 8025 reset_mask1 = 0xffffffff;
8026
8027 if (CHIP_IS_E1(bp))
8028 reset_mask2 = 0xffff;
8736c826 8029 else if (CHIP_IS_E1H(bp))
72fd0718 8030 reset_mask2 = 0x1ffff;
8736c826
VZ		 8031 else if (CHIP_IS_E2(bp))
8032 reset_mask2 = 0xfffff;
8033 else /* CHIP_IS_E3 */
8034 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 8035
8036 /* Don't reset global blocks unless we need to */
8037 if (!global)
8038 reset_mask2 &= ~global_bits2;
8039
8040 /*
8041 * In case of attention in the QM, we need to reset PXP
8042 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8043 * because otherwise QM reset would release 'close the gates' shortly
8044 * before resetting the PXP, then the PSWRQ would send a write
8045 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8046 * read the payload data from PSWWR, but PSWWR would not
8047 * respond. The write queue in PGLUE would stuck, dmae commands
8048 * would not return. Therefore it's important to reset the second
8049 * reset register (containing the
8050 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8051 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8052 * bit).
8053 */
72fd0718
VZ		 8054 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8055 reset_mask2 & (~not_reset_mask2));
8056
c9ee9206
VZ		 8057 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8058 reset_mask1 & (~not_reset_mask1));
8059
72fd0718
VZ		 8060 barrier();
8061 mmiowb();
8062
8736c826
VZ		 8063 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8064 reset_mask2 & (~stay_reset2));
8065
8066 barrier();
8067 mmiowb();
8068
c9ee9206 8069 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 8070 mmiowb();
8071}
8072
c9ee9206
VZ		 8073/**
8074 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8075 * It should get cleared in no more than 1s.
8076 *
8077 * @bp: driver handle
8078 *
8079 * It should get cleared in no more than 1s. Returns 0 if
8080 * pending writes bit gets cleared.
8081 */
8082static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8083{
8084 u32 cnt = 1000;
8085 u32 pend_bits = 0;
8086
8087 do {
8088 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8089
8090 if (pend_bits == 0)
8091 break;
8092
8093 usleep_range(1000, 1000);
8094 } while (cnt-- > 0);
8095
8096 if (cnt <= 0) {
8097 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8098 pend_bits);
8099 return -EBUSY;
8100 }
8101
8102 return 0;
8103}
8104
8105static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 8106{
8107 int cnt = 1000;
8108 u32 val = 0;
8109 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8110
8111
8112 /* Empty the Tetris buffer, wait for 1s */
8113 do {
8114 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8115 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8116 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8117 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8118 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8119 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8120 ((port_is_idle_0 & 0x1) == 0x1) &&
8121 ((port_is_idle_1 & 0x1) == 0x1) &&
8122 (pgl_exp_rom2 == 0xffffffff))
8123 break;
c9ee9206 8124 usleep_range(1000, 1000);
72fd0718
VZ		 8125 } while (cnt-- > 0);
8126
8127 if (cnt <= 0) {
8128 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8129 " are still"
8130 " outstanding read requests after 1s!\n");
8131 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8132 " port_is_idle_0=0x%08x,"
8133 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8134 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8135 pgl_exp_rom2);
8136 return -EAGAIN;
8137 }
8138
8139 barrier();
8140
8141 /* Close gates #2, #3 and #4 */
8142 bnx2x_set_234_gates(bp, true);
8143
c9ee9206
VZ		 8144 /* Poll for IGU VQs for 57712 and newer chips */
8145 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8146 return -EAGAIN;
8147
8148
72fd0718
VZ		 8149 /* TBD: Indicate that "process kill" is in progress to MCP */
8150
8151 /* Clear "unprepared" bit */
8152 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8153 barrier();
8154
8155 /* Make sure all is written to the chip before the reset */
8156 mmiowb();
8157
8158 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8159 * PSWHST, GRC and PSWRD Tetris buffer.
8160 */
c9ee9206 8161 usleep_range(1000, 1000);
72fd0718
VZ		 8162
8163 /* Prepare to chip reset: */
8164 /* MCP */
c9ee9206
VZ		 8165 if (global)
8166 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 8167
8168 /* PXP */
8169 bnx2x_pxp_prep(bp);
8170 barrier();
8171
8172 /* reset the chip */
c9ee9206 8173 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 8174 barrier();
8175
8176 /* Recover after reset: */
8177 /* MCP */
c9ee9206 8178 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 8179 return -EAGAIN;
8180
c9ee9206
VZ		 8181 /* TBD: Add resetting the NO_MCP mode DB here */
8182
72fd0718
VZ		 8183 /* PXP */
8184 bnx2x_pxp_prep(bp);
8185
8186 /* Open the gates #2, #3 and #4 */
8187 bnx2x_set_234_gates(bp, false);
8188
8189 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8190 * reset state, re-enable attentions. */
8191
a2fbb9ea
ET		 8192 return 0;
8193}
8194
c9ee9206 8195int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 8196{
8197 int rc = 0;
c9ee9206
VZ		 8198 bool global = bnx2x_reset_is_global(bp);
8199
72fd0718 8200 /* Try to recover after the failure */
c9ee9206
VZ		 8201 if (bnx2x_process_kill(bp, global)) {
8202 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8203 "Aii!\n", BP_PATH(bp));
72fd0718
VZ		 8204 rc = -EAGAIN;
8205 goto exit_leader_reset;
8206 }
8207
c9ee9206
VZ		 8208 /*
8209 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8210 * state.
8211 */
72fd0718 8212 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 8213 if (global)
8214 bnx2x_clear_reset_global(bp);
72fd0718
VZ		 8215
8216exit_leader_reset:
8217 bp->is_leader = 0;
c9ee9206
VZ		 8218 bnx2x_release_leader_lock(bp);
8219 smp_mb();
72fd0718
VZ		 8220 return rc;
8221}
8222
c9ee9206
VZ		 8223static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8224{
8225 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8226
8227 /* Disconnect this device */
8228 netif_device_detach(bp->dev);
8229
8230 /*
8231 * Block ifup for all function on this engine until "process kill"
8232 * or power cycle.
8233 */
8234 bnx2x_set_reset_in_progress(bp);
8235
8236 /* Shut down the power */
8237 bnx2x_set_power_state(bp, PCI_D3hot);
8238
8239 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8240
8241 smp_mb();
8242}
8243
8244/*
8245 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 8246 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 8247 * will never be called when netif_running(bp->dev) is false.
8248 */
8249static void bnx2x_parity_recover(struct bnx2x *bp)
8250{
c9ee9206
VZ		 8251 bool global = false;
8252
72fd0718
VZ		 8253 DP(NETIF_MSG_HW, "Handling parity\n");
8254 while (1) {
8255 switch (bp->recovery_state) {
8256 case BNX2X_RECOVERY_INIT:
8257 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
c9ee9206
VZ		 8258 bnx2x_chk_parity_attn(bp, &global, false);
8259
72fd0718 8260 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 8261 if (bnx2x_trylock_leader_lock(bp)) {
8262 bnx2x_set_reset_in_progress(bp);
8263 /*
8264 * Check if there is a global attention and if
8265 * there was a global attention, set the global
8266 * reset bit.
8267 */
8268
8269 if (global)
8270 bnx2x_set_reset_global(bp);
8271
72fd0718 8272 bp->is_leader = 1;
c9ee9206 8273 }
72fd0718
VZ		 8274
8275 /* Stop the driver */
8276 /* If interface has been removed - break */
8277 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8278 return;
8279
8280 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206
VZ		 8281
8282 /*
8283 * Reset MCP command sequence number and MCP mail box
8284 * sequence as we are going to reset the MCP.
8285 */
8286 if (global) {
8287 bp->fw_seq = 0;
8288 bp->fw_drv_pulse_wr_seq = 0;
8289 }
8290
8291 /* Ensure "is_leader", MCP command sequence and
8292 * "recovery_state" update values are seen on other
8293 * CPUs.
72fd0718 8294 */
c9ee9206 8295 smp_mb();
72fd0718
VZ		 8296 break;
8297
8298 case BNX2X_RECOVERY_WAIT:
8299 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8300 if (bp->is_leader) {
c9ee9206
VZ		 8301 int other_engine = BP_PATH(bp) ? 0 : 1;
8302 u32 other_load_counter =
8303 bnx2x_get_load_cnt(bp, other_engine);
8304 u32 load_counter =
8305 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8306 global = bnx2x_reset_is_global(bp);
8307
8308 /*
8309 * In case of a parity in a global block, let
8310 * the first leader that performs a
8311 * leader_reset() reset the global blocks in
8312 * order to clear global attentions. Otherwise
8313 * the the gates will remain closed for that
8314 * engine.
8315 */
8316 if (load_counter ||
8317 (global && other_load_counter)) {
72fd0718
VZ		 8318 /* Wait until all other functions get
8319 * down.
8320 */
7be08a72 8321 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8322 HZ/10);
8323 return;
8324 } else {
8325 /* If all other functions got down -
8326 * try to bring the chip back to
8327 * normal. In any case it's an exit
8328 * point for a leader.
8329 */
c9ee9206
VZ		 8330 if (bnx2x_leader_reset(bp)) {
8331 bnx2x_recovery_failed(bp);
72fd0718
VZ		 8332 return;
8333 }
8334
c9ee9206
VZ		 8335 /* If we are here, means that the
8336 * leader has succeeded and doesn't
8337 * want to be a leader any more. Try
8338 * to continue as a none-leader.
8339 */
8340 break;
72fd0718
VZ		 8341 }
8342 } else { /* non-leader */
c9ee9206 8343 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 8344 /* Try to get a LEADER_LOCK HW lock as
8345 * long as a former leader may have
8346 * been unloaded by the user or
8347 * released a leadership by another
8348 * reason.
8349 */
c9ee9206 8350 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 8351 /* I'm a leader now! Restart a
8352 * switch case.
8353 */
8354 bp->is_leader = 1;
8355 break;
8356 }
8357
7be08a72 8358 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8359 HZ/10);
8360 return;
8361
c9ee9206
VZ		 8362 } else {
8363 /*
8364 * If there was a global attention, wait
8365 * for it to be cleared.
8366 */
8367 if (bnx2x_reset_is_global(bp)) {
8368 schedule_delayed_work(
7be08a72
AE		 8369 &bp->sp_rtnl_task,
8370 HZ/10);
c9ee9206
VZ		 8371 return;
8372 }
8373
8374 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8375 bnx2x_recovery_failed(bp);
8376 else {
8377 bp->recovery_state =
8378 BNX2X_RECOVERY_DONE;
8379 smp_mb();
8380 }
8381
72fd0718
VZ		 8382 return;
8383 }
8384 }
8385 default:
8386 return;
8387 }
8388 }
8389}
8390
8391/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8392 * scheduled on a general queue in order to prevent a dead lock.
8393 */
7be08a72 8394static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 8395{
7be08a72 8396 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 8397
8398 rtnl_lock();
8399
8400 if (!netif_running(bp->dev))
7be08a72
AE		 8401 goto sp_rtnl_exit;
8402
6383c0b3
AE		 8403 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8404 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8405
7be08a72
AE		 8406 /* if stop on error is defined no recovery flows should be executed */
8407#ifdef BNX2X_STOP_ON_ERROR
8408 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8409 "so reset not done to allow debug dump,\n"
8410 "you will need to reboot when done\n");
8411 goto sp_rtnl_exit;
8412#endif
34f80b04 8413
7be08a72
AE		 8414 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8415 /*
8416 * Clear TX_TIMEOUT bit as we are going to reset the function
8417 * anyway.
8418 */
8419 smp_mb__before_clear_bit();
8420 clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state);
8421 smp_mb__after_clear_bit();
72fd0718 8422 bnx2x_parity_recover(bp);
7be08a72
AE		 8423 } else if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT,
8424 &bp->sp_rtnl_state)){
72fd0718
VZ		 8425 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8426 bnx2x_nic_load(bp, LOAD_NORMAL);
8427 }
34f80b04 8428
7be08a72 8429sp_rtnl_exit:
34f80b04
EG		 8430 rtnl_unlock();
8431}
8432
a2fbb9ea
ET		 8433/* end of nic load/unload */
8434
3deb8167
YR		 8435static void bnx2x_period_task(struct work_struct *work)
8436{
8437 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8438
8439 if (!netif_running(bp->dev))
8440 goto period_task_exit;
8441
8442 if (CHIP_REV_IS_SLOW(bp)) {
8443 BNX2X_ERR("period task called on emulation, ignoring\n");
8444 goto period_task_exit;
8445 }
8446
8447 bnx2x_acquire_phy_lock(bp);
8448 /*
8449 * The barrier is needed to ensure the ordering between the writing to
8450 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8451 * the reading here.
8452 */
8453 smp_mb();
8454 if (bp->port.pmf) {
8455 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8456
8457 /* Re-queue task in 1 sec */
8458 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8459 }
8460
8461 bnx2x_release_phy_lock(bp);
8462period_task_exit:
8463 return;
8464}
8465
a2fbb9ea
ET		 8466/*
8467 * Init service functions
8468 */
8469
8d96286a 8470static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 8471{
8472 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8473 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8474 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 8475}
8476
f2e0899f 8477static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 8478{
f2e0899f 8479 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 8480
8481 /* Flush all outstanding writes */
8482 mmiowb();
8483
8484 /* Pretend to be function 0 */
8485 REG_WR(bp, reg, 0);
f2e0899f 8486 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 8487
8488 /* From now we are in the "like-E1" mode */
8489 bnx2x_int_disable(bp);
8490
8491 /* Flush all outstanding writes */
8492 mmiowb();
8493
f2e0899f
DK		 8494 /* Restore the original function */
8495 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8496 REG_RD(bp, reg);
f1ef27ef
EG		 8497}
8498
f2e0899f 8499static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 8500{
f2e0899f 8501 if (CHIP_IS_E1(bp))
f1ef27ef 8502 bnx2x_int_disable(bp);
f2e0899f
DK		 8503 else
8504 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 8505}
8506
34f80b04
EG		 8507static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8508{
8509 u32 val;
8510
8511 /* Check if there is any driver already loaded */
8512 val = REG_RD(bp, MISC_REG_UNPREPARED);
8513 if (val == 0x1) {
8514 /* Check if it is the UNDI driver
8515 * UNDI driver initializes CID offset for normal bell to 0x7
8516 */
4a37fb66 8517 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 8518 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8519 if (val == 0x7) {
8520 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 8521 /* save our pf_num */
8522 int orig_pf_num = bp->pf_num;
619c5cb6
VZ		 8523 int port;
8524 u32 swap_en, swap_val, value;
34f80b04 8525
b4661739
EG		 8526 /* clear the UNDI indication */
8527 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8528
34f80b04
EG		 8529 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8530
8531 /* try unload UNDI on port 0 */
f2e0899f 8532 bp->pf_num = 0;
da5a662a 8533 bp->fw_seq =
f2e0899f 8534 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8535 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 8536 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8537
8538 /* if UNDI is loaded on the other port */
8539 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8540
da5a662a 8541 /* send "DONE" for previous unload */
a22f0788
YR		 8542 bnx2x_fw_command(bp,
8543 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8544
8545 /* unload UNDI on port 1 */
f2e0899f 8546 bp->pf_num = 1;
da5a662a 8547 bp->fw_seq =
f2e0899f 8548 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 8549 DRV_MSG_SEQ_NUMBER_MASK);
8550 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8551
a22f0788 8552 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8553 }
8554
b4661739
EG		 8555 /* now it's safe to release the lock */
8556 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8557
f2e0899f 8558 bnx2x_undi_int_disable(bp);
619c5cb6 8559 port = BP_PORT(bp);
da5a662a
VZ		 8560
8561 /* close input traffic and wait for it */
8562 /* Do not rcv packets to BRB */
619c5cb6
VZ		 8563 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8564 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
da5a662a
VZ		 8565 /* Do not direct rcv packets that are not for MCP to
8566 * the BRB */
619c5cb6
VZ		 8567 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8568 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
da5a662a 8569 /* clear AEU */
619c5cb6
VZ		 8570 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8571 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
da5a662a
VZ		 8572 msleep(10);
8573
8574 /* save NIG port swap info */
8575 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8576 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 8577 /* reset device */
8578 REG_WR(bp,
8579 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 8580 0xd3ffffff);
619c5cb6
VZ		 8581
8582 value = 0x1400;
8583 if (CHIP_IS_E3(bp)) {
8584 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8585 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8586 }
8587
34f80b04
EG		 8588 REG_WR(bp,
8589 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
619c5cb6
VZ		 8590 value);
8591
da5a662a
VZ		 8592 /* take the NIG out of reset and restore swap values */
8593 REG_WR(bp,
8594 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8595 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8596 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8597 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8598
8599 /* send unload done to the MCP */
a22f0788 8600 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8601
8602 /* restore our func and fw_seq */
f2e0899f 8603 bp->pf_num = orig_pf_num;
da5a662a 8604 bp->fw_seq =
f2e0899f 8605 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8606 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 8607 } else
8608 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 8609 }
8610}
8611
8612static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8613{
8614 u32 val, val2, val3, val4, id;
72ce58c3 8615 u16 pmc;
34f80b04
EG		 8616
8617 /* Get the chip revision id and number. */
8618 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8619 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8620 id = ((val & 0xffff) << 16);
8621 val = REG_RD(bp, MISC_REG_CHIP_REV);
8622 id |= ((val & 0xf) << 12);
8623 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8624 id |= ((val & 0xff) << 4);
5a40e08e 8625 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 8626 id |= (val & 0xf);
8627 bp->common.chip_id = id;
523224a3
DK		 8628
8629 /* Set doorbell size */
8630 bp->db_size = (1 << BNX2X_DB_SHIFT);
8631
619c5cb6 8632 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8633 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8634 if ((val & 1) == 0)
8635 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8636 else
8637 val = (val >> 1) & 1;
8638 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8639 "2_PORT_MODE");
8640 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8641 CHIP_2_PORT_MODE;
8642
8643 if (CHIP_MODE_IS_4_PORT(bp))
8644 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8645 else
8646 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8647 } else {
8648 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8649 bp->pfid = bp->pf_num; /* 0..7 */
8650 }
8651
f2e0899f
DK		 8652 bp->link_params.chip_id = bp->common.chip_id;
8653 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 8654
1c06328c
EG		 8655 val = (REG_RD(bp, 0x2874) & 0x55);
8656 if ((bp->common.chip_id & 0x1) ||
8657 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8658 bp->flags |= ONE_PORT_FLAG;
8659 BNX2X_DEV_INFO("single port device\n");
8660 }
8661
34f80b04 8662 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 8663 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 8664 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8665 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8666 bp->common.flash_size, bp->common.flash_size);
8667
1b6e2ceb
DK		 8668 bnx2x_init_shmem(bp);
8669
619c5cb6
VZ		 8670
8671
f2e0899f
DK		 8672 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8673 MISC_REG_GENERIC_CR_1 :
8674 MISC_REG_GENERIC_CR_0));
1b6e2ceb 8675
34f80b04 8676 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 8677 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 8678 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8679 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 8680
f2e0899f 8681 if (!bp->common.shmem_base) {
34f80b04
EG		 8682 BNX2X_DEV_INFO("MCP not active\n");
8683 bp->flags |= NO_MCP_FLAG;
8684 return;
8685 }
8686
34f80b04 8687 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 8688 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 8689
8690 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8691 SHARED_HW_CFG_LED_MODE_MASK) >>
8692 SHARED_HW_CFG_LED_MODE_SHIFT);
8693
c2c8b03e
EG		 8694 bp->link_params.feature_config_flags = 0;
8695 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8696 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8697 bp->link_params.feature_config_flags |=
8698 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8699 else
8700 bp->link_params.feature_config_flags &=
8701 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8702
34f80b04
EG		 8703 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8704 bp->common.bc_ver = val;
8705 BNX2X_DEV_INFO("bc_ver %X\n", val);
8706 if (val < BNX2X_BC_VER) {
8707 /* for now only warn
8708 * later we might need to enforce this */
f2e0899f
DK		 8709 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8710 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 8711 }
4d295db0 8712 bp->link_params.feature_config_flags |=
a22f0788 8713 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 8714 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8715
a22f0788
YR		 8716 bp->link_params.feature_config_flags |=
8717 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8718 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 8719
85242eea
YR		 8720 bp->link_params.feature_config_flags |=
8721 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8722 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8723
f9a3ebbe
DK		 8724 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8725 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8726
72ce58c3 8727 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 8728 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 8729
8730 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8731 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8732 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8733 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8734
cdaa7cb8
VZ		 8735 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8736 val, val2, val3, val4);
34f80b04
EG		 8737}
8738
f2e0899f
DK		 8739#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8740#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8741
8742static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8743{
8744 int pfid = BP_FUNC(bp);
8745 int vn = BP_E1HVN(bp);
8746 int igu_sb_id;
8747 u32 val;
6383c0b3 8748 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 8749
8750 bp->igu_base_sb = 0xff;
f2e0899f 8751 if (CHIP_INT_MODE_IS_BC(bp)) {
6383c0b3 8752 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 8753 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8754 FP_SB_MAX_E1x;
8755
8756 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8757 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8758
8759 return;
8760 }
8761
8762 /* IGU in normal mode - read CAM */
8763 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8764 igu_sb_id++) {
8765 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8766 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8767 continue;
8768 fid = IGU_FID(val);
8769 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8770 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8771 continue;
8772 if (IGU_VEC(val) == 0)
8773 /* default status block */
8774 bp->igu_dsb_id = igu_sb_id;
8775 else {
8776 if (bp->igu_base_sb == 0xff)
8777 bp->igu_base_sb = igu_sb_id;
6383c0b3 8778 igu_sb_cnt++;
f2e0899f
DK		 8779 }
8780 }
8781 }
619c5cb6 8782
6383c0b3
AE		 8783#ifdef CONFIG_PCI_MSI
8784 /*
8785 * It's expected that number of CAM entries for this functions is equal
8786 * to the number evaluated based on the MSI-X table size. We want a
8787 * harsh warning if these values are different!
619c5cb6 8788 */
6383c0b3
AE		 8789 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8790#endif
619c5cb6 8791
6383c0b3 8792 if (igu_sb_cnt == 0)
f2e0899f
DK		 8793 BNX2X_ERR("CAM configuration error\n");
8794}
8795
34f80b04
EG		 8796static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8797 u32 switch_cfg)
a2fbb9ea 8798{
a22f0788
YR		 8799 int cfg_size = 0, idx, port = BP_PORT(bp);
8800
8801 /* Aggregation of supported attributes of all external phys */
8802 bp->port.supported[0] = 0;
8803 bp->port.supported[1] = 0;
b7737c9b
YR		 8804 switch (bp->link_params.num_phys) {
8805 case 1:
a22f0788
YR		 8806 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8807 cfg_size = 1;
8808 break;
b7737c9b 8809 case 2:
a22f0788
YR		 8810 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8811 cfg_size = 1;
8812 break;
8813 case 3:
8814 if (bp->link_params.multi_phy_config &
8815 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8816 bp->port.supported[1] =
8817 bp->link_params.phy[EXT_PHY1].supported;
8818 bp->port.supported[0] =
8819 bp->link_params.phy[EXT_PHY2].supported;
8820 } else {
8821 bp->port.supported[0] =
8822 bp->link_params.phy[EXT_PHY1].supported;
8823 bp->port.supported[1] =
8824 bp->link_params.phy[EXT_PHY2].supported;
8825 }
8826 cfg_size = 2;
8827 break;
b7737c9b 8828 }
a2fbb9ea 8829
a22f0788 8830 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8831 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8832 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8833 SHMEM_RD(bp,
a22f0788
YR		 8834 dev_info.port_hw_config[port].external_phy_config),
8835 SHMEM_RD(bp,
8836 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8837 return;
f85582f8 8838 }
a2fbb9ea 8839
619c5cb6
VZ		 8840 if (CHIP_IS_E3(bp))
8841 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8842 else {
8843 switch (switch_cfg) {
8844 case SWITCH_CFG_1G:
8845 bp->port.phy_addr = REG_RD(
8846 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8847 break;
8848 case SWITCH_CFG_10G:
8849 bp->port.phy_addr = REG_RD(
8850 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8851 break;
8852 default:
8853 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8854 bp->port.link_config[0]);
8855 return;
8856 }
a2fbb9ea 8857 }
619c5cb6 8858 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 8859 /* mask what we support according to speed_cap_mask per configuration */
8860 for (idx = 0; idx < cfg_size; idx++) {
8861 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8862 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8863 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8864
a22f0788 8865 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8866 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8867 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8868
a22f0788 8869 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8870 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8871 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8872
a22f0788 8873 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8874 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8875 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8876
a22f0788 8877 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8878 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8879 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8880 SUPPORTED_1000baseT_Full);
a2fbb9ea 8881
a22f0788 8882 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8883 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8884 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8885
a22f0788 8886 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8887 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8888 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8889
8890 }
a2fbb9ea 8891
a22f0788
YR		 8892 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8893 bp->port.supported[1]);
a2fbb9ea
ET		 8894}
8895
34f80b04 8896static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8897{
a22f0788
YR		 8898 u32 link_config, idx, cfg_size = 0;
8899 bp->port.advertising[0] = 0;
8900 bp->port.advertising[1] = 0;
8901 switch (bp->link_params.num_phys) {
8902 case 1:
8903 case 2:
8904 cfg_size = 1;
8905 break;
8906 case 3:
8907 cfg_size = 2;
8908 break;
8909 }
8910 for (idx = 0; idx < cfg_size; idx++) {
8911 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8912 link_config = bp->port.link_config[idx];
8913 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8914 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8915 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8916 bp->link_params.req_line_speed[idx] =
8917 SPEED_AUTO_NEG;
8918 bp->port.advertising[idx] |=
8919 bp->port.supported[idx];
f85582f8
DK		 8920 } else {
8921 /* force 10G, no AN */
a22f0788
YR		 8922 bp->link_params.req_line_speed[idx] =
8923 SPEED_10000;
8924 bp->port.advertising[idx] |=
8925 (ADVERTISED_10000baseT_Full |
f85582f8 8926 ADVERTISED_FIBRE);
a22f0788 8927 continue;
f85582f8
DK		 8928 }
8929 break;
a2fbb9ea 8930
f85582f8 8931 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8932 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8933 bp->link_params.req_line_speed[idx] =
8934 SPEED_10;
8935 bp->port.advertising[idx] |=
8936 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8937 ADVERTISED_TP);
8938 } else {
754a2f52 8939 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 8940 "Invalid link_config 0x%x"
8941 " speed_cap_mask 0x%x\n",
8942 link_config,
a22f0788 8943 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8944 return;
8945 }
8946 break;
a2fbb9ea 8947
f85582f8 8948 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8949 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8950 bp->link_params.req_line_speed[idx] =
8951 SPEED_10;
8952 bp->link_params.req_duplex[idx] =
8953 DUPLEX_HALF;
8954 bp->port.advertising[idx] |=
8955 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8956 ADVERTISED_TP);
8957 } else {
754a2f52 8958 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 8959 "Invalid link_config 0x%x"
8960 " speed_cap_mask 0x%x\n",
8961 link_config,
8962 bp->link_params.speed_cap_mask[idx]);
8963 return;
8964 }
8965 break;
a2fbb9ea 8966
f85582f8
DK		 8967 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8968 if (bp->port.supported[idx] &
8969 SUPPORTED_100baseT_Full) {
a22f0788
YR		 8970 bp->link_params.req_line_speed[idx] =
8971 SPEED_100;
8972 bp->port.advertising[idx] |=
8973 (ADVERTISED_100baseT_Full |
f85582f8
DK		 8974 ADVERTISED_TP);
8975 } else {
754a2f52 8976 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 8977 "Invalid link_config 0x%x"
8978 " speed_cap_mask 0x%x\n",
8979 link_config,
8980 bp->link_params.speed_cap_mask[idx]);
8981 return;
8982 }
8983 break;
a2fbb9ea 8984
f85582f8
DK		 8985 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8986 if (bp->port.supported[idx] &
8987 SUPPORTED_100baseT_Half) {
8988 bp->link_params.req_line_speed[idx] =
8989 SPEED_100;
8990 bp->link_params.req_duplex[idx] =
8991 DUPLEX_HALF;
a22f0788
YR		 8992 bp->port.advertising[idx] |=
8993 (ADVERTISED_100baseT_Half |
f85582f8
DK		 8994 ADVERTISED_TP);
8995 } else {
754a2f52 8996 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 8997 "Invalid link_config 0x%x"
8998 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8999 link_config,
9000 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9001 return;
9002 }
9003 break;
a2fbb9ea 9004
f85582f8 9005 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 9006 if (bp->port.supported[idx] &
9007 SUPPORTED_1000baseT_Full) {
9008 bp->link_params.req_line_speed[idx] =
9009 SPEED_1000;
9010 bp->port.advertising[idx] |=
9011 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 9012 ADVERTISED_TP);
9013 } else {
754a2f52 9014 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9015 "Invalid link_config 0x%x"
9016 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9017 link_config,
9018 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9019 return;
9020 }
9021 break;
a2fbb9ea 9022
f85582f8 9023 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 9024 if (bp->port.supported[idx] &
9025 SUPPORTED_2500baseX_Full) {
9026 bp->link_params.req_line_speed[idx] =
9027 SPEED_2500;
9028 bp->port.advertising[idx] |=
9029 (ADVERTISED_2500baseX_Full |
34f80b04 9030 ADVERTISED_TP);
f85582f8 9031 } else {
754a2f52 9032 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9033 "Invalid link_config 0x%x"
9034 " speed_cap_mask 0x%x\n",
a22f0788 9035 link_config,
f85582f8
DK		 9036 bp->link_params.speed_cap_mask[idx]);
9037 return;
9038 }
9039 break;
a2fbb9ea 9040
f85582f8 9041 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 9042 if (bp->port.supported[idx] &
9043 SUPPORTED_10000baseT_Full) {
9044 bp->link_params.req_line_speed[idx] =
9045 SPEED_10000;
9046 bp->port.advertising[idx] |=
9047 (ADVERTISED_10000baseT_Full |
34f80b04 9048 ADVERTISED_FIBRE);
f85582f8 9049 } else {
754a2f52 9050 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9051 "Invalid link_config 0x%x"
9052 " speed_cap_mask 0x%x\n",
a22f0788 9053 link_config,
f85582f8
DK		 9054 bp->link_params.speed_cap_mask[idx]);
9055 return;
9056 }
9057 break;
3c9ada22
YR		 9058 case PORT_FEATURE_LINK_SPEED_20G:
9059 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 9060
3c9ada22 9061 break;
f85582f8 9062 default:
754a2f52
DK		 9063 BNX2X_ERR("NVRAM config error. "
9064 "BAD link speed link_config 0x%x\n",
9065 link_config);
f85582f8
DK		 9066 bp->link_params.req_line_speed[idx] =
9067 SPEED_AUTO_NEG;
9068 bp->port.advertising[idx] =
9069 bp->port.supported[idx];
9070 break;
9071 }
a2fbb9ea 9072
a22f0788 9073 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 9074 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 9075 if ((bp->link_params.req_flow_ctrl[idx] ==
9076 BNX2X_FLOW_CTRL_AUTO) &&
9077 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9078 bp->link_params.req_flow_ctrl[idx] =
9079 BNX2X_FLOW_CTRL_NONE;
9080 }
a2fbb9ea 9081
a22f0788
YR		 9082 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9083 " 0x%x advertising 0x%x\n",
9084 bp->link_params.req_line_speed[idx],
9085 bp->link_params.req_duplex[idx],
9086 bp->link_params.req_flow_ctrl[idx],
9087 bp->port.advertising[idx]);
9088 }
a2fbb9ea
ET		 9089}
9090
e665bfda
MC		 9091static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9092{
9093 mac_hi = cpu_to_be16(mac_hi);
9094 mac_lo = cpu_to_be32(mac_lo);
9095 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9096 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9097}
9098
34f80b04 9099static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 9100{
34f80b04 9101 int port = BP_PORT(bp);
589abe3a 9102 u32 config;
6f38ad93 9103 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 9104
c18487ee 9105 bp->link_params.bp = bp;
34f80b04 9106 bp->link_params.port = port;
c18487ee 9107
c18487ee 9108 bp->link_params.lane_config =
a2fbb9ea 9109 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 9110
a22f0788 9111 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 9112 SHMEM_RD(bp,
9113 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 9114 bp->link_params.speed_cap_mask[1] =
9115 SHMEM_RD(bp,
9116 dev_info.port_hw_config[port].speed_capability_mask2);
9117 bp->port.link_config[0] =
a2fbb9ea
ET		 9118 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9119
a22f0788
YR		 9120 bp->port.link_config[1] =
9121 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 9122
a22f0788
YR		 9123 bp->link_params.multi_phy_config =
9124 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 9125 /* If the device is capable of WoL, set the default state according
9126 * to the HW
9127 */
4d295db0 9128 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 9129 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9130 (config & PORT_FEATURE_WOL_ENABLED));
9131
f85582f8 9132 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 9133 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 9134 bp->link_params.lane_config,
a22f0788
YR		 9135 bp->link_params.speed_cap_mask[0],
9136 bp->port.link_config[0]);
a2fbb9ea 9137
a22f0788 9138 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 9139 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 9140 bnx2x_phy_probe(&bp->link_params);
c18487ee 9141 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 9142
9143 bnx2x_link_settings_requested(bp);
9144
01cd4528
EG		 9145 /*
9146 * If connected directly, work with the internal PHY, otherwise, work
9147 * with the external PHY
9148 */
b7737c9b
YR		 9149 ext_phy_config =
9150 SHMEM_RD(bp,
9151 dev_info.port_hw_config[port].external_phy_config);
9152 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 9153 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 9154 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 9155
9156 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9157 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9158 bp->mdio.prtad =
b7737c9b 9159 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 9160
9161 /*
9162 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9163 * In MF mode, it is set to cover self test cases
9164 */
9165 if (IS_MF(bp))
9166 bp->port.need_hw_lock = 1;
9167 else
9168 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9169 bp->common.shmem_base,
9170 bp->common.shmem2_base);
0793f83f 9171}
01cd4528 9172
2ba45142
VZ		 9173#ifdef BCM_CNIC
9174static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9175{
bf61ee14
VZ		 9176 int port = BP_PORT(bp);
9177 int func = BP_ABS_FUNC(bp);
9178
2ba45142 9179 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9180 drv_lic_key[port].max_iscsi_conn);
2ba45142 9181 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9182 drv_lic_key[port].max_fcoe_conn);
2ba45142
VZ		 9183
9184 /* Get the number of maximum allowed iSCSI and FCoE connections */
9185 bp->cnic_eth_dev.max_iscsi_conn =
9186 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9187 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9188
9189 bp->cnic_eth_dev.max_fcoe_conn =
9190 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9191 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9192
bf61ee14
VZ		 9193 /* Read the WWN: */
9194 if (!IS_MF(bp)) {
9195 /* Port info */
9196 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9197 SHMEM_RD(bp,
9198 dev_info.port_hw_config[port].
9199 fcoe_wwn_port_name_upper);
9200 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9201 SHMEM_RD(bp,
9202 dev_info.port_hw_config[port].
9203 fcoe_wwn_port_name_lower);
9204
9205 /* Node info */
9206 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9207 SHMEM_RD(bp,
9208 dev_info.port_hw_config[port].
9209 fcoe_wwn_node_name_upper);
9210 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9211 SHMEM_RD(bp,
9212 dev_info.port_hw_config[port].
9213 fcoe_wwn_node_name_lower);
9214 } else if (!IS_MF_SD(bp)) {
9215 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9216
9217 /*
9218 * Read the WWN info only if the FCoE feature is enabled for
9219 * this function.
9220 */
9221 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9222 /* Port info */
9223 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9224 MF_CFG_RD(bp, func_ext_config[func].
9225 fcoe_wwn_port_name_upper);
9226 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9227 MF_CFG_RD(bp, func_ext_config[func].
9228 fcoe_wwn_port_name_lower);
9229
9230 /* Node info */
9231 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9232 MF_CFG_RD(bp, func_ext_config[func].
9233 fcoe_wwn_node_name_upper);
9234 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9235 MF_CFG_RD(bp, func_ext_config[func].
9236 fcoe_wwn_node_name_lower);
9237 }
9238 }
9239
2ba45142
VZ		 9240 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9241 bp->cnic_eth_dev.max_iscsi_conn,
9242 bp->cnic_eth_dev.max_fcoe_conn);
9243
bf61ee14
VZ		 9244 /*
9245 * If maximum allowed number of connections is zero -
2ba45142
VZ		 9246 * disable the feature.
9247 */
9248 if (!bp->cnic_eth_dev.max_iscsi_conn)
9249 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9250
9251 if (!bp->cnic_eth_dev.max_fcoe_conn)
9252 bp->flags |= NO_FCOE_FLAG;
9253}
9254#endif
9255
0793f83f
DK		 9256static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9257{
9258 u32 val, val2;
9259 int func = BP_ABS_FUNC(bp);
9260 int port = BP_PORT(bp);
2ba45142
VZ		 9261#ifdef BCM_CNIC
9262 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9263 u8 *fip_mac = bp->fip_mac;
9264#endif
0793f83f 9265
619c5cb6
VZ		 9266 /* Zero primary MAC configuration */
9267 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9268
0793f83f
DK		 9269 if (BP_NOMCP(bp)) {
9270 BNX2X_ERROR("warning: random MAC workaround active\n");
9271 random_ether_addr(bp->dev->dev_addr);
9272 } else if (IS_MF(bp)) {
9273 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9274 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9275 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9276 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9277 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 9278
9279#ifdef BCM_CNIC
2ba45142
VZ		 9280 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9281 * FCoE MAC then the appropriate feature should be disabled.
9282 */
0793f83f
DK		 9283 if (IS_MF_SI(bp)) {
9284 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9285 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9286 val2 = MF_CFG_RD(bp, func_ext_config[func].
9287 iscsi_mac_addr_upper);
9288 val = MF_CFG_RD(bp, func_ext_config[func].
9289 iscsi_mac_addr_lower);
2ba45142 9290 bnx2x_set_mac_buf(iscsi_mac, val, val2);
619c5cb6
VZ		 9291 BNX2X_DEV_INFO("Read iSCSI MAC: "
9292 BNX2X_MAC_FMT"\n",
9293 BNX2X_MAC_PRN_LIST(iscsi_mac));
2ba45142
VZ		 9294 } else
9295 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9296
9297 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9298 val2 = MF_CFG_RD(bp, func_ext_config[func].
9299 fcoe_mac_addr_upper);
9300 val = MF_CFG_RD(bp, func_ext_config[func].
9301 fcoe_mac_addr_lower);
2ba45142 9302 bnx2x_set_mac_buf(fip_mac, val, val2);
619c5cb6
VZ		 9303 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9304 BNX2X_MAC_FMT"\n",
9305 BNX2X_MAC_PRN_LIST(fip_mac));
2ba45142 9306
2ba45142
VZ		 9307 } else
9308 bp->flags |= NO_FCOE_FLAG;
0793f83f 9309 }
37b091ba 9310#endif
0793f83f
DK		 9311 } else {
9312 /* in SF read MACs from port configuration */
9313 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9314 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9315 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9316
9317#ifdef BCM_CNIC
9318 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9319 iscsi_mac_upper);
9320 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9321 iscsi_mac_lower);
2ba45142 9322 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 9323
9324 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9325 fcoe_fip_mac_upper);
9326 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9327 fcoe_fip_mac_lower);
9328 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 9329#endif
9330 }
9331
9332 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9333 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9334
ec6ba945 9335#ifdef BCM_CNIC
c03bd39c
VZ		 9336 /* Set the FCoE MAC in MF_SD mode */
9337 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9338 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
426b9241
DK		 9339
9340 /* Disable iSCSI if MAC configuration is
9341 * invalid.
9342 */
9343 if (!is_valid_ether_addr(iscsi_mac)) {
9344 bp->flags |= NO_ISCSI_FLAG;
9345 memset(iscsi_mac, 0, ETH_ALEN);
9346 }
9347
9348 /* Disable FCoE if MAC configuration is
9349 * invalid.
9350 */
9351 if (!is_valid_ether_addr(fip_mac)) {
9352 bp->flags |= NO_FCOE_FLAG;
9353 memset(bp->fip_mac, 0, ETH_ALEN);
9354 }
ec6ba945 9355#endif
619c5cb6
VZ		 9356
9357 if (!is_valid_ether_addr(bp->dev->dev_addr))
9358 dev_err(&bp->pdev->dev,
9359 "bad Ethernet MAC address configuration: "
9360 BNX2X_MAC_FMT", change it manually before bringing up "
9361 "the appropriate network interface\n",
9362 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
34f80b04
EG		 9363}
9364
9365static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9366{
0793f83f 9367 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 9368 int vn;
0793f83f 9369 u32 val = 0;
34f80b04 9370 int rc = 0;
a2fbb9ea 9371
34f80b04 9372 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 9373
6383c0b3
AE		 9374 /*
9375 * initialize IGU parameters
9376 */
f2e0899f
DK		 9377 if (CHIP_IS_E1x(bp)) {
9378 bp->common.int_block = INT_BLOCK_HC;
9379
9380 bp->igu_dsb_id = DEF_SB_IGU_ID;
9381 bp->igu_base_sb = 0;
f2e0899f
DK		 9382 } else {
9383 bp->common.int_block = INT_BLOCK_IGU;
9384 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 9385
9386 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9387 int tout = 5000;
9388
9389 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9390
9391 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9392 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9393 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9394
9395 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9396 tout--;
9397 usleep_range(1000, 1000);
9398 }
9399
9400 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9401 dev_err(&bp->pdev->dev,
9402 "FORCING Normal Mode failed!!!\n");
9403 return -EPERM;
9404 }
9405 }
9406
f2e0899f 9407 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 9408 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 9409 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9410 } else
619c5cb6 9411 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 9412
f2e0899f
DK		 9413 bnx2x_get_igu_cam_info(bp);
9414
9415 }
619c5cb6
VZ		 9416
9417 /*
9418 * set base FW non-default (fast path) status block id, this value is
9419 * used to initialize the fw_sb_id saved on the fp/queue structure to
9420 * determine the id used by the FW.
9421 */
9422 if (CHIP_IS_E1x(bp))
9423 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9424 else /*
9425 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9426 * the same queue are indicated on the same IGU SB). So we prefer
9427 * FW and IGU SBs to be the same value.
9428 */
9429 bp->base_fw_ndsb = bp->igu_base_sb;
9430
9431 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9432 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9433 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 9434
9435 /*
9436 * Initialize MF configuration
9437 */
523224a3 9438
fb3bff17
DK		 9439 bp->mf_ov = 0;
9440 bp->mf_mode = 0;
f2e0899f 9441 vn = BP_E1HVN(bp);
0793f83f 9442
f2e0899f 9443 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 9444 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9445 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9446 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9447
f2e0899f
DK		 9448 if (SHMEM2_HAS(bp, mf_cfg_addr))
9449 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9450 else
9451 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 9452 offsetof(struct shmem_region, func_mb) +
9453 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 9454 /*
9455 * get mf configuration:
25985edc 9456 * 1. existence of MF configuration
0793f83f
DK		 9457 * 2. MAC address must be legal (check only upper bytes)
9458 * for Switch-Independent mode;
9459 * OVLAN must be legal for Switch-Dependent mode
9460 * 3. SF_MODE configures specific MF mode
9461 */
9462 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9463 /* get mf configuration */
9464 val = SHMEM_RD(bp,
9465 dev_info.shared_feature_config.config);
9466 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9467
9468 switch (val) {
9469 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9470 val = MF_CFG_RD(bp, func_mf_config[func].
9471 mac_upper);
9472 /* check for legal mac (upper bytes)*/
9473 if (val != 0xffff) {
9474 bp->mf_mode = MULTI_FUNCTION_SI;
9475 bp->mf_config[vn] = MF_CFG_RD(bp,
9476 func_mf_config[func].config);
9477 } else
619c5cb6
VZ		 9478 BNX2X_DEV_INFO("illegal MAC address "
9479 "for SI\n");
0793f83f
DK		 9480 break;
9481 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9482 /* get OV configuration */
9483 val = MF_CFG_RD(bp,
9484 func_mf_config[FUNC_0].e1hov_tag);
9485 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9486
9487 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9488 bp->mf_mode = MULTI_FUNCTION_SD;
9489 bp->mf_config[vn] = MF_CFG_RD(bp,
9490 func_mf_config[func].config);
9491 } else
754a2f52 9492 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 9493 break;
9494 default:
9495 /* Unknown configuration: reset mf_config */
9496 bp->mf_config[vn] = 0;
754a2f52 9497 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
0793f83f
DK		 9498 }
9499 }
a2fbb9ea 9500
2691d51d 9501 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 9502 IS_MF(bp) ? "multi" : "single");
2691d51d 9503
0793f83f
DK		 9504 switch (bp->mf_mode) {
9505 case MULTI_FUNCTION_SD:
9506 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9507 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 9508 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 9509 bp->mf_ov = val;
619c5cb6
VZ		 9510 bp->path_has_ovlan = true;
9511
9512 BNX2X_DEV_INFO("MF OV for func %d is %d "
9513 "(0x%04x)\n", func, bp->mf_ov,
9514 bp->mf_ov);
2691d51d 9515 } else {
619c5cb6
VZ		 9516 dev_err(&bp->pdev->dev,
9517 "No valid MF OV for func %d, "
9518 "aborting\n", func);
9519 return -EPERM;
34f80b04 9520 }
0793f83f
DK		 9521 break;
9522 case MULTI_FUNCTION_SI:
9523 BNX2X_DEV_INFO("func %d is in MF "
9524 "switch-independent mode\n", func);
9525 break;
9526 default:
9527 if (vn) {
619c5cb6
VZ		 9528 dev_err(&bp->pdev->dev,
9529 "VN %d is in a single function mode, "
9530 "aborting\n", vn);
9531 return -EPERM;
2691d51d 9532 }
0793f83f 9533 break;
34f80b04 9534 }
0793f83f 9535
619c5cb6
VZ		 9536 /* check if other port on the path needs ovlan:
9537 * Since MF configuration is shared between ports
9538 * Possible mixed modes are only
9539 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9540 */
9541 if (CHIP_MODE_IS_4_PORT(bp) &&
9542 !bp->path_has_ovlan &&
9543 !IS_MF(bp) &&
9544 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9545 u8 other_port = !BP_PORT(bp);
9546 u8 other_func = BP_PATH(bp) + 2*other_port;
9547 val = MF_CFG_RD(bp,
9548 func_mf_config[other_func].e1hov_tag);
9549 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9550 bp->path_has_ovlan = true;
9551 }
34f80b04 9552 }
a2fbb9ea 9553
f2e0899f
DK		 9554 /* adjust igu_sb_cnt to MF for E1x */
9555 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 9556 bp->igu_sb_cnt /= E1HVN_MAX;
9557
619c5cb6
VZ		 9558 /* port info */
9559 bnx2x_get_port_hwinfo(bp);
f2e0899f 9560
34f80b04 9561 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9562 bp->fw_seq =
9563 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9564 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 9565 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9566 }
9567
0793f83f
DK		 9568 /* Get MAC addresses */
9569 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 9570
2ba45142
VZ		 9571#ifdef BCM_CNIC
9572 bnx2x_get_cnic_info(bp);
9573#endif
9574
619c5cb6
VZ		 9575 /* Get current FW pulse sequence */
9576 if (!BP_NOMCP(bp)) {
9577 int mb_idx = BP_FW_MB_IDX(bp);
9578
9579 bp->fw_drv_pulse_wr_seq =
9580 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9581 DRV_PULSE_SEQ_MASK);
9582 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9583 }
9584
34f80b04
EG		 9585 return rc;
9586}
9587
34f24c7f
VZ		 9588static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9589{
9590 int cnt, i, block_end, rodi;
9591 char vpd_data[BNX2X_VPD_LEN+1];
9592 char str_id_reg[VENDOR_ID_LEN+1];
9593 char str_id_cap[VENDOR_ID_LEN+1];
9594 u8 len;
9595
9596 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9597 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9598
9599 if (cnt < BNX2X_VPD_LEN)
9600 goto out_not_found;
9601
9602 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9603 PCI_VPD_LRDT_RO_DATA);
9604 if (i < 0)
9605 goto out_not_found;
9606
9607
9608 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9609 pci_vpd_lrdt_size(&vpd_data[i]);
9610
9611 i += PCI_VPD_LRDT_TAG_SIZE;
9612
9613 if (block_end > BNX2X_VPD_LEN)
9614 goto out_not_found;
9615
9616 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9617 PCI_VPD_RO_KEYWORD_MFR_ID);
9618 if (rodi < 0)
9619 goto out_not_found;
9620
9621 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9622
9623 if (len != VENDOR_ID_LEN)
9624 goto out_not_found;
9625
9626 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9627
9628 /* vendor specific info */
9629 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9630 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9631 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9632 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9633
9634 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9635 PCI_VPD_RO_KEYWORD_VENDOR0);
9636 if (rodi >= 0) {
9637 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9638
9639 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9640
9641 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9642 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9643 bp->fw_ver[len] = ' ';
9644 }
9645 }
9646 return;
9647 }
9648out_not_found:
9649 return;
9650}
9651
619c5cb6
VZ		 9652static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9653{
9654 u32 flags = 0;
9655
9656 if (CHIP_REV_IS_FPGA(bp))
9657 SET_FLAGS(flags, MODE_FPGA);
9658 else if (CHIP_REV_IS_EMUL(bp))
9659 SET_FLAGS(flags, MODE_EMUL);
9660 else
9661 SET_FLAGS(flags, MODE_ASIC);
9662
9663 if (CHIP_MODE_IS_4_PORT(bp))
9664 SET_FLAGS(flags, MODE_PORT4);
9665 else
9666 SET_FLAGS(flags, MODE_PORT2);
9667
9668 if (CHIP_IS_E2(bp))
9669 SET_FLAGS(flags, MODE_E2);
9670 else if (CHIP_IS_E3(bp)) {
9671 SET_FLAGS(flags, MODE_E3);
9672 if (CHIP_REV(bp) == CHIP_REV_Ax)
9673 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 9674 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9675 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 9676 }
9677
9678 if (IS_MF(bp)) {
9679 SET_FLAGS(flags, MODE_MF);
9680 switch (bp->mf_mode) {
9681 case MULTI_FUNCTION_SD:
9682 SET_FLAGS(flags, MODE_MF_SD);
9683 break;
9684 case MULTI_FUNCTION_SI:
9685 SET_FLAGS(flags, MODE_MF_SI);
9686 break;
9687 }
9688 } else
9689 SET_FLAGS(flags, MODE_SF);
9690
9691#if defined(__LITTLE_ENDIAN)
9692 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9693#else /*(__BIG_ENDIAN)*/
9694 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9695#endif
9696 INIT_MODE_FLAGS(bp) = flags;
9697}
9698
34f80b04
EG		 9699static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9700{
f2e0899f 9701 int func;
87942b46 9702 int timer_interval;
34f80b04
EG		 9703 int rc;
9704
34f80b04 9705 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 9706 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 9707 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 9708#ifdef BCM_CNIC
9709 mutex_init(&bp->cnic_mutex);
9710#endif
a2fbb9ea 9711
1cf167f2 9712 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 9713 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 9714 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
34f80b04 9715 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 9716 if (rc)
9717 return rc;
34f80b04 9718
619c5cb6
VZ		 9719 bnx2x_set_modes_bitmap(bp);
9720
9721 rc = bnx2x_alloc_mem_bp(bp);
9722 if (rc)
9723 return rc;
523224a3 9724
34f24c7f 9725 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 9726
9727 func = BP_FUNC(bp);
9728
34f80b04
EG		 9729 /* need to reset chip if undi was active */
9730 if (!BP_NOMCP(bp))
9731 bnx2x_undi_unload(bp);
9732
9733 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 9734 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 9735
9736 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 9737 dev_err(&bp->pdev->dev, "MCP disabled, "
9738 "must load devices in order!\n");
34f80b04 9739
555f6c78 9740 bp->multi_mode = multi_mode;
555f6c78 9741
7a9b2557
VZ		 9742 /* Set TPA flags */
9743 if (disable_tpa) {
9744 bp->flags &= ~TPA_ENABLE_FLAG;
9745 bp->dev->features &= ~NETIF_F_LRO;
9746 } else {
9747 bp->flags |= TPA_ENABLE_FLAG;
9748 bp->dev->features |= NETIF_F_LRO;
9749 }
5d7cd496 9750 bp->disable_tpa = disable_tpa;
7a9b2557 9751
a18f5128
EG		 9752 if (CHIP_IS_E1(bp))
9753 bp->dropless_fc = 0;
9754 else
9755 bp->dropless_fc = dropless_fc;
9756
8d5726c4 9757 bp->mrrs = mrrs;
7a9b2557 9758
34f80b04 9759 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 9760
7d323bfd 9761 /* make sure that the numbers are in the right granularity */
523224a3
DK		 9762 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9763 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 9764
87942b46
EG		 9765 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9766 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 9767
9768 init_timer(&bp->timer);
9769 bp->timer.expires = jiffies + bp->current_interval;
9770 bp->timer.data = (unsigned long) bp;
9771 bp->timer.function = bnx2x_timer;
9772
785b9b1a 9773 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 9774 bnx2x_dcbx_init_params(bp);
9775
619c5cb6
VZ		 9776#ifdef BCM_CNIC
9777 if (CHIP_IS_E1x(bp))
9778 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9779 else
9780 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9781#endif
9782
6383c0b3
AE		 9783 /* multiple tx priority */
9784 if (CHIP_IS_E1x(bp))
9785 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9786 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9787 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9788 if (CHIP_IS_E3B0(bp))
9789 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9790
34f80b04 9791 return rc;
a2fbb9ea
ET		 9792}
9793
a2fbb9ea 9794
de0c62db
DK		 9795/****************************************************************************
9796* General service functions
9797****************************************************************************/
a2fbb9ea 9798
619c5cb6
VZ		 9799/*
9800 * net_device service functions
9801 */
9802
bb2a0f7a 9803/* called with rtnl_lock */
a2fbb9ea
ET		 9804static int bnx2x_open(struct net_device *dev)
9805{
9806 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 9807 bool global = false;
9808 int other_engine = BP_PATH(bp) ? 0 : 1;
9809 u32 other_load_counter, load_counter;
a2fbb9ea 9810
6eccabb3
EG		 9811 netif_carrier_off(dev);
9812
a2fbb9ea
ET		 9813 bnx2x_set_power_state(bp, PCI_D0);
9814
c9ee9206
VZ		 9815 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9816 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9817
9818 /*
9819 * If parity had happen during the unload, then attentions
9820 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9821 * want the first function loaded on the current engine to
9822 * complete the recovery.
9823 */
9824 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9825 bnx2x_chk_parity_attn(bp, &global, true))
72fd0718 9826 do {
c9ee9206
VZ		 9827 /*
9828 * If there are attentions and they are in a global
9829 * blocks, set the GLOBAL_RESET bit regardless whether
9830 * it will be this function that will complete the
9831 * recovery or not.
72fd0718 9832 */
c9ee9206
VZ		 9833 if (global)
9834 bnx2x_set_reset_global(bp);
72fd0718 9835
c9ee9206
VZ		 9836 /*
9837 * Only the first function on the current engine should
9838 * try to recover in open. In case of attentions in
9839 * global blocks only the first in the chip should try
9840 * to recover.
72fd0718 9841 */
c9ee9206
VZ		 9842 if ((!load_counter &&
9843 (!global || !other_load_counter)) &&
9844 bnx2x_trylock_leader_lock(bp) &&
9845 !bnx2x_leader_reset(bp)) {
9846 netdev_info(bp->dev, "Recovered in open\n");
72fd0718
VZ		 9847 break;
9848 }
9849
c9ee9206 9850 /* recovery has failed... */
72fd0718 9851 bnx2x_set_power_state(bp, PCI_D3hot);
c9ee9206 9852 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 9853
c9ee9206 9854 netdev_err(bp->dev, "Recovery flow hasn't been properly"
72fd0718
VZ		 9855 " completed yet. Try again later. If u still see this"
9856 " message after a few retries then power cycle is"
c9ee9206 9857 " required.\n");
72fd0718
VZ		 9858
9859 return -EAGAIN;
9860 } while (0);
72fd0718
VZ		 9861
9862 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 9863 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 9864}
9865
bb2a0f7a 9866/* called with rtnl_lock */
a2fbb9ea
ET		 9867static int bnx2x_close(struct net_device *dev)
9868{
a2fbb9ea
ET		 9869 struct bnx2x *bp = netdev_priv(dev);
9870
9871 /* Unload the driver, release IRQs */
bb2a0f7a 9872 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
c9ee9206
VZ		 9873
9874 /* Power off */
d3dbfee0 9875 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 9876
9877 return 0;
9878}
9879
619c5cb6
VZ		 9880static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9881 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 9882{
619c5cb6
VZ		 9883 int mc_count = netdev_mc_count(bp->dev);
9884 struct bnx2x_mcast_list_elem *mc_mac =
9885 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9886 struct netdev_hw_addr *ha;
6e30dd4e 9887
619c5cb6
VZ		 9888 if (!mc_mac)
9889 return -ENOMEM;
6e30dd4e 9890
619c5cb6 9891 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 9892
619c5cb6
VZ		 9893 netdev_for_each_mc_addr(ha, bp->dev) {
9894 mc_mac->mac = bnx2x_mc_addr(ha);
9895 list_add_tail(&mc_mac->link, &p->mcast_list);
9896 mc_mac++;
6e30dd4e 9897 }
619c5cb6
VZ		 9898
9899 p->mcast_list_len = mc_count;
9900
9901 return 0;
6e30dd4e
VZ		 9902}
9903
619c5cb6
VZ		 9904static inline void bnx2x_free_mcast_macs_list(
9905 struct bnx2x_mcast_ramrod_params *p)
9906{
9907 struct bnx2x_mcast_list_elem *mc_mac =
9908 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9909 link);
9910
9911 WARN_ON(!mc_mac);
9912 kfree(mc_mac);
9913}
9914
9915/**
9916 * bnx2x_set_uc_list - configure a new unicast MACs list.
9917 *
9918 * @bp: driver handle
6e30dd4e 9919 *
619c5cb6 9920 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 9921 */
619c5cb6 9922static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 9923{
619c5cb6 9924 int rc;
6e30dd4e 9925 struct net_device *dev = bp->dev;
6e30dd4e 9926 struct netdev_hw_addr *ha;
619c5cb6
VZ		 9927 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9928 unsigned long ramrod_flags = 0;
6e30dd4e 9929
619c5cb6
VZ		 9930 /* First schedule a cleanup up of old configuration */
9931 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9932 if (rc < 0) {
9933 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9934 return rc;
9935 }
6e30dd4e
VZ		 9936
9937 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 9938 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9939 BNX2X_UC_LIST_MAC, &ramrod_flags);
9940 if (rc < 0) {
9941 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9942 rc);
9943 return rc;
6e30dd4e
VZ		 9944 }
9945 }
9946
619c5cb6
VZ		 9947 /* Execute the pending commands */
9948 __set_bit(RAMROD_CONT, &ramrod_flags);
9949 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9950 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 9951}
9952
619c5cb6 9953static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 9954{
619c5cb6
VZ		 9955 struct net_device *dev = bp->dev;
9956 struct bnx2x_mcast_ramrod_params rparam = {0};
9957 int rc = 0;
6e30dd4e 9958
619c5cb6 9959 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 9960
619c5cb6
VZ		 9961 /* first, clear all configured multicast MACs */
9962 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9963 if (rc < 0) {
9964 BNX2X_ERR("Failed to clear multicast "
9965 "configuration: %d\n", rc);
9966 return rc;
9967 }
6e30dd4e 9968
619c5cb6
VZ		 9969 /* then, configure a new MACs list */
9970 if (netdev_mc_count(dev)) {
9971 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
9972 if (rc) {
9973 BNX2X_ERR("Failed to create multicast MACs "
9974 "list: %d\n", rc);
9975 return rc;
9976 }
6e30dd4e 9977
619c5cb6
VZ		 9978 /* Now add the new MACs */
9979 rc = bnx2x_config_mcast(bp, &rparam,
9980 BNX2X_MCAST_CMD_ADD);
9981 if (rc < 0)
9982 BNX2X_ERR("Failed to set a new multicast "
9983 "configuration: %d\n", rc);
6e30dd4e 9984
619c5cb6
VZ		 9985 bnx2x_free_mcast_macs_list(&rparam);
9986 }
6e30dd4e 9987
619c5cb6 9988 return rc;
6e30dd4e
VZ		 9989}
9990
6e30dd4e 9991
619c5cb6 9992/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 9993void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 9994{
9995 struct bnx2x *bp = netdev_priv(dev);
9996 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 9997
9998 if (bp->state != BNX2X_STATE_OPEN) {
9999 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10000 return;
10001 }
10002
619c5cb6 10003 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 10004
10005 if (dev->flags & IFF_PROMISC)
10006 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 10007 else if ((dev->flags & IFF_ALLMULTI) ||
10008 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10009 CHIP_IS_E1(bp)))
34f80b04 10010 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 10011 else {
10012 /* some multicasts */
619c5cb6 10013 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 10014 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 10015
619c5cb6 10016 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 10017 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 10018 }
10019
10020 bp->rx_mode = rx_mode;
619c5cb6
VZ		 10021
10022 /* Schedule the rx_mode command */
10023 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10024 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10025 return;
10026 }
10027
34f80b04
EG		 10028 bnx2x_set_storm_rx_mode(bp);
10029}
10030
c18487ee 10031/* called with rtnl_lock */
01cd4528
EG		 10032static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10033 int devad, u16 addr)
a2fbb9ea 10034{
01cd4528
EG		 10035 struct bnx2x *bp = netdev_priv(netdev);
10036 u16 value;
10037 int rc;
a2fbb9ea 10038
01cd4528
EG		 10039 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10040 prtad, devad, addr);
a2fbb9ea 10041
01cd4528
EG		 10042 /* The HW expects different devad if CL22 is used */
10043 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 10044
01cd4528 10045 bnx2x_acquire_phy_lock(bp);
e10bc84d 10046 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 10047 bnx2x_release_phy_lock(bp);
10048 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 10049
01cd4528
EG		 10050 if (!rc)
10051 rc = value;
10052 return rc;
10053}
a2fbb9ea 10054
01cd4528
EG		 10055/* called with rtnl_lock */
10056static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10057 u16 addr, u16 value)
10058{
10059 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 10060 int rc;
10061
10062 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10063 " value 0x%x\n", prtad, devad, addr, value);
10064
01cd4528
EG		 10065 /* The HW expects different devad if CL22 is used */
10066 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 10067
01cd4528 10068 bnx2x_acquire_phy_lock(bp);
e10bc84d 10069 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 10070 bnx2x_release_phy_lock(bp);
10071 return rc;
10072}
c18487ee 10073
01cd4528
EG		 10074/* called with rtnl_lock */
10075static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10076{
10077 struct bnx2x *bp = netdev_priv(dev);
10078 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 10079
01cd4528
EG		 10080 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10081 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 10082
01cd4528
EG		 10083 if (!netif_running(dev))
10084 return -EAGAIN;
10085
10086 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 10087}
10088
257ddbda 10089#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 10090static void poll_bnx2x(struct net_device *dev)
10091{
10092 struct bnx2x *bp = netdev_priv(dev);
10093
10094 disable_irq(bp->pdev->irq);
10095 bnx2x_interrupt(bp->pdev->irq, dev);
10096 enable_irq(bp->pdev->irq);
10097}
10098#endif
10099
c64213cd
SH		 10100static const struct net_device_ops bnx2x_netdev_ops = {
10101 .ndo_open = bnx2x_open,
10102 .ndo_stop = bnx2x_close,
10103 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 10104 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 10105 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd
SH		 10106 .ndo_set_mac_address = bnx2x_change_mac_addr,
10107 .ndo_validate_addr = eth_validate_addr,
10108 .ndo_do_ioctl = bnx2x_ioctl,
10109 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 10110 .ndo_fix_features = bnx2x_fix_features,
10111 .ndo_set_features = bnx2x_set_features,
c64213cd 10112 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 10113#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 10114 .ndo_poll_controller = poll_bnx2x,
10115#endif
6383c0b3
AE		 10116 .ndo_setup_tc = bnx2x_setup_tc,
10117
bf61ee14
VZ		 10118#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10119 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10120#endif
c64213cd
SH		 10121};
10122
619c5cb6
VZ		 10123static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10124{
10125 struct device *dev = &bp->pdev->dev;
10126
10127 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10128 bp->flags |= USING_DAC_FLAG;
10129 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10130 dev_err(dev, "dma_set_coherent_mask failed, "
10131 "aborting\n");
10132 return -EIO;
10133 }
10134 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10135 dev_err(dev, "System does not support DMA, aborting\n");
10136 return -EIO;
10137 }
10138
10139 return 0;
10140}
10141
34f80b04 10142static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 10143 struct net_device *dev,
10144 unsigned long board_type)
a2fbb9ea
ET		 10145{
10146 struct bnx2x *bp;
10147 int rc;
10148
10149 SET_NETDEV_DEV(dev, &pdev->dev);
10150 bp = netdev_priv(dev);
10151
34f80b04
EG		 10152 bp->dev = dev;
10153 bp->pdev = pdev;
a2fbb9ea 10154 bp->flags = 0;
f2e0899f 10155 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 10156
10157 rc = pci_enable_device(pdev);
10158 if (rc) {
cdaa7cb8
VZ		 10159 dev_err(&bp->pdev->dev,
10160 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 10161 goto err_out;
10162 }
10163
10164 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10165 dev_err(&bp->pdev->dev,
10166 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 10167 rc = -ENODEV;
10168 goto err_out_disable;
10169 }
10170
10171 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10172 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10173 " base address, aborting\n");
a2fbb9ea
ET		 10174 rc = -ENODEV;
10175 goto err_out_disable;
10176 }
10177
34f80b04
EG		 10178 if (atomic_read(&pdev->enable_cnt) == 1) {
10179 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10180 if (rc) {
cdaa7cb8
VZ		 10181 dev_err(&bp->pdev->dev,
10182 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 10183 goto err_out_disable;
10184 }
a2fbb9ea 10185
34f80b04
EG		 10186 pci_set_master(pdev);
10187 pci_save_state(pdev);
10188 }
a2fbb9ea
ET		 10189
10190 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10191 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 10192 dev_err(&bp->pdev->dev,
10193 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 10194 rc = -EIO;
10195 goto err_out_release;
10196 }
10197
77c98e6a
JM		 10198 if (!pci_is_pcie(pdev)) {
10199 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 10200 rc = -EIO;
10201 goto err_out_release;
10202 }
10203
619c5cb6
VZ		 10204 rc = bnx2x_set_coherency_mask(bp);
10205 if (rc)
a2fbb9ea 10206 goto err_out_release;
a2fbb9ea 10207
34f80b04
EG		 10208 dev->mem_start = pci_resource_start(pdev, 0);
10209 dev->base_addr = dev->mem_start;
10210 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 10211
10212 dev->irq = pdev->irq;
10213
275f165f 10214 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 10215 if (!bp->regview) {
cdaa7cb8
VZ		 10216 dev_err(&bp->pdev->dev,
10217 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 10218 rc = -ENOMEM;
10219 goto err_out_release;
10220 }
10221
a2fbb9ea
ET		 10222 bnx2x_set_power_state(bp, PCI_D0);
10223
34f80b04
EG		 10224 /* clean indirect addresses */
10225 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10226 PCICFG_VENDOR_ID_OFFSET);
10227 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
10228 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
10229 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
10230 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 10231
619c5cb6
VZ		 10232 /**
10233 * Enable internal target-read (in case we are probed after PF FLR).
10234 * Must be done prior to any BAR read access
10235 */
10236 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10237
72fd0718
VZ		 10238 /* Reset the load counter */
10239 bnx2x_clear_load_cnt(bp);
10240
34f80b04 10241 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 10242
c64213cd 10243 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 10244 bnx2x_set_ethtool_ops(dev);
5316bc0b 10245
66371c44
MM		 10246 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10247 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10248 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10249
10250 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10251 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10252
10253 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 10254 if (bp->flags & USING_DAC_FLAG)
66371c44 10255 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 10256
538dd2e3
MB		 10257 /* Add Loopback capability to the device */
10258 dev->hw_features |= NETIF_F_LOOPBACK;
10259
98507672 10260#ifdef BCM_DCBNL
785b9b1a
SR		 10261 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10262#endif
10263
01cd4528
EG		 10264 /* get_port_hwinfo() will set prtad and mmds properly */
10265 bp->mdio.prtad = MDIO_PRTAD_NONE;
10266 bp->mdio.mmds = 0;
10267 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10268 bp->mdio.dev = dev;
10269 bp->mdio.mdio_read = bnx2x_mdio_read;
10270 bp->mdio.mdio_write = bnx2x_mdio_write;
10271
a2fbb9ea
ET		 10272 return 0;
10273
a2fbb9ea 10274err_out_release:
34f80b04
EG		 10275 if (atomic_read(&pdev->enable_cnt) == 1)
10276 pci_release_regions(pdev);
a2fbb9ea
ET		 10277
10278err_out_disable:
10279 pci_disable_device(pdev);
10280 pci_set_drvdata(pdev, NULL);
10281
10282err_out:
10283 return rc;
10284}
10285
37f9ce62
EG		 10286static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10287 int *width, int *speed)
25047950
ET		 10288{
10289 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10290
37f9ce62 10291 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 10292
37f9ce62
EG		 10293 /* return value of 1=2.5GHz 2=5GHz */
10294 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 10295}
37f9ce62 10296
6891dd25 10297static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 10298{
37f9ce62 10299 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 10300 struct bnx2x_fw_file_hdr *fw_hdr;
10301 struct bnx2x_fw_file_section *sections;
94a78b79 10302 u32 offset, len, num_ops;
37f9ce62 10303 u16 *ops_offsets;
94a78b79 10304 int i;
37f9ce62 10305 const u8 *fw_ver;
94a78b79
VZ		 10306
10307 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10308 return -EINVAL;
10309
10310 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10311 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10312
10313 /* Make sure none of the offsets and sizes make us read beyond
10314 * the end of the firmware data */
10315 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10316 offset = be32_to_cpu(sections[i].offset);
10317 len = be32_to_cpu(sections[i].len);
10318 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 10319 dev_err(&bp->pdev->dev,
10320 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 10321 return -EINVAL;
10322 }
10323 }
10324
10325 /* Likewise for the init_ops offsets */
10326 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10327 ops_offsets = (u16 *)(firmware->data + offset);
10328 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10329
10330 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10331 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 10332 dev_err(&bp->pdev->dev,
10333 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 10334 return -EINVAL;
10335 }
10336 }
10337
10338 /* Check FW version */
10339 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10340 fw_ver = firmware->data + offset;
10341 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10342 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10343 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10344 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 10345 dev_err(&bp->pdev->dev,
10346 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 10347 fw_ver[0], fw_ver[1], fw_ver[2],
10348 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10349 BCM_5710_FW_MINOR_VERSION,
10350 BCM_5710_FW_REVISION_VERSION,
10351 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 10352 return -EINVAL;
94a78b79
VZ		 10353 }
10354
10355 return 0;
10356}
10357
ab6ad5a4 10358static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10359{
ab6ad5a4
EG		 10360 const __be32 *source = (const __be32 *)_source;
10361 u32 *target = (u32 *)_target;
94a78b79 10362 u32 i;
94a78b79
VZ		 10363
10364 for (i = 0; i < n/4; i++)
10365 target[i] = be32_to_cpu(source[i]);
10366}
10367
10368/*
10369 Ops array is stored in the following format:
10370 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10371 */
ab6ad5a4 10372static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 10373{
ab6ad5a4
EG		 10374 const __be32 *source = (const __be32 *)_source;
10375 struct raw_op *target = (struct raw_op *)_target;
94a78b79 10376 u32 i, j, tmp;
94a78b79 10377
ab6ad5a4 10378 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 10379 tmp = be32_to_cpu(source[j]);
10380 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 10381 target[i].offset = tmp & 0xffffff;
10382 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 10383 }
10384}
ab6ad5a4 10385
523224a3
DK		 10386/**
10387 * IRO array is stored in the following format:
10388 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10389 */
10390static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10391{
10392 const __be32 *source = (const __be32 *)_source;
10393 struct iro *target = (struct iro *)_target;
10394 u32 i, j, tmp;
10395
10396 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10397 target[i].base = be32_to_cpu(source[j]);
10398 j++;
10399 tmp = be32_to_cpu(source[j]);
10400 target[i].m1 = (tmp >> 16) & 0xffff;
10401 target[i].m2 = tmp & 0xffff;
10402 j++;
10403 tmp = be32_to_cpu(source[j]);
10404 target[i].m3 = (tmp >> 16) & 0xffff;
10405 target[i].size = tmp & 0xffff;
10406 j++;
10407 }
10408}
10409
ab6ad5a4 10410static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10411{
ab6ad5a4
EG		 10412 const __be16 *source = (const __be16 *)_source;
10413 u16 *target = (u16 *)_target;
94a78b79 10414 u32 i;
94a78b79
VZ		 10415
10416 for (i = 0; i < n/2; i++)
10417 target[i] = be16_to_cpu(source[i]);
10418}
10419
7995c64e
JP		 10420#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10421do { \
10422 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10423 bp->arr = kmalloc(len, GFP_KERNEL); \
10424 if (!bp->arr) { \
10425 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10426 goto lbl; \
10427 } \
10428 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10429 (u8 *)bp->arr, len); \
10430} while (0)
94a78b79 10431
6891dd25 10432int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 10433{
45229b42 10434 const char *fw_file_name;
94a78b79 10435 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 10436 int rc;
94a78b79 10437
94a78b79 10438 if (CHIP_IS_E1(bp))
45229b42 10439 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 10440 else if (CHIP_IS_E1H(bp))
45229b42 10441 fw_file_name = FW_FILE_NAME_E1H;
619c5cb6 10442 else if (!CHIP_IS_E1x(bp))
f2e0899f 10443 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 10444 else {
6891dd25 10445 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 10446 return -EINVAL;
10447 }
94a78b79 10448
6891dd25 10449 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 10450
6891dd25 10451 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 10452 if (rc) {
6891dd25 10453 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 10454 goto request_firmware_exit;
10455 }
10456
10457 rc = bnx2x_check_firmware(bp);
10458 if (rc) {
6891dd25 10459 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 10460 goto request_firmware_exit;
10461 }
10462
10463 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10464
10465 /* Initialize the pointers to the init arrays */
10466 /* Blob */
10467 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10468
10469 /* Opcodes */
10470 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10471
10472 /* Offsets */
ab6ad5a4
EG		 10473 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10474 be16_to_cpu_n);
94a78b79
VZ		 10475
10476 /* STORMs firmware */
573f2035
EG		 10477 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10478 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10479 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10480 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10481 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10482 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10483 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10484 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10485 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10486 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10487 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10488 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10489 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10490 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10491 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10492 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 10493 /* IRO */
10494 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 10495
10496 return 0;
ab6ad5a4 10497
523224a3
DK		 10498iro_alloc_err:
10499 kfree(bp->init_ops_offsets);
94a78b79
VZ		 10500init_offsets_alloc_err:
10501 kfree(bp->init_ops);
10502init_ops_alloc_err:
10503 kfree(bp->init_data);
10504request_firmware_exit:
10505 release_firmware(bp->firmware);
10506
10507 return rc;
10508}
10509
619c5cb6
VZ		 10510static void bnx2x_release_firmware(struct bnx2x *bp)
10511{
10512 kfree(bp->init_ops_offsets);
10513 kfree(bp->init_ops);
10514 kfree(bp->init_data);
10515 release_firmware(bp->firmware);
10516}
10517
10518
10519static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10520 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10521 .init_hw_cmn = bnx2x_init_hw_common,
10522 .init_hw_port = bnx2x_init_hw_port,
10523 .init_hw_func = bnx2x_init_hw_func,
10524
10525 .reset_hw_cmn = bnx2x_reset_common,
10526 .reset_hw_port = bnx2x_reset_port,
10527 .reset_hw_func = bnx2x_reset_func,
10528
10529 .gunzip_init = bnx2x_gunzip_init,
10530 .gunzip_end = bnx2x_gunzip_end,
10531
10532 .init_fw = bnx2x_init_firmware,
10533 .release_fw = bnx2x_release_firmware,
10534};
10535
10536void bnx2x__init_func_obj(struct bnx2x *bp)
10537{
10538 /* Prepare DMAE related driver resources */
10539 bnx2x_setup_dmae(bp);
10540
10541 bnx2x_init_func_obj(bp, &bp->func_obj,
10542 bnx2x_sp(bp, func_rdata),
10543 bnx2x_sp_mapping(bp, func_rdata),
10544 &bnx2x_func_sp_drv);
10545}
10546
10547/* must be called after sriov-enable */
6383c0b3 10548static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 10549{
6383c0b3 10550 int cid_count = BNX2X_L2_CID_COUNT(bp);
94a78b79 10551
523224a3
DK		 10552#ifdef BCM_CNIC
10553 cid_count += CNIC_CID_MAX;
10554#endif
10555 return roundup(cid_count, QM_CID_ROUND);
10556}
f85582f8 10557
619c5cb6 10558/**
6383c0b3 10559 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 10560 *
10561 * @dev: pci device
10562 *
10563 */
6383c0b3 10564static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
619c5cb6
VZ		 10565{
10566 int pos;
10567 u16 control;
10568
10569 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 10570
10571 /*
10572 * If MSI-X is not supported - return number of SBs needed to support
10573 * one fast path queue: one FP queue + SB for CNIC
10574 */
619c5cb6 10575 if (!pos)
6383c0b3 10576 return 1 + CNIC_PRESENT;
619c5cb6 10577
6383c0b3
AE		 10578 /*
10579 * The value in the PCI configuration space is the index of the last
10580 * entry, namely one less than the actual size of the table, which is
10581 * exactly what we want to return from this function: number of all SBs
10582 * without the default SB.
10583 */
619c5cb6 10584 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
6383c0b3 10585 return control & PCI_MSIX_FLAGS_QSIZE;
619c5cb6
VZ		 10586}
10587
a2fbb9ea
ET		 10588static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10589 const struct pci_device_id *ent)
10590{
a2fbb9ea
ET		 10591 struct net_device *dev = NULL;
10592 struct bnx2x *bp;
37f9ce62 10593 int pcie_width, pcie_speed;
6383c0b3
AE		 10594 int rc, max_non_def_sbs;
10595 int rx_count, tx_count, rss_count;
10596 /*
10597 * An estimated maximum supported CoS number according to the chip
10598 * version.
10599 * We will try to roughly estimate the maximum number of CoSes this chip
10600 * may support in order to minimize the memory allocated for Tx
10601 * netdev_queue's. This number will be accurately calculated during the
10602 * initialization of bp->max_cos based on the chip versions AND chip
10603 * revision in the bnx2x_init_bp().
10604 */
10605 u8 max_cos_est = 0;
523224a3 10606
f2e0899f
DK		 10607 switch (ent->driver_data) {
10608 case BCM57710:
10609 case BCM57711:
10610 case BCM57711E:
6383c0b3
AE		 10611 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10612 break;
10613
f2e0899f 10614 case BCM57712:
619c5cb6 10615 case BCM57712_MF:
6383c0b3
AE		 10616 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10617 break;
10618
619c5cb6
VZ		 10619 case BCM57800:
10620 case BCM57800_MF:
10621 case BCM57810:
10622 case BCM57810_MF:
10623 case BCM57840:
10624 case BCM57840_MF:
6383c0b3 10625 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
f2e0899f 10626 break;
a2fbb9ea 10627
f2e0899f
DK		 10628 default:
10629 pr_err("Unknown board_type (%ld), aborting\n",
10630 ent->driver_data);
870634b0 10631 return -ENODEV;
f2e0899f
DK		 10632 }
10633
6383c0b3
AE		 10634 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10635
10636 /* !!! FIXME !!!
10637 * Do not allow the maximum SB count to grow above 16
10638 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10639 * We will use the FP_SB_MAX_E1x macro for this matter.
10640 */
10641 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10642
10643 WARN_ON(!max_non_def_sbs);
10644
10645 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10646 rss_count = max_non_def_sbs - CNIC_PRESENT;
10647
10648 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10649 rx_count = rss_count + FCOE_PRESENT;
10650
10651 /*
10652 * Maximum number of netdev Tx queues:
10653 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10654 */
10655 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
f85582f8 10656
a2fbb9ea 10657 /* dev zeroed in init_etherdev */
6383c0b3 10658 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
34f80b04 10659 if (!dev) {
cdaa7cb8 10660 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 10661 return -ENOMEM;
34f80b04 10662 }
a2fbb9ea 10663
a2fbb9ea 10664 bp = netdev_priv(dev);
a2fbb9ea 10665
6383c0b3
AE		 10666 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10667 tx_count, rx_count);
df4770de 10668
6383c0b3
AE		 10669 bp->igu_sb_cnt = max_non_def_sbs;
10670 bp->msg_enable = debug;
10671 pci_set_drvdata(pdev, dev);
523224a3 10672
619c5cb6 10673 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 10674 if (rc < 0) {
10675 free_netdev(dev);
10676 return rc;
10677 }
10678
6383c0b3 10679 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
619c5cb6 10680
34f80b04 10681 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 10682 if (rc)
10683 goto init_one_exit;
10684
6383c0b3
AE		 10685 /*
10686 * Map doorbels here as we need the real value of bp->max_cos which
10687 * is initialized in bnx2x_init_bp().
10688 */
10689 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10690 min_t(u64, BNX2X_DB_SIZE(bp),
10691 pci_resource_len(pdev, 2)));
10692 if (!bp->doorbells) {
10693 dev_err(&bp->pdev->dev,
10694 "Cannot map doorbell space, aborting\n");
10695 rc = -ENOMEM;
10696 goto init_one_exit;
10697 }
10698
523224a3 10699 /* calc qm_cid_count */
6383c0b3 10700 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
523224a3 10701
ec6ba945 10702#ifdef BCM_CNIC
928ad22a
DK		 10703 /* disable FCOE L2 queue for E1x and E3*/
10704 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
ec6ba945
VZ		 10705 bp->flags |= NO_FCOE_FLAG;
10706
10707#endif
10708
25985edc 10709 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 10710 * needed, set bp->num_queues appropriately.
10711 */
10712 bnx2x_set_int_mode(bp);
10713
10714 /* Add all NAPI objects */
10715 bnx2x_add_all_napi(bp);
10716
b340007f
VZ		 10717 rc = register_netdev(dev);
10718 if (rc) {
10719 dev_err(&pdev->dev, "Cannot register net device\n");
10720 goto init_one_exit;
10721 }
10722
ec6ba945
VZ		 10723#ifdef BCM_CNIC
10724 if (!NO_FCOE(bp)) {
10725 /* Add storage MAC address */
10726 rtnl_lock();
10727 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10728 rtnl_unlock();
10729 }
10730#endif
10731
37f9ce62 10732 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 10733
cdaa7cb8
VZ		 10734 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10735 " IRQ %d, ", board_info[ent->driver_data].name,
10736 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 10737 pcie_width,
10738 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10739 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10740 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 10741 dev->base_addr, bp->pdev->irq);
10742 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 10743
a2fbb9ea 10744 return 0;
34f80b04
EG		 10745
10746init_one_exit:
10747 if (bp->regview)
10748 iounmap(bp->regview);
10749
10750 if (bp->doorbells)
10751 iounmap(bp->doorbells);
10752
10753 free_netdev(dev);
10754
10755 if (atomic_read(&pdev->enable_cnt) == 1)
10756 pci_release_regions(pdev);
10757
10758 pci_disable_device(pdev);
10759 pci_set_drvdata(pdev, NULL);
10760
10761 return rc;
a2fbb9ea
ET		 10762}
10763
10764static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10765{
10766 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 10767 struct bnx2x *bp;
10768
10769 if (!dev) {
cdaa7cb8 10770 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 10771 return;
10772 }
228241eb 10773 bp = netdev_priv(dev);
a2fbb9ea 10774
ec6ba945
VZ		 10775#ifdef BCM_CNIC
10776 /* Delete storage MAC address */
10777 if (!NO_FCOE(bp)) {
10778 rtnl_lock();
10779 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10780 rtnl_unlock();
10781 }
10782#endif
10783
98507672
SR		 10784#ifdef BCM_DCBNL
10785 /* Delete app tlvs from dcbnl */
10786 bnx2x_dcbnl_update_applist(bp, true);
10787#endif
10788
a2fbb9ea
ET		 10789 unregister_netdev(dev);
10790
d6214d7a
DK		 10791 /* Delete all NAPI objects */
10792 bnx2x_del_all_napi(bp);
10793
084d6cbb
VZ		 10794 /* Power on: we can't let PCI layer write to us while we are in D3 */
10795 bnx2x_set_power_state(bp, PCI_D0);
10796
d6214d7a
DK		 10797 /* Disable MSI/MSI-X */
10798 bnx2x_disable_msi(bp);
f85582f8 10799
084d6cbb
VZ		 10800 /* Power off */
10801 bnx2x_set_power_state(bp, PCI_D3hot);
10802
72fd0718 10803 /* Make sure RESET task is not scheduled before continuing */
7be08a72 10804 cancel_delayed_work_sync(&bp->sp_rtnl_task);
72fd0718 10805
a2fbb9ea
ET		 10806 if (bp->regview)
10807 iounmap(bp->regview);
10808
10809 if (bp->doorbells)
10810 iounmap(bp->doorbells);
10811
523224a3
DK		 10812 bnx2x_free_mem_bp(bp);
10813
a2fbb9ea 10814 free_netdev(dev);
34f80b04
EG		 10815
10816 if (atomic_read(&pdev->enable_cnt) == 1)
10817 pci_release_regions(pdev);
10818
a2fbb9ea
ET		 10819 pci_disable_device(pdev);
10820 pci_set_drvdata(pdev, NULL);
10821}
10822
f8ef6e44
YG		 10823static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10824{
10825 int i;
10826
10827 bp->state = BNX2X_STATE_ERROR;
10828
10829 bp->rx_mode = BNX2X_RX_MODE_NONE;
10830
619c5cb6
VZ		 10831#ifdef BCM_CNIC
10832 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10833#endif
10834 /* Stop Tx */
10835 bnx2x_tx_disable(bp);
10836
f8ef6e44
YG		 10837 bnx2x_netif_stop(bp, 0);
10838
10839 del_timer_sync(&bp->timer);
619c5cb6
VZ		 10840
10841 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 10842
10843 /* Release IRQs */
d6214d7a 10844 bnx2x_free_irq(bp);
f8ef6e44 10845
f8ef6e44
YG		 10846 /* Free SKBs, SGEs, TPA pool and driver internals */
10847 bnx2x_free_skbs(bp);
523224a3 10848
ec6ba945 10849 for_each_rx_queue(bp, i)
f8ef6e44 10850 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 10851
f8ef6e44
YG		 10852 bnx2x_free_mem(bp);
10853
10854 bp->state = BNX2X_STATE_CLOSED;
10855
619c5cb6
VZ		 10856 netif_carrier_off(bp->dev);
10857
f8ef6e44
YG		 10858 return 0;
10859}
10860
10861static void bnx2x_eeh_recover(struct bnx2x *bp)
10862{
10863 u32 val;
10864
10865 mutex_init(&bp->port.phy_mutex);
10866
10867 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10868 bp->link_params.shmem_base = bp->common.shmem_base;
10869 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10870
10871 if (!bp->common.shmem_base ||
10872 (bp->common.shmem_base < 0xA0000) ||
10873 (bp->common.shmem_base >= 0xC0000)) {
10874 BNX2X_DEV_INFO("MCP not active\n");
10875 bp->flags |= NO_MCP_FLAG;
10876 return;
10877 }
10878
10879 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10880 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10881 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10882 BNX2X_ERR("BAD MCP validity signature\n");
10883
10884 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 10885 bp->fw_seq =
10886 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10887 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 10888 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10889 }
10890}
10891
493adb1f
WX		 10892/**
10893 * bnx2x_io_error_detected - called when PCI error is detected
10894 * @pdev: Pointer to PCI device
10895 * @state: The current pci connection state
10896 *
10897 * This function is called after a PCI bus error affecting
10898 * this device has been detected.
10899 */
10900static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10901 pci_channel_state_t state)
10902{
10903 struct net_device *dev = pci_get_drvdata(pdev);
10904 struct bnx2x *bp = netdev_priv(dev);
10905
10906 rtnl_lock();
10907
10908 netif_device_detach(dev);
10909
07ce50e4
DN		 10910 if (state == pci_channel_io_perm_failure) {
10911 rtnl_unlock();
10912 return PCI_ERS_RESULT_DISCONNECT;
10913 }
10914
493adb1f 10915 if (netif_running(dev))
f8ef6e44 10916 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 10917
10918 pci_disable_device(pdev);
10919
10920 rtnl_unlock();
10921
10922 /* Request a slot reset */
10923 return PCI_ERS_RESULT_NEED_RESET;
10924}
10925
10926/**
10927 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10928 * @pdev: Pointer to PCI device
10929 *
10930 * Restart the card from scratch, as if from a cold-boot.
10931 */
10932static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10933{
10934 struct net_device *dev = pci_get_drvdata(pdev);
10935 struct bnx2x *bp = netdev_priv(dev);
10936
10937 rtnl_lock();
10938
10939 if (pci_enable_device(pdev)) {
10940 dev_err(&pdev->dev,
10941 "Cannot re-enable PCI device after reset\n");
10942 rtnl_unlock();
10943 return PCI_ERS_RESULT_DISCONNECT;
10944 }
10945
10946 pci_set_master(pdev);
10947 pci_restore_state(pdev);
10948
10949 if (netif_running(dev))
10950 bnx2x_set_power_state(bp, PCI_D0);
10951
10952 rtnl_unlock();
10953
10954 return PCI_ERS_RESULT_RECOVERED;
10955}
10956
10957/**
10958 * bnx2x_io_resume - called when traffic can start flowing again
10959 * @pdev: Pointer to PCI device
10960 *
10961 * This callback is called when the error recovery driver tells us that
10962 * its OK to resume normal operation.
10963 */
10964static void bnx2x_io_resume(struct pci_dev *pdev)
10965{
10966 struct net_device *dev = pci_get_drvdata(pdev);
10967 struct bnx2x *bp = netdev_priv(dev);
10968
72fd0718 10969 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
754a2f52
DK		 10970 netdev_err(bp->dev, "Handling parity error recovery. "
10971 "Try again later\n");
72fd0718
VZ		 10972 return;
10973 }
10974
493adb1f
WX		 10975 rtnl_lock();
10976
f8ef6e44
YG		 10977 bnx2x_eeh_recover(bp);
10978
493adb1f 10979 if (netif_running(dev))
f8ef6e44 10980 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 10981
10982 netif_device_attach(dev);
10983
10984 rtnl_unlock();
10985}
10986
10987static struct pci_error_handlers bnx2x_err_handler = {
10988 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 10989 .slot_reset = bnx2x_io_slot_reset,
10990 .resume = bnx2x_io_resume,
493adb1f
WX		 10991};
10992
a2fbb9ea 10993static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 10994 .name = DRV_MODULE_NAME,
10995 .id_table = bnx2x_pci_tbl,
10996 .probe = bnx2x_init_one,
10997 .remove = __devexit_p(bnx2x_remove_one),
10998 .suspend = bnx2x_suspend,
10999 .resume = bnx2x_resume,
11000 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 11001};
11002
11003static int __init bnx2x_init(void)
11004{
dd21ca6d
SG		 11005 int ret;
11006
7995c64e 11007 pr_info("%s", version);
938cf541 11008
1cf167f2
EG		 11009 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11010 if (bnx2x_wq == NULL) {
7995c64e 11011 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 11012 return -ENOMEM;
11013 }
11014
dd21ca6d
SG		 11015 ret = pci_register_driver(&bnx2x_pci_driver);
11016 if (ret) {
7995c64e 11017 pr_err("Cannot register driver\n");
dd21ca6d
SG		 11018 destroy_workqueue(bnx2x_wq);
11019 }
11020 return ret;
a2fbb9ea
ET		 11021}
11022
11023static void __exit bnx2x_cleanup(void)
11024{
11025 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 11026
11027 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 11028}
11029
3deb8167
YR		 11030void bnx2x_notify_link_changed(struct bnx2x *bp)
11031{
11032 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11033}
11034
a2fbb9ea
ET		 11035module_init(bnx2x_init);
11036module_exit(bnx2x_cleanup);
11037
993ac7b5 11038#ifdef BCM_CNIC
619c5cb6
VZ		 11039/**
11040 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11041 *
11042 * @bp: driver handle
11043 * @set: set or clear the CAM entry
11044 *
11045 * This function will wait until the ramdord completion returns.
11046 * Return 0 if success, -ENODEV if ramrod doesn't return.
11047 */
11048static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11049{
11050 unsigned long ramrod_flags = 0;
11051
11052 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11053 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11054 &bp->iscsi_l2_mac_obj, true,
11055 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11056}
993ac7b5
MC		 11057
11058/* count denotes the number of new completions we have seen */
11059static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11060{
11061 struct eth_spe *spe;
11062
11063#ifdef BNX2X_STOP_ON_ERROR
11064 if (unlikely(bp->panic))
11065 return;
11066#endif
11067
11068 spin_lock_bh(&bp->spq_lock);
c2bff63f 11069 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 11070 bp->cnic_spq_pending -= count;
11071
993ac7b5 11072
c2bff63f
DK		 11073 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11074 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11075 & SPE_HDR_CONN_TYPE) >>
11076 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 11077 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11078 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 11079
11080 /* Set validation for iSCSI L2 client before sending SETUP
11081 * ramrod
11082 */
11083 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 11084 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 11085 bnx2x_set_ctx_validation(bp, &bp->context.
11086 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11087 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 11088 }
11089
619c5cb6
VZ		 11090 /*
11091 * There may be not more than 8 L2, not more than 8 L5 SPEs
11092 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 11093 * COMMON ramrods is not more than the EQ and SPQ can
11094 * accommodate.
c2bff63f 11095 */
6e30dd4e
VZ		 11096 if (type == ETH_CONNECTION_TYPE) {
11097 if (!atomic_read(&bp->cq_spq_left))
11098 break;
11099 else
11100 atomic_dec(&bp->cq_spq_left);
11101 } else if (type == NONE_CONNECTION_TYPE) {
11102 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 11103 break;
11104 else
6e30dd4e 11105 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 11106 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11107 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 11108 if (bp->cnic_spq_pending >=
11109 bp->cnic_eth_dev.max_kwqe_pending)
11110 break;
11111 else
11112 bp->cnic_spq_pending++;
11113 } else {
11114 BNX2X_ERR("Unknown SPE type: %d\n", type);
11115 bnx2x_panic();
993ac7b5 11116 break;
c2bff63f 11117 }
993ac7b5
MC		 11118
11119 spe = bnx2x_sp_get_next(bp);
11120 *spe = *bp->cnic_kwq_cons;
11121
993ac7b5
MC		 11122 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11123 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11124
11125 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11126 bp->cnic_kwq_cons = bp->cnic_kwq;
11127 else
11128 bp->cnic_kwq_cons++;
11129 }
11130 bnx2x_sp_prod_update(bp);
11131 spin_unlock_bh(&bp->spq_lock);
11132}
11133
11134static int bnx2x_cnic_sp_queue(struct net_device *dev,
11135 struct kwqe_16 *kwqes[], u32 count)
11136{
11137 struct bnx2x *bp = netdev_priv(dev);
11138 int i;
11139
11140#ifdef BNX2X_STOP_ON_ERROR
11141 if (unlikely(bp->panic))
11142 return -EIO;
11143#endif
11144
11145 spin_lock_bh(&bp->spq_lock);
11146
11147 for (i = 0; i < count; i++) {
11148 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11149
11150 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11151 break;
11152
11153 *bp->cnic_kwq_prod = *spe;
11154
11155 bp->cnic_kwq_pending++;
11156
11157 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11158 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 11159 spe->data.update_data_addr.hi,
11160 spe->data.update_data_addr.lo,
993ac7b5
MC		 11161 bp->cnic_kwq_pending);
11162
11163 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11164 bp->cnic_kwq_prod = bp->cnic_kwq;
11165 else
11166 bp->cnic_kwq_prod++;
11167 }
11168
11169 spin_unlock_bh(&bp->spq_lock);
11170
11171 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11172 bnx2x_cnic_sp_post(bp, 0);
11173
11174 return i;
11175}
11176
11177static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11178{
11179 struct cnic_ops *c_ops;
11180 int rc = 0;
11181
11182 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 11183 c_ops = rcu_dereference_protected(bp->cnic_ops,
11184 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 11185 if (c_ops)
11186 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11187 mutex_unlock(&bp->cnic_mutex);
11188
11189 return rc;
11190}
11191
11192static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11193{
11194 struct cnic_ops *c_ops;
11195 int rc = 0;
11196
11197 rcu_read_lock();
11198 c_ops = rcu_dereference(bp->cnic_ops);
11199 if (c_ops)
11200 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11201 rcu_read_unlock();
11202
11203 return rc;
11204}
11205
11206/*
11207 * for commands that have no data
11208 */
9f6c9258 11209int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 11210{
11211 struct cnic_ctl_info ctl = {0};
11212
11213 ctl.cmd = cmd;
11214
11215 return bnx2x_cnic_ctl_send(bp, &ctl);
11216}
11217
619c5cb6 11218static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 11219{
619c5cb6 11220 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 11221
11222 /* first we tell CNIC and only then we count this as a completion */
11223 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11224 ctl.data.comp.cid = cid;
619c5cb6 11225 ctl.data.comp.error = err;
993ac7b5
MC		 11226
11227 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 11228 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 11229}
11230
619c5cb6
VZ		 11231
11232/* Called with netif_addr_lock_bh() taken.
11233 * Sets an rx_mode config for an iSCSI ETH client.
11234 * Doesn't block.
11235 * Completion should be checked outside.
11236 */
11237static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11238{
11239 unsigned long accept_flags = 0, ramrod_flags = 0;
11240 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11241 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11242
11243 if (start) {
11244 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11245 * because it's the only way for UIO Queue to accept
11246 * multicasts (in non-promiscuous mode only one Queue per
11247 * function will receive multicast packets (leading in our
11248 * case).
11249 */
11250 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11251 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11252 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11253 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11254
11255 /* Clear STOP_PENDING bit if START is requested */
11256 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11257
11258 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11259 } else
11260 /* Clear START_PENDING bit if STOP is requested */
11261 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11262
11263 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11264 set_bit(sched_state, &bp->sp_state);
11265 else {
11266 __set_bit(RAMROD_RX, &ramrod_flags);
11267 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11268 ramrod_flags);
11269 }
11270}
11271
11272
993ac7b5
MC		 11273static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11274{
11275 struct bnx2x *bp = netdev_priv(dev);
11276 int rc = 0;
11277
11278 switch (ctl->cmd) {
11279 case DRV_CTL_CTXTBL_WR_CMD: {
11280 u32 index = ctl->data.io.offset;
11281 dma_addr_t addr = ctl->data.io.dma_addr;
11282
11283 bnx2x_ilt_wr(bp, index, addr);
11284 break;
11285 }
11286
c2bff63f
DK		 11287 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11288 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 11289
11290 bnx2x_cnic_sp_post(bp, count);
11291 break;
11292 }
11293
11294 /* rtnl_lock is held. */
11295 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 11296 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11297 unsigned long sp_bits = 0;
11298
11299 /* Configure the iSCSI classification object */
11300 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11301 cp->iscsi_l2_client_id,
11302 cp->iscsi_l2_cid, BP_FUNC(bp),
11303 bnx2x_sp(bp, mac_rdata),
11304 bnx2x_sp_mapping(bp, mac_rdata),
11305 BNX2X_FILTER_MAC_PENDING,
11306 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11307 &bp->macs_pool);
ec6ba945 11308
523224a3 11309 /* Set iSCSI MAC address */
619c5cb6
VZ		 11310 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11311 if (rc)
11312 break;
523224a3
DK		 11313
11314 mmiowb();
11315 barrier();
11316
619c5cb6
VZ		 11317 /* Start accepting on iSCSI L2 ring */
11318
11319 netif_addr_lock_bh(dev);
11320 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11321 netif_addr_unlock_bh(dev);
11322
11323 /* bits to wait on */
11324 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11325 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11326
11327 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11328 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 11329
993ac7b5
MC		 11330 break;
11331 }
11332
11333 /* rtnl_lock is held. */
11334 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 11335 unsigned long sp_bits = 0;
993ac7b5 11336
523224a3 11337 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 11338 netif_addr_lock_bh(dev);
11339 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11340 netif_addr_unlock_bh(dev);
11341
11342 /* bits to wait on */
11343 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11344 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11345
11346 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11347 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 11348
11349 mmiowb();
11350 barrier();
11351
11352 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 11353 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11354 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 11355 break;
11356 }
c2bff63f
DK		 11357 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11358 int count = ctl->data.credit.credit_count;
11359
11360 smp_mb__before_atomic_inc();
6e30dd4e 11361 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 11362 smp_mb__after_atomic_inc();
11363 break;
11364 }
993ac7b5
MC		 11365
11366 default:
11367 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11368 rc = -EINVAL;
11369 }
11370
11371 return rc;
11372}
11373
9f6c9258 11374void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 11375{
11376 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11377
11378 if (bp->flags & USING_MSIX_FLAG) {
11379 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11380 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11381 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11382 } else {
11383 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11384 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11385 }
619c5cb6 11386 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 11387 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11388 else
11389 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11390
619c5cb6
VZ		 11391 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11392 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 11393 cp->irq_arr[1].status_blk = bp->def_status_blk;
11394 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 11395 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 11396
11397 cp->num_irq = 2;
11398}
11399
11400static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11401 void *data)
11402{
11403 struct bnx2x *bp = netdev_priv(dev);
11404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11405
11406 if (ops == NULL)
11407 return -EINVAL;
11408
993ac7b5
MC		 11409 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11410 if (!bp->cnic_kwq)
11411 return -ENOMEM;
11412
11413 bp->cnic_kwq_cons = bp->cnic_kwq;
11414 bp->cnic_kwq_prod = bp->cnic_kwq;
11415 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11416
11417 bp->cnic_spq_pending = 0;
11418 bp->cnic_kwq_pending = 0;
11419
11420 bp->cnic_data = data;
11421
11422 cp->num_irq = 0;
619c5cb6 11423 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 11424 cp->iro_arr = bp->iro_arr;
993ac7b5 11425
993ac7b5 11426 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 11427
993ac7b5
MC		 11428 rcu_assign_pointer(bp->cnic_ops, ops);
11429
11430 return 0;
11431}
11432
11433static int bnx2x_unregister_cnic(struct net_device *dev)
11434{
11435 struct bnx2x *bp = netdev_priv(dev);
11436 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11437
11438 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 11439 cp->drv_state = 0;
11440 rcu_assign_pointer(bp->cnic_ops, NULL);
11441 mutex_unlock(&bp->cnic_mutex);
11442 synchronize_rcu();
11443 kfree(bp->cnic_kwq);
11444 bp->cnic_kwq = NULL;
11445
11446 return 0;
11447}
11448
11449struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11450{
11451 struct bnx2x *bp = netdev_priv(dev);
11452 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11453
2ba45142
VZ		 11454 /* If both iSCSI and FCoE are disabled - return NULL in
11455 * order to indicate CNIC that it should not try to work
11456 * with this device.
11457 */
11458 if (NO_ISCSI(bp) && NO_FCOE(bp))
11459 return NULL;
11460
993ac7b5
MC		 11461 cp->drv_owner = THIS_MODULE;
11462 cp->chip_id = CHIP_ID(bp);
11463 cp->pdev = bp->pdev;
11464 cp->io_base = bp->regview;
11465 cp->io_base2 = bp->doorbells;
11466 cp->max_kwqe_pending = 8;
523224a3 11467 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 11468 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11469 bnx2x_cid_ilt_lines(bp);
993ac7b5 11470 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 11471 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 11472 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11473 cp->drv_ctl = bnx2x_drv_ctl;
11474 cp->drv_register_cnic = bnx2x_register_cnic;
11475 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 11476 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 11477 cp->iscsi_l2_client_id =
11478 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 11479 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11480
2ba45142
VZ		 11481 if (NO_ISCSI_OOO(bp))
11482 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11483
11484 if (NO_ISCSI(bp))
11485 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11486
11487 if (NO_FCOE(bp))
11488 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11489
c2bff63f
DK		 11490 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11491 "starting cid %d\n",
11492 cp->ctx_blk_size,
11493 cp->ctx_tbl_offset,
11494 cp->ctx_tbl_len,
11495 cp->starting_cid);
993ac7b5
MC		 11496 return cp;
11497}
11498EXPORT_SYMBOL(bnx2x_cnic_probe);
11499
11500#endif /* BCM_CNIC */
94a78b79 11501
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