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ipv4: Consolidate all default route selection implementations.
[thirdparty/linux.git] / drivers / net / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
3359fced 3 * Copyright (c) 2007-2010 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
a2fbb9ea
ET		 18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
a2fbb9ea
ET		 26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <linux/bitops.h>
34#include <linux/irq.h>
35#include <linux/delay.h>
36#include <asm/byteorder.h>
37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
0c6671b0 40#include <linux/if_vlan.h>
a2fbb9ea
ET		 41#include <net/ip.h>
42#include <net/tcp.h>
43#include <net/checksum.h>
34f80b04 44#include <net/ip6_checksum.h>
a2fbb9ea
ET		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
34f80b04 47#include <linux/crc32c.h>
a2fbb9ea
ET		 48#include <linux/prefetch.h>
49#include <linux/zlib.h>
a2fbb9ea 50#include <linux/io.h>
45229b42 51#include <linux/stringify.h>
a2fbb9ea 52
b0efbb99 53#define BNX2X_MAIN
a2fbb9ea
ET		 54#include "bnx2x.h"
55#include "bnx2x_init.h"
94a78b79 56#include "bnx2x_init_ops.h"
9f6c9258 57#include "bnx2x_cmn.h"
e4901dde 58#include "bnx2x_dcb.h"
a2fbb9ea 59
94a78b79
VZ		 60#include <linux/firmware.h>
61#include "bnx2x_fw_file_hdr.h"
62/* FW files */
45229b42
BH		 63#define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 68#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 70#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 71
34f80b04
EG		 72/* Time in jiffies before concluding the transmitter is hung */
73#define TX_TIMEOUT (5*HZ)
a2fbb9ea 74
53a10565 75static char version[] __devinitdata =
34f80b04 76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
a2fbb9ea
ET		 77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78
24e3fcef 79MODULE_AUTHOR("Eliezer Tamir");
f2e0899f
DK		 80MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
a2fbb9ea
ET		 82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 84MODULE_FIRMWARE(FW_FILE_NAME_E1);
85MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 86MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 87
555f6c78
EG		 88static int multi_mode = 1;
89module_param(multi_mode, int, 0);
ca00392c
EG		 90MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
92
d6214d7a 93int num_queues;
54b9ddaa
VZ		 94module_param(num_queues, int, 0);
95MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
555f6c78 97
19680c48 98static int disable_tpa;
19680c48 99module_param(disable_tpa, int, 0);
9898f86d 100MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a
EG		 101
102static int int_mode;
103module_param(int_mode, int, 0);
cdaa7cb8
VZ		 104MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
105 "(1 INT#x; 2 MSI)");
8badd27a 106
a18f5128
EG		 107static int dropless_fc;
108module_param(dropless_fc, int, 0);
109MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
9898f86d 111static int poll;
a2fbb9ea 112module_param(poll, int, 0);
9898f86d 113MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 114
115static int mrrs = -1;
116module_param(mrrs, int, 0);
117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
a2fbb9ea 120module_param(debug, int, 0);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
1cf167f2 123static struct workqueue_struct *bnx2x_wq;
a2fbb9ea 124
ec6ba945
VZ		 125#ifdef BCM_CNIC
126static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
127#endif
128
a2fbb9ea
ET		 129enum bnx2x_board_type {
130 BCM57710 = 0,
34f80b04
EG		 131 BCM57711 = 1,
132 BCM57711E = 2,
f2e0899f
DK		 133 BCM57712 = 3,
134 BCM57712E = 4
a2fbb9ea
ET		 135};
136
34f80b04 137/* indexed by board_type, above */
53a10565 138static struct {
a2fbb9ea
ET		 139 char *name;
140} board_info[] __devinitdata = {
34f80b04
EG		 141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
f2e0899f
DK		 143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
a2fbb9ea
ET		 146};
147
f2e0899f
DK		 148#ifndef PCI_DEVICE_ID_NX2_57712
149#define PCI_DEVICE_ID_NX2_57712 0x1662
150#endif
151#ifndef PCI_DEVICE_ID_NX2_57712E
152#define PCI_DEVICE_ID_NX2_57712E 0x1663
153#endif
34f80b04 154
a3aa1884 155static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 156 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
157 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
158 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f
DK		 159 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
160 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
a2fbb9ea
ET		 161 { 0 }
162};
163
164MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
165
166/****************************************************************************
167* General service functions
168****************************************************************************/
169
523224a3
DK		 170static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
171 u32 addr, dma_addr_t mapping)
172{
173 REG_WR(bp, addr, U64_LO(mapping));
174 REG_WR(bp, addr + 4, U64_HI(mapping));
175}
176
177static inline void __storm_memset_fill(struct bnx2x *bp,
178 u32 addr, size_t size, u32 val)
179{
180 int i;
181 for (i = 0; i < size/4; i++)
182 REG_WR(bp, addr + (i * 4), val);
183}
184
185static inline void storm_memset_ustats_zero(struct bnx2x *bp,
186 u8 port, u16 stat_id)
187{
188 size_t size = sizeof(struct ustorm_per_client_stats);
189
190 u32 addr = BAR_USTRORM_INTMEM +
191 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
192
193 __storm_memset_fill(bp, addr, size, 0);
194}
195
196static inline void storm_memset_tstats_zero(struct bnx2x *bp,
197 u8 port, u16 stat_id)
198{
199 size_t size = sizeof(struct tstorm_per_client_stats);
200
201 u32 addr = BAR_TSTRORM_INTMEM +
202 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
203
204 __storm_memset_fill(bp, addr, size, 0);
205}
206
207static inline void storm_memset_xstats_zero(struct bnx2x *bp,
208 u8 port, u16 stat_id)
209{
210 size_t size = sizeof(struct xstorm_per_client_stats);
211
212 u32 addr = BAR_XSTRORM_INTMEM +
213 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
214
215 __storm_memset_fill(bp, addr, size, 0);
216}
217
218
219static inline void storm_memset_spq_addr(struct bnx2x *bp,
220 dma_addr_t mapping, u16 abs_fid)
221{
222 u32 addr = XSEM_REG_FAST_MEMORY +
223 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
224
225 __storm_memset_dma_mapping(bp, addr, mapping);
226}
227
228static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
229{
230 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
231}
232
233static inline void storm_memset_func_cfg(struct bnx2x *bp,
234 struct tstorm_eth_function_common_config *tcfg,
235 u16 abs_fid)
236{
237 size_t size = sizeof(struct tstorm_eth_function_common_config);
238
239 u32 addr = BAR_TSTRORM_INTMEM +
240 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
241
242 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
243}
244
245static inline void storm_memset_xstats_flags(struct bnx2x *bp,
246 struct stats_indication_flags *flags,
247 u16 abs_fid)
248{
249 size_t size = sizeof(struct stats_indication_flags);
250
251 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
252
253 __storm_memset_struct(bp, addr, size, (u32 *)flags);
254}
255
256static inline void storm_memset_tstats_flags(struct bnx2x *bp,
257 struct stats_indication_flags *flags,
258 u16 abs_fid)
259{
260 size_t size = sizeof(struct stats_indication_flags);
261
262 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
263
264 __storm_memset_struct(bp, addr, size, (u32 *)flags);
265}
266
267static inline void storm_memset_ustats_flags(struct bnx2x *bp,
268 struct stats_indication_flags *flags,
269 u16 abs_fid)
270{
271 size_t size = sizeof(struct stats_indication_flags);
272
273 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
274
275 __storm_memset_struct(bp, addr, size, (u32 *)flags);
276}
277
278static inline void storm_memset_cstats_flags(struct bnx2x *bp,
279 struct stats_indication_flags *flags,
280 u16 abs_fid)
281{
282 size_t size = sizeof(struct stats_indication_flags);
283
284 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
285
286 __storm_memset_struct(bp, addr, size, (u32 *)flags);
287}
288
289static inline void storm_memset_xstats_addr(struct bnx2x *bp,
290 dma_addr_t mapping, u16 abs_fid)
291{
292 u32 addr = BAR_XSTRORM_INTMEM +
293 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
294
295 __storm_memset_dma_mapping(bp, addr, mapping);
296}
297
298static inline void storm_memset_tstats_addr(struct bnx2x *bp,
299 dma_addr_t mapping, u16 abs_fid)
300{
301 u32 addr = BAR_TSTRORM_INTMEM +
302 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
303
304 __storm_memset_dma_mapping(bp, addr, mapping);
305}
306
307static inline void storm_memset_ustats_addr(struct bnx2x *bp,
308 dma_addr_t mapping, u16 abs_fid)
309{
310 u32 addr = BAR_USTRORM_INTMEM +
311 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
312
313 __storm_memset_dma_mapping(bp, addr, mapping);
314}
315
316static inline void storm_memset_cstats_addr(struct bnx2x *bp,
317 dma_addr_t mapping, u16 abs_fid)
318{
319 u32 addr = BAR_CSTRORM_INTMEM +
320 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
321
322 __storm_memset_dma_mapping(bp, addr, mapping);
323}
324
325static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
326 u16 pf_id)
327{
328 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
329 pf_id);
330 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
331 pf_id);
332 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
333 pf_id);
334 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
335 pf_id);
336}
337
338static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
339 u8 enable)
340{
341 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
342 enable);
343 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
344 enable);
345 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
346 enable);
347 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
348 enable);
349}
350
351static inline void storm_memset_eq_data(struct bnx2x *bp,
352 struct event_ring_data *eq_data,
353 u16 pfid)
354{
355 size_t size = sizeof(struct event_ring_data);
356
357 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
358
359 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
360}
361
362static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
363 u16 pfid)
364{
365 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
366 REG_WR16(bp, addr, eq_prod);
367}
368
369static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
370 u16 fw_sb_id, u8 sb_index,
371 u8 ticks)
372{
373
f2e0899f
DK		 374 int index_offset = CHIP_IS_E2(bp) ?
375 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 376 offsetof(struct hc_status_block_data_e1x, index_data);
377 u32 addr = BAR_CSTRORM_INTMEM +
378 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
379 index_offset +
380 sizeof(struct hc_index_data)*sb_index +
381 offsetof(struct hc_index_data, timeout);
382 REG_WR8(bp, addr, ticks);
383 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
384 port, fw_sb_id, sb_index, ticks);
385}
386static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
387 u16 fw_sb_id, u8 sb_index,
388 u8 disable)
389{
390 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
f2e0899f
DK		 391 int index_offset = CHIP_IS_E2(bp) ?
392 offsetof(struct hc_status_block_data_e2, index_data) :
523224a3
DK		 393 offsetof(struct hc_status_block_data_e1x, index_data);
394 u32 addr = BAR_CSTRORM_INTMEM +
395 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
396 index_offset +
397 sizeof(struct hc_index_data)*sb_index +
398 offsetof(struct hc_index_data, flags);
399 u16 flags = REG_RD16(bp, addr);
400 /* clear and set */
401 flags &= ~HC_INDEX_DATA_HC_ENABLED;
402 flags |= enable_flag;
403 REG_WR16(bp, addr, flags);
404 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
405 port, fw_sb_id, sb_index, disable);
406}
407
a2fbb9ea
ET		 408/* used only at init
409 * locking is done by mcp
410 */
8d96286a 411static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 412{
413 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
414 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
415 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
416 PCICFG_VENDOR_ID_OFFSET);
417}
418
a2fbb9ea
ET		 419static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
420{
421 u32 val;
422
423 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
424 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
425 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
426 PCICFG_VENDOR_ID_OFFSET);
427
428 return val;
429}
a2fbb9ea 430
f2e0899f
DK		 431#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
432#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
433#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
434#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
435#define DMAE_DP_DST_NONE "dst_addr [none]"
436
8d96286a 437static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
438 int msglvl)
f2e0899f
DK		 439{
440 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
441
442 switch (dmae->opcode & DMAE_COMMAND_DST) {
443 case DMAE_CMD_DST_PCI:
444 if (src_type == DMAE_CMD_SRC_PCI)
445 DP(msglvl, "DMAE: opcode 0x%08x\n"
446 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
447 "comp_addr [%x:%08x], comp_val 0x%08x\n",
448 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
449 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
450 dmae->comp_addr_hi, dmae->comp_addr_lo,
451 dmae->comp_val);
452 else
453 DP(msglvl, "DMAE: opcode 0x%08x\n"
454 "src [%08x], len [%d*4], dst [%x:%08x]\n"
455 "comp_addr [%x:%08x], comp_val 0x%08x\n",
456 dmae->opcode, dmae->src_addr_lo >> 2,
457 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
458 dmae->comp_addr_hi, dmae->comp_addr_lo,
459 dmae->comp_val);
460 break;
461 case DMAE_CMD_DST_GRC:
462 if (src_type == DMAE_CMD_SRC_PCI)
463 DP(msglvl, "DMAE: opcode 0x%08x\n"
464 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
465 "comp_addr [%x:%08x], comp_val 0x%08x\n",
466 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
467 dmae->len, dmae->dst_addr_lo >> 2,
468 dmae->comp_addr_hi, dmae->comp_addr_lo,
469 dmae->comp_val);
470 else
471 DP(msglvl, "DMAE: opcode 0x%08x\n"
472 "src [%08x], len [%d*4], dst [%08x]\n"
473 "comp_addr [%x:%08x], comp_val 0x%08x\n",
474 dmae->opcode, dmae->src_addr_lo >> 2,
475 dmae->len, dmae->dst_addr_lo >> 2,
476 dmae->comp_addr_hi, dmae->comp_addr_lo,
477 dmae->comp_val);
478 break;
479 default:
480 if (src_type == DMAE_CMD_SRC_PCI)
481 DP(msglvl, "DMAE: opcode 0x%08x\n"
482 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
483 "dst_addr [none]\n"
484 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
485 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
486 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
487 dmae->comp_val);
488 else
489 DP(msglvl, "DMAE: opcode 0x%08x\n"
490 DP_LEVEL "src_addr [%08x] len [%d * 4] "
491 "dst_addr [none]\n"
492 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
493 dmae->opcode, dmae->src_addr_lo >> 2,
494 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
495 dmae->comp_val);
496 break;
497 }
498
499}
500
6c719d00 501const u32 dmae_reg_go_c[] = {
a2fbb9ea
ET		 502 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
503 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
504 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
505 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
506};
507
508/* copy command into DMAE command memory and set DMAE command go */
6c719d00 509void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 510{
511 u32 cmd_offset;
512 int i;
513
514 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
515 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
516 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
517
ad8d3948
EG		 518 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
519 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 520 }
521 REG_WR(bp, dmae_reg_go_c[idx], 1);
522}
523
f2e0899f 524u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 525{
f2e0899f
DK		 526 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
527 DMAE_CMD_C_ENABLE);
528}
ad8d3948 529
f2e0899f
DK		 530u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
531{
532 return opcode & ~DMAE_CMD_SRC_RESET;
533}
ad8d3948 534
f2e0899f
DK		 535u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
536 bool with_comp, u8 comp_type)
537{
538 u32 opcode = 0;
539
540 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
541 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 542
f2e0899f
DK		 543 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
544
545 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
546 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
547 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
548 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 549
a2fbb9ea 550#ifdef __BIG_ENDIAN
f2e0899f 551 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 552#else
f2e0899f 553 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 554#endif
f2e0899f
DK		 555 if (with_comp)
556 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
557 return opcode;
558}
559
8d96286a 560static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
561 struct dmae_command *dmae,
562 u8 src_type, u8 dst_type)
f2e0899f
DK		 563{
564 memset(dmae, 0, sizeof(struct dmae_command));
565
566 /* set the opcode */
567 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
568 true, DMAE_COMP_PCI);
569
570 /* fill in the completion parameters */
571 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
572 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
573 dmae->comp_val = DMAE_COMP_VAL;
574}
575
576/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 577static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
578 struct dmae_command *dmae)
f2e0899f
DK		 579{
580 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
581 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
582 int rc = 0;
583
584 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 585 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
586 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 587
f2e0899f 588 /* lock the dmae channel */
5ff7b6d4
EG		 589 mutex_lock(&bp->dmae_mutex);
590
f2e0899f 591 /* reset completion */
a2fbb9ea
ET		 592 *wb_comp = 0;
593
f2e0899f
DK		 594 /* post the command on the channel used for initializations */
595 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 596
f2e0899f 597 /* wait for completion */
a2fbb9ea 598 udelay(5);
f2e0899f 599 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 600 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
601
ad8d3948 602 if (!cnt) {
c3eefaf6 603 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 604 rc = DMAE_TIMEOUT;
605 goto unlock;
a2fbb9ea 606 }
ad8d3948 607 cnt--;
f2e0899f 608 udelay(50);
a2fbb9ea 609 }
f2e0899f
DK		 610 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
611 BNX2X_ERR("DMAE PCI error!\n");
612 rc = DMAE_PCI_ERROR;
613 }
614
615 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
616 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
617 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 618
f2e0899f 619unlock:
ad8d3948 620 mutex_unlock(&bp->dmae_mutex);
f2e0899f
DK		 621 return rc;
622}
623
624void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
625 u32 len32)
626{
627 struct dmae_command dmae;
628
629 if (!bp->dmae_ready) {
630 u32 *data = bnx2x_sp(bp, wb_data[0]);
631
632 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
633 " using indirect\n", dst_addr, len32);
634 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
635 return;
636 }
637
638 /* set opcode and fixed command fields */
639 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
640
641 /* fill in addresses and len */
642 dmae.src_addr_lo = U64_LO(dma_addr);
643 dmae.src_addr_hi = U64_HI(dma_addr);
644 dmae.dst_addr_lo = dst_addr >> 2;
645 dmae.dst_addr_hi = 0;
646 dmae.len = len32;
647
648 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
649
650 /* issue the command and wait for completion */
651 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 652}
653
c18487ee 654void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 655{
5ff7b6d4 656 struct dmae_command dmae;
ad8d3948
EG		 657
658 if (!bp->dmae_ready) {
659 u32 *data = bnx2x_sp(bp, wb_data[0]);
660 int i;
661
662 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
663 " using indirect\n", src_addr, len32);
664 for (i = 0; i < len32; i++)
665 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
666 return;
667 }
668
f2e0899f
DK		 669 /* set opcode and fixed command fields */
670 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 671
f2e0899f 672 /* fill in addresses and len */
5ff7b6d4
EG		 673 dmae.src_addr_lo = src_addr >> 2;
674 dmae.src_addr_hi = 0;
675 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
676 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
677 dmae.len = len32;
ad8d3948 678
f2e0899f 679 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 680
f2e0899f
DK		 681 /* issue the command and wait for completion */
682 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 683}
684
8d96286a 685static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
686 u32 addr, u32 len)
573f2035 687{
02e3c6cb 688 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 689 int offset = 0;
690
02e3c6cb 691 while (len > dmae_wr_max) {
573f2035 692 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 693 addr + offset, dmae_wr_max);
694 offset += dmae_wr_max * 4;
695 len -= dmae_wr_max;
573f2035
EG		 696 }
697
698 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
699}
700
ad8d3948
EG		 701/* used only for slowpath so not inlined */
702static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
703{
704 u32 wb_write[2];
705
706 wb_write[0] = val_hi;
707 wb_write[1] = val_lo;
708 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 709}
a2fbb9ea 710
ad8d3948
EG		 711#ifdef USE_WB_RD
712static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
713{
714 u32 wb_data[2];
715
716 REG_RD_DMAE(bp, reg, wb_data, 2);
717
718 return HILO_U64(wb_data[0], wb_data[1]);
719}
720#endif
721
a2fbb9ea
ET		 722static int bnx2x_mc_assert(struct bnx2x *bp)
723{
a2fbb9ea 724 char last_idx;
34f80b04
EG		 725 int i, rc = 0;
726 u32 row0, row1, row2, row3;
727
728 /* XSTORM */
729 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
730 XSTORM_ASSERT_LIST_INDEX_OFFSET);
731 if (last_idx)
732 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
733
734 /* print the asserts */
735 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
736
737 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
738 XSTORM_ASSERT_LIST_OFFSET(i));
739 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
740 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
741 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
742 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
743 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
744 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
745
746 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
747 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
748 " 0x%08x 0x%08x 0x%08x\n",
749 i, row3, row2, row1, row0);
750 rc++;
751 } else {
752 break;
753 }
754 }
755
756 /* TSTORM */
757 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
758 TSTORM_ASSERT_LIST_INDEX_OFFSET);
759 if (last_idx)
760 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
761
762 /* print the asserts */
763 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
764
765 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
766 TSTORM_ASSERT_LIST_OFFSET(i));
767 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
768 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
769 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
770 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
771 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
772 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
773
774 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
775 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
776 " 0x%08x 0x%08x 0x%08x\n",
777 i, row3, row2, row1, row0);
778 rc++;
779 } else {
780 break;
781 }
782 }
783
784 /* CSTORM */
785 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
786 CSTORM_ASSERT_LIST_INDEX_OFFSET);
787 if (last_idx)
788 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
789
790 /* print the asserts */
791 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
792
793 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
794 CSTORM_ASSERT_LIST_OFFSET(i));
795 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
796 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
797 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
799 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
800 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
801
802 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
803 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
804 " 0x%08x 0x%08x 0x%08x\n",
805 i, row3, row2, row1, row0);
806 rc++;
807 } else {
808 break;
809 }
810 }
811
812 /* USTORM */
813 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
814 USTORM_ASSERT_LIST_INDEX_OFFSET);
815 if (last_idx)
816 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
817
818 /* print the asserts */
819 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
820
821 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
822 USTORM_ASSERT_LIST_OFFSET(i));
823 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
824 USTORM_ASSERT_LIST_OFFSET(i) + 4);
825 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
826 USTORM_ASSERT_LIST_OFFSET(i) + 8);
827 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
828 USTORM_ASSERT_LIST_OFFSET(i) + 12);
829
830 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
831 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
832 " 0x%08x 0x%08x 0x%08x\n",
833 i, row3, row2, row1, row0);
834 rc++;
835 } else {
836 break;
a2fbb9ea
ET		 837 }
838 }
34f80b04 839
a2fbb9ea
ET		 840 return rc;
841}
c14423fe 842
a2fbb9ea
ET		 843static void bnx2x_fw_dump(struct bnx2x *bp)
844{
cdaa7cb8 845 u32 addr;
a2fbb9ea 846 u32 mark, offset;
4781bfad 847 __be32 data[9];
a2fbb9ea 848 int word;
f2e0899f 849 u32 trace_shmem_base;
2145a920
VZ		 850 if (BP_NOMCP(bp)) {
851 BNX2X_ERR("NO MCP - can not dump\n");
852 return;
853 }
cdaa7cb8 854
f2e0899f
DK		 855 if (BP_PATH(bp) == 0)
856 trace_shmem_base = bp->common.shmem_base;
857 else
858 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
859 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 860 mark = REG_RD(bp, addr);
f2e0899f
DK		 861 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
862 + ((mark + 0x3) & ~0x3) - 0x08000000;
7995c64e 863 pr_err("begin fw dump (mark 0x%x)\n", mark);
a2fbb9ea 864
7995c64e 865 pr_err("");
f2e0899f 866 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 867 for (word = 0; word < 8; word++)
cdaa7cb8 868 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 869 data[8] = 0x0;
7995c64e 870 pr_cont("%s", (char *)data);
a2fbb9ea 871 }
cdaa7cb8 872 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 873 for (word = 0; word < 8; word++)
cdaa7cb8 874 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 875 data[8] = 0x0;
7995c64e 876 pr_cont("%s", (char *)data);
a2fbb9ea 877 }
7995c64e 878 pr_err("end of fw dump\n");
a2fbb9ea
ET		 879}
880
6c719d00 881void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 882{
883 int i;
523224a3
DK		 884 u16 j;
885 struct hc_sp_status_block_data sp_sb_data;
886 int func = BP_FUNC(bp);
887#ifdef BNX2X_STOP_ON_ERROR
888 u16 start = 0, end = 0;
889#endif
a2fbb9ea 890
66e855f3
YG		 891 bp->stats_state = STATS_STATE_DISABLED;
892 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
893
a2fbb9ea
ET		 894 BNX2X_ERR("begin crash dump -----------------\n");
895
8440d2b6
EG		 896 /* Indices */
897 /* Common */
523224a3 898 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
cdaa7cb8 899 " spq_prod_idx(0x%x)\n",
523224a3
DK		 900 bp->def_idx, bp->def_att_idx,
901 bp->attn_state, bp->spq_prod_idx);
902 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
903 bp->def_status_blk->atten_status_block.attn_bits,
904 bp->def_status_blk->atten_status_block.attn_bits_ack,
905 bp->def_status_blk->atten_status_block.status_block_id,
906 bp->def_status_blk->atten_status_block.attn_bits_index);
907 BNX2X_ERR(" def (");
908 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
909 pr_cont("0x%x%s",
910 bp->def_status_blk->sp_sb.index_values[i],
911 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
912
913 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
914 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
915 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
916 i*sizeof(u32));
917
918 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
919 "pf_id(0x%x) vnic_id(0x%x) "
920 "vf_id(0x%x) vf_valid (0x%x)\n",
921 sp_sb_data.igu_sb_id,
922 sp_sb_data.igu_seg_id,
923 sp_sb_data.p_func.pf_id,
924 sp_sb_data.p_func.vnic_id,
925 sp_sb_data.p_func.vf_id,
926 sp_sb_data.p_func.vf_valid);
927
8440d2b6 928
ec6ba945 929 for_each_eth_queue(bp, i) {
a2fbb9ea 930 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 931 int loop;
f2e0899f 932 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 933 struct hc_status_block_data_e1x sb_data_e1x;
934 struct hc_status_block_sm *hc_sm_p =
f2e0899f
DK		 935 CHIP_IS_E2(bp) ?
936 sb_data_e2.common.state_machine :
523224a3
DK		 937 sb_data_e1x.common.state_machine;
938 struct hc_index_data *hc_index_p =
f2e0899f
DK		 939 CHIP_IS_E2(bp) ?
940 sb_data_e2.index_data :
523224a3
DK		 941 sb_data_e1x.index_data;
942 int data_size;
943 u32 *sb_data_p;
944
945 /* Rx */
cdaa7cb8 946 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 947 " rx_comp_prod(0x%x)"
cdaa7cb8 948 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 949 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 950 fp->rx_comp_prod,
66e855f3 951 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 952 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 953 " fp_hc_idx(0x%x)\n",
8440d2b6 954 fp->rx_sge_prod, fp->last_max_sge,
523224a3 955 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 956
523224a3 957 /* Tx */
cdaa7cb8
VZ		 958 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
959 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
960 " *tx_cons_sb(0x%x)\n",
8440d2b6
EG		 961 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
962 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
523224a3 963
f2e0899f
DK		 964 loop = CHIP_IS_E2(bp) ?
965 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
523224a3
DK		 966
967 /* host sb data */
968
ec6ba945
VZ		 969#ifdef BCM_CNIC
970 if (IS_FCOE_FP(fp))
971 continue;
972#endif
523224a3
DK		 973 BNX2X_ERR(" run indexes (");
974 for (j = 0; j < HC_SB_MAX_SM; j++)
975 pr_cont("0x%x%s",
976 fp->sb_running_index[j],
977 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
978
979 BNX2X_ERR(" indexes (");
980 for (j = 0; j < loop; j++)
981 pr_cont("0x%x%s",
982 fp->sb_index_values[j],
983 (j == loop - 1) ? ")" : " ");
984 /* fw sb data */
f2e0899f
DK		 985 data_size = CHIP_IS_E2(bp) ?
986 sizeof(struct hc_status_block_data_e2) :
523224a3
DK		 987 sizeof(struct hc_status_block_data_e1x);
988 data_size /= sizeof(u32);
f2e0899f
DK		 989 sb_data_p = CHIP_IS_E2(bp) ?
990 (u32 *)&sb_data_e2 :
991 (u32 *)&sb_data_e1x;
523224a3
DK		 992 /* copy sb data in here */
993 for (j = 0; j < data_size; j++)
994 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
995 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
996 j * sizeof(u32));
997
f2e0899f
DK		 998 if (CHIP_IS_E2(bp)) {
999 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1000 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1001 sb_data_e2.common.p_func.pf_id,
1002 sb_data_e2.common.p_func.vf_id,
1003 sb_data_e2.common.p_func.vf_valid,
1004 sb_data_e2.common.p_func.vnic_id,
1005 sb_data_e2.common.same_igu_sb_1b);
1006 } else {
1007 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1008 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1009 sb_data_e1x.common.p_func.pf_id,
1010 sb_data_e1x.common.p_func.vf_id,
1011 sb_data_e1x.common.p_func.vf_valid,
1012 sb_data_e1x.common.p_func.vnic_id,
1013 sb_data_e1x.common.same_igu_sb_1b);
1014 }
523224a3
DK		 1015
1016 /* SB_SMs data */
1017 for (j = 0; j < HC_SB_MAX_SM; j++) {
1018 pr_cont("SM[%d] __flags (0x%x) "
1019 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1020 "time_to_expire (0x%x) "
1021 "timer_value(0x%x)\n", j,
1022 hc_sm_p[j].__flags,
1023 hc_sm_p[j].igu_sb_id,
1024 hc_sm_p[j].igu_seg_id,
1025 hc_sm_p[j].time_to_expire,
1026 hc_sm_p[j].timer_value);
1027 }
1028
1029 /* Indecies data */
1030 for (j = 0; j < loop; j++) {
1031 pr_cont("INDEX[%d] flags (0x%x) "
1032 "timeout (0x%x)\n", j,
1033 hc_index_p[j].flags,
1034 hc_index_p[j].timeout);
1035 }
8440d2b6 1036 }
a2fbb9ea 1037
523224a3 1038#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 1039 /* Rings */
1040 /* Rx */
ec6ba945 1041 for_each_rx_queue(bp, i) {
8440d2b6 1042 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1043
1044 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1046 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1047 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1049
c3eefaf6
EG		 1050 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1051 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 1052 }
1053
3196a88a
EG		 1054 start = RX_SGE(fp->rx_sge_prod);
1055 end = RX_SGE(fp->last_max_sge);
8440d2b6 1056 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1057 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1059
c3eefaf6
EG		 1060 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1061 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1062 }
1063
a2fbb9ea
ET		 1064 start = RCQ_BD(fp->rx_comp_cons - 10);
1065 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1066 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1067 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1068
c3eefaf6
EG		 1069 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1071 }
1072 }
1073
8440d2b6 1074 /* Tx */
ec6ba945 1075 for_each_tx_queue(bp, i) {
8440d2b6
EG		 1076 struct bnx2x_fastpath *fp = &bp->fp[i];
1077
1078 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1079 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1080 for (j = start; j != end; j = TX_BD(j + 1)) {
1081 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1082
c3eefaf6
EG		 1083 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1084 i, j, sw_bd->skb, sw_bd->first_bd);
8440d2b6
EG		 1085 }
1086
1087 start = TX_BD(fp->tx_bd_cons - 10);
1088 end = TX_BD(fp->tx_bd_cons + 254);
1089 for (j = start; j != end; j = TX_BD(j + 1)) {
1090 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1091
c3eefaf6
EG		 1092 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1093 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
8440d2b6
EG		 1094 }
1095 }
523224a3 1096#endif
34f80b04 1097 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1098 bnx2x_mc_assert(bp);
1099 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1100}
1101
f2e0899f 1102static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1103{
34f80b04 1104 int port = BP_PORT(bp);
a2fbb9ea
ET		 1105 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1106 u32 val = REG_RD(bp, addr);
1107 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1108 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1109
1110 if (msix) {
8badd27a
EG		 1111 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1112 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1113 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1114 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1115 } else if (msi) {
1116 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1117 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1118 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1119 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1120 } else {
1121 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1122 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1123 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1124 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1125
a0fd065c
DK		 1126 if (!CHIP_IS_E1(bp)) {
1127 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1128 val, port, addr);
615f8fd9 1129
a0fd065c 1130 REG_WR(bp, addr, val);
615f8fd9 1131
a0fd065c
DK		 1132 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1133 }
a2fbb9ea
ET		 1134 }
1135
a0fd065c
DK		 1136 if (CHIP_IS_E1(bp))
1137 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1138
8badd27a
EG		 1139 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1140 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1141
1142 REG_WR(bp, addr, val);
37dbbf32
EG		 1143 /*
1144 * Ensure that HC_CONFIG is written before leading/trailing edge config
1145 */
1146 mmiowb();
1147 barrier();
34f80b04 1148
f2e0899f 1149 if (!CHIP_IS_E1(bp)) {
34f80b04 1150 /* init leading/trailing edge */
fb3bff17 1151 if (IS_MF(bp)) {
8badd27a 1152 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
34f80b04 1153 if (bp->port.pmf)
4acac6a5
EG		 1154 /* enable nig and gpio3 attention */
1155 val |= 0x1100;
34f80b04
EG		 1156 } else
1157 val = 0xffff;
1158
1159 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1160 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1161 }
37dbbf32
EG		 1162
1163 /* Make sure that interrupts are indeed enabled from here on */
1164 mmiowb();
a2fbb9ea
ET		 1165}
1166
f2e0899f
DK		 1167static void bnx2x_igu_int_enable(struct bnx2x *bp)
1168{
1169 u32 val;
1170 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1171 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1172
1173 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1174
1175 if (msix) {
1176 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1177 IGU_PF_CONF_SINGLE_ISR_EN);
1178 val |= (IGU_PF_CONF_FUNC_EN |
1179 IGU_PF_CONF_MSI_MSIX_EN |
1180 IGU_PF_CONF_ATTN_BIT_EN);
1181 } else if (msi) {
1182 val &= ~IGU_PF_CONF_INT_LINE_EN;
1183 val |= (IGU_PF_CONF_FUNC_EN |
1184 IGU_PF_CONF_MSI_MSIX_EN |
1185 IGU_PF_CONF_ATTN_BIT_EN |
1186 IGU_PF_CONF_SINGLE_ISR_EN);
1187 } else {
1188 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1189 val |= (IGU_PF_CONF_FUNC_EN |
1190 IGU_PF_CONF_INT_LINE_EN |
1191 IGU_PF_CONF_ATTN_BIT_EN |
1192 IGU_PF_CONF_SINGLE_ISR_EN);
1193 }
1194
1195 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1196 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1197
1198 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1199
1200 barrier();
1201
1202 /* init leading/trailing edge */
1203 if (IS_MF(bp)) {
1204 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1205 if (bp->port.pmf)
1206 /* enable nig and gpio3 attention */
1207 val |= 0x1100;
1208 } else
1209 val = 0xffff;
1210
1211 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1212 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1213
1214 /* Make sure that interrupts are indeed enabled from here on */
1215 mmiowb();
1216}
1217
1218void bnx2x_int_enable(struct bnx2x *bp)
1219{
1220 if (bp->common.int_block == INT_BLOCK_HC)
1221 bnx2x_hc_int_enable(bp);
1222 else
1223 bnx2x_igu_int_enable(bp);
1224}
1225
1226static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1227{
34f80b04 1228 int port = BP_PORT(bp);
a2fbb9ea
ET		 1229 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1230 u32 val = REG_RD(bp, addr);
1231
a0fd065c
DK		 1232 /*
1233 * in E1 we must use only PCI configuration space to disable
1234 * MSI/MSIX capablility
1235 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1236 */
1237 if (CHIP_IS_E1(bp)) {
1238 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1239 * Use mask register to prevent from HC sending interrupts
1240 * after we exit the function
1241 */
1242 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1243
1244 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1245 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1246 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1247 } else
1248 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1249 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1250 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1251 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1252
1253 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1254 val, port, addr);
1255
8badd27a
EG		 1256 /* flush all outstanding writes */
1257 mmiowb();
1258
a2fbb9ea
ET		 1259 REG_WR(bp, addr, val);
1260 if (REG_RD(bp, addr) != val)
1261 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1262}
1263
f2e0899f
DK		 1264static void bnx2x_igu_int_disable(struct bnx2x *bp)
1265{
1266 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1267
1268 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1269 IGU_PF_CONF_INT_LINE_EN |
1270 IGU_PF_CONF_ATTN_BIT_EN);
1271
1272 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1273
1274 /* flush all outstanding writes */
1275 mmiowb();
1276
1277 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1278 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1279 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1280}
1281
8d96286a 1282static void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1283{
1284 if (bp->common.int_block == INT_BLOCK_HC)
1285 bnx2x_hc_int_disable(bp);
1286 else
1287 bnx2x_igu_int_disable(bp);
1288}
1289
9f6c9258 1290void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1291{
a2fbb9ea 1292 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1293 int i, offset;
a2fbb9ea 1294
34f80b04 1295 /* disable interrupt handling */
a2fbb9ea 1296 atomic_inc(&bp->intr_sem);
e1510706
EG		 1297 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1298
f8ef6e44
YG		 1299 if (disable_hw)
1300 /* prevent the HW from sending interrupts */
1301 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1302
1303 /* make sure all ISRs are done */
1304 if (msix) {
8badd27a
EG		 1305 synchronize_irq(bp->msix_table[0].vector);
1306 offset = 1;
37b091ba
MC		 1307#ifdef BCM_CNIC
1308 offset++;
1309#endif
ec6ba945 1310 for_each_eth_queue(bp, i)
8badd27a 1311 synchronize_irq(bp->msix_table[i + offset].vector);
a2fbb9ea
ET		 1312 } else
1313 synchronize_irq(bp->pdev->irq);
1314
1315 /* make sure sp_task is not running */
1cf167f2
EG		 1316 cancel_delayed_work(&bp->sp_task);
1317 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1318}
1319
34f80b04 1320/* fast path */
a2fbb9ea
ET		 1321
1322/*
34f80b04 1323 * General service functions
a2fbb9ea
ET		 1324 */
1325
72fd0718
VZ		 1326/* Return true if succeeded to acquire the lock */
1327static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1328{
1329 u32 lock_status;
1330 u32 resource_bit = (1 << resource);
1331 int func = BP_FUNC(bp);
1332 u32 hw_lock_control_reg;
1333
1334 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1335
1336 /* Validating that the resource is within range */
1337 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1338 DP(NETIF_MSG_HW,
1339 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1340 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1341 return false;
72fd0718
VZ		 1342 }
1343
1344 if (func <= 5)
1345 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1346 else
1347 hw_lock_control_reg =
1348 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1349
1350 /* Try to acquire the lock */
1351 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1352 lock_status = REG_RD(bp, hw_lock_control_reg);
1353 if (lock_status & resource_bit)
1354 return true;
1355
1356 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1357 return false;
1358}
1359
993ac7b5
MC		 1360#ifdef BCM_CNIC
1361static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1362#endif
3196a88a 1363
9f6c9258 1364void bnx2x_sp_event(struct bnx2x_fastpath *fp,
a2fbb9ea
ET		 1365 union eth_rx_cqe *rr_cqe)
1366{
1367 struct bnx2x *bp = fp->bp;
1368 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1369 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1370
34f80b04 1371 DP(BNX2X_MSG_SP,
a2fbb9ea 1372 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1373 fp->index, cid, command, bp->state,
34f80b04 1374 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1375
523224a3
DK		 1376 switch (command | fp->state) {
1377 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1378 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1379 fp->state = BNX2X_FP_STATE_OPEN;
a2fbb9ea
ET		 1380 break;
1381
523224a3
DK		 1382 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1383 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
a2fbb9ea
ET		 1384 fp->state = BNX2X_FP_STATE_HALTED;
1385 break;
1386
523224a3
DK		 1387 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1388 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1389 fp->state = BNX2X_FP_STATE_TERMINATED;
a2fbb9ea
ET		 1390 break;
1391
523224a3
DK		 1392 default:
1393 BNX2X_ERR("unexpected MC reply (%d) "
1394 "fp[%d] state is %x\n",
1395 command, fp->index, fp->state);
993ac7b5 1396 break;
523224a3 1397 }
3196a88a 1398
8fe23fbd
DK		 1399 smp_mb__before_atomic_inc();
1400 atomic_inc(&bp->spq_left);
523224a3
DK		 1401 /* push the change in fp->state and towards the memory */
1402 smp_wmb();
49d66772 1403
523224a3 1404 return;
a2fbb9ea
ET		 1405}
1406
9f6c9258 1407irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1408{
555f6c78 1409 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1410 u16 status = bnx2x_ack_int(bp);
34f80b04 1411 u16 mask;
ca00392c 1412 int i;
a2fbb9ea 1413
34f80b04 1414 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1415 if (unlikely(status == 0)) {
1416 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1417 return IRQ_NONE;
1418 }
f5372251 1419 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1420
34f80b04 1421 /* Return here if interrupt is disabled */
a2fbb9ea
ET		 1422 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1423 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1424 return IRQ_HANDLED;
1425 }
1426
3196a88a
EG		 1427#ifdef BNX2X_STOP_ON_ERROR
1428 if (unlikely(bp->panic))
1429 return IRQ_HANDLED;
1430#endif
1431
ec6ba945 1432 for_each_eth_queue(bp, i) {
ca00392c 1433 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1434
523224a3 1435 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
ca00392c 1436 if (status & mask) {
54b9ddaa
VZ		 1437 /* Handle Rx and Tx according to SB id */
1438 prefetch(fp->rx_cons_sb);
54b9ddaa 1439 prefetch(fp->tx_cons_sb);
523224a3 1440 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1441 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1442 status &= ~mask;
1443 }
a2fbb9ea
ET		 1444 }
1445
993ac7b5 1446#ifdef BCM_CNIC
523224a3 1447 mask = 0x2;
993ac7b5
MC		 1448 if (status & (mask | 0x1)) {
1449 struct cnic_ops *c_ops = NULL;
1450
1451 rcu_read_lock();
1452 c_ops = rcu_dereference(bp->cnic_ops);
1453 if (c_ops)
1454 c_ops->cnic_handler(bp->cnic_data, NULL);
1455 rcu_read_unlock();
1456
1457 status &= ~mask;
1458 }
1459#endif
a2fbb9ea 1460
34f80b04 1461 if (unlikely(status & 0x1)) {
1cf167f2 1462 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1463
1464 status &= ~0x1;
1465 if (!status)
1466 return IRQ_HANDLED;
1467 }
1468
cdaa7cb8
VZ		 1469 if (unlikely(status))
1470 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1471 status);
a2fbb9ea 1472
c18487ee 1473 return IRQ_HANDLED;
a2fbb9ea
ET		 1474}
1475
c18487ee 1476/* end of fast path */
a2fbb9ea 1477
a2fbb9ea 1478
c18487ee
YR		 1479/* Link */
1480
1481/*
1482 * General service functions
1483 */
a2fbb9ea 1484
9f6c9258 1485int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1486{
1487 u32 lock_status;
1488 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1489 int func = BP_FUNC(bp);
1490 u32 hw_lock_control_reg;
c18487ee 1491 int cnt;
a2fbb9ea 1492
c18487ee
YR		 1493 /* Validating that the resource is within range */
1494 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1495 DP(NETIF_MSG_HW,
1496 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1497 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1498 return -EINVAL;
1499 }
a2fbb9ea 1500
4a37fb66
YG		 1501 if (func <= 5) {
1502 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1503 } else {
1504 hw_lock_control_reg =
1505 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1506 }
1507
c18487ee 1508 /* Validating that the resource is not already taken */
4a37fb66 1509 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1510 if (lock_status & resource_bit) {
1511 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1512 lock_status, resource_bit);
1513 return -EEXIST;
1514 }
a2fbb9ea 1515
46230476
EG		 1516 /* Try for 5 second every 5ms */
1517 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1518 /* Try to acquire the lock */
4a37fb66
YG		 1519 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1520 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1521 if (lock_status & resource_bit)
1522 return 0;
a2fbb9ea 1523
c18487ee 1524 msleep(5);
a2fbb9ea 1525 }
c18487ee
YR		 1526 DP(NETIF_MSG_HW, "Timeout\n");
1527 return -EAGAIN;
1528}
a2fbb9ea 1529
9f6c9258 1530int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1531{
1532 u32 lock_status;
1533 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1534 int func = BP_FUNC(bp);
1535 u32 hw_lock_control_reg;
a2fbb9ea 1536
72fd0718
VZ		 1537 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1538
c18487ee
YR		 1539 /* Validating that the resource is within range */
1540 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1541 DP(NETIF_MSG_HW,
1542 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1543 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1544 return -EINVAL;
1545 }
1546
4a37fb66
YG		 1547 if (func <= 5) {
1548 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1549 } else {
1550 hw_lock_control_reg =
1551 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1552 }
1553
c18487ee 1554 /* Validating that the resource is currently taken */
4a37fb66 1555 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1556 if (!(lock_status & resource_bit)) {
1557 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1558 lock_status, resource_bit);
1559 return -EFAULT;
a2fbb9ea
ET		 1560 }
1561
9f6c9258
DK		 1562 REG_WR(bp, hw_lock_control_reg, resource_bit);
1563 return 0;
c18487ee 1564}
a2fbb9ea 1565
9f6c9258 1566
4acac6a5
EG		 1567int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1568{
1569 /* The GPIO should be swapped if swap register is set and active */
1570 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1571 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1572 int gpio_shift = gpio_num +
1573 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1574 u32 gpio_mask = (1 << gpio_shift);
1575 u32 gpio_reg;
1576 int value;
1577
1578 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1579 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1580 return -EINVAL;
1581 }
1582
1583 /* read GPIO value */
1584 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1585
1586 /* get the requested pin value */
1587 if ((gpio_reg & gpio_mask) == gpio_mask)
1588 value = 1;
1589 else
1590 value = 0;
1591
1592 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1593
1594 return value;
1595}
1596
17de50b7 1597int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1598{
1599 /* The GPIO should be swapped if swap register is set and active */
1600 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1601 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1602 int gpio_shift = gpio_num +
1603 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1604 u32 gpio_mask = (1 << gpio_shift);
1605 u32 gpio_reg;
a2fbb9ea 1606
c18487ee
YR		 1607 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1608 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1609 return -EINVAL;
1610 }
a2fbb9ea 1611
4a37fb66 1612 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1613 /* read GPIO and mask except the float bits */
1614 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1615
c18487ee
YR		 1616 switch (mode) {
1617 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1618 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1619 gpio_num, gpio_shift);
1620 /* clear FLOAT and set CLR */
1621 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1622 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1623 break;
a2fbb9ea 1624
c18487ee
YR		 1625 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1626 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1627 gpio_num, gpio_shift);
1628 /* clear FLOAT and set SET */
1629 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1631 break;
a2fbb9ea 1632
17de50b7 1633 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1634 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1635 gpio_num, gpio_shift);
1636 /* set FLOAT */
1637 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1638 break;
a2fbb9ea 1639
c18487ee
YR		 1640 default:
1641 break;
a2fbb9ea
ET		 1642 }
1643
c18487ee 1644 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1645 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1646
c18487ee 1647 return 0;
a2fbb9ea
ET		 1648}
1649
4acac6a5
EG		 1650int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1651{
1652 /* The GPIO should be swapped if swap register is set and active */
1653 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1654 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1655 int gpio_shift = gpio_num +
1656 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1657 u32 gpio_mask = (1 << gpio_shift);
1658 u32 gpio_reg;
1659
1660 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1661 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1662 return -EINVAL;
1663 }
1664
1665 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1666 /* read GPIO int */
1667 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1668
1669 switch (mode) {
1670 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1671 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1672 "output low\n", gpio_num, gpio_shift);
1673 /* clear SET and set CLR */
1674 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1675 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676 break;
1677
1678 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1679 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1680 "output high\n", gpio_num, gpio_shift);
1681 /* clear CLR and set SET */
1682 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1683 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1684 break;
1685
1686 default:
1687 break;
1688 }
1689
1690 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1691 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1692
1693 return 0;
1694}
1695
c18487ee 1696static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 1697{
c18487ee
YR		 1698 u32 spio_mask = (1 << spio_num);
1699 u32 spio_reg;
a2fbb9ea 1700
c18487ee
YR		 1701 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1702 (spio_num > MISC_REGISTERS_SPIO_7)) {
1703 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1704 return -EINVAL;
a2fbb9ea
ET		 1705 }
1706
4a37fb66 1707 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 1708 /* read SPIO and mask except the float bits */
1709 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 1710
c18487ee 1711 switch (mode) {
6378c025 1712 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1714 /* clear FLOAT and set CLR */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1717 break;
a2fbb9ea 1718
6378c025 1719 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1721 /* clear FLOAT and set SET */
1722 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1724 break;
a2fbb9ea 1725
c18487ee
YR		 1726 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1727 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1728 /* set FLOAT */
1729 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1730 break;
a2fbb9ea 1731
c18487ee
YR		 1732 default:
1733 break;
a2fbb9ea
ET		 1734 }
1735
c18487ee 1736 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 1737 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 1738
a2fbb9ea
ET		 1739 return 0;
1740}
1741
a22f0788
YR		 1742int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1743{
1744 u32 sel_phy_idx = 0;
1745 if (bp->link_vars.link_up) {
1746 sel_phy_idx = EXT_PHY1;
1747 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1748 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1749 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1750 sel_phy_idx = EXT_PHY2;
1751 } else {
1752
1753 switch (bnx2x_phy_selection(&bp->link_params)) {
1754 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1755 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1756 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1757 sel_phy_idx = EXT_PHY1;
1758 break;
1759 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1760 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1761 sel_phy_idx = EXT_PHY2;
1762 break;
1763 }
1764 }
1765 /*
1766 * The selected actived PHY is always after swapping (in case PHY
1767 * swapping is enabled). So when swapping is enabled, we need to reverse
1768 * the configuration
1769 */
1770
1771 if (bp->link_params.multi_phy_config &
1772 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1773 if (sel_phy_idx == EXT_PHY1)
1774 sel_phy_idx = EXT_PHY2;
1775 else if (sel_phy_idx == EXT_PHY2)
1776 sel_phy_idx = EXT_PHY1;
1777 }
1778 return LINK_CONFIG_IDX(sel_phy_idx);
1779}
1780
9f6c9258 1781void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 1782{
a22f0788 1783 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 1784 switch (bp->link_vars.ieee_fc &
1785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 1786 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 1787 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1788 ADVERTISED_Pause);
c18487ee 1789 break;
356e2385 1790
c18487ee 1791 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 1792 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 1793 ADVERTISED_Pause);
c18487ee 1794 break;
356e2385 1795
c18487ee 1796 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 1797 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 1798 break;
356e2385 1799
c18487ee 1800 default:
a22f0788 1801 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 1802 ADVERTISED_Pause);
c18487ee
YR		 1803 break;
1804 }
1805}
f1410647 1806
9f6c9258 1807u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 1808{
19680c48
EG		 1809 if (!BP_NOMCP(bp)) {
1810 u8 rc;
a22f0788
YR		 1811 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1812 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
19680c48 1813 /* Initialize link parameters structure variables */
8c99e7b0
YR		 1814 /* It is recommended to turn off RX FC for jumbo frames
1815 for better performance */
f2e0899f 1816 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
c0700f90 1817 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 1818 else
c0700f90 1819 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 1820
4a37fb66 1821 bnx2x_acquire_phy_lock(bp);
b5bf9068 1822
a22f0788 1823 if (load_mode == LOAD_DIAG) {
de6eae1f 1824 bp->link_params.loopback_mode = LOOPBACK_XGXS;
a22f0788
YR		 1825 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1826 }
b5bf9068 1827
19680c48 1828 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 1829
4a37fb66 1830 bnx2x_release_phy_lock(bp);
a2fbb9ea 1831
3c96c68b
EG		 1832 bnx2x_calc_fc_adv(bp);
1833
b5bf9068
EG		 1834 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1835 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 1836 bnx2x_link_report(bp);
b5bf9068 1837 }
a22f0788 1838 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 1839 return rc;
1840 }
f5372251 1841 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 1842 return -EINVAL;
a2fbb9ea
ET		 1843}
1844
9f6c9258 1845void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 1846{
19680c48 1847 if (!BP_NOMCP(bp)) {
4a37fb66 1848 bnx2x_acquire_phy_lock(bp);
54c2fb78 1849 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 1850 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 1851 bnx2x_release_phy_lock(bp);
a2fbb9ea 1852
19680c48
EG		 1853 bnx2x_calc_fc_adv(bp);
1854 } else
f5372251 1855 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 1856}
a2fbb9ea 1857
c18487ee
YR		 1858static void bnx2x__link_reset(struct bnx2x *bp)
1859{
19680c48 1860 if (!BP_NOMCP(bp)) {
4a37fb66 1861 bnx2x_acquire_phy_lock(bp);
589abe3a 1862 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 1863 bnx2x_release_phy_lock(bp);
19680c48 1864 } else
f5372251 1865 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 1866}
a2fbb9ea 1867
a22f0788 1868u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 1869{
2145a920 1870 u8 rc = 0;
a2fbb9ea 1871
2145a920
VZ		 1872 if (!BP_NOMCP(bp)) {
1873 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 1874 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1875 is_serdes);
2145a920
VZ		 1876 bnx2x_release_phy_lock(bp);
1877 } else
1878 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 1879
c18487ee
YR		 1880 return rc;
1881}
a2fbb9ea 1882
8a1c38d1 1883static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 1884{
8a1c38d1
EG		 1885 u32 r_param = bp->link_vars.line_speed / 8;
1886 u32 fair_periodic_timeout_usec;
1887 u32 t_fair;
34f80b04 1888
8a1c38d1
EG		 1889 memset(&(bp->cmng.rs_vars), 0,
1890 sizeof(struct rate_shaping_vars_per_port));
1891 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 1892
8a1c38d1
EG		 1893 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1894 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 1895
8a1c38d1
EG		 1896 /* this is the threshold below which no timer arming will occur
1897 1.25 coefficient is for the threshold to be a little bigger
1898 than the real time, to compensate for timer in-accuracy */
1899 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 1900 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1901
8a1c38d1
EG		 1902 /* resolution of fairness timer */
1903 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1904 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1905 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 1906
8a1c38d1
EG		 1907 /* this is the threshold below which we won't arm the timer anymore */
1908 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 1909
8a1c38d1
EG		 1910 /* we multiply by 1e3/8 to get bytes/msec.
1911 We don't want the credits to pass a credit
1912 of the t_fair*FAIR_MEM (algorithm resolution) */
1913 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1914 /* since each tick is 4 usec */
1915 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 1916}
1917
2691d51d
EG		 1918/* Calculates the sum of vn_min_rates.
1919 It's needed for further normalizing of the min_rates.
1920 Returns:
1921 sum of vn_min_rates.
1922 or
1923 0 - if all the min_rates are 0.
1924 In the later case fainess algorithm should be deactivated.
1925 If not all min_rates are zero then those that are zeroes will be set to 1.
1926 */
1927static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1928{
1929 int all_zero = 1;
2691d51d
EG		 1930 int vn;
1931
1932 bp->vn_weight_sum = 0;
1933 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
f2e0899f 1934 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 1935 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1936 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1937
1938 /* Skip hidden vns */
1939 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1940 continue;
1941
1942 /* If min rate is zero - set it to 1 */
1943 if (!vn_min_rate)
1944 vn_min_rate = DEF_MIN_RATE;
1945 else
1946 all_zero = 0;
1947
1948 bp->vn_weight_sum += vn_min_rate;
1949 }
1950
1951 /* ... only if all min rates are zeros - disable fairness */
b015e3d1
EG		 1952 if (all_zero) {
1953 bp->cmng.flags.cmng_enables &=
1954 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1955 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1956 " fairness will be disabled\n");
1957 } else
1958 bp->cmng.flags.cmng_enables |=
1959 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 1960}
1961
f2e0899f 1962static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 1963{
1964 struct rate_shaping_vars_per_vn m_rs_vn;
1965 struct fairness_vars_per_vn m_fair_vn;
f2e0899f
DK		 1966 u32 vn_cfg = bp->mf_config[vn];
1967 int func = 2*vn + BP_PORT(bp);
34f80b04
EG		 1968 u16 vn_min_rate, vn_max_rate;
1969 int i;
1970
1971 /* If function is hidden - set min and max to zeroes */
1972 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1973 vn_min_rate = 0;
1974 vn_max_rate = 0;
1975
1976 } else {
1977 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1978 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
b015e3d1 1979 /* If min rate is zero - set it to 1 */
f2e0899f 1980 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04
EG		 1981 vn_min_rate = DEF_MIN_RATE;
1982 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1983 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
1984 }
f85582f8 1985
8a1c38d1 1986 DP(NETIF_MSG_IFUP,
b015e3d1 1987 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 1988 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 1989
1990 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1991 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1992
1993 /* global vn counter - maximal Mbps for this vn */
1994 m_rs_vn.vn_counter.rate = vn_max_rate;
1995
1996 /* quota - number of bytes transmitted in this period */
1997 m_rs_vn.vn_counter.quota =
1998 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
1999
8a1c38d1 2000 if (bp->vn_weight_sum) {
34f80b04
EG		 2001 /* credit for each period of the fairness algorithm:
2002 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2003 vn_weight_sum should not be larger than 10000, thus
2004 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2005 than zero */
34f80b04 2006 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2007 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2008 (8 * bp->vn_weight_sum))),
2009 (bp->cmng.fair_vars.fair_threshold * 2));
2010 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2011 m_fair_vn.vn_credit_delta);
2012 }
2013
34f80b04
EG		 2014 /* Store it to internal memory */
2015 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2016 REG_WR(bp, BAR_XSTRORM_INTMEM +
2017 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2018 ((u32 *)(&m_rs_vn))[i]);
2019
2020 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2021 REG_WR(bp, BAR_XSTRORM_INTMEM +
2022 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2023 ((u32 *)(&m_fair_vn))[i]);
2024}
f85582f8 2025
523224a3
DK		 2026static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2027{
2028 if (CHIP_REV_IS_SLOW(bp))
2029 return CMNG_FNS_NONE;
fb3bff17 2030 if (IS_MF(bp))
523224a3
DK		 2031 return CMNG_FNS_MINMAX;
2032
2033 return CMNG_FNS_NONE;
2034}
2035
2036static void bnx2x_read_mf_cfg(struct bnx2x *bp)
2037{
0793f83f 2038 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2039
2040 if (BP_NOMCP(bp))
2041 return; /* what should be the default bvalue in this case */
2042
0793f83f
DK		 2043 /* For 2 port configuration the absolute function number formula
2044 * is:
2045 * abs_func = 2 * vn + BP_PORT + BP_PATH
2046 *
2047 * and there are 4 functions per port
2048 *
2049 * For 4 port configuration it is
2050 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2051 *
2052 * and there are 2 functions per port
2053 */
523224a3 2054 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
0793f83f
DK		 2055 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2056
2057 if (func >= E1H_FUNC_MAX)
2058 break;
2059
f2e0899f 2060 bp->mf_config[vn] =
523224a3
DK		 2061 MF_CFG_RD(bp, func_mf_config[func].config);
2062 }
2063}
2064
2065static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2066{
2067
2068 if (cmng_type == CMNG_FNS_MINMAX) {
2069 int vn;
2070
2071 /* clear cmng_enables */
2072 bp->cmng.flags.cmng_enables = 0;
2073
2074 /* read mf conf from shmem */
2075 if (read_cfg)
2076 bnx2x_read_mf_cfg(bp);
2077
2078 /* Init rate shaping and fairness contexts */
2079 bnx2x_init_port_minmax(bp);
2080
2081 /* vn_weight_sum and enable fairness if not 0 */
2082 bnx2x_calc_vn_weight_sum(bp);
2083
2084 /* calculate and set min-max rate for each vn */
2085 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2086 bnx2x_init_vn_minmax(bp, vn);
2087
2088 /* always enable rate shaping and fairness */
2089 bp->cmng.flags.cmng_enables |=
2090 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2091 if (!bp->vn_weight_sum)
2092 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2093 " fairness will be disabled\n");
2094 return;
2095 }
2096
2097 /* rate shaping and fairness are disabled */
2098 DP(NETIF_MSG_IFUP,
2099 "rate shaping and fairness are disabled\n");
2100}
34f80b04 2101
523224a3
DK		 2102static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2103{
2104 int port = BP_PORT(bp);
2105 int func;
2106 int vn;
2107
2108 /* Set the attention towards other drivers on the same port */
2109 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2110 if (vn == BP_E1HVN(bp))
2111 continue;
2112
2113 func = ((vn << 1) | port);
2114 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2115 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2116 }
2117}
8a1c38d1 2118
c18487ee
YR		 2119/* This function is called upon link interrupt */
2120static void bnx2x_link_attn(struct bnx2x *bp)
2121{
d9e8b185 2122 u32 prev_link_status = bp->link_vars.link_status;
bb2a0f7a
YG		 2123 /* Make sure that we are synced with the current statistics */
2124 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2125
c18487ee 2126 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2127
bb2a0f7a
YG		 2128 if (bp->link_vars.link_up) {
2129
1c06328c 2130 /* dropless flow control */
f2e0899f 2131 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2132 int port = BP_PORT(bp);
2133 u32 pause_enabled = 0;
2134
2135 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2136 pause_enabled = 1;
2137
2138 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2139 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2140 pause_enabled);
2141 }
2142
bb2a0f7a
YG		 2143 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2144 struct host_port_stats *pstats;
2145
2146 pstats = bnx2x_sp(bp, port_stats);
2147 /* reset old bmac stats */
2148 memset(&(pstats->mac_stx[0]), 0,
2149 sizeof(struct mac_stx));
2150 }
f34d28ea 2151 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2152 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2153 }
2154
d9e8b185
VZ		 2155 /* indicate link status only if link status actually changed */
2156 if (prev_link_status != bp->link_vars.link_status)
2157 bnx2x_link_report(bp);
34f80b04 2158
f2e0899f
DK		 2159 if (IS_MF(bp))
2160 bnx2x_link_sync_notify(bp);
34f80b04 2161
f2e0899f
DK		 2162 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2163 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2164
f2e0899f
DK		 2165 if (cmng_fns != CMNG_FNS_NONE) {
2166 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2167 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2168 } else
2169 /* rate shaping and fairness are disabled */
2170 DP(NETIF_MSG_IFUP,
2171 "single function mode without fairness\n");
34f80b04 2172 }
c18487ee 2173}
a2fbb9ea 2174
9f6c9258 2175void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2176{
f34d28ea 2177 if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
c18487ee 2178 return;
a2fbb9ea 2179
c18487ee 2180 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2181
bb2a0f7a
YG		 2182 if (bp->link_vars.link_up)
2183 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2184 else
2185 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2186
f2e0899f
DK		 2187 /* the link status update could be the result of a DCC event
2188 hence re-read the shmem mf configuration */
2189 bnx2x_read_mf_cfg(bp);
2691d51d 2190
c18487ee
YR		 2191 /* indicate link status */
2192 bnx2x_link_report(bp);
a2fbb9ea 2193}
a2fbb9ea 2194
34f80b04
EG		 2195static void bnx2x_pmf_update(struct bnx2x *bp)
2196{
2197 int port = BP_PORT(bp);
2198 u32 val;
2199
2200 bp->port.pmf = 1;
2201 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2202
2203 /* enable nig attention */
2204 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
f2e0899f
DK		 2205 if (bp->common.int_block == INT_BLOCK_HC) {
2206 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2207 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2208 } else if (CHIP_IS_E2(bp)) {
2209 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2210 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2211 }
bb2a0f7a
YG		 2212
2213 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2214}
2215
c18487ee 2216/* end of Link */
a2fbb9ea
ET		 2217
2218/* slow path */
2219
2220/*
2221 * General service functions
2222 */
2223
2691d51d 2224/* send the MCP a request, block until there is a reply */
a22f0788 2225u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2226{
f2e0899f 2227 int mb_idx = BP_FW_MB_IDX(bp);
2691d51d
EG		 2228 u32 seq = ++bp->fw_seq;
2229 u32 rc = 0;
2230 u32 cnt = 1;
2231 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2232
c4ff7cbf 2233 mutex_lock(&bp->fw_mb_mutex);
f2e0899f
DK		 2234 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2235 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2236
2691d51d
EG		 2237 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2238
2239 do {
2240 /* let the FW do it's magic ... */
2241 msleep(delay);
2242
f2e0899f 2243 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2244
c4ff7cbf
EG		 2245 /* Give the FW up to 5 second (500*10ms) */
2246 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2247
2248 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2249 cnt*delay, rc, seq);
2250
2251 /* is this a reply to our command? */
2252 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2253 rc &= FW_MSG_CODE_MASK;
2254 else {
2255 /* FW BUG! */
2256 BNX2X_ERR("FW failed to respond!\n");
2257 bnx2x_fw_dump(bp);
2258 rc = 0;
2259 }
c4ff7cbf 2260 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2261
2262 return rc;
2263}
2264
ec6ba945
VZ		 2265static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2266{
2267#ifdef BCM_CNIC
2268 if (IS_FCOE_FP(fp) && IS_MF(bp))
2269 return false;
2270#endif
2271 return true;
2272}
2273
523224a3 2274/* must be called under rtnl_lock */
8d96286a 2275static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2691d51d 2276{
523224a3 2277 u32 mask = (1 << cl_id);
2691d51d 2278
523224a3
DK		 2279 /* initial seeting is BNX2X_ACCEPT_NONE */
2280 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2281 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2282 u8 unmatched_unicast = 0;
2691d51d 2283
0793f83f
DK		 2284 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2285 unmatched_unicast = 1;
2286
523224a3
DK		 2287 if (filters & BNX2X_PROMISCUOUS_MODE) {
2288 /* promiscious - accept all, drop none */
2289 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2290 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
0793f83f
DK		 2291 if (IS_MF_SI(bp)) {
2292 /*
2293 * SI mode defines to accept in promiscuos mode
2294 * only unmatched packets
2295 */
2296 unmatched_unicast = 1;
2297 accp_all_ucast = 0;
2298 }
523224a3
DK		 2299 }
2300 if (filters & BNX2X_ACCEPT_UNICAST) {
2301 /* accept matched ucast */
2302 drop_all_ucast = 0;
2303 }
2304 if (filters & BNX2X_ACCEPT_MULTICAST) {
2305 /* accept matched mcast */
2306 drop_all_mcast = 0;
0793f83f
DK		 2307 if (IS_MF_SI(bp))
2308 /* since mcast addresses won't arrive with ovlan,
2309 * fw needs to accept all of them in
2310 * switch-independent mode */
2311 accp_all_mcast = 1;
523224a3
DK		 2312 }
2313 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2314 /* accept all mcast */
2315 drop_all_ucast = 0;
2316 accp_all_ucast = 1;
2317 }
2318 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2319 /* accept all mcast */
2320 drop_all_mcast = 0;
2321 accp_all_mcast = 1;
2322 }
2323 if (filters & BNX2X_ACCEPT_BROADCAST) {
2324 /* accept (all) bcast */
2325 drop_all_bcast = 0;
2326 accp_all_bcast = 1;
2327 }
2691d51d 2328
523224a3
DK		 2329 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2330 bp->mac_filters.ucast_drop_all | mask :
2331 bp->mac_filters.ucast_drop_all & ~mask;
2691d51d 2332
523224a3
DK		 2333 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2334 bp->mac_filters.mcast_drop_all | mask :
2335 bp->mac_filters.mcast_drop_all & ~mask;
2691d51d 2336
523224a3
DK		 2337 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2338 bp->mac_filters.bcast_drop_all | mask :
2339 bp->mac_filters.bcast_drop_all & ~mask;
2691d51d 2340
523224a3
DK		 2341 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2342 bp->mac_filters.ucast_accept_all | mask :
2343 bp->mac_filters.ucast_accept_all & ~mask;
2691d51d 2344
523224a3
DK		 2345 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2346 bp->mac_filters.mcast_accept_all | mask :
2347 bp->mac_filters.mcast_accept_all & ~mask;
2348
2349 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2350 bp->mac_filters.bcast_accept_all | mask :
2351 bp->mac_filters.bcast_accept_all & ~mask;
2352
2353 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2354 bp->mac_filters.unmatched_unicast | mask :
2355 bp->mac_filters.unmatched_unicast & ~mask;
2691d51d
EG		 2356}
2357
8d96286a 2358static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2691d51d 2359{
030f3356
DK		 2360 struct tstorm_eth_function_common_config tcfg = {0};
2361 u16 rss_flgs;
2691d51d 2362
030f3356
DK		 2363 /* tpa */
2364 if (p->func_flgs & FUNC_FLG_TPA)
2365 tcfg.config_flags |=
2366 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2691d51d 2367
030f3356
DK		 2368 /* set rss flags */
2369 rss_flgs = (p->rss->mode <<
2370 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2371
2372 if (p->rss->cap & RSS_IPV4_CAP)
2373 rss_flgs |= RSS_IPV4_CAP_MASK;
2374 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2375 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2376 if (p->rss->cap & RSS_IPV6_CAP)
2377 rss_flgs |= RSS_IPV6_CAP_MASK;
2378 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2379 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2380
2381 tcfg.config_flags |= rss_flgs;
2382 tcfg.rss_result_mask = p->rss->result_mask;
2383
2384 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2691d51d 2385
523224a3
DK		 2386 /* Enable the function in the FW */
2387 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2388 storm_memset_func_en(bp, p->func_id, 1);
2691d51d 2389
523224a3
DK		 2390 /* statistics */
2391 if (p->func_flgs & FUNC_FLG_STATS) {
2392 struct stats_indication_flags stats_flags = {0};
2393 stats_flags.collect_eth = 1;
2691d51d 2394
523224a3
DK		 2395 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2396 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2397
523224a3
DK		 2398 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2399 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2400
523224a3
DK		 2401 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2402 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d 2403
523224a3
DK		 2404 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2405 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2691d51d
EG		 2406 }
2407
523224a3
DK		 2408 /* spq */
2409 if (p->func_flgs & FUNC_FLG_SPQ) {
2410 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2411 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2412 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2413 }
2691d51d
EG		 2414}
2415
523224a3
DK		 2416static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2417 struct bnx2x_fastpath *fp)
28912902 2418{
523224a3 2419 u16 flags = 0;
28912902 2420
523224a3
DK		 2421 /* calculate queue flags */
2422 flags |= QUEUE_FLG_CACHE_ALIGN;
2423 flags |= QUEUE_FLG_HC;
0793f83f 2424 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
28912902 2425
523224a3
DK		 2426 flags |= QUEUE_FLG_VLAN;
2427 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
523224a3
DK		 2428
2429 if (!fp->disable_tpa)
2430 flags |= QUEUE_FLG_TPA;
2431
ec6ba945
VZ		 2432 flags = stat_counter_valid(bp, fp) ?
2433 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
523224a3
DK		 2434
2435 return flags;
2436}
2437
2438static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2439 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2440 struct bnx2x_rxq_init_params *rxq_init)
2441{
2442 u16 max_sge = 0;
2443 u16 sge_sz = 0;
2444 u16 tpa_agg_size = 0;
2445
2446 /* calculate queue flags */
2447 u16 flags = bnx2x_get_cl_flags(bp, fp);
2448
2449 if (!fp->disable_tpa) {
2450 pause->sge_th_hi = 250;
2451 pause->sge_th_lo = 150;
2452 tpa_agg_size = min_t(u32,
2453 (min_t(u32, 8, MAX_SKB_FRAGS) *
2454 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2455 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2456 SGE_PAGE_SHIFT;
2457 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2458 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2459 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2460 0xffff);
2461 }
2462
2463 /* pause - not for e1 */
2464 if (!CHIP_IS_E1(bp)) {
2465 pause->bd_th_hi = 350;
2466 pause->bd_th_lo = 250;
2467 pause->rcq_th_hi = 350;
2468 pause->rcq_th_lo = 250;
2469 pause->sge_th_hi = 0;
2470 pause->sge_th_lo = 0;
2471 pause->pri_map = 1;
2472 }
2473
2474 /* rxq setup */
2475 rxq_init->flags = flags;
2476 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2477 rxq_init->dscr_map = fp->rx_desc_mapping;
2478 rxq_init->sge_map = fp->rx_sge_mapping;
2479 rxq_init->rcq_map = fp->rx_comp_mapping;
2480 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2481 rxq_init->mtu = bp->dev->mtu;
2482 rxq_init->buf_sz = bp->rx_buf_size;
2483 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2484 rxq_init->cl_id = fp->cl_id;
2485 rxq_init->spcl_id = fp->cl_id;
2486 rxq_init->stat_id = fp->cl_id;
2487 rxq_init->tpa_agg_sz = tpa_agg_size;
2488 rxq_init->sge_buf_sz = sge_sz;
2489 rxq_init->max_sges_pkt = max_sge;
2490 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2491 rxq_init->fw_sb_id = fp->fw_sb_id;
2492
ec6ba945
VZ		 2493 if (IS_FCOE_FP(fp))
2494 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2495 else
2496 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
523224a3
DK		 2497
2498 rxq_init->cid = HW_CID(bp, fp->cid);
2499
2500 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2501}
2502
2503static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2504 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2505{
2506 u16 flags = bnx2x_get_cl_flags(bp, fp);
2507
2508 txq_init->flags = flags;
2509 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2510 txq_init->dscr_map = fp->tx_desc_mapping;
2511 txq_init->stat_id = fp->cl_id;
2512 txq_init->cid = HW_CID(bp, fp->cid);
2513 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2514 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2515 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945
VZ		 2516
2517 if (IS_FCOE_FP(fp)) {
2518 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2519 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2520 }
2521
523224a3
DK		 2522 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2523}
2524
8d96286a 2525static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2526{
2527 struct bnx2x_func_init_params func_init = {0};
2528 struct bnx2x_rss_params rss = {0};
2529 struct event_ring_data eq_data = { {0} };
2530 u16 flags;
2531
2532 /* pf specific setups */
2533 if (!CHIP_IS_E1(bp))
fb3bff17 2534 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
523224a3 2535
f2e0899f
DK		 2536 if (CHIP_IS_E2(bp)) {
2537 /* reset IGU PF statistics: MSIX + ATTN */
2538 /* PF */
2539 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2540 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2541 (CHIP_MODE_IS_4_PORT(bp) ?
2542 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2543 /* ATTN */
2544 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2545 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2546 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2547 (CHIP_MODE_IS_4_PORT(bp) ?
2548 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2549 }
2550
523224a3
DK		 2551 /* function setup flags */
2552 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2553
f2e0899f
DK		 2554 if (CHIP_IS_E1x(bp))
2555 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2556 else
2557 flags |= FUNC_FLG_TPA;
523224a3 2558
030f3356
DK		 2559 /* function setup */
2560
523224a3
DK		 2561 /**
2562 * Although RSS is meaningless when there is a single HW queue we
2563 * still need it enabled in order to have HW Rx hash generated.
523224a3 2564 */
030f3356
DK		 2565 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2566 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2567 rss.mode = bp->multi_mode;
2568 rss.result_mask = MULTI_MASK;
2569 func_init.rss = &rss;
523224a3
DK		 2570
2571 func_init.func_flgs = flags;
2572 func_init.pf_id = BP_FUNC(bp);
2573 func_init.func_id = BP_FUNC(bp);
2574 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2575 func_init.spq_map = bp->spq_mapping;
2576 func_init.spq_prod = bp->spq_prod_idx;
2577
2578 bnx2x_func_init(bp, &func_init);
2579
2580 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2581
2582 /*
2583 Congestion management values depend on the link rate
2584 There is no active link so initial link rate is set to 10 Gbps.
2585 When the link comes up The congestion management values are
2586 re-calculated according to the actual link rate.
2587 */
2588 bp->link_vars.line_speed = SPEED_10000;
2589 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2590
2591 /* Only the PMF sets the HW */
2592 if (bp->port.pmf)
2593 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2594
2595 /* no rx until link is up */
2596 bp->rx_mode = BNX2X_RX_MODE_NONE;
2597 bnx2x_set_storm_rx_mode(bp);
2598
2599 /* init Event Queue */
2600 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2601 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2602 eq_data.producer = bp->eq_prod;
2603 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2604 eq_data.sb_id = DEF_SB_ID;
2605 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2606}
2607
2608
2609static void bnx2x_e1h_disable(struct bnx2x *bp)
2610{
2611 int port = BP_PORT(bp);
2612
2613 netif_tx_disable(bp->dev);
2614
2615 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2616
2617 netif_carrier_off(bp->dev);
2618}
2619
2620static void bnx2x_e1h_enable(struct bnx2x *bp)
2621{
2622 int port = BP_PORT(bp);
2623
2624 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2625
2626 /* Tx queue should be only reenabled */
2627 netif_tx_wake_all_queues(bp->dev);
2628
2629 /*
2630 * Should not call netif_carrier_on since it will be called if the link
2631 * is up when checking for link state
2632 */
2633}
2634
0793f83f
DK		 2635/* called due to MCP event (on pmf):
2636 * reread new bandwidth configuration
2637 * configure FW
2638 * notify others function about the change
2639 */
2640static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2641{
2642 if (bp->link_vars.link_up) {
2643 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2644 bnx2x_link_sync_notify(bp);
2645 }
2646 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2647}
2648
2649static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2650{
2651 bnx2x_config_mf_bw(bp);
2652 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2653}
2654
523224a3
DK		 2655static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2656{
2657 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2658
2659 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2660
2661 /*
2662 * This is the only place besides the function initialization
2663 * where the bp->flags can change so it is done without any
2664 * locks
2665 */
f2e0899f 2666 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2667 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2668 bp->flags |= MF_FUNC_DIS;
2669
2670 bnx2x_e1h_disable(bp);
2671 } else {
2672 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2673 bp->flags &= ~MF_FUNC_DIS;
2674
2675 bnx2x_e1h_enable(bp);
2676 }
2677 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2678 }
2679 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2680 bnx2x_config_mf_bw(bp);
523224a3
DK		 2681 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2682 }
2683
2684 /* Report results to MCP */
2685 if (dcc_event)
2686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2687 else
2688 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2689}
2690
2691/* must be called under the spq lock */
2692static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2693{
2694 struct eth_spe *next_spe = bp->spq_prod_bd;
2695
2696 if (bp->spq_prod_bd == bp->spq_last_bd) {
2697 bp->spq_prod_bd = bp->spq;
2698 bp->spq_prod_idx = 0;
2699 DP(NETIF_MSG_TIMER, "end of spq\n");
2700 } else {
2701 bp->spq_prod_bd++;
2702 bp->spq_prod_idx++;
2703 }
2704 return next_spe;
2705}
2706
2707/* must be called under the spq lock */
28912902
MC		 2708static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2709{
2710 int func = BP_FUNC(bp);
2711
2712 /* Make sure that BD data is updated before writing the producer */
2713 wmb();
2714
523224a3 2715 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 2716 bp->spq_prod_idx);
28912902
MC		 2717 mmiowb();
2718}
2719
a2fbb9ea 2720/* the slow path queue is odd since completions arrive on the fastpath ring */
9f6c9258 2721int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
f85582f8 2722 u32 data_hi, u32 data_lo, int common)
a2fbb9ea 2723{
28912902 2724 struct eth_spe *spe;
523224a3 2725 u16 type;
a2fbb9ea 2726
a2fbb9ea
ET		 2727#ifdef BNX2X_STOP_ON_ERROR
2728 if (unlikely(bp->panic))
2729 return -EIO;
2730#endif
2731
34f80b04 2732 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 2733
8fe23fbd 2734 if (!atomic_read(&bp->spq_left)) {
a2fbb9ea 2735 BNX2X_ERR("BUG! SPQ ring full!\n");
34f80b04 2736 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 2737 bnx2x_panic();
2738 return -EBUSY;
2739 }
f1410647 2740
28912902
MC		 2741 spe = bnx2x_sp_get_next(bp);
2742
a2fbb9ea 2743 /* CID needs port number to be encoded int it */
28912902 2744 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 2745 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2746 HW_CID(bp, cid));
523224a3 2747
a2fbb9ea 2748 if (common)
523224a3
DK		 2749 /* Common ramrods:
2750 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2751 * TRAFFIC_STOP, TRAFFIC_START
2752 */
2753 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2754 & SPE_HDR_CONN_TYPE;
2755 else
2756 /* ETH ramrods: SETUP, HALT */
2757 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2758 & SPE_HDR_CONN_TYPE;
a2fbb9ea 2759
523224a3
DK		 2760 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2761 SPE_HDR_FUNCTION_ID);
a2fbb9ea 2762
523224a3
DK		 2763 spe->hdr.type = cpu_to_le16(type);
2764
2765 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2766 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2767
2768 /* stats ramrod has it's own slot on the spq */
2769 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY)
2770 /* It's ok if the actual decrement is issued towards the memory
2771 * somewhere between the spin_lock and spin_unlock. Thus no
2772 * more explict memory barrier is needed.
2773 */
8fe23fbd 2774 atomic_dec(&bp->spq_left);
a2fbb9ea 2775
cdaa7cb8 2776 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
523224a3
DK		 2777 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2778 "type(0x%x) left %x\n",
cdaa7cb8
VZ		 2779 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2780 (u32)(U64_LO(bp->spq_mapping) +
2781 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
8fe23fbd 2782 HW_CID(bp, cid), data_hi, data_lo, type, atomic_read(&bp->spq_left));
cdaa7cb8 2783
28912902 2784 bnx2x_sp_prod_update(bp);
34f80b04 2785 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 2786 return 0;
2787}
2788
2789/* acquire split MCP access lock register */
4a37fb66 2790static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 2791{
72fd0718 2792 u32 j, val;
34f80b04 2793 int rc = 0;
a2fbb9ea
ET		 2794
2795 might_sleep();
72fd0718 2796 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 2797 val = (1UL << 31);
2798 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2799 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2800 if (val & (1L << 31))
2801 break;
2802
2803 msleep(5);
2804 }
a2fbb9ea 2805 if (!(val & (1L << 31))) {
19680c48 2806 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 2807 rc = -EBUSY;
2808 }
2809
2810 return rc;
2811}
2812
4a37fb66
YG		 2813/* release split MCP access lock register */
2814static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 2815{
72fd0718 2816 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 2817}
2818
523224a3
DK		 2819#define BNX2X_DEF_SB_ATT_IDX 0x0001
2820#define BNX2X_DEF_SB_IDX 0x0002
2821
a2fbb9ea
ET		 2822static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2823{
523224a3 2824 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 2825 u16 rc = 0;
2826
2827 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 2828 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2829 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 2830 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 2831 }
523224a3
DK		 2832
2833 if (bp->def_idx != def_sb->sp_sb.running_index) {
2834 bp->def_idx = def_sb->sp_sb.running_index;
2835 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 2836 }
523224a3
DK		 2837
2838 /* Do not reorder: indecies reading should complete before handling */
2839 barrier();
a2fbb9ea
ET		 2840 return rc;
2841}
2842
2843/*
2844 * slow path service functions
2845 */
2846
2847static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2848{
34f80b04 2849 int port = BP_PORT(bp);
a2fbb9ea
ET		 2850 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2851 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 2852 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2853 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 2854 u32 aeu_mask;
87942b46 2855 u32 nig_mask = 0;
f2e0899f 2856 u32 reg_addr;
a2fbb9ea 2857
a2fbb9ea
ET		 2858 if (bp->attn_state & asserted)
2859 BNX2X_ERR("IGU ERROR\n");
2860
3fcaf2e5
EG		 2861 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2862 aeu_mask = REG_RD(bp, aeu_addr);
2863
a2fbb9ea 2864 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 2865 aeu_mask, asserted);
72fd0718 2866 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 2867 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 2868
3fcaf2e5
EG		 2869 REG_WR(bp, aeu_addr, aeu_mask);
2870 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 2871
3fcaf2e5 2872 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 2873 bp->attn_state |= asserted;
3fcaf2e5 2874 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 2875
2876 if (asserted & ATTN_HARD_WIRED_MASK) {
2877 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 2878
a5e9a7cf
EG		 2879 bnx2x_acquire_phy_lock(bp);
2880
877e9aa4 2881 /* save nig interrupt mask */
87942b46 2882 nig_mask = REG_RD(bp, nig_int_mask_addr);
877e9aa4 2883 REG_WR(bp, nig_int_mask_addr, 0);
a2fbb9ea 2884
c18487ee 2885 bnx2x_link_attn(bp);
a2fbb9ea
ET		 2886
2887 /* handle unicore attn? */
2888 }
2889 if (asserted & ATTN_SW_TIMER_4_FUNC)
2890 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2891
2892 if (asserted & GPIO_2_FUNC)
2893 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2894
2895 if (asserted & GPIO_3_FUNC)
2896 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2897
2898 if (asserted & GPIO_4_FUNC)
2899 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2900
2901 if (port == 0) {
2902 if (asserted & ATTN_GENERAL_ATTN_1) {
2903 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2904 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2905 }
2906 if (asserted & ATTN_GENERAL_ATTN_2) {
2907 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2908 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2909 }
2910 if (asserted & ATTN_GENERAL_ATTN_3) {
2911 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2912 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2913 }
2914 } else {
2915 if (asserted & ATTN_GENERAL_ATTN_4) {
2916 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2917 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2918 }
2919 if (asserted & ATTN_GENERAL_ATTN_5) {
2920 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2921 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2922 }
2923 if (asserted & ATTN_GENERAL_ATTN_6) {
2924 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2925 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2926 }
2927 }
2928
2929 } /* if hardwired */
2930
f2e0899f
DK		 2931 if (bp->common.int_block == INT_BLOCK_HC)
2932 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2933 COMMAND_REG_ATTN_BITS_SET);
2934 else
2935 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2936
2937 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2938 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2939 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 2940
2941 /* now set back the mask */
a5e9a7cf 2942 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 2943 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 2944 bnx2x_release_phy_lock(bp);
2945 }
a2fbb9ea
ET		 2946}
2947
fd4ef40d
EG		 2948static inline void bnx2x_fan_failure(struct bnx2x *bp)
2949{
2950 int port = BP_PORT(bp);
b7737c9b 2951 u32 ext_phy_config;
fd4ef40d 2952 /* mark the failure */
b7737c9b
YR		 2953 ext_phy_config =
2954 SHMEM_RD(bp,
2955 dev_info.port_hw_config[port].external_phy_config);
2956
2957 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2958 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 2959 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 2960 ext_phy_config);
fd4ef40d
EG		 2961
2962 /* log the failure */
cdaa7cb8
VZ		 2963 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2964 " the driver to shutdown the card to prevent permanent"
2965 " damage. Please contact OEM Support for assistance\n");
fd4ef40d 2966}
ab6ad5a4 2967
877e9aa4 2968static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 2969{
34f80b04 2970 int port = BP_PORT(bp);
877e9aa4 2971 int reg_offset;
d90d96ba 2972 u32 val;
877e9aa4 2973
34f80b04
EG		 2974 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2975 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 2976
34f80b04 2977 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 2978
2979 val = REG_RD(bp, reg_offset);
2980 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2981 REG_WR(bp, reg_offset, val);
2982
2983 BNX2X_ERR("SPIO5 hw attention\n");
2984
fd4ef40d 2985 /* Fan failure attention */
d90d96ba 2986 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 2987 bnx2x_fan_failure(bp);
877e9aa4 2988 }
34f80b04 2989
589abe3a
EG		 2990 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
2991 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
2992 bnx2x_acquire_phy_lock(bp);
2993 bnx2x_handle_module_detect_int(&bp->link_params);
2994 bnx2x_release_phy_lock(bp);
2995 }
2996
34f80b04
EG		 2997 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2998
2999 val = REG_RD(bp, reg_offset);
3000 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3001 REG_WR(bp, reg_offset, val);
3002
3003 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3004 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3005 bnx2x_panic();
3006 }
877e9aa4
ET		 3007}
3008
3009static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3010{
3011 u32 val;
3012
0626b899 3013 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3014
3015 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3016 BNX2X_ERR("DB hw attention 0x%x\n", val);
3017 /* DORQ discard attention */
3018 if (val & 0x2)
3019 BNX2X_ERR("FATAL error from DORQ\n");
3020 }
34f80b04
EG		 3021
3022 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3023
3024 int port = BP_PORT(bp);
3025 int reg_offset;
3026
3027 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3028 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3029
3030 val = REG_RD(bp, reg_offset);
3031 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3032 REG_WR(bp, reg_offset, val);
3033
3034 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3035 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3036 bnx2x_panic();
3037 }
877e9aa4
ET		 3038}
3039
3040static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3041{
3042 u32 val;
3043
3044 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3045
3046 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3047 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3048 /* CFC error attention */
3049 if (val & 0x2)
3050 BNX2X_ERR("FATAL error from CFC\n");
3051 }
3052
3053 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3054
3055 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3056 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3057 /* RQ_USDMDP_FIFO_OVERFLOW */
3058 if (val & 0x18000)
3059 BNX2X_ERR("FATAL error from PXP\n");
f2e0899f
DK		 3060 if (CHIP_IS_E2(bp)) {
3061 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3062 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3063 }
877e9aa4 3064 }
34f80b04
EG		 3065
3066 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3067
3068 int port = BP_PORT(bp);
3069 int reg_offset;
3070
3071 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3072 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3073
3074 val = REG_RD(bp, reg_offset);
3075 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3076 REG_WR(bp, reg_offset, val);
3077
3078 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3079 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3080 bnx2x_panic();
3081 }
877e9aa4
ET		 3082}
3083
3084static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3085{
34f80b04
EG		 3086 u32 val;
3087
877e9aa4
ET		 3088 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3089
34f80b04
EG		 3090 if (attn & BNX2X_PMF_LINK_ASSERT) {
3091 int func = BP_FUNC(bp);
3092
3093 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3094 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3095 func_mf_config[BP_ABS_FUNC(bp)].config);
3096 val = SHMEM_RD(bp,
3097 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3098 if (val & DRV_STATUS_DCC_EVENT_MASK)
3099 bnx2x_dcc_event(bp,
3100 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3101
3102 if (val & DRV_STATUS_SET_MF_BW)
3103 bnx2x_set_mf_bw(bp);
3104
34f80b04 3105 bnx2x__link_status_update(bp);
2691d51d 3106 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3107 bnx2x_pmf_update(bp);
3108
e4901dde 3109 if (bp->port.pmf &&
785b9b1a
SR		 3110 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3111 bp->dcbx_enabled > 0)
e4901dde
VZ		 3112 /* start dcbx state machine */
3113 bnx2x_dcbx_set_params(bp,
3114 BNX2X_DCBX_STATE_NEG_RECEIVED);
34f80b04 3115 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3116
3117 BNX2X_ERR("MC assert!\n");
3118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3119 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3120 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3121 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3122 bnx2x_panic();
3123
3124 } else if (attn & BNX2X_MCP_ASSERT) {
3125
3126 BNX2X_ERR("MCP assert!\n");
3127 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3128 bnx2x_fw_dump(bp);
877e9aa4
ET		 3129
3130 } else
3131 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3132 }
3133
3134 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3135 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3136 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3137 val = CHIP_IS_E1(bp) ? 0 :
3138 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3139 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3140 }
3141 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3142 val = CHIP_IS_E1(bp) ? 0 :
3143 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3144 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3145 }
877e9aa4 3146 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3147 }
3148}
3149
72fd0718
VZ		 3150#define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3151#define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3152#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3153#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3154#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
f85582f8 3155
72fd0718
VZ		 3156/*
3157 * should be run under rtnl lock
3158 */
3159static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3160{
3161 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3162 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3163 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3164 barrier();
3165 mmiowb();
3166}
3167
3168/*
3169 * should be run under rtnl lock
3170 */
3171static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3172{
3173 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3174 val |= (1 << 16);
3175 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3176 barrier();
3177 mmiowb();
3178}
3179
3180/*
3181 * should be run under rtnl lock
3182 */
9f6c9258 3183bool bnx2x_reset_is_done(struct bnx2x *bp)
72fd0718
VZ		 3184{
3185 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3186 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3187 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3188}
3189
3190/*
3191 * should be run under rtnl lock
3192 */
9f6c9258 3193inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3194{
3195 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3196
3197 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3198
3199 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3200 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3201 barrier();
3202 mmiowb();
3203}
3204
3205/*
3206 * should be run under rtnl lock
3207 */
9f6c9258 3208u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718
VZ		 3209{
3210 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3211
3212 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3213
3214 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3215 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3216 barrier();
3217 mmiowb();
3218
3219 return val1;
3220}
3221
3222/*
3223 * should be run under rtnl lock
3224 */
3225static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3226{
3227 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3228}
3229
3230static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3231{
3232 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3233 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3234}
3235
3236static inline void _print_next_block(int idx, const char *blk)
3237{
3238 if (idx)
3239 pr_cont(", ");
3240 pr_cont("%s", blk);
3241}
3242
3243static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3244{
3245 int i = 0;
3246 u32 cur_bit = 0;
3247 for (i = 0; sig; i++) {
3248 cur_bit = ((u32)0x1 << i);
3249 if (sig & cur_bit) {
3250 switch (cur_bit) {
3251 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3252 _print_next_block(par_num++, "BRB");
3253 break;
3254 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3255 _print_next_block(par_num++, "PARSER");
3256 break;
3257 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3258 _print_next_block(par_num++, "TSDM");
3259 break;
3260 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3261 _print_next_block(par_num++, "SEARCHER");
3262 break;
3263 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3264 _print_next_block(par_num++, "TSEMI");
3265 break;
3266 }
3267
3268 /* Clear the bit */
3269 sig &= ~cur_bit;
3270 }
3271 }
3272
3273 return par_num;
3274}
3275
3276static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3277{
3278 int i = 0;
3279 u32 cur_bit = 0;
3280 for (i = 0; sig; i++) {
3281 cur_bit = ((u32)0x1 << i);
3282 if (sig & cur_bit) {
3283 switch (cur_bit) {
3284 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3285 _print_next_block(par_num++, "PBCLIENT");
3286 break;
3287 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3288 _print_next_block(par_num++, "QM");
3289 break;
3290 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3291 _print_next_block(par_num++, "XSDM");
3292 break;
3293 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3294 _print_next_block(par_num++, "XSEMI");
3295 break;
3296 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3297 _print_next_block(par_num++, "DOORBELLQ");
3298 break;
3299 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3300 _print_next_block(par_num++, "VAUX PCI CORE");
3301 break;
3302 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3303 _print_next_block(par_num++, "DEBUG");
3304 break;
3305 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3306 _print_next_block(par_num++, "USDM");
3307 break;
3308 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3309 _print_next_block(par_num++, "USEMI");
3310 break;
3311 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3312 _print_next_block(par_num++, "UPB");
3313 break;
3314 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3315 _print_next_block(par_num++, "CSDM");
3316 break;
3317 }
3318
3319 /* Clear the bit */
3320 sig &= ~cur_bit;
3321 }
3322 }
3323
3324 return par_num;
3325}
3326
3327static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3328{
3329 int i = 0;
3330 u32 cur_bit = 0;
3331 for (i = 0; sig; i++) {
3332 cur_bit = ((u32)0x1 << i);
3333 if (sig & cur_bit) {
3334 switch (cur_bit) {
3335 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3336 _print_next_block(par_num++, "CSEMI");
3337 break;
3338 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3339 _print_next_block(par_num++, "PXP");
3340 break;
3341 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3342 _print_next_block(par_num++,
3343 "PXPPCICLOCKCLIENT");
3344 break;
3345 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3346 _print_next_block(par_num++, "CFC");
3347 break;
3348 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3349 _print_next_block(par_num++, "CDU");
3350 break;
3351 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3352 _print_next_block(par_num++, "IGU");
3353 break;
3354 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3355 _print_next_block(par_num++, "MISC");
3356 break;
3357 }
3358
3359 /* Clear the bit */
3360 sig &= ~cur_bit;
3361 }
3362 }
3363
3364 return par_num;
3365}
3366
3367static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3368{
3369 int i = 0;
3370 u32 cur_bit = 0;
3371 for (i = 0; sig; i++) {
3372 cur_bit = ((u32)0x1 << i);
3373 if (sig & cur_bit) {
3374 switch (cur_bit) {
3375 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3376 _print_next_block(par_num++, "MCP ROM");
3377 break;
3378 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3379 _print_next_block(par_num++, "MCP UMP RX");
3380 break;
3381 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3382 _print_next_block(par_num++, "MCP UMP TX");
3383 break;
3384 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3385 _print_next_block(par_num++, "MCP SCPAD");
3386 break;
3387 }
3388
3389 /* Clear the bit */
3390 sig &= ~cur_bit;
3391 }
3392 }
3393
3394 return par_num;
3395}
3396
3397static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3398 u32 sig2, u32 sig3)
3399{
3400 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3401 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3402 int par_num = 0;
3403 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3404 "[0]:0x%08x [1]:0x%08x "
3405 "[2]:0x%08x [3]:0x%08x\n",
3406 sig0 & HW_PRTY_ASSERT_SET_0,
3407 sig1 & HW_PRTY_ASSERT_SET_1,
3408 sig2 & HW_PRTY_ASSERT_SET_2,
3409 sig3 & HW_PRTY_ASSERT_SET_3);
3410 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3411 bp->dev->name);
3412 par_num = bnx2x_print_blocks_with_parity0(
3413 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3414 par_num = bnx2x_print_blocks_with_parity1(
3415 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3416 par_num = bnx2x_print_blocks_with_parity2(
3417 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3418 par_num = bnx2x_print_blocks_with_parity3(
3419 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3420 printk("\n");
3421 return true;
3422 } else
3423 return false;
3424}
3425
9f6c9258 3426bool bnx2x_chk_parity_attn(struct bnx2x *bp)
877e9aa4 3427{
a2fbb9ea 3428 struct attn_route attn;
72fd0718
VZ		 3429 int port = BP_PORT(bp);
3430
3431 attn.sig[0] = REG_RD(bp,
3432 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3433 port*4);
3434 attn.sig[1] = REG_RD(bp,
3435 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3436 port*4);
3437 attn.sig[2] = REG_RD(bp,
3438 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3439 port*4);
3440 attn.sig[3] = REG_RD(bp,
3441 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3442 port*4);
3443
3444 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3445 attn.sig[3]);
3446}
3447
f2e0899f
DK		 3448
3449static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3450{
3451 u32 val;
3452 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3453
3454 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3455 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3456 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3457 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3458 "ADDRESS_ERROR\n");
3459 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3460 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3461 "INCORRECT_RCV_BEHAVIOR\n");
3462 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3463 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3464 "WAS_ERROR_ATTN\n");
3465 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3466 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3467 "VF_LENGTH_VIOLATION_ATTN\n");
3468 if (val &
3469 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3470 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3471 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3472 if (val &
3473 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3474 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3475 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3476 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3477 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3478 "TCPL_ERROR_ATTN\n");
3479 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3480 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3481 "TCPL_IN_TWO_RCBS_ATTN\n");
3482 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3483 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3484 "CSSNOOP_FIFO_OVERFLOW\n");
3485 }
3486 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3487 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3488 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3489 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3490 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3491 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3492 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3493 "_ATC_TCPL_TO_NOT_PEND\n");
3494 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3495 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3496 "ATC_GPA_MULTIPLE_HITS\n");
3497 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3498 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3499 "ATC_RCPL_TO_EMPTY_CNT\n");
3500 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3501 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3502 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3503 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3504 "ATC_IREQ_LESS_THAN_STU\n");
3505 }
3506
3507 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3508 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3509 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3510 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3511 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3512 }
3513
3514}
3515
72fd0718
VZ		 3516static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3517{
3518 struct attn_route attn, *group_mask;
34f80b04 3519 int port = BP_PORT(bp);
877e9aa4 3520 int index;
a2fbb9ea
ET		 3521 u32 reg_addr;
3522 u32 val;
3fcaf2e5 3523 u32 aeu_mask;
a2fbb9ea
ET		 3524
3525 /* need to take HW lock because MCP or other port might also
3526 try to handle this event */
4a37fb66 3527 bnx2x_acquire_alr(bp);
a2fbb9ea 3528
4a33bc03 3529 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
72fd0718
VZ		 3530 bp->recovery_state = BNX2X_RECOVERY_INIT;
3531 bnx2x_set_reset_in_progress(bp);
3532 schedule_delayed_work(&bp->reset_task, 0);
3533 /* Disable HW interrupts */
3534 bnx2x_int_disable(bp);
3535 bnx2x_release_alr(bp);
3536 /* In case of parity errors don't handle attentions so that
3537 * other function would "see" parity errors.
3538 */
3539 return;
3540 }
3541
a2fbb9ea
ET		 3542 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3543 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3544 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3545 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
f2e0899f
DK		 3546 if (CHIP_IS_E2(bp))
3547 attn.sig[4] =
3548 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3549 else
3550 attn.sig[4] = 0;
3551
3552 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3553 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 3554
3555 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3556 if (deasserted & (1 << index)) {
72fd0718 3557 group_mask = &bp->attn_group[index];
a2fbb9ea 3558
f2e0899f
DK		 3559 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3560 "%08x %08x %08x\n",
3561 index,
3562 group_mask->sig[0], group_mask->sig[1],
3563 group_mask->sig[2], group_mask->sig[3],
3564 group_mask->sig[4]);
a2fbb9ea 3565
f2e0899f
DK		 3566 bnx2x_attn_int_deasserted4(bp,
3567 attn.sig[4] & group_mask->sig[4]);
877e9aa4 3568 bnx2x_attn_int_deasserted3(bp,
72fd0718 3569 attn.sig[3] & group_mask->sig[3]);
877e9aa4 3570 bnx2x_attn_int_deasserted1(bp,
72fd0718 3571 attn.sig[1] & group_mask->sig[1]);
877e9aa4 3572 bnx2x_attn_int_deasserted2(bp,
72fd0718 3573 attn.sig[2] & group_mask->sig[2]);
877e9aa4 3574 bnx2x_attn_int_deasserted0(bp,
72fd0718 3575 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 3576 }
3577 }
3578
4a37fb66 3579 bnx2x_release_alr(bp);
a2fbb9ea 3580
f2e0899f
DK		 3581 if (bp->common.int_block == INT_BLOCK_HC)
3582 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3583 COMMAND_REG_ATTN_BITS_CLR);
3584 else
3585 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 3586
3587 val = ~deasserted;
f2e0899f
DK		 3588 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3589 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 3590 REG_WR(bp, reg_addr, val);
a2fbb9ea 3591
a2fbb9ea 3592 if (~bp->attn_state & deasserted)
3fcaf2e5 3593 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 3594
3595 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3596 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3597
3fcaf2e5
EG		 3598 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3599 aeu_mask = REG_RD(bp, reg_addr);
3600
3601 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3602 aeu_mask, deasserted);
72fd0718 3603 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 3604 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3605
3fcaf2e5
EG		 3606 REG_WR(bp, reg_addr, aeu_mask);
3607 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 3608
3609 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3610 bp->attn_state &= ~deasserted;
3611 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3612}
3613
3614static void bnx2x_attn_int(struct bnx2x *bp)
3615{
3616 /* read local copy of bits */
68d59484
EG		 3617 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3618 attn_bits);
3619 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3620 attn_bits_ack);
a2fbb9ea
ET		 3621 u32 attn_state = bp->attn_state;
3622
3623 /* look for changed bits */
3624 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3625 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3626
3627 DP(NETIF_MSG_HW,
3628 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3629 attn_bits, attn_ack, asserted, deasserted);
3630
3631 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 3632 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 3633
3634 /* handle bits that were raised */
3635 if (asserted)
3636 bnx2x_attn_int_asserted(bp, asserted);
3637
3638 if (deasserted)
3639 bnx2x_attn_int_deasserted(bp, deasserted);
3640}
3641
523224a3
DK		 3642static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3643{
3644 /* No memory barriers */
3645 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3646 mmiowb(); /* keep prod updates ordered */
3647}
3648
3649#ifdef BCM_CNIC
3650static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3651 union event_ring_elem *elem)
3652{
3653 if (!bp->cnic_eth_dev.starting_cid ||
3654 cid < bp->cnic_eth_dev.starting_cid)
3655 return 1;
3656
3657 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3658
3659 if (unlikely(elem->message.data.cfc_del_event.error)) {
3660 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3661 cid);
3662 bnx2x_panic_dump(bp);
3663 }
3664 bnx2x_cnic_cfc_comp(bp, cid);
3665 return 0;
3666}
3667#endif
3668
3669static void bnx2x_eq_int(struct bnx2x *bp)
3670{
3671 u16 hw_cons, sw_cons, sw_prod;
3672 union event_ring_elem *elem;
3673 u32 cid;
3674 u8 opcode;
3675 int spqe_cnt = 0;
3676
3677 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3678
3679 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3680 * when we get the the next-page we nned to adjust so the loop
3681 * condition below will be met. The next element is the size of a
3682 * regular element and hence incrementing by 1
3683 */
3684 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3685 hw_cons++;
3686
3687 /* This function may never run in parralel with itself for a
3688 * specific bp, thus there is no need in "paired" read memory
3689 * barrier here.
3690 */
3691 sw_cons = bp->eq_cons;
3692 sw_prod = bp->eq_prod;
3693
3694 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->spq_left %u\n",
8fe23fbd 3695 hw_cons, sw_cons, atomic_read(&bp->spq_left));
523224a3
DK		 3696
3697 for (; sw_cons != hw_cons;
3698 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3699
3700
3701 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3702
3703 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3704 opcode = elem->message.opcode;
3705
3706
3707 /* handle eq element */
3708 switch (opcode) {
3709 case EVENT_RING_OPCODE_STAT_QUERY:
3710 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3711 /* nothing to do with stats comp */
3712 continue;
3713
3714 case EVENT_RING_OPCODE_CFC_DEL:
3715 /* handle according to cid range */
3716 /*
3717 * we may want to verify here that the bp state is
3718 * HALTING
3719 */
3720 DP(NETIF_MSG_IFDOWN,
3721 "got delete ramrod for MULTI[%d]\n", cid);
3722#ifdef BCM_CNIC
3723 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3724 goto next_spqe;
ec6ba945
VZ		 3725 if (cid == BNX2X_FCOE_ETH_CID)
3726 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3727 else
523224a3 3728#endif
ec6ba945 3729 bnx2x_fp(bp, cid, state) =
523224a3
DK		 3730 BNX2X_FP_STATE_CLOSED;
3731
3732 goto next_spqe;
e4901dde
VZ		 3733
3734 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3735 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3736 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3737 goto next_spqe;
3738 case EVENT_RING_OPCODE_START_TRAFFIC:
3739 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3740 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3741 goto next_spqe;
523224a3
DK		 3742 }
3743
3744 switch (opcode | bp->state) {
3745 case (EVENT_RING_OPCODE_FUNCTION_START |
3746 BNX2X_STATE_OPENING_WAIT4_PORT):
3747 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3748 bp->state = BNX2X_STATE_FUNC_STARTED;
3749 break;
3750
3751 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3752 BNX2X_STATE_CLOSING_WAIT4_HALT):
3753 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3754 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3755 break;
3756
3757 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3758 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3759 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3760 bp->set_mac_pending = 0;
3761 break;
3762
3763 case (EVENT_RING_OPCODE_SET_MAC |
3764 BNX2X_STATE_CLOSING_WAIT4_HALT):
3765 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3766 bp->set_mac_pending = 0;
3767 break;
3768 default:
3769 /* unknown event log error and continue */
3770 BNX2X_ERR("Unknown EQ event %d\n",
3771 elem->message.opcode);
3772 }
3773next_spqe:
3774 spqe_cnt++;
3775 } /* for */
3776
8fe23fbd
DK		 3777 smp_mb__before_atomic_inc();
3778 atomic_add(spqe_cnt, &bp->spq_left);
523224a3
DK		 3779
3780 bp->eq_cons = sw_cons;
3781 bp->eq_prod = sw_prod;
3782 /* Make sure that above mem writes were issued towards the memory */
3783 smp_wmb();
3784
3785 /* update producer */
3786 bnx2x_update_eq_prod(bp, bp->eq_prod);
3787}
3788
a2fbb9ea
ET		 3789static void bnx2x_sp_task(struct work_struct *work)
3790{
1cf167f2 3791 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 3792 u16 status;
3793
3794 /* Return here if interrupt is disabled */
3795 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3196a88a 3796 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
a2fbb9ea
ET		 3797 return;
3798 }
3799
3800 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 3801/* if (status == 0) */
3802/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 3803
cdaa7cb8 3804 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 3805
877e9aa4 3806 /* HW attentions */
523224a3 3807 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 3808 bnx2x_attn_int(bp);
523224a3 3809 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 3810 }
3811
523224a3
DK		 3812 /* SP events: STAT_QUERY and others */
3813 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 3814#ifdef BCM_CNIC
3815 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 3816
ec6ba945
VZ		 3817 if ((!NO_FCOE(bp)) &&
3818 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3819 napi_schedule(&bnx2x_fcoe(bp, napi));
3820#endif
523224a3
DK		 3821 /* Handle EQ completions */
3822 bnx2x_eq_int(bp);
3823
3824 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3825 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3826
3827 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 3828 }
3829
3830 if (unlikely(status))
3831 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3832 status);
a2fbb9ea 3833
523224a3
DK		 3834 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3835 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 3836}
3837
9f6c9258 3838irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 3839{
3840 struct net_device *dev = dev_instance;
3841 struct bnx2x *bp = netdev_priv(dev);
3842
3843 /* Return here if interrupt is disabled */
3844 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3196a88a 3845 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
a2fbb9ea
ET		 3846 return IRQ_HANDLED;
3847 }
3848
523224a3
DK		 3849 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3850 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 3851
3852#ifdef BNX2X_STOP_ON_ERROR
3853 if (unlikely(bp->panic))
3854 return IRQ_HANDLED;
3855#endif
3856
993ac7b5
MC		 3857#ifdef BCM_CNIC
3858 {
3859 struct cnic_ops *c_ops;
3860
3861 rcu_read_lock();
3862 c_ops = rcu_dereference(bp->cnic_ops);
3863 if (c_ops)
3864 c_ops->cnic_handler(bp->cnic_data, NULL);
3865 rcu_read_unlock();
3866 }
3867#endif
1cf167f2 3868 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 3869
3870 return IRQ_HANDLED;
3871}
3872
3873/* end of slow path */
3874
a2fbb9ea
ET		 3875static void bnx2x_timer(unsigned long data)
3876{
3877 struct bnx2x *bp = (struct bnx2x *) data;
3878
3879 if (!netif_running(bp->dev))
3880 return;
3881
3882 if (atomic_read(&bp->intr_sem) != 0)
f1410647 3883 goto timer_restart;
a2fbb9ea
ET		 3884
3885 if (poll) {
3886 struct bnx2x_fastpath *fp = &bp->fp[0];
3887 int rc;
3888
7961f791 3889 bnx2x_tx_int(fp);
a2fbb9ea
ET		 3890 rc = bnx2x_rx_int(fp, 1000);
3891 }
3892
34f80b04 3893 if (!BP_NOMCP(bp)) {
f2e0899f 3894 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 3895 u32 drv_pulse;
3896 u32 mcp_pulse;
3897
3898 ++bp->fw_drv_pulse_wr_seq;
3899 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3900 /* TBD - add SYSTEM_TIME */
3901 drv_pulse = bp->fw_drv_pulse_wr_seq;
f2e0899f 3902 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
a2fbb9ea 3903
f2e0899f 3904 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 3905 MCP_PULSE_SEQ_MASK);
3906 /* The delta between driver pulse and mcp response
3907 * should be 1 (before mcp response) or 0 (after mcp response)
3908 */
3909 if ((drv_pulse != mcp_pulse) &&
3910 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3911 /* someone lost a heartbeat... */
3912 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3913 drv_pulse, mcp_pulse);
3914 }
3915 }
3916
f34d28ea 3917 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 3918 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 3919
f1410647 3920timer_restart:
a2fbb9ea
ET		 3921 mod_timer(&bp->timer, jiffies + bp->current_interval);
3922}
3923
3924/* end of Statistics */
3925
3926/* nic init */
3927
3928/*
3929 * nic init service functions
3930 */
3931
523224a3 3932static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 3933{
523224a3
DK		 3934 u32 i;
3935 if (!(len%4) && !(addr%4))
3936 for (i = 0; i < len; i += 4)
3937 REG_WR(bp, addr + i, fill);
3938 else
3939 for (i = 0; i < len; i++)
3940 REG_WR8(bp, addr + i, fill);
34f80b04 3941
34f80b04
EG		 3942}
3943
523224a3
DK		 3944/* helper: writes FP SP data to FW - data_size in dwords */
3945static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3946 int fw_sb_id,
3947 u32 *sb_data_p,
3948 u32 data_size)
34f80b04 3949{
a2fbb9ea 3950 int index;
523224a3
DK		 3951 for (index = 0; index < data_size; index++)
3952 REG_WR(bp, BAR_CSTRORM_INTMEM +
3953 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3954 sizeof(u32)*index,
3955 *(sb_data_p + index));
3956}
a2fbb9ea 3957
523224a3
DK		 3958static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3959{
3960 u32 *sb_data_p;
3961 u32 data_size = 0;
f2e0899f 3962 struct hc_status_block_data_e2 sb_data_e2;
523224a3 3963 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 3964
523224a3 3965 /* disable the function first */
f2e0899f
DK		 3966 if (CHIP_IS_E2(bp)) {
3967 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3968 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3969 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3970 sb_data_e2.common.p_func.vf_valid = false;
3971 sb_data_p = (u32 *)&sb_data_e2;
3972 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3973 } else {
3974 memset(&sb_data_e1x, 0,
3975 sizeof(struct hc_status_block_data_e1x));
3976 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3977 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3978 sb_data_e1x.common.p_func.vf_valid = false;
3979 sb_data_p = (u32 *)&sb_data_e1x;
3980 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3981 }
523224a3 3982 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 3983
523224a3
DK		 3984 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3985 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
3986 CSTORM_STATUS_BLOCK_SIZE);
3987 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3988 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
3989 CSTORM_SYNC_BLOCK_SIZE);
3990}
34f80b04 3991
523224a3
DK		 3992/* helper: writes SP SB data to FW */
3993static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
3994 struct hc_sp_status_block_data *sp_sb_data)
3995{
3996 int func = BP_FUNC(bp);
3997 int i;
3998 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
3999 REG_WR(bp, BAR_CSTRORM_INTMEM +
4000 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4001 i*sizeof(u32),
4002 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4003}
4004
523224a3 4005static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4006{
4007 int func = BP_FUNC(bp);
523224a3
DK		 4008 struct hc_sp_status_block_data sp_sb_data;
4009 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4010
523224a3
DK		 4011 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4012 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4013 sp_sb_data.p_func.vf_valid = false;
4014
4015 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4016
4017 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4018 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4019 CSTORM_SP_STATUS_BLOCK_SIZE);
4020 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4021 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4022 CSTORM_SP_SYNC_BLOCK_SIZE);
4023
4024}
4025
4026
4027static inline
4028void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4029 int igu_sb_id, int igu_seg_id)
4030{
4031 hc_sm->igu_sb_id = igu_sb_id;
4032 hc_sm->igu_seg_id = igu_seg_id;
4033 hc_sm->timer_value = 0xFF;
4034 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4035}
4036
8d96286a 4037static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4038 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4039{
523224a3
DK		 4040 int igu_seg_id;
4041
f2e0899f 4042 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4043 struct hc_status_block_data_e1x sb_data_e1x;
4044 struct hc_status_block_sm *hc_sm_p;
4045 struct hc_index_data *hc_index_p;
4046 int data_size;
4047 u32 *sb_data_p;
4048
f2e0899f
DK		 4049 if (CHIP_INT_MODE_IS_BC(bp))
4050 igu_seg_id = HC_SEG_ACCESS_NORM;
4051 else
4052 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4053
4054 bnx2x_zero_fp_sb(bp, fw_sb_id);
4055
f2e0899f
DK		 4056 if (CHIP_IS_E2(bp)) {
4057 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4058 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4059 sb_data_e2.common.p_func.vf_id = vfid;
4060 sb_data_e2.common.p_func.vf_valid = vf_valid;
4061 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4062 sb_data_e2.common.same_igu_sb_1b = true;
4063 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4064 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4065 hc_sm_p = sb_data_e2.common.state_machine;
4066 hc_index_p = sb_data_e2.index_data;
4067 sb_data_p = (u32 *)&sb_data_e2;
4068 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4069 } else {
4070 memset(&sb_data_e1x, 0,
4071 sizeof(struct hc_status_block_data_e1x));
4072 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4073 sb_data_e1x.common.p_func.vf_id = 0xff;
4074 sb_data_e1x.common.p_func.vf_valid = false;
4075 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4076 sb_data_e1x.common.same_igu_sb_1b = true;
4077 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4078 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4079 hc_sm_p = sb_data_e1x.common.state_machine;
4080 hc_index_p = sb_data_e1x.index_data;
4081 sb_data_p = (u32 *)&sb_data_e1x;
4082 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4083 }
523224a3
DK		 4084
4085 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4086 igu_sb_id, igu_seg_id);
4087 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4088 igu_sb_id, igu_seg_id);
4089
4090 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4091
4092 /* write indecies to HW */
4093 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4094}
4095
4096static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4097 u8 sb_index, u8 disable, u16 usec)
4098{
4099 int port = BP_PORT(bp);
4100 u8 ticks = usec / BNX2X_BTR;
4101
4102 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4103
4104 disable = disable ? 1 : (usec ? 0 : 1);
4105 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4106}
4107
4108static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4109 u16 tx_usec, u16 rx_usec)
4110{
4111 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4112 false, rx_usec);
4113 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4114 false, tx_usec);
4115}
f2e0899f 4116
523224a3
DK		 4117static void bnx2x_init_def_sb(struct bnx2x *bp)
4118{
4119 struct host_sp_status_block *def_sb = bp->def_status_blk;
4120 dma_addr_t mapping = bp->def_status_blk_mapping;
4121 int igu_sp_sb_index;
4122 int igu_seg_id;
34f80b04
EG		 4123 int port = BP_PORT(bp);
4124 int func = BP_FUNC(bp);
523224a3 4125 int reg_offset;
a2fbb9ea 4126 u64 section;
523224a3
DK		 4127 int index;
4128 struct hc_sp_status_block_data sp_sb_data;
4129 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4130
f2e0899f
DK		 4131 if (CHIP_INT_MODE_IS_BC(bp)) {
4132 igu_sp_sb_index = DEF_SB_IGU_ID;
4133 igu_seg_id = HC_SEG_ACCESS_DEF;
4134 } else {
4135 igu_sp_sb_index = bp->igu_dsb_id;
4136 igu_seg_id = IGU_SEG_ACCESS_DEF;
4137 }
a2fbb9ea
ET		 4138
4139 /* ATTN */
523224a3 4140 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4141 atten_status_block);
523224a3 4142 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4143
49d66772
ET		 4144 bp->attn_state = 0;
4145
a2fbb9ea
ET		 4146 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4147 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
34f80b04 4148 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4149 int sindex;
4150 /* take care of sig[0]..sig[4] */
4151 for (sindex = 0; sindex < 4; sindex++)
4152 bp->attn_group[index].sig[sindex] =
4153 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f
DK		 4154
4155 if (CHIP_IS_E2(bp))
4156 /*
4157 * enable5 is separate from the rest of the registers,
4158 * and therefore the address skip is 4
4159 * and not 16 between the different groups
4160 */
4161 bp->attn_group[index].sig[4] = REG_RD(bp,
4162 reg_offset + 0x10 + 0x4*index);
4163 else
4164 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4165 }
4166
f2e0899f
DK		 4167 if (bp->common.int_block == INT_BLOCK_HC) {
4168 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4169 HC_REG_ATTN_MSG0_ADDR_L);
4170
4171 REG_WR(bp, reg_offset, U64_LO(section));
4172 REG_WR(bp, reg_offset + 4, U64_HI(section));
4173 } else if (CHIP_IS_E2(bp)) {
4174 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4175 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4176 }
a2fbb9ea 4177
523224a3
DK		 4178 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4179 sp_sb);
a2fbb9ea 4180
523224a3 4181 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4182
523224a3
DK		 4183 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4184 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4185 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4186 sp_sb_data.igu_seg_id = igu_seg_id;
4187 sp_sb_data.p_func.pf_id = func;
f2e0899f 4188 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4189 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4190
523224a3 4191 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4192
bb2a0f7a 4193 bp->stats_pending = 0;
66e855f3 4194 bp->set_mac_pending = 0;
bb2a0f7a 4195
523224a3 4196 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4197}
4198
9f6c9258 4199void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4200{
a2fbb9ea
ET		 4201 int i;
4202
ec6ba945 4203 for_each_eth_queue(bp, i)
523224a3
DK		 4204 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4205 bp->rx_ticks, bp->tx_ticks);
a2fbb9ea
ET		 4206}
4207
a2fbb9ea
ET		 4208static void bnx2x_init_sp_ring(struct bnx2x *bp)
4209{
a2fbb9ea 4210 spin_lock_init(&bp->spq_lock);
8fe23fbd 4211 atomic_set(&bp->spq_left, MAX_SPQ_PENDING);
a2fbb9ea 4212
a2fbb9ea 4213 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 4214 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4215 bp->spq_prod_bd = bp->spq;
4216 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 4217}
4218
523224a3 4219static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 4220{
4221 int i;
523224a3
DK		 4222 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4223 union event_ring_elem *elem =
4224 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 4225
523224a3
DK		 4226 elem->next_page.addr.hi =
4227 cpu_to_le32(U64_HI(bp->eq_mapping +
4228 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4229 elem->next_page.addr.lo =
4230 cpu_to_le32(U64_LO(bp->eq_mapping +
4231 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 4232 }
523224a3
DK		 4233 bp->eq_cons = 0;
4234 bp->eq_prod = NUM_EQ_DESC;
4235 bp->eq_cons_sb = BNX2X_EQ_INDEX;
a2fbb9ea
ET		 4236}
4237
4238static void bnx2x_init_ind_table(struct bnx2x *bp)
4239{
26c8fa4d 4240 int func = BP_FUNC(bp);
a2fbb9ea
ET		 4241 int i;
4242
555f6c78 4243 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
a2fbb9ea
ET		 4244 return;
4245
555f6c78
EG		 4246 DP(NETIF_MSG_IFUP,
4247 "Initializing indirection table multi_mode %d\n", bp->multi_mode);
a2fbb9ea 4248 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
34f80b04 4249 REG_WR8(bp, BAR_TSTRORM_INTMEM +
26c8fa4d 4250 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
ec6ba945
VZ		 4251 bp->fp->cl_id + (i % (bp->num_queues -
4252 NONE_ETH_CONTEXT_USE)));
a2fbb9ea
ET		 4253}
4254
9f6c9258 4255void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
a2fbb9ea 4256{
34f80b04 4257 int mode = bp->rx_mode;
ec6ba945 4258 int port = BP_PORT(bp);
523224a3 4259 u16 cl_id;
ec6ba945 4260 u32 def_q_filters = 0;
523224a3 4261
581ce43d
EG		 4262 /* All but management unicast packets should pass to the host as well */
4263 u32 llh_mask =
4264 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4265 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4266 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4267 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
a2fbb9ea 4268
a2fbb9ea
ET		 4269 switch (mode) {
4270 case BNX2X_RX_MODE_NONE: /* no Rx */
ec6ba945
VZ		 4271 def_q_filters = BNX2X_ACCEPT_NONE;
4272#ifdef BCM_CNIC
4273 if (!NO_FCOE(bp)) {
4274 cl_id = bnx2x_fcoe(bp, cl_id);
4275 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4276 }
4277#endif
a2fbb9ea 4278 break;
356e2385 4279
a2fbb9ea 4280 case BNX2X_RX_MODE_NORMAL:
ec6ba945
VZ		 4281 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4282 BNX2X_ACCEPT_MULTICAST;
4283#ifdef BCM_CNIC
4284 cl_id = bnx2x_fcoe(bp, cl_id);
4285 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4286 BNX2X_ACCEPT_MULTICAST);
4287#endif
a2fbb9ea 4288 break;
356e2385 4289
a2fbb9ea 4290 case BNX2X_RX_MODE_ALLMULTI:
ec6ba945
VZ		 4291 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4292 BNX2X_ACCEPT_ALL_MULTICAST;
4293#ifdef BCM_CNIC
4294 cl_id = bnx2x_fcoe(bp, cl_id);
4295 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4296 BNX2X_ACCEPT_MULTICAST);
4297#endif
a2fbb9ea 4298 break;
356e2385 4299
a2fbb9ea 4300 case BNX2X_RX_MODE_PROMISC:
ec6ba945
VZ		 4301 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4302#ifdef BCM_CNIC
4303 cl_id = bnx2x_fcoe(bp, cl_id);
4304 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4305 BNX2X_ACCEPT_MULTICAST);
4306#endif
581ce43d
EG		 4307 /* pass management unicast packets as well */
4308 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
a2fbb9ea 4309 break;
356e2385 4310
a2fbb9ea 4311 default:
34f80b04
EG		 4312 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4313 break;
a2fbb9ea
ET		 4314 }
4315
ec6ba945
VZ		 4316 cl_id = BP_L_ID(bp);
4317 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4318
581ce43d 4319 REG_WR(bp,
ec6ba945
VZ		 4320 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4321 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
581ce43d 4322
523224a3
DK		 4323 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4324 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
ec6ba945
VZ		 4325 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4326 "unmatched_ucast 0x%x\n", mode,
523224a3
DK		 4327 bp->mac_filters.ucast_drop_all,
4328 bp->mac_filters.mcast_drop_all,
4329 bp->mac_filters.bcast_drop_all,
4330 bp->mac_filters.ucast_accept_all,
4331 bp->mac_filters.mcast_accept_all,
ec6ba945
VZ		 4332 bp->mac_filters.bcast_accept_all,
4333 bp->mac_filters.unmatched_unicast
523224a3 4334 );
a2fbb9ea 4335
523224a3 4336 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
a2fbb9ea
ET		 4337}
4338
471de716
EG		 4339static void bnx2x_init_internal_common(struct bnx2x *bp)
4340{
4341 int i;
4342
523224a3 4343 if (!CHIP_IS_E1(bp)) {
de832a55 4344
523224a3
DK		 4345 /* xstorm needs to know whether to add ovlan to packets or not,
4346 * in switch-independent we'll write 0 to here... */
34f80b04 4347 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4348 bp->mf_mode);
34f80b04 4349 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4350 bp->mf_mode);
34f80b04 4351 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4352 bp->mf_mode);
34f80b04 4353 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
fb3bff17 4354 bp->mf_mode);
34f80b04
EG		 4355 }
4356
0793f83f
DK		 4357 if (IS_MF_SI(bp))
4358 /*
4359 * In switch independent mode, the TSTORM needs to accept
4360 * packets that failed classification, since approximate match
4361 * mac addresses aren't written to NIG LLH
4362 */
4363 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4364 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4365
523224a3
DK		 4366 /* Zero this manually as its initialization is
4367 currently missing in the initTool */
4368 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 4369 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 4370 USTORM_AGG_DATA_OFFSET + i * 4, 0);
f2e0899f
DK		 4371 if (CHIP_IS_E2(bp)) {
4372 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4373 CHIP_INT_MODE_IS_BC(bp) ?
4374 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4375 }
523224a3 4376}
8a1c38d1 4377
523224a3
DK		 4378static void bnx2x_init_internal_port(struct bnx2x *bp)
4379{
4380 /* port */
e4901dde 4381 bnx2x_dcb_init_intmem_pfc(bp);
a2fbb9ea
ET		 4382}
4383
471de716
EG		 4384static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4385{
4386 switch (load_code) {
4387 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 4388 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 4389 bnx2x_init_internal_common(bp);
4390 /* no break */
4391
4392 case FW_MSG_CODE_DRV_LOAD_PORT:
4393 bnx2x_init_internal_port(bp);
4394 /* no break */
4395
4396 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 4397 /* internal memory per function is
4398 initialized inside bnx2x_pf_init */
471de716
EG		 4399 break;
4400
4401 default:
4402 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4403 break;
4404 }
4405}
4406
523224a3
DK		 4407static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4408{
4409 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4410
4411 fp->state = BNX2X_FP_STATE_CLOSED;
4412
4413 fp->index = fp->cid = fp_idx;
4414 fp->cl_id = BP_L_ID(bp) + fp_idx;
4415 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4416 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4417 /* qZone id equals to FW (per path) client id */
4418 fp->cl_qzone_id = fp->cl_id +
f2e0899f
DK		 4419 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4420 ETH_MAX_RX_CLIENTS_E1H);
523224a3 4421 /* init shortcut */
f2e0899f
DK		 4422 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4423 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
523224a3
DK		 4424 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4425 /* Setup SB indicies */
4426 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4427 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4428
4429 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4430 "cl_id %d fw_sb %d igu_sb %d\n",
4431 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4432 fp->igu_sb_id);
4433 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4434 fp->fw_sb_id, fp->igu_sb_id);
4435
4436 bnx2x_update_fpsb_idx(fp);
4437}
4438
9f6c9258 4439void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 4440{
4441 int i;
4442
ec6ba945 4443 for_each_eth_queue(bp, i)
523224a3 4444 bnx2x_init_fp_sb(bp, i);
37b091ba 4445#ifdef BCM_CNIC
ec6ba945
VZ		 4446 if (!NO_FCOE(bp))
4447 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 4448
4449 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4450 BNX2X_VF_ID_INVALID, false,
4451 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4452
37b091ba 4453#endif
a2fbb9ea 4454
16119785
EG		 4455 /* ensure status block indices were read */
4456 rmb();
4457
523224a3 4458 bnx2x_init_def_sb(bp);
5c862848 4459 bnx2x_update_dsb_idx(bp);
a2fbb9ea 4460 bnx2x_init_rx_rings(bp);
523224a3 4461 bnx2x_init_tx_rings(bp);
a2fbb9ea 4462 bnx2x_init_sp_ring(bp);
523224a3 4463 bnx2x_init_eq_ring(bp);
471de716 4464 bnx2x_init_internal(bp, load_code);
523224a3 4465 bnx2x_pf_init(bp);
a2fbb9ea 4466 bnx2x_init_ind_table(bp);
0ef00459
EG		 4467 bnx2x_stats_init(bp);
4468
4469 /* At this point, we are ready for interrupts */
4470 atomic_set(&bp->intr_sem, 0);
4471
4472 /* flush all before enabling interrupts */
4473 mb();
4474 mmiowb();
4475
615f8fd9 4476 bnx2x_int_enable(bp);
eb8da205
EG		 4477
4478 /* Check for SPIO5 */
4479 bnx2x_attn_int_deasserted0(bp,
4480 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4481 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 4482}
4483
4484/* end of nic init */
4485
4486/*
4487 * gzip service functions
4488 */
4489
4490static int bnx2x_gunzip_init(struct bnx2x *bp)
4491{
1a983142
FT		 4492 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4493 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 4494 if (bp->gunzip_buf == NULL)
4495 goto gunzip_nomem1;
4496
4497 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4498 if (bp->strm == NULL)
4499 goto gunzip_nomem2;
4500
4501 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4502 GFP_KERNEL);
4503 if (bp->strm->workspace == NULL)
4504 goto gunzip_nomem3;
4505
4506 return 0;
4507
4508gunzip_nomem3:
4509 kfree(bp->strm);
4510 bp->strm = NULL;
4511
4512gunzip_nomem2:
1a983142
FT		 4513 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4514 bp->gunzip_mapping);
a2fbb9ea
ET		 4515 bp->gunzip_buf = NULL;
4516
4517gunzip_nomem1:
cdaa7cb8
VZ		 4518 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4519 " un-compression\n");
a2fbb9ea
ET		 4520 return -ENOMEM;
4521}
4522
4523static void bnx2x_gunzip_end(struct bnx2x *bp)
4524{
4525 kfree(bp->strm->workspace);
a2fbb9ea
ET		 4526 kfree(bp->strm);
4527 bp->strm = NULL;
4528
4529 if (bp->gunzip_buf) {
1a983142
FT		 4530 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4531 bp->gunzip_mapping);
a2fbb9ea
ET		 4532 bp->gunzip_buf = NULL;
4533 }
4534}
4535
94a78b79 4536static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 4537{
4538 int n, rc;
4539
4540 /* check gzip header */
94a78b79
VZ		 4541 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4542 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 4543 return -EINVAL;
94a78b79 4544 }
a2fbb9ea
ET		 4545
4546 n = 10;
4547
34f80b04 4548#define FNAME 0x8
a2fbb9ea
ET		 4549
4550 if (zbuf[3] & FNAME)
4551 while ((zbuf[n++] != 0) && (n < len));
4552
94a78b79 4553 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 4554 bp->strm->avail_in = len - n;
4555 bp->strm->next_out = bp->gunzip_buf;
4556 bp->strm->avail_out = FW_BUF_SIZE;
4557
4558 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4559 if (rc != Z_OK)
4560 return rc;
4561
4562 rc = zlib_inflate(bp->strm, Z_FINISH);
4563 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 4564 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4565 bp->strm->msg);
a2fbb9ea
ET		 4566
4567 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4568 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 4569 netdev_err(bp->dev, "Firmware decompression error:"
4570 " gunzip_outlen (%d) not aligned\n",
4571 bp->gunzip_outlen);
a2fbb9ea
ET		 4572 bp->gunzip_outlen >>= 2;
4573
4574 zlib_inflateEnd(bp->strm);
4575
4576 if (rc == Z_STREAM_END)
4577 return 0;
4578
4579 return rc;
4580}
4581
4582/* nic load/unload */
4583
4584/*
34f80b04 4585 * General service functions
a2fbb9ea
ET		 4586 */
4587
4588/* send a NIG loopback debug packet */
4589static void bnx2x_lb_pckt(struct bnx2x *bp)
4590{
a2fbb9ea 4591 u32 wb_write[3];
a2fbb9ea
ET		 4592
4593 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 4594 wb_write[0] = 0x55555555;
4595 wb_write[1] = 0x55555555;
34f80b04 4596 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 4597 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4598
4599 /* NON-IP protocol */
a2fbb9ea
ET		 4600 wb_write[0] = 0x09000000;
4601 wb_write[1] = 0x55555555;
34f80b04 4602 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 4603 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 4604}
4605
4606/* some of the internal memories
4607 * are not directly readable from the driver
4608 * to test them we send debug packets
4609 */
4610static int bnx2x_int_mem_test(struct bnx2x *bp)
4611{
4612 int factor;
4613 int count, i;
4614 u32 val = 0;
4615
ad8d3948 4616 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 4617 factor = 120;
ad8d3948
EG		 4618 else if (CHIP_REV_IS_EMUL(bp))
4619 factor = 200;
4620 else
a2fbb9ea 4621 factor = 1;
a2fbb9ea 4622
a2fbb9ea
ET		 4623 /* Disable inputs of parser neighbor blocks */
4624 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4625 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4626 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4627 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4628
4629 /* Write 0 to parser credits for CFC search request */
4630 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4631
4632 /* send Ethernet packet */
4633 bnx2x_lb_pckt(bp);
4634
4635 /* TODO do i reset NIG statistic? */
4636 /* Wait until NIG register shows 1 packet of size 0x10 */
4637 count = 1000 * factor;
4638 while (count) {
34f80b04 4639
a2fbb9ea
ET		 4640 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4641 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4642 if (val == 0x10)
4643 break;
4644
4645 msleep(10);
4646 count--;
4647 }
4648 if (val != 0x10) {
4649 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4650 return -1;
4651 }
4652
4653 /* Wait until PRS register shows 1 packet */
4654 count = 1000 * factor;
4655 while (count) {
4656 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 4657 if (val == 1)
4658 break;
4659
4660 msleep(10);
4661 count--;
4662 }
4663 if (val != 0x1) {
4664 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4665 return -2;
4666 }
4667
4668 /* Reset and init BRB, PRS */
34f80b04 4669 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 4670 msleep(50);
34f80b04 4671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 4672 msleep(50);
94a78b79
VZ		 4673 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4674 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
a2fbb9ea
ET		 4675
4676 DP(NETIF_MSG_HW, "part2\n");
4677
4678 /* Disable inputs of parser neighbor blocks */
4679 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4680 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4681 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 4682 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 4683
4684 /* Write 0 to parser credits for CFC search request */
4685 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4686
4687 /* send 10 Ethernet packets */
4688 for (i = 0; i < 10; i++)
4689 bnx2x_lb_pckt(bp);
4690
4691 /* Wait until NIG register shows 10 + 1
4692 packets of size 11*0x10 = 0xb0 */
4693 count = 1000 * factor;
4694 while (count) {
34f80b04 4695
a2fbb9ea
ET		 4696 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4697 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 4698 if (val == 0xb0)
4699 break;
4700
4701 msleep(10);
4702 count--;
4703 }
4704 if (val != 0xb0) {
4705 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4706 return -3;
4707 }
4708
4709 /* Wait until PRS register shows 2 packets */
4710 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4711 if (val != 2)
4712 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4713
4714 /* Write 1 to parser credits for CFC search request */
4715 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4716
4717 /* Wait until PRS register shows 3 packets */
4718 msleep(10 * factor);
4719 /* Wait until NIG register shows 1 packet of size 0x10 */
4720 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4721 if (val != 3)
4722 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4723
4724 /* clear NIG EOP FIFO */
4725 for (i = 0; i < 11; i++)
4726 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4727 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4728 if (val != 1) {
4729 BNX2X_ERR("clear of NIG failed\n");
4730 return -4;
4731 }
4732
4733 /* Reset and init BRB, PRS, NIG */
4734 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4735 msleep(50);
4736 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4737 msleep(50);
94a78b79
VZ		 4738 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4739 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
37b091ba 4740#ifndef BCM_CNIC
a2fbb9ea
ET		 4741 /* set NIC mode */
4742 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4743#endif
4744
4745 /* Enable inputs of parser neighbor blocks */
4746 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4747 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4748 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 4749 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 4750
4751 DP(NETIF_MSG_HW, "done\n");
4752
4753 return 0; /* OK */
4754}
4755
4a33bc03 4756static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 4757{
4758 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
f2e0899f
DK		 4759 if (CHIP_IS_E2(bp))
4760 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4761 else
4762 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 4763 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4764 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 4765 /*
4766 * mask read length error interrupts in brb for parser
4767 * (parsing unit and 'checksum and crc' unit)
4768 * these errors are legal (PU reads fixed length and CAC can cause
4769 * read length error on truncated packets)
4770 */
4771 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 4772 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4773 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4774 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4775 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4776 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 4777/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4778/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4779 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4780 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4781 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 4782/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4783/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4784 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4785 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4786 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4787 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 4788/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4789/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 4790
34f80b04
EG		 4791 if (CHIP_REV_IS_FPGA(bp))
4792 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
f2e0899f
DK		 4793 else if (CHIP_IS_E2(bp))
4794 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4795 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4796 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4797 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4798 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4799 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 4800 else
4801 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 4802 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4803 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4804 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04
EG		 4805/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4806/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 4807 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4808 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 4809/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 4810 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 4811}
4812
81f75bbf
EG		 4813static void bnx2x_reset_common(struct bnx2x *bp)
4814{
4815 /* reset_common */
4816 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4817 0xd3ffff7f);
4818 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4819}
4820
573f2035
EG		 4821static void bnx2x_init_pxp(struct bnx2x *bp)
4822{
4823 u16 devctl;
4824 int r_order, w_order;
4825
4826 pci_read_config_word(bp->pdev,
4827 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4828 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4829 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4830 if (bp->mrrs == -1)
4831 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4832 else {
4833 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4834 r_order = bp->mrrs;
4835 }
4836
4837 bnx2x_init_pxp_arb(bp, r_order, w_order);
4838}
fd4ef40d
EG		 4839
4840static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4841{
2145a920 4842 int is_required;
fd4ef40d 4843 u32 val;
2145a920 4844 int port;
fd4ef40d 4845
2145a920
VZ		 4846 if (BP_NOMCP(bp))
4847 return;
4848
4849 is_required = 0;
fd4ef40d
EG		 4850 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4851 SHARED_HW_CFG_FAN_FAILURE_MASK;
4852
4853 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4854 is_required = 1;
4855
4856 /*
4857 * The fan failure mechanism is usually related to the PHY type since
4858 * the power consumption of the board is affected by the PHY. Currently,
4859 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4860 */
4861 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4862 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 4863 is_required |=
d90d96ba
YR		 4864 bnx2x_fan_failure_det_req(
4865 bp,
4866 bp->common.shmem_base,
a22f0788 4867 bp->common.shmem2_base,
d90d96ba 4868 port);
fd4ef40d
EG		 4869 }
4870
4871 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4872
4873 if (is_required == 0)
4874 return;
4875
4876 /* Fan failure is indicated by SPIO 5 */
4877 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4878 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4879
4880 /* set to active low mode */
4881 val = REG_RD(bp, MISC_REG_SPIO_INT);
4882 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 4883 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 4884 REG_WR(bp, MISC_REG_SPIO_INT, val);
4885
4886 /* enable interrupt to signal the IGU */
4887 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4888 val |= (1 << MISC_REGISTERS_SPIO_5);
4889 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4890}
4891
f2e0899f
DK		 4892static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4893{
4894 u32 offset = 0;
4895
4896 if (CHIP_IS_E1(bp))
4897 return;
4898 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4899 return;
4900
4901 switch (BP_ABS_FUNC(bp)) {
4902 case 0:
4903 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4904 break;
4905 case 1:
4906 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4907 break;
4908 case 2:
4909 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4910 break;
4911 case 3:
4912 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4913 break;
4914 case 4:
4915 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4916 break;
4917 case 5:
4918 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4919 break;
4920 case 6:
4921 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4922 break;
4923 case 7:
4924 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4925 break;
4926 default:
4927 return;
4928 }
4929
4930 REG_WR(bp, offset, pretend_func_num);
4931 REG_RD(bp, offset);
4932 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4933}
4934
4935static void bnx2x_pf_disable(struct bnx2x *bp)
4936{
4937 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4938 val &= ~IGU_PF_CONF_FUNC_EN;
4939
4940 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4941 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4942 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4943}
4944
523224a3 4945static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
a2fbb9ea 4946{
a2fbb9ea 4947 u32 val, i;
a2fbb9ea 4948
f2e0899f 4949 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 4950
81f75bbf 4951 bnx2x_reset_common(bp);
34f80b04
EG		 4952 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4953 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
a2fbb9ea 4954
94a78b79 4955 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
f2e0899f 4956 if (!CHIP_IS_E1(bp))
fb3bff17 4957 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
a2fbb9ea 4958
f2e0899f
DK		 4959 if (CHIP_IS_E2(bp)) {
4960 u8 fid;
4961
4962 /**
4963 * 4-port mode or 2-port mode we need to turn of master-enable
4964 * for everyone, after that, turn it back on for self.
4965 * so, we disregard multi-function or not, and always disable
4966 * for all functions on the given path, this means 0,2,4,6 for
4967 * path 0 and 1,3,5,7 for path 1
4968 */
4969 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
4970 if (fid == BP_ABS_FUNC(bp)) {
4971 REG_WR(bp,
4972 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
4973 1);
4974 continue;
4975 }
4976
4977 bnx2x_pretend_func(bp, fid);
4978 /* clear pf enable */
4979 bnx2x_pf_disable(bp);
4980 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
4981 }
4982 }
a2fbb9ea 4983
94a78b79 4984 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
34f80b04
EG		 4985 if (CHIP_IS_E1(bp)) {
4986 /* enable HW interrupt from PXP on USDM overflow
4987 bit 16 on INT_MASK_0 */
4988 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4989 }
a2fbb9ea 4990
94a78b79 4991 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
34f80b04 4992 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 4993
4994#ifdef __BIG_ENDIAN
34f80b04
EG		 4995 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
4996 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
4997 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
4998 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
4999 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5000 /* make sure this value is 0 */
5001 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5002
5003/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5004 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5005 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5006 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5007 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5008#endif
5009
523224a3
DK		 5010 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5011
34f80b04
EG		 5012 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5013 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5014
34f80b04
EG		 5015 /* let the HW do it's magic ... */
5016 msleep(100);
5017 /* finish PXP init */
5018 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5019 if (val != 1) {
5020 BNX2X_ERR("PXP2 CFG failed\n");
5021 return -EBUSY;
5022 }
5023 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5024 if (val != 1) {
5025 BNX2X_ERR("PXP2 RD_INIT failed\n");
5026 return -EBUSY;
5027 }
a2fbb9ea 5028
f2e0899f
DK		 5029 /* Timers bug workaround E2 only. We need to set the entire ILT to
5030 * have entries with value "0" and valid bit on.
5031 * This needs to be done by the first PF that is loaded in a path
5032 * (i.e. common phase)
5033 */
5034 if (CHIP_IS_E2(bp)) {
5035 struct ilt_client_info ilt_cli;
5036 struct bnx2x_ilt ilt;
5037 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5038 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5039
b595076a 5040 /* initialize dummy TM client */
f2e0899f
DK		 5041 ilt_cli.start = 0;
5042 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5043 ilt_cli.client_num = ILT_CLIENT_TM;
5044
5045 /* Step 1: set zeroes to all ilt page entries with valid bit on
5046 * Step 2: set the timers first/last ilt entry to point
5047 * to the entire range to prevent ILT range error for 3rd/4th
5048 * vnic (this code assumes existance of the vnic)
5049 *
5050 * both steps performed by call to bnx2x_ilt_client_init_op()
5051 * with dummy TM client
5052 *
5053 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5054 * and his brother are split registers
5055 */
5056 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5057 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5058 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5059
5060 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5061 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5062 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5063 }
5064
5065
34f80b04
EG		 5066 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5067 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 5068
f2e0899f
DK		 5069 if (CHIP_IS_E2(bp)) {
5070 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5071 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5072 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5073
5074 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5075
5076 /* let the HW do it's magic ... */
5077 do {
5078 msleep(200);
5079 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5080 } while (factor-- && (val != 1));
5081
5082 if (val != 1) {
5083 BNX2X_ERR("ATC_INIT failed\n");
5084 return -EBUSY;
5085 }
5086 }
5087
94a78b79 5088 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
a2fbb9ea 5089
34f80b04
EG		 5090 /* clean the DMAE memory */
5091 bp->dmae_ready = 1;
5092 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
a2fbb9ea 5093
94a78b79
VZ		 5094 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5095 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5096 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5097 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
a2fbb9ea 5098
34f80b04
EG		 5099 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5100 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5101 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5102 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5103
94a78b79 5104 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
37b091ba 5105
f2e0899f
DK		 5106 if (CHIP_MODE_IS_4_PORT(bp))
5107 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
f85582f8 5108
523224a3
DK		 5109 /* QM queues pointers table */
5110 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5111
34f80b04
EG		 5112 /* soft reset pulse */
5113 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5114 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 5115
37b091ba 5116#ifdef BCM_CNIC
94a78b79 5117 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
a2fbb9ea 5118#endif
a2fbb9ea 5119
94a78b79 5120 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
523224a3
DK		 5121 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5122
34f80b04
EG		 5123 if (!CHIP_REV_IS_SLOW(bp)) {
5124 /* enable hw interrupt from doorbell Q */
5125 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5126 }
a2fbb9ea 5127
94a78b79 5128 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5129 if (CHIP_MODE_IS_4_PORT(bp)) {
5130 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5131 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5132 }
5133
94a78b79 5134 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
26c8fa4d 5135 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
37b091ba 5136#ifndef BCM_CNIC
3196a88a
EG		 5137 /* set NIC mode */
5138 REG_WR(bp, PRS_REG_NIC_MODE, 1);
37b091ba 5139#endif
f2e0899f 5140 if (!CHIP_IS_E1(bp))
0793f83f 5141 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
f85582f8 5142
f2e0899f
DK		 5143 if (CHIP_IS_E2(bp)) {
5144 /* Bit-map indicating which L2 hdrs may appear after the
5145 basic Ethernet header */
0793f83f 5146 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5147 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5148 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5149 }
a2fbb9ea 5150
94a78b79
VZ		 5151 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5152 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5153 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5154 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
a2fbb9ea 5155
ca00392c
EG		 5156 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5157 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5158 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5159 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
a2fbb9ea 5160
94a78b79
VZ		 5161 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5162 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5163 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5164 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
a2fbb9ea 5165
f2e0899f
DK		 5166 if (CHIP_MODE_IS_4_PORT(bp))
5167 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5168
34f80b04
EG		 5169 /* sync semi rtc */
5170 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5171 0x80000000);
5172 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5173 0x80000000);
a2fbb9ea 5174
94a78b79
VZ		 5175 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5176 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5177 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
a2fbb9ea 5178
f2e0899f 5179 if (CHIP_IS_E2(bp)) {
0793f83f 5180 int has_ovlan = IS_MF_SD(bp);
f2e0899f
DK		 5181 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5182 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5183 }
5184
34f80b04 5185 REG_WR(bp, SRC_REG_SOFT_RST, 1);
c68ed255
TH		 5186 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5187 REG_WR(bp, i, random32());
f85582f8 5188
94a78b79 5189 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
37b091ba
MC		 5190#ifdef BCM_CNIC
5191 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5192 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5193 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5194 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5195 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5196 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5197 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5198 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5199 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5200 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5201#endif
34f80b04 5202 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 5203
34f80b04
EG		 5204 if (sizeof(union cdu_context) != 1024)
5205 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 5206 dev_alert(&bp->pdev->dev, "please adjust the size "
5207 "of cdu_context(%ld)\n",
7995c64e 5208 (long)sizeof(union cdu_context));
a2fbb9ea 5209
94a78b79 5210 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
34f80b04
EG		 5211 val = (4 << 24) + (0 << 12) + 1024;
5212 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 5213
94a78b79 5214 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
34f80b04 5215 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 5216 /* enable context validation interrupt from CFC */
5217 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5218
5219 /* set the thresholds to prevent CFC/CDU race */
5220 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 5221
94a78b79 5222 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
f2e0899f
DK		 5223
5224 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5225 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5226
5227 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
94a78b79 5228 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
a2fbb9ea 5229
94a78b79 5230 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
34f80b04
EG		 5231 /* Reset PCIE errors for debug */
5232 REG_WR(bp, 0x2814, 0xffffffff);
5233 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 5234
f2e0899f
DK		 5235 if (CHIP_IS_E2(bp)) {
5236 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5237 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5238 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5239 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5240 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5241 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5242 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5243 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5244 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5245 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5246 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5247 }
5248
94a78b79 5249 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
94a78b79 5250 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
94a78b79 5251 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
94a78b79 5252 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
34f80b04 5253
94a78b79 5254 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
f2e0899f 5255 if (!CHIP_IS_E1(bp)) {
fb3bff17 5256 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
0793f83f 5257 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04 5258 }
f2e0899f
DK		 5259 if (CHIP_IS_E2(bp)) {
5260 /* Bit-map indicating which L2 hdrs may appear after the
5261 basic Ethernet header */
0793f83f 5262 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
f2e0899f 5263 }
34f80b04
EG		 5264
5265 if (CHIP_REV_IS_SLOW(bp))
5266 msleep(200);
5267
5268 /* finish CFC init */
5269 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5270 if (val != 1) {
5271 BNX2X_ERR("CFC LL_INIT failed\n");
5272 return -EBUSY;
5273 }
5274 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5275 if (val != 1) {
5276 BNX2X_ERR("CFC AC_INIT failed\n");
5277 return -EBUSY;
5278 }
5279 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5280 if (val != 1) {
5281 BNX2X_ERR("CFC CAM_INIT failed\n");
5282 return -EBUSY;
5283 }
5284 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 5285
f2e0899f
DK		 5286 if (CHIP_IS_E1(bp)) {
5287 /* read NIG statistic
5288 to see if this is our first up since powerup */
5289 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5290 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 5291
f2e0899f
DK		 5292 /* do internal memory self test */
5293 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5294 BNX2X_ERR("internal mem self test failed\n");
5295 return -EBUSY;
5296 }
34f80b04
EG		 5297 }
5298
fd4ef40d
EG		 5299 bnx2x_setup_fan_failure_detection(bp);
5300
34f80b04
EG		 5301 /* clear PXP2 attentions */
5302 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 5303
4a33bc03
VZ		 5304 bnx2x_enable_blocks_attention(bp);
5305 if (CHIP_PARITY_ENABLED(bp))
5306 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 5307
6bbca910 5308 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 5309 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5310 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5311 CHIP_IS_E1x(bp)) {
5312 u32 shmem_base[2], shmem2_base[2];
5313 shmem_base[0] = bp->common.shmem_base;
5314 shmem2_base[0] = bp->common.shmem2_base;
5315 if (CHIP_IS_E2(bp)) {
5316 shmem_base[1] =
5317 SHMEM2_RD(bp, other_shmem_base_addr);
5318 shmem2_base[1] =
5319 SHMEM2_RD(bp, other_shmem2_base_addr);
5320 }
5321 bnx2x_acquire_phy_lock(bp);
5322 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5323 bp->common.chip_id);
5324 bnx2x_release_phy_lock(bp);
5325 }
6bbca910
YR		 5326 } else
5327 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5328
34f80b04
EG		 5329 return 0;
5330}
a2fbb9ea 5331
523224a3 5332static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 5333{
5334 int port = BP_PORT(bp);
94a78b79 5335 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
1c06328c 5336 u32 low, high;
34f80b04 5337 u32 val;
a2fbb9ea 5338
cdaa7cb8 5339 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 5340
5341 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 5342
94a78b79 5343 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
94a78b79 5344 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
ca00392c 5345
f2e0899f
DK		 5346 /* Timers bug workaround: disables the pf_master bit in pglue at
5347 * common phase, we need to enable it here before any dmae access are
5348 * attempted. Therefore we manually added the enable-master to the
5349 * port phase (it also happens in the function phase)
5350 */
5351 if (CHIP_IS_E2(bp))
5352 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5353
ca00392c
EG		 5354 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5355 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5356 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
94a78b79 5357 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
a2fbb9ea 5358
523224a3
DK		 5359 /* QM cid (connection) count */
5360 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 5361
523224a3 5362#ifdef BCM_CNIC
94a78b79 5363 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
37b091ba
MC		 5364 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5365 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 5366#endif
cdaa7cb8 5367
94a78b79 5368 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
1c06328c 5369
f2e0899f
DK		 5370 if (CHIP_MODE_IS_4_PORT(bp))
5371 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5372
5373 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5374 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5375 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5376 /* no pause for emulation and FPGA */
5377 low = 0;
5378 high = 513;
5379 } else {
5380 if (IS_MF(bp))
5381 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5382 else if (bp->dev->mtu > 4096) {
5383 if (bp->flags & ONE_PORT_FLAG)
5384 low = 160;
5385 else {
5386 val = bp->dev->mtu;
5387 /* (24*1024 + val*4)/256 */
5388 low = 96 + (val/64) +
5389 ((val % 64) ? 1 : 0);
5390 }
5391 } else
5392 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5393 high = low + 56; /* 14*1024/256 */
5394 }
5395 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5396 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 5397 }
1c06328c 5398
f2e0899f
DK		 5399 if (CHIP_MODE_IS_4_PORT(bp)) {
5400 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5401 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5402 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5403 BRB1_REG_MAC_GUARANTIED_0), 40);
5404 }
1c06328c 5405
94a78b79 5406 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
ca00392c 5407
94a78b79 5408 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
94a78b79 5409 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
94a78b79 5410 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
94a78b79 5411 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
356e2385 5412
94a78b79
VZ		 5413 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5414 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5415 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5416 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
f2e0899f
DK		 5417 if (CHIP_MODE_IS_4_PORT(bp))
5418 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
356e2385 5419
94a78b79 5420 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
94a78b79 5421 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
34f80b04 5422
94a78b79 5423 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
a2fbb9ea 5424
f2e0899f
DK		 5425 if (!CHIP_IS_E2(bp)) {
5426 /* configure PBF to work without PAUSE mtu 9000 */
5427 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 5428
f2e0899f
DK		 5429 /* update threshold */
5430 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5431 /* update init credit */
5432 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 5433
f2e0899f
DK		 5434 /* probe changes */
5435 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5436 udelay(50);
5437 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5438 }
a2fbb9ea 5439
37b091ba
MC		 5440#ifdef BCM_CNIC
5441 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
a2fbb9ea 5442#endif
94a78b79 5443 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
94a78b79 5444 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
34f80b04
EG		 5445
5446 if (CHIP_IS_E1(bp)) {
5447 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5448 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5449 }
94a78b79 5450 bnx2x_init_block(bp, HC_BLOCK, init_stage);
34f80b04 5451
f2e0899f
DK		 5452 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5453
94a78b79 5454 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
34f80b04
EG		 5455 /* init aeu_mask_attn_func_0/1:
5456 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5457 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5458 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 5459 val = IS_MF(bp) ? 0xF7 : 0x7;
5460 /* Enable DCBX attention for all but E1 */
5461 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5462 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 5463
94a78b79 5464 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
94a78b79 5465 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
94a78b79 5466 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
94a78b79 5467 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
94a78b79 5468 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
356e2385 5469
94a78b79 5470 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
34f80b04
EG		 5471
5472 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5473
f2e0899f 5474 if (!CHIP_IS_E1(bp)) {
fb3bff17 5475 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 5476 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 5477 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 5478
f2e0899f
DK		 5479 if (CHIP_IS_E2(bp)) {
5480 val = 0;
5481 switch (bp->mf_mode) {
5482 case MULTI_FUNCTION_SD:
5483 val = 1;
5484 break;
5485 case MULTI_FUNCTION_SI:
5486 val = 2;
5487 break;
5488 }
5489
5490 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5491 NIG_REG_LLH0_CLS_TYPE), val);
5492 }
1c06328c
EG		 5493 {
5494 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5495 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5496 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5497 }
34f80b04
EG		 5498 }
5499
94a78b79 5500 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
94a78b79 5501 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
d90d96ba 5502 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
a22f0788 5503 bp->common.shmem2_base, port)) {
4d295db0
EG		 5504 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5505 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5506 val = REG_RD(bp, reg_addr);
f1410647 5507 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 5508 REG_WR(bp, reg_addr, val);
f1410647 5509 }
c18487ee 5510 bnx2x__link_reset(bp);
a2fbb9ea 5511
34f80b04
EG		 5512 return 0;
5513}
5514
34f80b04
EG		 5515static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5516{
5517 int reg;
5518
f2e0899f 5519 if (CHIP_IS_E1(bp))
34f80b04 5520 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 5521 else
5522 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 5523
5524 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5525}
5526
f2e0899f
DK		 5527static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5528{
5529 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5530}
5531
5532static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5533{
5534 u32 i, base = FUNC_ILT_BASE(func);
5535 for (i = base; i < base + ILT_PER_FUNC; i++)
5536 bnx2x_ilt_wr(bp, i, 0);
5537}
5538
523224a3 5539static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 5540{
5541 int port = BP_PORT(bp);
5542 int func = BP_FUNC(bp);
523224a3
DK		 5543 struct bnx2x_ilt *ilt = BP_ILT(bp);
5544 u16 cdu_ilt_start;
8badd27a 5545 u32 addr, val;
f4a66897
VZ		 5546 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5547 int i, main_mem_width;
34f80b04 5548
cdaa7cb8 5549 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 5550
8badd27a 5551 /* set MSI reconfigure capability */
f2e0899f
DK		 5552 if (bp->common.int_block == INT_BLOCK_HC) {
5553 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5554 val = REG_RD(bp, addr);
5555 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5556 REG_WR(bp, addr, val);
5557 }
8badd27a 5558
523224a3
DK		 5559 ilt = BP_ILT(bp);
5560 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 5561
523224a3
DK		 5562 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5563 ilt->lines[cdu_ilt_start + i].page =
5564 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5565 ilt->lines[cdu_ilt_start + i].page_mapping =
5566 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5567 /* cdu ilt pages are allocated manually so there's no need to
5568 set the size */
37b091ba 5569 }
523224a3 5570 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 5571
523224a3
DK		 5572#ifdef BCM_CNIC
5573 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 5574
523224a3
DK		 5575 /* T1 hash bits value determines the T1 number of entries */
5576 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5577#endif
37b091ba 5578
523224a3
DK		 5579#ifndef BCM_CNIC
5580 /* set NIC mode */
5581 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5582#endif /* BCM_CNIC */
37b091ba 5583
f2e0899f
DK		 5584 if (CHIP_IS_E2(bp)) {
5585 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5586
5587 /* Turn on a single ISR mode in IGU if driver is going to use
5588 * INT#x or MSI
5589 */
5590 if (!(bp->flags & USING_MSIX_FLAG))
5591 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5592 /*
5593 * Timers workaround bug: function init part.
5594 * Need to wait 20msec after initializing ILT,
5595 * needed to make sure there are no requests in
5596 * one of the PXP internal queues with "old" ILT addresses
5597 */
5598 msleep(20);
5599 /*
5600 * Master enable - Due to WB DMAE writes performed before this
5601 * register is re-initialized as part of the regular function
5602 * init
5603 */
5604 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5605 /* Enable the function in IGU */
5606 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5607 }
5608
523224a3 5609 bp->dmae_ready = 1;
34f80b04 5610
523224a3
DK		 5611 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5612
f2e0899f
DK		 5613 if (CHIP_IS_E2(bp))
5614 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5615
523224a3
DK		 5616 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5617 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5618 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5619 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5620 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5621 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5622 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5623 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5624 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5625
f2e0899f
DK		 5626 if (CHIP_IS_E2(bp)) {
5627 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5628 BP_PATH(bp));
5629 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5630 BP_PATH(bp));
5631 }
5632
5633 if (CHIP_MODE_IS_4_PORT(bp))
5634 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5635
5636 if (CHIP_IS_E2(bp))
5637 REG_WR(bp, QM_REG_PF_EN, 1);
5638
523224a3 5639 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5640
5641 if (CHIP_MODE_IS_4_PORT(bp))
5642 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5643
523224a3
DK		 5644 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5645 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5646 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5647 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5648 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5649 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5650 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5651 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5652 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5653 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5654 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
f2e0899f
DK		 5655 if (CHIP_IS_E2(bp))
5656 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5657
523224a3
DK		 5658 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5659
5660 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
34f80b04 5661
f2e0899f
DK		 5662 if (CHIP_IS_E2(bp))
5663 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5664
fb3bff17 5665 if (IS_MF(bp)) {
34f80b04 5666 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 5667 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 5668 }
5669
523224a3
DK		 5670 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5671
34f80b04 5672 /* HC init per function */
f2e0899f
DK		 5673 if (bp->common.int_block == INT_BLOCK_HC) {
5674 if (CHIP_IS_E1H(bp)) {
5675 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5676
5677 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5678 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5679 }
5680 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5681
5682 } else {
5683 int num_segs, sb_idx, prod_offset;
5684
34f80b04
EG		 5685 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5686
f2e0899f
DK		 5687 if (CHIP_IS_E2(bp)) {
5688 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5689 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5690 }
5691
5692 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5693
5694 if (CHIP_IS_E2(bp)) {
5695 int dsb_idx = 0;
5696 /**
5697 * Producer memory:
5698 * E2 mode: address 0-135 match to the mapping memory;
5699 * 136 - PF0 default prod; 137 - PF1 default prod;
5700 * 138 - PF2 default prod; 139 - PF3 default prod;
5701 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5702 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5703 * 144-147 reserved.
5704 *
5705 * E1.5 mode - In backward compatible mode;
5706 * for non default SB; each even line in the memory
5707 * holds the U producer and each odd line hold
5708 * the C producer. The first 128 producers are for
5709 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5710 * producers are for the DSB for each PF.
5711 * Each PF has five segments: (the order inside each
5712 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5713 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5714 * 144-147 attn prods;
5715 */
5716 /* non-default-status-blocks */
5717 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5718 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5719 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5720 prod_offset = (bp->igu_base_sb + sb_idx) *
5721 num_segs;
5722
5723 for (i = 0; i < num_segs; i++) {
5724 addr = IGU_REG_PROD_CONS_MEMORY +
5725 (prod_offset + i) * 4;
5726 REG_WR(bp, addr, 0);
5727 }
5728 /* send consumer update with value 0 */
5729 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5730 USTORM_ID, 0, IGU_INT_NOP, 1);
5731 bnx2x_igu_clear_sb(bp,
5732 bp->igu_base_sb + sb_idx);
5733 }
5734
5735 /* default-status-blocks */
5736 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5737 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5738
5739 if (CHIP_MODE_IS_4_PORT(bp))
5740 dsb_idx = BP_FUNC(bp);
5741 else
5742 dsb_idx = BP_E1HVN(bp);
5743
5744 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5745 IGU_BC_BASE_DSB_PROD + dsb_idx :
5746 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5747
5748 for (i = 0; i < (num_segs * E1HVN_MAX);
5749 i += E1HVN_MAX) {
5750 addr = IGU_REG_PROD_CONS_MEMORY +
5751 (prod_offset + i)*4;
5752 REG_WR(bp, addr, 0);
5753 }
5754 /* send consumer update with 0 */
5755 if (CHIP_INT_MODE_IS_BC(bp)) {
5756 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5757 USTORM_ID, 0, IGU_INT_NOP, 1);
5758 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5759 CSTORM_ID, 0, IGU_INT_NOP, 1);
5760 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5761 XSTORM_ID, 0, IGU_INT_NOP, 1);
5762 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5763 TSTORM_ID, 0, IGU_INT_NOP, 1);
5764 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5765 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5766 } else {
5767 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5768 USTORM_ID, 0, IGU_INT_NOP, 1);
5769 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5770 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5771 }
5772 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5773
5774 /* !!! these should become driver const once
5775 rf-tool supports split-68 const */
5776 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5777 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5778 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5779 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5780 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5781 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5782 }
34f80b04 5783 }
34f80b04 5784
c14423fe 5785 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 5786 REG_WR(bp, 0x2114, 0xffffffff);
5787 REG_WR(bp, 0x2120, 0xffffffff);
523224a3
DK		 5788
5789 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5790 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5791 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5792 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5793 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5794 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5795
f4a66897
VZ		 5796 if (CHIP_IS_E1x(bp)) {
5797 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5798 main_mem_base = HC_REG_MAIN_MEMORY +
5799 BP_PORT(bp) * (main_mem_size * 4);
5800 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5801 main_mem_width = 8;
5802
5803 val = REG_RD(bp, main_mem_prty_clr);
5804 if (val)
5805 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5806 "block during "
5807 "function init (0x%x)!\n", val);
5808
5809 /* Clear "false" parity errors in MSI-X table */
5810 for (i = main_mem_base;
5811 i < main_mem_base + main_mem_size * 4;
5812 i += main_mem_width) {
5813 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5814 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5815 i, main_mem_width / 4);
5816 }
5817 /* Clear HC parity attention */
5818 REG_RD(bp, main_mem_prty_clr);
5819 }
5820
b7737c9b 5821 bnx2x_phy_probe(&bp->link_params);
f85582f8 5822
34f80b04
EG		 5823 return 0;
5824}
5825
9f6c9258 5826int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
34f80b04 5827{
523224a3 5828 int rc = 0;
a2fbb9ea 5829
34f80b04 5830 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
f2e0899f 5831 BP_ABS_FUNC(bp), load_code);
a2fbb9ea 5832
34f80b04
EG		 5833 bp->dmae_ready = 0;
5834 mutex_init(&bp->dmae_mutex);
54016b26
EG		 5835 rc = bnx2x_gunzip_init(bp);
5836 if (rc)
5837 return rc;
a2fbb9ea 5838
34f80b04
EG		 5839 switch (load_code) {
5840 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5841 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
523224a3 5842 rc = bnx2x_init_hw_common(bp, load_code);
34f80b04
EG		 5843 if (rc)
5844 goto init_hw_err;
5845 /* no break */
5846
5847 case FW_MSG_CODE_DRV_LOAD_PORT:
523224a3 5848 rc = bnx2x_init_hw_port(bp);
34f80b04
EG		 5849 if (rc)
5850 goto init_hw_err;
5851 /* no break */
5852
5853 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3 5854 rc = bnx2x_init_hw_func(bp);
34f80b04
EG		 5855 if (rc)
5856 goto init_hw_err;
5857 break;
5858
5859 default:
5860 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5861 break;
5862 }
5863
5864 if (!BP_NOMCP(bp)) {
f2e0899f 5865 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 5866
5867 bp->fw_drv_pulse_wr_seq =
f2e0899f 5868 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
a2fbb9ea 5869 DRV_PULSE_SEQ_MASK);
6fe49bb9
EG		 5870 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5871 }
a2fbb9ea 5872
34f80b04
EG		 5873init_hw_err:
5874 bnx2x_gunzip_end(bp);
5875
5876 return rc;
a2fbb9ea
ET		 5877}
5878
9f6c9258 5879void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea
ET		 5880{
5881
5882#define BNX2X_PCI_FREE(x, y, size) \
5883 do { \
5884 if (x) { \
523224a3 5885 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
a2fbb9ea
ET		 5886 x = NULL; \
5887 y = 0; \
5888 } \
5889 } while (0)
5890
5891#define BNX2X_FREE(x) \
5892 do { \
5893 if (x) { \
523224a3 5894 kfree((void *)x); \
a2fbb9ea
ET		 5895 x = NULL; \
5896 } \
5897 } while (0)
5898
5899 int i;
5900
5901 /* fastpath */
555f6c78 5902 /* Common */
a2fbb9ea 5903 for_each_queue(bp, i) {
ec6ba945
VZ		 5904#ifdef BCM_CNIC
5905 /* FCoE client uses default status block */
5906 if (IS_FCOE_IDX(i)) {
5907 union host_hc_status_block *sb =
5908 &bnx2x_fp(bp, i, status_blk);
5909 memset(sb, 0, sizeof(union host_hc_status_block));
5910 bnx2x_fp(bp, i, status_blk_mapping) = 0;
5911 } else {
5912#endif
555f6c78 5913 /* status blocks */
f2e0899f
DK		 5914 if (CHIP_IS_E2(bp))
5915 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),
5916 bnx2x_fp(bp, i, status_blk_mapping),
5917 sizeof(struct host_hc_status_block_e2));
5918 else
5919 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),
5920 bnx2x_fp(bp, i, status_blk_mapping),
5921 sizeof(struct host_hc_status_block_e1x));
ec6ba945
VZ		 5922#ifdef BCM_CNIC
5923 }
5924#endif
555f6c78
EG		 5925 }
5926 /* Rx */
ec6ba945 5927 for_each_rx_queue(bp, i) {
a2fbb9ea 5928
555f6c78 5929 /* fastpath rx rings: rx_buf rx_desc rx_comp */
a2fbb9ea
ET		 5930 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5931 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5932 bnx2x_fp(bp, i, rx_desc_mapping),
5933 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5934
5935 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5936 bnx2x_fp(bp, i, rx_comp_mapping),
5937 sizeof(struct eth_fast_path_rx_cqe) *
5938 NUM_RCQ_BD);
a2fbb9ea 5939
7a9b2557 5940 /* SGE ring */
32626230 5941 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
7a9b2557
VZ		 5942 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5943 bnx2x_fp(bp, i, rx_sge_mapping),
5944 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5945 }
555f6c78 5946 /* Tx */
ec6ba945 5947 for_each_tx_queue(bp, i) {
555f6c78
EG		 5948
5949 /* fastpath tx rings: tx_buf tx_desc */
5950 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5951 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5952 bnx2x_fp(bp, i, tx_desc_mapping),
ca00392c 5953 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
555f6c78 5954 }
a2fbb9ea
ET		 5955 /* end of fastpath */
5956
5957 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 5958 sizeof(struct host_sp_status_block));
a2fbb9ea
ET		 5959
5960 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 5961 sizeof(struct bnx2x_slowpath));
a2fbb9ea 5962
523224a3
DK		 5963 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5964 bp->context.size);
5965
5966 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5967
5968 BNX2X_FREE(bp->ilt->lines);
f85582f8 5969
37b091ba 5970#ifdef BCM_CNIC
f2e0899f
DK		 5971 if (CHIP_IS_E2(bp))
5972 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5973 sizeof(struct host_hc_status_block_e2));
5974 else
5975 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5976 sizeof(struct host_hc_status_block_e1x));
f85582f8 5977
523224a3 5978 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 5979#endif
f85582f8 5980
7a9b2557 5981 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 5982
523224a3
DK		 5983 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5984 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5985
a2fbb9ea
ET		 5986#undef BNX2X_PCI_FREE
5987#undef BNX2X_KFREE
5988}
5989
f2e0899f
DK		 5990static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
5991{
5992 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
5993 if (CHIP_IS_E2(bp)) {
5994 bnx2x_fp(bp, index, sb_index_values) =
5995 (__le16 *)status_blk.e2_sb->sb.index_values;
5996 bnx2x_fp(bp, index, sb_running_index) =
5997 (__le16 *)status_blk.e2_sb->sb.running_index;
5998 } else {
5999 bnx2x_fp(bp, index, sb_index_values) =
6000 (__le16 *)status_blk.e1x_sb->sb.index_values;
6001 bnx2x_fp(bp, index, sb_running_index) =
6002 (__le16 *)status_blk.e1x_sb->sb.running_index;
6003 }
6004}
6005
9f6c9258 6006int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6007{
a2fbb9ea
ET		 6008#define BNX2X_PCI_ALLOC(x, y, size) \
6009 do { \
1a983142 6010 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
9f6c9258
DK		 6011 if (x == NULL) \
6012 goto alloc_mem_err; \
6013 memset(x, 0, size); \
6014 } while (0)
a2fbb9ea 6015
9f6c9258
DK		 6016#define BNX2X_ALLOC(x, size) \
6017 do { \
523224a3 6018 x = kzalloc(size, GFP_KERNEL); \
9f6c9258
DK		 6019 if (x == NULL) \
6020 goto alloc_mem_err; \
9f6c9258 6021 } while (0)
a2fbb9ea 6022
9f6c9258 6023 int i;
a2fbb9ea 6024
9f6c9258
DK		 6025 /* fastpath */
6026 /* Common */
a2fbb9ea 6027 for_each_queue(bp, i) {
f2e0899f 6028 union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);
9f6c9258 6029 bnx2x_fp(bp, i, bp) = bp;
9f6c9258 6030 /* status blocks */
ec6ba945
VZ		 6031#ifdef BCM_CNIC
6032 if (!IS_FCOE_IDX(i)) {
6033#endif
6034 if (CHIP_IS_E2(bp))
6035 BNX2X_PCI_ALLOC(sb->e2_sb,
6036 &bnx2x_fp(bp, i, status_blk_mapping),
6037 sizeof(struct host_hc_status_block_e2));
6038 else
6039 BNX2X_PCI_ALLOC(sb->e1x_sb,
6040 &bnx2x_fp(bp, i, status_blk_mapping),
6041 sizeof(struct host_hc_status_block_e1x));
6042#ifdef BCM_CNIC
6043 }
6044#endif
f2e0899f 6045 set_sb_shortcuts(bp, i);
a2fbb9ea 6046 }
9f6c9258
DK		 6047 /* Rx */
6048 for_each_queue(bp, i) {
a2fbb9ea 6049
9f6c9258
DK		 6050 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6051 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6052 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6053 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6054 &bnx2x_fp(bp, i, rx_desc_mapping),
6055 sizeof(struct eth_rx_bd) * NUM_RX_BD);
555f6c78 6056
9f6c9258
DK		 6057 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6058 &bnx2x_fp(bp, i, rx_comp_mapping),
6059 sizeof(struct eth_fast_path_rx_cqe) *
6060 NUM_RCQ_BD);
a2fbb9ea 6061
9f6c9258
DK		 6062 /* SGE ring */
6063 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
6064 sizeof(struct sw_rx_page) * NUM_RX_SGE);
6065 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
6066 &bnx2x_fp(bp, i, rx_sge_mapping),
6067 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6068 }
6069 /* Tx */
6070 for_each_queue(bp, i) {
8badd27a 6071
9f6c9258
DK		 6072 /* fastpath tx rings: tx_buf tx_desc */
6073 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6074 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6075 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6076 &bnx2x_fp(bp, i, tx_desc_mapping),
6077 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
8badd27a 6078 }
9f6c9258 6079 /* end of fastpath */
8badd27a 6080
523224a3 6081#ifdef BCM_CNIC
f2e0899f
DK		 6082 if (CHIP_IS_E2(bp))
6083 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6084 sizeof(struct host_hc_status_block_e2));
6085 else
6086 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6087 sizeof(struct host_hc_status_block_e1x));
8badd27a 6088
523224a3
DK		 6089 /* allocate searcher T2 table */
6090 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6091#endif
a2fbb9ea 6092
8badd27a 6093
523224a3
DK		 6094 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6095 sizeof(struct host_sp_status_block));
a2fbb9ea 6096
523224a3
DK		 6097 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6098 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6099
523224a3 6100 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
f85582f8 6101
523224a3
DK		 6102 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6103 bp->context.size);
65abd74d 6104
523224a3 6105 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6106
523224a3
DK		 6107 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6108 goto alloc_mem_err;
65abd74d 6109
9f6c9258
DK		 6110 /* Slow path ring */
6111 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6112
523224a3
DK		 6113 /* EQ */
6114 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6115 BCM_PAGE_SIZE * NUM_EQ_PAGES);
9f6c9258 6116 return 0;
e1510706 6117
9f6c9258
DK		 6118alloc_mem_err:
6119 bnx2x_free_mem(bp);
6120 return -ENOMEM;
e1510706 6121
9f6c9258
DK		 6122#undef BNX2X_PCI_ALLOC
6123#undef BNX2X_ALLOC
65abd74d
YG		 6124}
6125
a2fbb9ea
ET		 6126/*
6127 * Init service functions
6128 */
8d96286a 6129static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6130 int *state_p, int flags);
6131
523224a3 6132int bnx2x_func_start(struct bnx2x *bp)
a2fbb9ea 6133{
523224a3 6134 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
a2fbb9ea 6135
523224a3
DK		 6136 /* Wait for completion */
6137 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6138 WAIT_RAMROD_COMMON);
6139}
a2fbb9ea 6140
8d96286a 6141static int bnx2x_func_stop(struct bnx2x *bp)
523224a3
DK		 6142{
6143 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
a2fbb9ea 6144
523224a3
DK		 6145 /* Wait for completion */
6146 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6147 0, &(bp->state), WAIT_RAMROD_COMMON);
a2fbb9ea
ET		 6148}
6149
e665bfda 6150/**
f85582f8 6151 * Sets a MAC in a CAM for a few L2 Clients for E1x chips
e665bfda
MC		 6152 *
6153 * @param bp driver descriptor
6154 * @param set set or clear an entry (1 or 0)
6155 * @param mac pointer to a buffer containing a MAC
6156 * @param cl_bit_vec bit vector of clients to register a MAC for
6157 * @param cam_offset offset in a CAM to use
523224a3 6158 * @param is_bcast is the set MAC a broadcast address (for E1 only)
e665bfda 6159 */
215faf9c 6160static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
f85582f8
DK		 6161 u32 cl_bit_vec, u8 cam_offset,
6162 u8 is_bcast)
34f80b04 6163{
523224a3
DK		 6164 struct mac_configuration_cmd *config =
6165 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6166 int ramrod_flags = WAIT_RAMROD_COMMON;
6167
6168 bp->set_mac_pending = 1;
6169 smp_wmb();
6170
8d9c5f34 6171 config->hdr.length = 1;
e665bfda
MC		 6172 config->hdr.offset = cam_offset;
6173 config->hdr.client_id = 0xff;
34f80b04
EG		 6174 config->hdr.reserved1 = 0;
6175
6176 /* primary MAC */
6177 config->config_table[0].msb_mac_addr =
e665bfda 6178 swab16(*(u16 *)&mac[0]);
34f80b04 6179 config->config_table[0].middle_mac_addr =
e665bfda 6180 swab16(*(u16 *)&mac[2]);
34f80b04 6181 config->config_table[0].lsb_mac_addr =
e665bfda 6182 swab16(*(u16 *)&mac[4]);
ca00392c 6183 config->config_table[0].clients_bit_vector =
e665bfda 6184 cpu_to_le32(cl_bit_vec);
34f80b04 6185 config->config_table[0].vlan_id = 0;
523224a3 6186 config->config_table[0].pf_id = BP_FUNC(bp);
3101c2bc 6187 if (set)
523224a3
DK		 6188 SET_FLAG(config->config_table[0].flags,
6189 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6190 T_ETH_MAC_COMMAND_SET);
3101c2bc 6191 else
523224a3
DK		 6192 SET_FLAG(config->config_table[0].flags,
6193 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6194 T_ETH_MAC_COMMAND_INVALIDATE);
34f80b04 6195
523224a3
DK		 6196 if (is_bcast)
6197 SET_FLAG(config->config_table[0].flags,
6198 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6199
6200 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
3101c2bc 6201 (set ? "setting" : "clearing"),
34f80b04
EG		 6202 config->config_table[0].msb_mac_addr,
6203 config->config_table[0].middle_mac_addr,
523224a3 6204 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
34f80b04 6205
523224a3 6206 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
34f80b04 6207 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3
DK		 6208 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6209
6210 /* Wait for a completion */
6211 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
34f80b04
EG		 6212}
6213
8d96286a 6214static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6215 int *state_p, int flags)
a2fbb9ea
ET		 6216{
6217 /* can take a while if any port is running */
8b3a0f0b 6218 int cnt = 5000;
523224a3
DK		 6219 u8 poll = flags & WAIT_RAMROD_POLL;
6220 u8 common = flags & WAIT_RAMROD_COMMON;
a2fbb9ea 6221
c14423fe
ET		 6222 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6223 poll ? "polling" : "waiting", state, idx);
a2fbb9ea
ET		 6224
6225 might_sleep();
34f80b04 6226 while (cnt--) {
a2fbb9ea 6227 if (poll) {
523224a3
DK		 6228 if (common)
6229 bnx2x_eq_int(bp);
6230 else {
6231 bnx2x_rx_int(bp->fp, 10);
6232 /* if index is different from 0
6233 * the reply for some commands will
6234 * be on the non default queue
6235 */
6236 if (idx)
6237 bnx2x_rx_int(&bp->fp[idx], 10);
6238 }
a2fbb9ea 6239 }
a2fbb9ea 6240
3101c2bc 6241 mb(); /* state is changed by bnx2x_sp_event() */
8b3a0f0b
EG		 6242 if (*state_p == state) {
6243#ifdef BNX2X_STOP_ON_ERROR
6244 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6245#endif
a2fbb9ea 6246 return 0;
8b3a0f0b 6247 }
a2fbb9ea 6248
a2fbb9ea 6249 msleep(1);
e3553b29
EG		 6250
6251 if (bp->panic)
6252 return -EIO;
a2fbb9ea
ET		 6253 }
6254
a2fbb9ea 6255 /* timeout! */
49d66772
ET		 6256 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6257 poll ? "polling" : "waiting", state, idx);
34f80b04
EG		 6258#ifdef BNX2X_STOP_ON_ERROR
6259 bnx2x_panic();
6260#endif
a2fbb9ea 6261
49d66772 6262 return -EBUSY;
a2fbb9ea
ET		 6263}
6264
8d96286a 6265static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
e665bfda 6266{
f2e0899f
DK		 6267 if (CHIP_IS_E1H(bp))
6268 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6269 else if (CHIP_MODE_IS_4_PORT(bp))
6270 return BP_FUNC(bp) * 32 + rel_offset;
6271 else
6272 return BP_VN(bp) * 32 + rel_offset;
523224a3
DK		 6273}
6274
0793f83f
DK		 6275/**
6276 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6277 * relevant. In addition, current implementation is tuned for a
6278 * single ETH MAC.
6279 *
6280 * When multiple unicast ETH MACs PF configuration in switch
6281 * independent mode is required (NetQ, multiple netdev MACs,
6282 * etc.), consider better utilisation of 16 per function MAC
6283 * entries in the LLH memory.
6284 */
6285enum {
6286 LLH_CAM_ISCSI_ETH_LINE = 0,
6287 LLH_CAM_ETH_LINE,
6288 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6289};
6290
6291static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6292 int set,
6293 unsigned char *dev_addr,
6294 int index)
6295{
6296 u32 wb_data[2];
6297 u32 mem_offset, ena_offset, mem_index;
6298 /**
6299 * indexes mapping:
6300 * 0..7 - goes to MEM
6301 * 8..15 - goes to MEM2
6302 */
6303
6304 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6305 return;
6306
6307 /* calculate memory start offset according to the mapping
6308 * and index in the memory */
6309 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6310 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6311 NIG_REG_LLH0_FUNC_MEM;
6312 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6313 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6314 mem_index = index;
6315 } else {
6316 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6317 NIG_REG_P0_LLH_FUNC_MEM2;
6318 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6319 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6320 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6321 }
6322
6323 if (set) {
6324 /* LLH_FUNC_MEM is a u64 WB register */
6325 mem_offset += 8*mem_index;
6326
6327 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6328 (dev_addr[4] << 8) | dev_addr[5]);
6329 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6330
6331 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6332 }
6333
6334 /* enable/disable the entry */
6335 REG_WR(bp, ena_offset + 4*mem_index, set);
6336
6337}
6338
523224a3
DK		 6339void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6340{
6341 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6342 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
e665bfda 6343
523224a3
DK		 6344 /* networking MAC */
6345 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6346 (1 << bp->fp->cl_id), cam_offset , 0);
e665bfda 6347
0793f83f
DK		 6348 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6349
523224a3
DK		 6350 if (CHIP_IS_E1(bp)) {
6351 /* broadcast MAC */
215faf9c
JP		 6352 static const u8 bcast[ETH_ALEN] = {
6353 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6354 };
523224a3
DK		 6355 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6356 }
e665bfda 6357}
523224a3
DK		 6358static void bnx2x_set_e1_mc_list(struct bnx2x *bp, u8 offset)
6359{
6360 int i = 0, old;
6361 struct net_device *dev = bp->dev;
6362 struct netdev_hw_addr *ha;
6363 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6364 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6365
6366 netdev_for_each_mc_addr(ha, dev) {
6367 /* copy mac */
6368 config_cmd->config_table[i].msb_mac_addr =
6369 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6370 config_cmd->config_table[i].middle_mac_addr =
6371 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6372 config_cmd->config_table[i].lsb_mac_addr =
6373 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
e665bfda 6374
523224a3
DK		 6375 config_cmd->config_table[i].vlan_id = 0;
6376 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6377 config_cmd->config_table[i].clients_bit_vector =
6378 cpu_to_le32(1 << BP_L_ID(bp));
6379
6380 SET_FLAG(config_cmd->config_table[i].flags,
6381 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6382 T_ETH_MAC_COMMAND_SET);
6383
6384 DP(NETIF_MSG_IFUP,
6385 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6386 config_cmd->config_table[i].msb_mac_addr,
6387 config_cmd->config_table[i].middle_mac_addr,
6388 config_cmd->config_table[i].lsb_mac_addr);
6389 i++;
6390 }
6391 old = config_cmd->hdr.length;
6392 if (old > i) {
6393 for (; i < old; i++) {
6394 if (CAM_IS_INVALID(config_cmd->
6395 config_table[i])) {
6396 /* already invalidated */
6397 break;
6398 }
6399 /* invalidate */
6400 SET_FLAG(config_cmd->config_table[i].flags,
6401 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6402 T_ETH_MAC_COMMAND_INVALIDATE);
6403 }
6404 }
6405
6406 config_cmd->hdr.length = i;
6407 config_cmd->hdr.offset = offset;
6408 config_cmd->hdr.client_id = 0xff;
6409 config_cmd->hdr.reserved1 = 0;
6410
6411 bp->set_mac_pending = 1;
6412 smp_wmb();
6413
6414 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6415 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6416}
6417static void bnx2x_invlidate_e1_mc_list(struct bnx2x *bp)
e665bfda 6418{
523224a3
DK		 6419 int i;
6420 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6421 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6422 int ramrod_flags = WAIT_RAMROD_COMMON;
6423
6424 bp->set_mac_pending = 1;
e665bfda
MC		 6425 smp_wmb();
6426
523224a3
DK		 6427 for (i = 0; i < config_cmd->hdr.length; i++)
6428 SET_FLAG(config_cmd->config_table[i].flags,
6429 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6430 T_ETH_MAC_COMMAND_INVALIDATE);
6431
6432 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6433 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
e665bfda
MC		 6434
6435 /* Wait for a completion */
523224a3
DK		 6436 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6437 ramrod_flags);
6438
e665bfda
MC		 6439}
6440
993ac7b5
MC		 6441#ifdef BCM_CNIC
6442/**
6443 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
6444 * MAC(s). This function will wait until the ramdord completion
6445 * returns.
6446 *
6447 * @param bp driver handle
6448 * @param set set or clear the CAM entry
6449 *
6450 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6451 */
8d96286a 6452static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
993ac7b5 6453{
523224a3
DK		 6454 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6455 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
ec6ba945
VZ		 6456 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6457 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
523224a3 6458 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
993ac7b5
MC		 6459
6460 /* Send a SET_MAC ramrod */
523224a3
DK		 6461 bnx2x_set_mac_addr_gen(bp, set, bp->iscsi_mac, cl_bit_vec,
6462 cam_offset, 0);
0793f83f
DK		 6463
6464 bnx2x_set_mac_in_nig(bp, set, bp->iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
ec6ba945
VZ		 6465
6466 return 0;
6467}
6468
6469/**
6470 * Set FCoE L2 MAC(s) at the next enties in the CAM after the
6471 * ETH MAC(s). This function will wait until the ramdord
6472 * completion returns.
6473 *
6474 * @param bp driver handle
6475 * @param set set or clear the CAM entry
6476 *
6477 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6478 */
6479int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6480{
6481 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6482 /**
6483 * CAM allocation for E1H
6484 * eth unicasts: by func number
6485 * iscsi: by func number
6486 * fip unicast: by func number
6487 * fip multicast: by func number
6488 */
6489 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6490 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6491
6492 return 0;
6493}
6494
6495int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6496{
6497 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6498
6499 /**
6500 * CAM allocation for E1H
6501 * eth unicasts: by func number
6502 * iscsi: by func number
6503 * fip unicast: by func number
6504 * fip multicast: by func number
6505 */
6506 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6507 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6508
993ac7b5
MC		 6509 return 0;
6510}
6511#endif
6512
523224a3
DK		 6513static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6514 struct bnx2x_client_init_params *params,
6515 u8 activate,
6516 struct client_init_ramrod_data *data)
6517{
6518 /* Clear the buffer */
6519 memset(data, 0, sizeof(*data));
6520
6521 /* general */
6522 data->general.client_id = params->rxq_params.cl_id;
6523 data->general.statistics_counter_id = params->rxq_params.stat_id;
6524 data->general.statistics_en_flg =
6525 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
ec6ba945
VZ		 6526 data->general.is_fcoe_flg =
6527 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
523224a3
DK		 6528 data->general.activate_flg = activate;
6529 data->general.sp_client_id = params->rxq_params.spcl_id;
6530
6531 /* Rx data */
6532 data->rx.tpa_en_flg =
6533 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6534 data->rx.vmqueue_mode_en_flg = 0;
6535 data->rx.cache_line_alignment_log_size =
6536 params->rxq_params.cache_line_log;
6537 data->rx.enable_dynamic_hc =
6538 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6539 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6540 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6541 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6542
6543 /* We don't set drop flags */
6544 data->rx.drop_ip_cs_err_flg = 0;
6545 data->rx.drop_tcp_cs_err_flg = 0;
6546 data->rx.drop_ttl0_flg = 0;
6547 data->rx.drop_udp_cs_err_flg = 0;
6548
6549 data->rx.inner_vlan_removal_enable_flg =
6550 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6551 data->rx.outer_vlan_removal_enable_flg =
6552 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6553 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6554 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6555 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6556 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6557 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6558 data->rx.bd_page_base.lo =
6559 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6560 data->rx.bd_page_base.hi =
6561 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6562 data->rx.sge_page_base.lo =
6563 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6564 data->rx.sge_page_base.hi =
6565 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6566 data->rx.cqe_page_base.lo =
6567 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6568 data->rx.cqe_page_base.hi =
6569 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6570 data->rx.is_leading_rss =
6571 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6572 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6573
6574 /* Tx data */
6575 data->tx.enforce_security_flg = 0; /* VF specific */
6576 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6577 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6578 data->tx.mtu = 0; /* VF specific */
6579 data->tx.tx_bd_page_base.lo =
6580 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6581 data->tx.tx_bd_page_base.hi =
6582 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6583
6584 /* flow control data */
6585 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6586 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6587 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6588 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6589 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6590 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6591 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6592
6593 data->fc.safc_group_num = params->txq_params.cos;
6594 data->fc.safc_group_en_flg =
6595 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
ec6ba945
VZ		 6596 data->fc.traffic_type =
6597 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6598 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
523224a3
DK		 6599}
6600
6601static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6602{
6603 /* ustorm cxt validation */
6604 cxt->ustorm_ag_context.cdu_usage =
6605 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6606 ETH_CONNECTION_TYPE);
6607 /* xcontext validation */
6608 cxt->xstorm_ag_context.cdu_reserved =
6609 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6610 ETH_CONNECTION_TYPE);
6611}
6612
8d96286a 6613static int bnx2x_setup_fw_client(struct bnx2x *bp,
6614 struct bnx2x_client_init_params *params,
6615 u8 activate,
6616 struct client_init_ramrod_data *data,
6617 dma_addr_t data_mapping)
523224a3
DK		 6618{
6619 u16 hc_usec;
6620 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6621 int ramrod_flags = 0, rc;
6622
6623 /* HC and context validation values */
6624 hc_usec = params->txq_params.hc_rate ?
6625 1000000 / params->txq_params.hc_rate : 0;
6626 bnx2x_update_coalesce_sb_index(bp,
6627 params->txq_params.fw_sb_id,
6628 params->txq_params.sb_cq_index,
6629 !(params->txq_params.flags & QUEUE_FLG_HC),
6630 hc_usec);
6631
6632 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6633
6634 hc_usec = params->rxq_params.hc_rate ?
6635 1000000 / params->rxq_params.hc_rate : 0;
6636 bnx2x_update_coalesce_sb_index(bp,
6637 params->rxq_params.fw_sb_id,
6638 params->rxq_params.sb_cq_index,
6639 !(params->rxq_params.flags & QUEUE_FLG_HC),
6640 hc_usec);
6641
6642 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6643 params->rxq_params.cid);
6644
6645 /* zero stats */
6646 if (params->txq_params.flags & QUEUE_FLG_STATS)
6647 storm_memset_xstats_zero(bp, BP_PORT(bp),
6648 params->txq_params.stat_id);
6649
6650 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6651 storm_memset_ustats_zero(bp, BP_PORT(bp),
6652 params->rxq_params.stat_id);
6653 storm_memset_tstats_zero(bp, BP_PORT(bp),
6654 params->rxq_params.stat_id);
6655 }
6656
6657 /* Fill the ramrod data */
6658 bnx2x_fill_cl_init_data(bp, params, activate, data);
6659
6660 /* SETUP ramrod.
6661 *
6662 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6663 * barrier except from mmiowb() is needed to impose a
6664 * proper ordering of memory operations.
6665 */
6666 mmiowb();
a2fbb9ea 6667
a2fbb9ea 6668
523224a3
DK		 6669 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6670 U64_HI(data_mapping), U64_LO(data_mapping), 0);
a2fbb9ea 6671
34f80b04 6672 /* Wait for completion */
523224a3
DK		 6673 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6674 params->ramrod_params.index,
6675 params->ramrod_params.pstate,
6676 ramrod_flags);
34f80b04 6677 return rc;
a2fbb9ea
ET		 6678}
6679
d6214d7a
DK		 6680/**
6681 * Configure interrupt mode according to current configuration.
6682 * In case of MSI-X it will also try to enable MSI-X.
6683 *
6684 * @param bp
6685 *
6686 * @return int
6687 */
6688static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 6689{
d6214d7a 6690 int rc = 0;
ca00392c 6691
d6214d7a
DK		 6692 switch (bp->int_mode) {
6693 case INT_MODE_MSI:
6694 bnx2x_enable_msi(bp);
6695 /* falling through... */
6696 case INT_MODE_INTx:
ec6ba945 6697 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a 6698 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 6699 break;
d6214d7a
DK		 6700 default:
6701 /* Set number of queues according to bp->multi_mode value */
6702 bnx2x_set_num_queues(bp);
ca00392c 6703
d6214d7a
DK		 6704 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6705 bp->num_queues);
ca00392c 6706
d6214d7a
DK		 6707 /* if we can't use MSI-X we only need one fp,
6708 * so try to enable MSI-X with the requested number of fp's
6709 * and fallback to MSI or legacy INTx with one fp
6710 */
6711 rc = bnx2x_enable_msix(bp);
6712 if (rc) {
6713 /* failed to enable MSI-X */
6714 if (bp->multi_mode)
6715 DP(NETIF_MSG_IFUP,
6716 "Multi requested but failed to "
6717 "enable MSI-X (%d), "
6718 "set number of queues to %d\n",
6719 bp->num_queues,
ec6ba945
VZ		 6720 1 + NONE_ETH_CONTEXT_USE);
6721 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
d6214d7a
DK		 6722
6723 if (!(bp->flags & DISABLE_MSI_FLAG))
6724 bnx2x_enable_msi(bp);
6725 }
ca00392c 6726
9f6c9258
DK		 6727 break;
6728 }
d6214d7a
DK		 6729
6730 return rc;
a2fbb9ea
ET		 6731}
6732
c2bff63f
DK		 6733/* must be called prioir to any HW initializations */
6734static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6735{
6736 return L2_ILT_LINES(bp);
6737}
6738
523224a3
DK		 6739void bnx2x_ilt_set_info(struct bnx2x *bp)
6740{
6741 struct ilt_client_info *ilt_client;
6742 struct bnx2x_ilt *ilt = BP_ILT(bp);
6743 u16 line = 0;
6744
6745 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6746 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6747
6748 /* CDU */
6749 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6750 ilt_client->client_num = ILT_CLIENT_CDU;
6751 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6752 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6753 ilt_client->start = line;
6754 line += L2_ILT_LINES(bp);
6755#ifdef BCM_CNIC
6756 line += CNIC_ILT_LINES;
6757#endif
6758 ilt_client->end = line - 1;
6759
6760 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6761 "flags 0x%x, hw psz %d\n",
6762 ilt_client->start,
6763 ilt_client->end,
6764 ilt_client->page_size,
6765 ilt_client->flags,
6766 ilog2(ilt_client->page_size >> 12));
6767
6768 /* QM */
6769 if (QM_INIT(bp->qm_cid_count)) {
6770 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6771 ilt_client->client_num = ILT_CLIENT_QM;
6772 ilt_client->page_size = QM_ILT_PAGE_SZ;
6773 ilt_client->flags = 0;
6774 ilt_client->start = line;
6775
6776 /* 4 bytes for each cid */
6777 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6778 QM_ILT_PAGE_SZ);
6779
6780 ilt_client->end = line - 1;
6781
6782 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6783 "flags 0x%x, hw psz %d\n",
6784 ilt_client->start,
6785 ilt_client->end,
6786 ilt_client->page_size,
6787 ilt_client->flags,
6788 ilog2(ilt_client->page_size >> 12));
6789
6790 }
6791 /* SRC */
6792 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6793#ifdef BCM_CNIC
6794 ilt_client->client_num = ILT_CLIENT_SRC;
6795 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6796 ilt_client->flags = 0;
6797 ilt_client->start = line;
6798 line += SRC_ILT_LINES;
6799 ilt_client->end = line - 1;
6800
6801 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6802 "flags 0x%x, hw psz %d\n",
6803 ilt_client->start,
6804 ilt_client->end,
6805 ilt_client->page_size,
6806 ilt_client->flags,
6807 ilog2(ilt_client->page_size >> 12));
6808
6809#else
6810 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6811#endif
9f6c9258 6812
523224a3
DK		 6813 /* TM */
6814 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6815#ifdef BCM_CNIC
6816 ilt_client->client_num = ILT_CLIENT_TM;
6817 ilt_client->page_size = TM_ILT_PAGE_SZ;
6818 ilt_client->flags = 0;
6819 ilt_client->start = line;
6820 line += TM_ILT_LINES;
6821 ilt_client->end = line - 1;
6822
6823 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6824 "flags 0x%x, hw psz %d\n",
6825 ilt_client->start,
6826 ilt_client->end,
6827 ilt_client->page_size,
6828 ilt_client->flags,
6829 ilog2(ilt_client->page_size >> 12));
9f6c9258 6830
523224a3
DK		 6831#else
6832 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6833#endif
6834}
f85582f8 6835
523224a3
DK		 6836int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6837 int is_leading)
a2fbb9ea 6838{
523224a3 6839 struct bnx2x_client_init_params params = { {0} };
a2fbb9ea
ET		 6840 int rc;
6841
ec6ba945
VZ		 6842 /* reset IGU state skip FCoE L2 queue */
6843 if (!IS_FCOE_FP(fp))
6844 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 6845 IGU_INT_ENABLE, 0);
a2fbb9ea 6846
523224a3
DK		 6847 params.ramrod_params.pstate = &fp->state;
6848 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6849 params.ramrod_params.index = fp->index;
6850 params.ramrod_params.cid = fp->cid;
a2fbb9ea 6851
ec6ba945
VZ		 6852#ifdef BCM_CNIC
6853 if (IS_FCOE_FP(fp))
6854 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6855
6856#endif
6857
523224a3
DK		 6858 if (is_leading)
6859 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
a2fbb9ea 6860
523224a3
DK		 6861 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6862
6863 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6864
6865 rc = bnx2x_setup_fw_client(bp, &params, 1,
6866 bnx2x_sp(bp, client_init_data),
6867 bnx2x_sp_mapping(bp, client_init_data));
34f80b04 6868 return rc;
a2fbb9ea
ET		 6869}
6870
8d96286a 6871static int bnx2x_stop_fw_client(struct bnx2x *bp,
6872 struct bnx2x_client_ramrod_params *p)
a2fbb9ea 6873{
34f80b04 6874 int rc;
a2fbb9ea 6875
523224a3 6876 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
a2fbb9ea 6877
523224a3
DK		 6878 /* halt the connection */
6879 *p->pstate = BNX2X_FP_STATE_HALTING;
6880 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6881 p->cl_id, 0);
a2fbb9ea 6882
34f80b04 6883 /* Wait for completion */
523224a3
DK		 6884 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6885 p->pstate, poll_flag);
34f80b04 6886 if (rc) /* timeout */
da5a662a 6887 return rc;
a2fbb9ea 6888
523224a3
DK		 6889 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6890 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6891 p->cl_id, 0);
6892 /* Wait for completion */
6893 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6894 p->pstate, poll_flag);
6895 if (rc) /* timeout */
6896 return rc;
a2fbb9ea 6897
a2fbb9ea 6898
523224a3
DK		 6899 /* delete cfc entry */
6900 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
da5a662a 6901
523224a3
DK		 6902 /* Wait for completion */
6903 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6904 p->pstate, WAIT_RAMROD_COMMON);
da5a662a 6905 return rc;
a2fbb9ea
ET		 6906}
6907
523224a3
DK		 6908static int bnx2x_stop_client(struct bnx2x *bp, int index)
6909{
6910 struct bnx2x_client_ramrod_params client_stop = {0};
6911 struct bnx2x_fastpath *fp = &bp->fp[index];
6912
6913 client_stop.index = index;
6914 client_stop.cid = fp->cid;
6915 client_stop.cl_id = fp->cl_id;
6916 client_stop.pstate = &(fp->state);
6917 client_stop.poll = 0;
6918
6919 return bnx2x_stop_fw_client(bp, &client_stop);
6920}
6921
6922
34f80b04
EG		 6923static void bnx2x_reset_func(struct bnx2x *bp)
6924{
6925 int port = BP_PORT(bp);
6926 int func = BP_FUNC(bp);
f2e0899f 6927 int i;
523224a3 6928 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
f2e0899f
DK		 6929 (CHIP_IS_E2(bp) ?
6930 offsetof(struct hc_status_block_data_e2, common) :
6931 offsetof(struct hc_status_block_data_e1x, common));
523224a3
DK		 6932 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6933 int pfid_offset = offsetof(struct pci_entity, pf_id);
6934
6935 /* Disable the function in the FW */
6936 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6937 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6938 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6939 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6940
6941 /* FP SBs */
ec6ba945 6942 for_each_eth_queue(bp, i) {
523224a3
DK		 6943 struct bnx2x_fastpath *fp = &bp->fp[i];
6944 REG_WR8(bp,
6945 BAR_CSTRORM_INTMEM +
6946 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6947 + pfunc_offset_fp + pfid_offset,
6948 HC_FUNCTION_DISABLED);
6949 }
6950
6951 /* SP SB */
6952 REG_WR8(bp,
6953 BAR_CSTRORM_INTMEM +
6954 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6955 pfunc_offset_sp + pfid_offset,
6956 HC_FUNCTION_DISABLED);
6957
6958
6959 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6960 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6961 0);
34f80b04
EG		 6962
6963 /* Configure IGU */
f2e0899f
DK		 6964 if (bp->common.int_block == INT_BLOCK_HC) {
6965 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6966 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6967 } else {
6968 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6969 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6970 }
34f80b04 6971
37b091ba
MC		 6972#ifdef BCM_CNIC
6973 /* Disable Timer scan */
6974 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6975 /*
6976 * Wait for at least 10ms and up to 2 second for the timers scan to
6977 * complete
6978 */
6979 for (i = 0; i < 200; i++) {
6980 msleep(10);
6981 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6982 break;
6983 }
6984#endif
34f80b04 6985 /* Clear ILT */
f2e0899f
DK		 6986 bnx2x_clear_func_ilt(bp, func);
6987
6988 /* Timers workaround bug for E2: if this is vnic-3,
6989 * we need to set the entire ilt range for this timers.
6990 */
6991 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6992 struct ilt_client_info ilt_cli;
6993 /* use dummy TM client */
6994 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6995 ilt_cli.start = 0;
6996 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6997 ilt_cli.client_num = ILT_CLIENT_TM;
6998
6999 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7000 }
7001
7002 /* this assumes that reset_port() called before reset_func()*/
7003 if (CHIP_IS_E2(bp))
7004 bnx2x_pf_disable(bp);
523224a3
DK		 7005
7006 bp->dmae_ready = 0;
34f80b04
EG		 7007}
7008
7009static void bnx2x_reset_port(struct bnx2x *bp)
7010{
7011 int port = BP_PORT(bp);
7012 u32 val;
7013
7014 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7015
7016 /* Do not rcv packets to BRB */
7017 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7018 /* Do not direct rcv packets that are not for MCP to the BRB */
7019 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7020 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7021
7022 /* Configure AEU */
7023 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7024
7025 msleep(100);
7026 /* Check for BRB port occupancy */
7027 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7028 if (val)
7029 DP(NETIF_MSG_IFDOWN,
33471629 7030 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7031
7032 /* TODO: Close Doorbell port? */
7033}
7034
34f80b04
EG		 7035static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7036{
7037 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
f2e0899f 7038 BP_ABS_FUNC(bp), reset_code);
34f80b04
EG		 7039
7040 switch (reset_code) {
7041 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7042 bnx2x_reset_port(bp);
7043 bnx2x_reset_func(bp);
7044 bnx2x_reset_common(bp);
7045 break;
7046
7047 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7048 bnx2x_reset_port(bp);
7049 bnx2x_reset_func(bp);
7050 break;
7051
7052 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7053 bnx2x_reset_func(bp);
7054 break;
49d66772 7055
34f80b04
EG		 7056 default:
7057 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7058 break;
7059 }
7060}
7061
ec6ba945
VZ		 7062#ifdef BCM_CNIC
7063static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7064{
7065 if (bp->flags & FCOE_MACS_SET) {
7066 if (!IS_MF_SD(bp))
7067 bnx2x_set_fip_eth_mac_addr(bp, 0);
7068
7069 bnx2x_set_all_enode_macs(bp, 0);
7070
7071 bp->flags &= ~FCOE_MACS_SET;
7072 }
7073}
7074#endif
7075
9f6c9258 7076void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
a2fbb9ea 7077{
da5a662a 7078 int port = BP_PORT(bp);
a2fbb9ea 7079 u32 reset_code = 0;
da5a662a 7080 int i, cnt, rc;
a2fbb9ea 7081
555f6c78 7082 /* Wait until tx fastpath tasks complete */
ec6ba945 7083 for_each_tx_queue(bp, i) {
228241eb
ET		 7084 struct bnx2x_fastpath *fp = &bp->fp[i];
7085
34f80b04 7086 cnt = 1000;
e8b5fc51 7087 while (bnx2x_has_tx_work_unload(fp)) {
da5a662a 7088
34f80b04
EG		 7089 if (!cnt) {
7090 BNX2X_ERR("timeout waiting for queue[%d]\n",
7091 i);
7092#ifdef BNX2X_STOP_ON_ERROR
7093 bnx2x_panic();
7094 return -EBUSY;
7095#else
7096 break;
7097#endif
7098 }
7099 cnt--;
da5a662a 7100 msleep(1);
34f80b04 7101 }
228241eb 7102 }
da5a662a
VZ		 7103 /* Give HW time to discard old tx messages */
7104 msleep(1);
a2fbb9ea 7105
3101c2bc 7106 if (CHIP_IS_E1(bp)) {
523224a3
DK		 7107 /* invalidate mc list,
7108 * wait and poll (interrupts are off)
7109 */
7110 bnx2x_invlidate_e1_mc_list(bp);
7111 bnx2x_set_eth_mac(bp, 0);
3101c2bc 7112
523224a3 7113 } else {
65abd74d
YG		 7114 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7115
523224a3 7116 bnx2x_set_eth_mac(bp, 0);
3101c2bc
YG		 7117
7118 for (i = 0; i < MC_HASH_SIZE; i++)
7119 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
7120 }
523224a3 7121
993ac7b5 7122#ifdef BCM_CNIC
ec6ba945 7123 bnx2x_del_fcoe_eth_macs(bp);
993ac7b5 7124#endif
3101c2bc 7125
65abd74d
YG		 7126 if (unload_mode == UNLOAD_NORMAL)
7127 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7128
7d0446c2 7129 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7130 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7131
7d0446c2 7132 else if (bp->wol) {
65abd74d
YG		 7133 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7134 u8 *mac_addr = bp->dev->dev_addr;
7135 u32 val;
7136 /* The mac address is written to entries 1-4 to
7137 preserve entry 0 which is used by the PMF */
7138 u8 entry = (BP_E1HVN(bp) + 1)*8;
7139
7140 val = (mac_addr[0] << 8) | mac_addr[1];
7141 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7142
7143 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7144 (mac_addr[4] << 8) | mac_addr[5];
7145 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7146
7147 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7148
7149 } else
7150 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7151
34f80b04
EG		 7152 /* Close multi and leading connections
7153 Completions for ramrods are collected in a synchronous way */
523224a3
DK		 7154 for_each_queue(bp, i)
7155
7156 if (bnx2x_stop_client(bp, i))
7157#ifdef BNX2X_STOP_ON_ERROR
7158 return;
7159#else
228241eb 7160 goto unload_error;
523224a3 7161#endif
a2fbb9ea 7162
523224a3 7163 rc = bnx2x_func_stop(bp);
da5a662a 7164 if (rc) {
523224a3 7165 BNX2X_ERR("Function stop failed!\n");
da5a662a 7166#ifdef BNX2X_STOP_ON_ERROR
523224a3 7167 return;
da5a662a
VZ		 7168#else
7169 goto unload_error;
34f80b04 7170#endif
228241eb 7171 }
523224a3 7172#ifndef BNX2X_STOP_ON_ERROR
228241eb 7173unload_error:
523224a3 7174#endif
34f80b04 7175 if (!BP_NOMCP(bp))
a22f0788 7176 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04 7177 else {
f2e0899f
DK		 7178 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7179 "%d, %d, %d\n", BP_PATH(bp),
7180 load_count[BP_PATH(bp)][0],
7181 load_count[BP_PATH(bp)][1],
7182 load_count[BP_PATH(bp)][2]);
7183 load_count[BP_PATH(bp)][0]--;
7184 load_count[BP_PATH(bp)][1 + port]--;
7185 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7186 "%d, %d, %d\n", BP_PATH(bp),
7187 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7188 load_count[BP_PATH(bp)][2]);
7189 if (load_count[BP_PATH(bp)][0] == 0)
34f80b04 7190 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
f2e0899f 7191 else if (load_count[BP_PATH(bp)][1 + port] == 0)
34f80b04
EG		 7192 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7193 else
7194 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7195 }
a2fbb9ea 7196
34f80b04
EG		 7197 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7198 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7199 bnx2x__link_reset(bp);
a2fbb9ea 7200
523224a3
DK		 7201 /* Disable HW interrupts, NAPI */
7202 bnx2x_netif_stop(bp, 1);
7203
7204 /* Release IRQs */
d6214d7a 7205 bnx2x_free_irq(bp);
523224a3 7206
a2fbb9ea 7207 /* Reset the chip */
228241eb 7208 bnx2x_reset_chip(bp, reset_code);
a2fbb9ea
ET		 7209
7210 /* Report UNLOAD_DONE to MCP */
34f80b04 7211 if (!BP_NOMCP(bp))
a22f0788 7212 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
356e2385 7213
72fd0718
VZ		 7214}
7215
9f6c9258 7216void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7217{
7218 u32 val;
7219
7220 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7221
7222 if (CHIP_IS_E1(bp)) {
7223 int port = BP_PORT(bp);
7224 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7225 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7226
7227 val = REG_RD(bp, addr);
7228 val &= ~(0x300);
7229 REG_WR(bp, addr, val);
7230 } else if (CHIP_IS_E1H(bp)) {
7231 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7232 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7233 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7234 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7235 }
7236}
7237
72fd0718
VZ		 7238/* Close gates #2, #3 and #4: */
7239static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7240{
7241 u32 val, addr;
7242
7243 /* Gates #2 and #4a are closed/opened for "not E1" only */
7244 if (!CHIP_IS_E1(bp)) {
7245 /* #4 */
7246 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7247 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7248 close ? (val | 0x1) : (val & (~(u32)1)));
7249 /* #2 */
7250 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7251 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7252 close ? (val | 0x1) : (val & (~(u32)1)));
7253 }
7254
7255 /* #3 */
7256 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7257 val = REG_RD(bp, addr);
7258 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7259
7260 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7261 close ? "closing" : "opening");
7262 mmiowb();
7263}
7264
7265#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7266
7267static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7268{
7269 /* Do some magic... */
7270 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7271 *magic_val = val & SHARED_MF_CLP_MAGIC;
7272 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7273}
7274
7275/* Restore the value of the `magic' bit.
7276 *
7277 * @param pdev Device handle.
7278 * @param magic_val Old value of the `magic' bit.
7279 */
7280static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7281{
7282 /* Restore the `magic' bit value... */
72fd0718
VZ		 7283 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7284 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7285 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7286}
7287
f85582f8
DK		 7288/**
7289 * Prepares for MCP reset: takes care of CLP configurations.
72fd0718
VZ		 7290 *
7291 * @param bp
7292 * @param magic_val Old value of 'magic' bit.
7293 */
7294static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7295{
7296 u32 shmem;
7297 u32 validity_offset;
7298
7299 DP(NETIF_MSG_HW, "Starting\n");
7300
7301 /* Set `magic' bit in order to save MF config */
7302 if (!CHIP_IS_E1(bp))
7303 bnx2x_clp_reset_prep(bp, magic_val);
7304
7305 /* Get shmem offset */
7306 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7307 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7308
7309 /* Clear validity map flags */
7310 if (shmem > 0)
7311 REG_WR(bp, shmem + validity_offset, 0);
7312}
7313
7314#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7315#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7316
7317/* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,
7318 * depending on the HW type.
7319 *
7320 * @param bp
7321 */
7322static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7323{
7324 /* special handling for emulation and FPGA,
7325 wait 10 times longer */
7326 if (CHIP_REV_IS_SLOW(bp))
7327 msleep(MCP_ONE_TIMEOUT*10);
7328 else
7329 msleep(MCP_ONE_TIMEOUT);
7330}
7331
7332static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7333{
7334 u32 shmem, cnt, validity_offset, val;
7335 int rc = 0;
7336
7337 msleep(100);
7338
7339 /* Get shmem offset */
7340 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7341 if (shmem == 0) {
7342 BNX2X_ERR("Shmem 0 return failure\n");
7343 rc = -ENOTTY;
7344 goto exit_lbl;
7345 }
7346
7347 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7348
7349 /* Wait for MCP to come up */
7350 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7351 /* TBD: its best to check validity map of last port.
7352 * currently checks on port 0.
7353 */
7354 val = REG_RD(bp, shmem + validity_offset);
7355 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7356 shmem + validity_offset, val);
7357
7358 /* check that shared memory is valid. */
7359 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7360 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7361 break;
7362
7363 bnx2x_mcp_wait_one(bp);
7364 }
7365
7366 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7367
7368 /* Check that shared memory is valid. This indicates that MCP is up. */
7369 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7370 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7371 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7372 rc = -ENOTTY;
7373 goto exit_lbl;
7374 }
7375
7376exit_lbl:
7377 /* Restore the `magic' bit value */
7378 if (!CHIP_IS_E1(bp))
7379 bnx2x_clp_reset_done(bp, magic_val);
7380
7381 return rc;
7382}
7383
7384static void bnx2x_pxp_prep(struct bnx2x *bp)
7385{
7386 if (!CHIP_IS_E1(bp)) {
7387 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7388 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7389 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7390 mmiowb();
7391 }
7392}
7393
7394/*
7395 * Reset the whole chip except for:
7396 * - PCIE core
7397 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7398 * one reset bit)
7399 * - IGU
7400 * - MISC (including AEU)
7401 * - GRC
7402 * - RBCN, RBCP
7403 */
7404static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7405{
7406 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7407
7408 not_reset_mask1 =
7409 MISC_REGISTERS_RESET_REG_1_RST_HC |
7410 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7411 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7412
7413 not_reset_mask2 =
7414 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7415 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7416 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7417 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7418 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7419 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7420 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7421 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7422
7423 reset_mask1 = 0xffffffff;
7424
7425 if (CHIP_IS_E1(bp))
7426 reset_mask2 = 0xffff;
7427 else
7428 reset_mask2 = 0x1ffff;
7429
7430 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7431 reset_mask1 & (~not_reset_mask1));
7432 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7433 reset_mask2 & (~not_reset_mask2));
7434
7435 barrier();
7436 mmiowb();
7437
7438 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7439 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7440 mmiowb();
7441}
7442
7443static int bnx2x_process_kill(struct bnx2x *bp)
7444{
7445 int cnt = 1000;
7446 u32 val = 0;
7447 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7448
7449
7450 /* Empty the Tetris buffer, wait for 1s */
7451 do {
7452 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7453 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7454 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7455 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7456 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7457 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7458 ((port_is_idle_0 & 0x1) == 0x1) &&
7459 ((port_is_idle_1 & 0x1) == 0x1) &&
7460 (pgl_exp_rom2 == 0xffffffff))
7461 break;
7462 msleep(1);
7463 } while (cnt-- > 0);
7464
7465 if (cnt <= 0) {
7466 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7467 " are still"
7468 " outstanding read requests after 1s!\n");
7469 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7470 " port_is_idle_0=0x%08x,"
7471 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7472 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7473 pgl_exp_rom2);
7474 return -EAGAIN;
7475 }
7476
7477 barrier();
7478
7479 /* Close gates #2, #3 and #4 */
7480 bnx2x_set_234_gates(bp, true);
7481
7482 /* TBD: Indicate that "process kill" is in progress to MCP */
7483
7484 /* Clear "unprepared" bit */
7485 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7486 barrier();
7487
7488 /* Make sure all is written to the chip before the reset */
7489 mmiowb();
7490
7491 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7492 * PSWHST, GRC and PSWRD Tetris buffer.
7493 */
7494 msleep(1);
7495
7496 /* Prepare to chip reset: */
7497 /* MCP */
7498 bnx2x_reset_mcp_prep(bp, &val);
7499
7500 /* PXP */
7501 bnx2x_pxp_prep(bp);
7502 barrier();
7503
7504 /* reset the chip */
7505 bnx2x_process_kill_chip_reset(bp);
7506 barrier();
7507
7508 /* Recover after reset: */
7509 /* MCP */
7510 if (bnx2x_reset_mcp_comp(bp, val))
7511 return -EAGAIN;
7512
7513 /* PXP */
7514 bnx2x_pxp_prep(bp);
7515
7516 /* Open the gates #2, #3 and #4 */
7517 bnx2x_set_234_gates(bp, false);
7518
7519 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7520 * reset state, re-enable attentions. */
7521
a2fbb9ea
ET		 7522 return 0;
7523}
7524
72fd0718
VZ		 7525static int bnx2x_leader_reset(struct bnx2x *bp)
7526{
7527 int rc = 0;
7528 /* Try to recover after the failure */
7529 if (bnx2x_process_kill(bp)) {
7530 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7531 bp->dev->name);
7532 rc = -EAGAIN;
7533 goto exit_leader_reset;
7534 }
7535
7536 /* Clear "reset is in progress" bit and update the driver state */
7537 bnx2x_set_reset_done(bp);
7538 bp->recovery_state = BNX2X_RECOVERY_DONE;
7539
7540exit_leader_reset:
7541 bp->is_leader = 0;
7542 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7543 smp_wmb();
7544 return rc;
7545}
7546
72fd0718
VZ		 7547/* Assumption: runs under rtnl lock. This together with the fact
7548 * that it's called only from bnx2x_reset_task() ensure that it
7549 * will never be called when netif_running(bp->dev) is false.
7550 */
7551static void bnx2x_parity_recover(struct bnx2x *bp)
7552{
7553 DP(NETIF_MSG_HW, "Handling parity\n");
7554 while (1) {
7555 switch (bp->recovery_state) {
7556 case BNX2X_RECOVERY_INIT:
7557 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7558 /* Try to get a LEADER_LOCK HW lock */
7559 if (bnx2x_trylock_hw_lock(bp,
7560 HW_LOCK_RESOURCE_RESERVED_08))
7561 bp->is_leader = 1;
7562
7563 /* Stop the driver */
7564 /* If interface has been removed - break */
7565 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7566 return;
7567
7568 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7569 /* Ensure "is_leader" and "recovery_state"
7570 * update values are seen on other CPUs
7571 */
7572 smp_wmb();
7573 break;
7574
7575 case BNX2X_RECOVERY_WAIT:
7576 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7577 if (bp->is_leader) {
7578 u32 load_counter = bnx2x_get_load_cnt(bp);
7579 if (load_counter) {
7580 /* Wait until all other functions get
7581 * down.
7582 */
7583 schedule_delayed_work(&bp->reset_task,
7584 HZ/10);
7585 return;
7586 } else {
7587 /* If all other functions got down -
7588 * try to bring the chip back to
7589 * normal. In any case it's an exit
7590 * point for a leader.
7591 */
7592 if (bnx2x_leader_reset(bp) ||
7593 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7594 printk(KERN_ERR"%s: Recovery "
7595 "has failed. Power cycle is "
7596 "needed.\n", bp->dev->name);
7597 /* Disconnect this device */
7598 netif_device_detach(bp->dev);
7599 /* Block ifup for all function
7600 * of this ASIC until
7601 * "process kill" or power
7602 * cycle.
7603 */
7604 bnx2x_set_reset_in_progress(bp);
7605 /* Shut down the power */
7606 bnx2x_set_power_state(bp,
7607 PCI_D3hot);
7608 return;
7609 }
7610
7611 return;
7612 }
7613 } else { /* non-leader */
7614 if (!bnx2x_reset_is_done(bp)) {
7615 /* Try to get a LEADER_LOCK HW lock as
7616 * long as a former leader may have
7617 * been unloaded by the user or
7618 * released a leadership by another
7619 * reason.
7620 */
7621 if (bnx2x_trylock_hw_lock(bp,
7622 HW_LOCK_RESOURCE_RESERVED_08)) {
7623 /* I'm a leader now! Restart a
7624 * switch case.
7625 */
7626 bp->is_leader = 1;
7627 break;
7628 }
7629
7630 schedule_delayed_work(&bp->reset_task,
7631 HZ/10);
7632 return;
7633
7634 } else { /* A leader has completed
7635 * the "process kill". It's an exit
7636 * point for a non-leader.
7637 */
7638 bnx2x_nic_load(bp, LOAD_NORMAL);
7639 bp->recovery_state =
7640 BNX2X_RECOVERY_DONE;
7641 smp_wmb();
7642 return;
7643 }
7644 }
7645 default:
7646 return;
7647 }
7648 }
7649}
7650
7651/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7652 * scheduled on a general queue in order to prevent a dead lock.
7653 */
34f80b04
EG		 7654static void bnx2x_reset_task(struct work_struct *work)
7655{
72fd0718 7656 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
34f80b04
EG		 7657
7658#ifdef BNX2X_STOP_ON_ERROR
7659 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7660 " so reset not done to allow debug dump,\n"
72fd0718 7661 KERN_ERR " you will need to reboot when done\n");
34f80b04
EG		 7662 return;
7663#endif
7664
7665 rtnl_lock();
7666
7667 if (!netif_running(bp->dev))
7668 goto reset_task_exit;
7669
72fd0718
VZ		 7670 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7671 bnx2x_parity_recover(bp);
7672 else {
7673 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7674 bnx2x_nic_load(bp, LOAD_NORMAL);
7675 }
34f80b04
EG		 7676
7677reset_task_exit:
7678 rtnl_unlock();
7679}
7680
a2fbb9ea
ET		 7681/* end of nic load/unload */
7682
a2fbb9ea
ET		 7683/*
7684 * Init service functions
7685 */
7686
8d96286a 7687static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 7688{
7689 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7690 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7691 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 7692}
7693
f2e0899f 7694static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 7695{
f2e0899f 7696 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 7697
7698 /* Flush all outstanding writes */
7699 mmiowb();
7700
7701 /* Pretend to be function 0 */
7702 REG_WR(bp, reg, 0);
f2e0899f 7703 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 7704
7705 /* From now we are in the "like-E1" mode */
7706 bnx2x_int_disable(bp);
7707
7708 /* Flush all outstanding writes */
7709 mmiowb();
7710
f2e0899f
DK		 7711 /* Restore the original function */
7712 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7713 REG_RD(bp, reg);
f1ef27ef
EG		 7714}
7715
f2e0899f 7716static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 7717{
f2e0899f 7718 if (CHIP_IS_E1(bp))
f1ef27ef 7719 bnx2x_int_disable(bp);
f2e0899f
DK		 7720 else
7721 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 7722}
7723
34f80b04
EG		 7724static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7725{
7726 u32 val;
7727
7728 /* Check if there is any driver already loaded */
7729 val = REG_RD(bp, MISC_REG_UNPREPARED);
7730 if (val == 0x1) {
7731 /* Check if it is the UNDI driver
7732 * UNDI driver initializes CID offset for normal bell to 0x7
7733 */
4a37fb66 7734 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7735 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7736 if (val == 0x7) {
7737 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 7738 /* save our pf_num */
7739 int orig_pf_num = bp->pf_num;
da5a662a
VZ		 7740 u32 swap_en;
7741 u32 swap_val;
34f80b04 7742
b4661739
EG		 7743 /* clear the UNDI indication */
7744 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7745
34f80b04
EG		 7746 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7747
7748 /* try unload UNDI on port 0 */
f2e0899f 7749 bp->pf_num = 0;
da5a662a 7750 bp->fw_seq =
f2e0899f 7751 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7752 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 7753 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7754
7755 /* if UNDI is loaded on the other port */
7756 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7757
da5a662a 7758 /* send "DONE" for previous unload */
a22f0788
YR		 7759 bnx2x_fw_command(bp,
7760 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7761
7762 /* unload UNDI on port 1 */
f2e0899f 7763 bp->pf_num = 1;
da5a662a 7764 bp->fw_seq =
f2e0899f 7765 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 7766 DRV_MSG_SEQ_NUMBER_MASK);
7767 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7768
a22f0788 7769 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 7770 }
7771
b4661739
EG		 7772 /* now it's safe to release the lock */
7773 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7774
f2e0899f 7775 bnx2x_undi_int_disable(bp);
da5a662a
VZ		 7776
7777 /* close input traffic and wait for it */
7778 /* Do not rcv packets to BRB */
7779 REG_WR(bp,
7780 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7781 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7782 /* Do not direct rcv packets that are not for MCP to
7783 * the BRB */
7784 REG_WR(bp,
7785 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7786 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7787 /* clear AEU */
7788 REG_WR(bp,
7789 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7790 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7791 msleep(10);
7792
7793 /* save NIG port swap info */
7794 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7795 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 7796 /* reset device */
7797 REG_WR(bp,
7798 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 7799 0xd3ffffff);
34f80b04
EG		 7800 REG_WR(bp,
7801 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7802 0x1403);
da5a662a
VZ		 7803 /* take the NIG out of reset and restore swap values */
7804 REG_WR(bp,
7805 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7806 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7807 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7808 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7809
7810 /* send unload done to the MCP */
a22f0788 7811 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 7812
7813 /* restore our func and fw_seq */
f2e0899f 7814 bp->pf_num = orig_pf_num;
da5a662a 7815 bp->fw_seq =
f2e0899f 7816 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 7817 DRV_MSG_SEQ_NUMBER_MASK);
b4661739
EG		 7818 } else
7819 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
34f80b04
EG		 7820 }
7821}
7822
7823static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7824{
7825 u32 val, val2, val3, val4, id;
72ce58c3 7826 u16 pmc;
34f80b04
EG		 7827
7828 /* Get the chip revision id and number. */
7829 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7830 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7831 id = ((val & 0xffff) << 16);
7832 val = REG_RD(bp, MISC_REG_CHIP_REV);
7833 id |= ((val & 0xf) << 12);
7834 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7835 id |= ((val & 0xff) << 4);
5a40e08e 7836 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 7837 id |= (val & 0xf);
7838 bp->common.chip_id = id;
523224a3
DK		 7839
7840 /* Set doorbell size */
7841 bp->db_size = (1 << BNX2X_DB_SHIFT);
7842
f2e0899f
DK		 7843 if (CHIP_IS_E2(bp)) {
7844 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7845 if ((val & 1) == 0)
7846 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7847 else
7848 val = (val >> 1) & 1;
7849 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7850 "2_PORT_MODE");
7851 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7852 CHIP_2_PORT_MODE;
7853
7854 if (CHIP_MODE_IS_4_PORT(bp))
7855 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7856 else
7857 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7858 } else {
7859 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7860 bp->pfid = bp->pf_num; /* 0..7 */
7861 }
7862
523224a3
DK		 7863 /*
7864 * set base FW non-default (fast path) status block id, this value is
7865 * used to initialize the fw_sb_id saved on the fp/queue structure to
7866 * determine the id used by the FW.
7867 */
f2e0899f
DK		 7868 if (CHIP_IS_E1x(bp))
7869 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7870 else /* E2 */
7871 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7872
7873 bp->link_params.chip_id = bp->common.chip_id;
7874 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 7875
1c06328c
EG		 7876 val = (REG_RD(bp, 0x2874) & 0x55);
7877 if ((bp->common.chip_id & 0x1) ||
7878 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7879 bp->flags |= ONE_PORT_FLAG;
7880 BNX2X_DEV_INFO("single port device\n");
7881 }
7882
34f80b04
EG		 7883 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7884 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7885 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7886 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7887 bp->common.flash_size, bp->common.flash_size);
7888
7889 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
f2e0899f
DK		 7890 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7891 MISC_REG_GENERIC_CR_1 :
7892 MISC_REG_GENERIC_CR_0));
34f80b04 7893 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 7894 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 7895 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7896 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 7897
f2e0899f 7898 if (!bp->common.shmem_base) {
34f80b04
EG		 7899 BNX2X_DEV_INFO("MCP not active\n");
7900 bp->flags |= NO_MCP_FLAG;
7901 return;
7902 }
7903
7904 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7905 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7906 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
f2e0899f 7907 BNX2X_ERR("BAD MCP validity signature\n");
34f80b04
EG		 7908
7909 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 7910 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 7911
7912 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7913 SHARED_HW_CFG_LED_MODE_MASK) >>
7914 SHARED_HW_CFG_LED_MODE_SHIFT);
7915
c2c8b03e
EG		 7916 bp->link_params.feature_config_flags = 0;
7917 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7918 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7919 bp->link_params.feature_config_flags |=
7920 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7921 else
7922 bp->link_params.feature_config_flags &=
7923 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7924
34f80b04
EG		 7925 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7926 bp->common.bc_ver = val;
7927 BNX2X_DEV_INFO("bc_ver %X\n", val);
7928 if (val < BNX2X_BC_VER) {
7929 /* for now only warn
7930 * later we might need to enforce this */
f2e0899f
DK		 7931 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7932 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 7933 }
4d295db0 7934 bp->link_params.feature_config_flags |=
a22f0788 7935 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 7936 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7937
a22f0788
YR		 7938 bp->link_params.feature_config_flags |=
7939 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7940 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3
EG		 7941
7942 if (BP_E1HVN(bp) == 0) {
7943 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7944 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7945 } else {
7946 /* no WOL capability for E1HVN != 0 */
7947 bp->flags |= NO_WOL_FLAG;
7948 }
7949 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 7950 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 7951
7952 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7953 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7954 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7955 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7956
cdaa7cb8
VZ		 7957 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7958 val, val2, val3, val4);
34f80b04
EG		 7959}
7960
f2e0899f
DK		 7961#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7962#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7963
7964static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7965{
7966 int pfid = BP_FUNC(bp);
7967 int vn = BP_E1HVN(bp);
7968 int igu_sb_id;
7969 u32 val;
7970 u8 fid;
7971
7972 bp->igu_base_sb = 0xff;
7973 bp->igu_sb_cnt = 0;
7974 if (CHIP_INT_MODE_IS_BC(bp)) {
7975 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
ec6ba945 7976 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 7977
7978 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7979 FP_SB_MAX_E1x;
7980
7981 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7982 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7983
7984 return;
7985 }
7986
7987 /* IGU in normal mode - read CAM */
7988 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7989 igu_sb_id++) {
7990 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7991 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7992 continue;
7993 fid = IGU_FID(val);
7994 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7995 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7996 continue;
7997 if (IGU_VEC(val) == 0)
7998 /* default status block */
7999 bp->igu_dsb_id = igu_sb_id;
8000 else {
8001 if (bp->igu_base_sb == 0xff)
8002 bp->igu_base_sb = igu_sb_id;
8003 bp->igu_sb_cnt++;
8004 }
8005 }
8006 }
ec6ba945
VZ		 8007 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8008 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 8009 if (bp->igu_sb_cnt == 0)
8010 BNX2X_ERR("CAM configuration error\n");
8011}
8012
34f80b04
EG		 8013static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8014 u32 switch_cfg)
a2fbb9ea 8015{
a22f0788
YR		 8016 int cfg_size = 0, idx, port = BP_PORT(bp);
8017
8018 /* Aggregation of supported attributes of all external phys */
8019 bp->port.supported[0] = 0;
8020 bp->port.supported[1] = 0;
b7737c9b
YR		 8021 switch (bp->link_params.num_phys) {
8022 case 1:
a22f0788
YR		 8023 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8024 cfg_size = 1;
8025 break;
b7737c9b 8026 case 2:
a22f0788
YR		 8027 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8028 cfg_size = 1;
8029 break;
8030 case 3:
8031 if (bp->link_params.multi_phy_config &
8032 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8033 bp->port.supported[1] =
8034 bp->link_params.phy[EXT_PHY1].supported;
8035 bp->port.supported[0] =
8036 bp->link_params.phy[EXT_PHY2].supported;
8037 } else {
8038 bp->port.supported[0] =
8039 bp->link_params.phy[EXT_PHY1].supported;
8040 bp->port.supported[1] =
8041 bp->link_params.phy[EXT_PHY2].supported;
8042 }
8043 cfg_size = 2;
8044 break;
b7737c9b 8045 }
a2fbb9ea 8046
a22f0788 8047 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8048 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8049 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8050 SHMEM_RD(bp,
a22f0788
YR		 8051 dev_info.port_hw_config[port].external_phy_config),
8052 SHMEM_RD(bp,
8053 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8054 return;
f85582f8 8055 }
a2fbb9ea 8056
b7737c9b
YR		 8057 switch (switch_cfg) {
8058 case SWITCH_CFG_1G:
34f80b04
EG		 8059 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8060 port*0x10);
8061 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 8062 break;
8063
8064 case SWITCH_CFG_10G:
34f80b04
EG		 8065 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8066 port*0x18);
8067 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a2fbb9ea
ET		 8068 break;
8069
8070 default:
8071 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
a22f0788 8072 bp->port.link_config[0]);
a2fbb9ea
ET		 8073 return;
8074 }
a22f0788
YR		 8075 /* mask what we support according to speed_cap_mask per configuration */
8076 for (idx = 0; idx < cfg_size; idx++) {
8077 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8078 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8079 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8080
a22f0788 8081 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8082 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8083 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8084
a22f0788 8085 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8086 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8087 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8088
a22f0788 8089 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8090 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8091 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8092
a22f0788 8093 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8094 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8095 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8096 SUPPORTED_1000baseT_Full);
a2fbb9ea 8097
a22f0788 8098 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8099 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8100 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8101
a22f0788 8102 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8103 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8104 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8105
8106 }
a2fbb9ea 8107
a22f0788
YR		 8108 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8109 bp->port.supported[1]);
a2fbb9ea
ET		 8110}
8111
34f80b04 8112static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 8113{
a22f0788
YR		 8114 u32 link_config, idx, cfg_size = 0;
8115 bp->port.advertising[0] = 0;
8116 bp->port.advertising[1] = 0;
8117 switch (bp->link_params.num_phys) {
8118 case 1:
8119 case 2:
8120 cfg_size = 1;
8121 break;
8122 case 3:
8123 cfg_size = 2;
8124 break;
8125 }
8126 for (idx = 0; idx < cfg_size; idx++) {
8127 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8128 link_config = bp->port.link_config[idx];
8129 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 8130 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 8131 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8132 bp->link_params.req_line_speed[idx] =
8133 SPEED_AUTO_NEG;
8134 bp->port.advertising[idx] |=
8135 bp->port.supported[idx];
f85582f8
DK		 8136 } else {
8137 /* force 10G, no AN */
a22f0788
YR		 8138 bp->link_params.req_line_speed[idx] =
8139 SPEED_10000;
8140 bp->port.advertising[idx] |=
8141 (ADVERTISED_10000baseT_Full |
f85582f8 8142 ADVERTISED_FIBRE);
a22f0788 8143 continue;
f85582f8
DK		 8144 }
8145 break;
a2fbb9ea 8146
f85582f8 8147 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 8148 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8149 bp->link_params.req_line_speed[idx] =
8150 SPEED_10;
8151 bp->port.advertising[idx] |=
8152 (ADVERTISED_10baseT_Full |
f85582f8
DK		 8153 ADVERTISED_TP);
8154 } else {
8155 BNX2X_ERROR("NVRAM config error. "
8156 "Invalid link_config 0x%x"
8157 " speed_cap_mask 0x%x\n",
8158 link_config,
a22f0788 8159 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8160 return;
8161 }
8162 break;
a2fbb9ea 8163
f85582f8 8164 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 8165 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8166 bp->link_params.req_line_speed[idx] =
8167 SPEED_10;
8168 bp->link_params.req_duplex[idx] =
8169 DUPLEX_HALF;
8170 bp->port.advertising[idx] |=
8171 (ADVERTISED_10baseT_Half |
f85582f8
DK		 8172 ADVERTISED_TP);
8173 } else {
8174 BNX2X_ERROR("NVRAM config error. "
8175 "Invalid link_config 0x%x"
8176 " speed_cap_mask 0x%x\n",
8177 link_config,
8178 bp->link_params.speed_cap_mask[idx]);
8179 return;
8180 }
8181 break;
a2fbb9ea 8182
f85582f8
DK		 8183 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8184 if (bp->port.supported[idx] &
8185 SUPPORTED_100baseT_Full) {
a22f0788
YR		 8186 bp->link_params.req_line_speed[idx] =
8187 SPEED_100;
8188 bp->port.advertising[idx] |=
8189 (ADVERTISED_100baseT_Full |
f85582f8
DK		 8190 ADVERTISED_TP);
8191 } else {
8192 BNX2X_ERROR("NVRAM config error. "
8193 "Invalid link_config 0x%x"
8194 " speed_cap_mask 0x%x\n",
8195 link_config,
8196 bp->link_params.speed_cap_mask[idx]);
8197 return;
8198 }
8199 break;
a2fbb9ea 8200
f85582f8
DK		 8201 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8202 if (bp->port.supported[idx] &
8203 SUPPORTED_100baseT_Half) {
8204 bp->link_params.req_line_speed[idx] =
8205 SPEED_100;
8206 bp->link_params.req_duplex[idx] =
8207 DUPLEX_HALF;
a22f0788
YR		 8208 bp->port.advertising[idx] |=
8209 (ADVERTISED_100baseT_Half |
f85582f8
DK		 8210 ADVERTISED_TP);
8211 } else {
8212 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8213 "Invalid link_config 0x%x"
8214 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8215 link_config,
8216 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8217 return;
8218 }
8219 break;
a2fbb9ea 8220
f85582f8 8221 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 8222 if (bp->port.supported[idx] &
8223 SUPPORTED_1000baseT_Full) {
8224 bp->link_params.req_line_speed[idx] =
8225 SPEED_1000;
8226 bp->port.advertising[idx] |=
8227 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 8228 ADVERTISED_TP);
8229 } else {
8230 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8231 "Invalid link_config 0x%x"
8232 " speed_cap_mask 0x%x\n",
a22f0788
YR		 8233 link_config,
8234 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 8235 return;
8236 }
8237 break;
a2fbb9ea 8238
f85582f8 8239 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 8240 if (bp->port.supported[idx] &
8241 SUPPORTED_2500baseX_Full) {
8242 bp->link_params.req_line_speed[idx] =
8243 SPEED_2500;
8244 bp->port.advertising[idx] |=
8245 (ADVERTISED_2500baseX_Full |
34f80b04 8246 ADVERTISED_TP);
f85582f8
DK		 8247 } else {
8248 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8249 "Invalid link_config 0x%x"
8250 " speed_cap_mask 0x%x\n",
a22f0788 8251 link_config,
f85582f8
DK		 8252 bp->link_params.speed_cap_mask[idx]);
8253 return;
8254 }
8255 break;
a2fbb9ea 8256
f85582f8
DK		 8257 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8258 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8259 case PORT_FEATURE_LINK_SPEED_10G_KR:
a22f0788
YR		 8260 if (bp->port.supported[idx] &
8261 SUPPORTED_10000baseT_Full) {
8262 bp->link_params.req_line_speed[idx] =
8263 SPEED_10000;
8264 bp->port.advertising[idx] |=
8265 (ADVERTISED_10000baseT_Full |
34f80b04 8266 ADVERTISED_FIBRE);
f85582f8
DK		 8267 } else {
8268 BNX2X_ERROR("NVRAM config error. "
cdaa7cb8
VZ		 8269 "Invalid link_config 0x%x"
8270 " speed_cap_mask 0x%x\n",
a22f0788 8271 link_config,
f85582f8
DK		 8272 bp->link_params.speed_cap_mask[idx]);
8273 return;
8274 }
8275 break;
a2fbb9ea 8276
f85582f8
DK		 8277 default:
8278 BNX2X_ERROR("NVRAM config error. "
8279 "BAD link speed link_config 0x%x\n",
8280 link_config);
8281 bp->link_params.req_line_speed[idx] =
8282 SPEED_AUTO_NEG;
8283 bp->port.advertising[idx] =
8284 bp->port.supported[idx];
8285 break;
8286 }
a2fbb9ea 8287
a22f0788 8288 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 8289 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 8290 if ((bp->link_params.req_flow_ctrl[idx] ==
8291 BNX2X_FLOW_CTRL_AUTO) &&
8292 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8293 bp->link_params.req_flow_ctrl[idx] =
8294 BNX2X_FLOW_CTRL_NONE;
8295 }
a2fbb9ea 8296
a22f0788
YR		 8297 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8298 " 0x%x advertising 0x%x\n",
8299 bp->link_params.req_line_speed[idx],
8300 bp->link_params.req_duplex[idx],
8301 bp->link_params.req_flow_ctrl[idx],
8302 bp->port.advertising[idx]);
8303 }
a2fbb9ea
ET		 8304}
8305
e665bfda
MC		 8306static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8307{
8308 mac_hi = cpu_to_be16(mac_hi);
8309 mac_lo = cpu_to_be32(mac_lo);
8310 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8311 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8312}
8313
34f80b04 8314static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 8315{
34f80b04 8316 int port = BP_PORT(bp);
589abe3a 8317 u32 config;
6f38ad93 8318 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 8319
c18487ee 8320 bp->link_params.bp = bp;
34f80b04 8321 bp->link_params.port = port;
c18487ee 8322
c18487ee 8323 bp->link_params.lane_config =
a2fbb9ea 8324 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 8325
a22f0788 8326 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 8327 SHMEM_RD(bp,
8328 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 8329 bp->link_params.speed_cap_mask[1] =
8330 SHMEM_RD(bp,
8331 dev_info.port_hw_config[port].speed_capability_mask2);
8332 bp->port.link_config[0] =
a2fbb9ea
ET		 8333 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8334
a22f0788
YR		 8335 bp->port.link_config[1] =
8336 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 8337
a22f0788
YR		 8338 bp->link_params.multi_phy_config =
8339 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 8340 /* If the device is capable of WoL, set the default state according
8341 * to the HW
8342 */
4d295db0 8343 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 8344 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8345 (config & PORT_FEATURE_WOL_ENABLED));
8346
f85582f8 8347 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 8348 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 8349 bp->link_params.lane_config,
a22f0788
YR		 8350 bp->link_params.speed_cap_mask[0],
8351 bp->port.link_config[0]);
a2fbb9ea 8352
a22f0788 8353 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 8354 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 8355 bnx2x_phy_probe(&bp->link_params);
c18487ee 8356 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 8357
8358 bnx2x_link_settings_requested(bp);
8359
01cd4528
EG		 8360 /*
8361 * If connected directly, work with the internal PHY, otherwise, work
8362 * with the external PHY
8363 */
b7737c9b
YR		 8364 ext_phy_config =
8365 SHMEM_RD(bp,
8366 dev_info.port_hw_config[port].external_phy_config);
8367 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 8368 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 8369 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 8370
8371 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8372 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8373 bp->mdio.prtad =
b7737c9b 8374 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 8375
8376 /*
8377 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8378 * In MF mode, it is set to cover self test cases
8379 */
8380 if (IS_MF(bp))
8381 bp->port.need_hw_lock = 1;
8382 else
8383 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8384 bp->common.shmem_base,
8385 bp->common.shmem2_base);
0793f83f 8386}
01cd4528 8387
0793f83f
DK		 8388static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8389{
8390 u32 val, val2;
8391 int func = BP_ABS_FUNC(bp);
8392 int port = BP_PORT(bp);
8393
8394 if (BP_NOMCP(bp)) {
8395 BNX2X_ERROR("warning: random MAC workaround active\n");
8396 random_ether_addr(bp->dev->dev_addr);
8397 } else if (IS_MF(bp)) {
8398 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8399 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8400 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8401 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8402 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 8403
8404#ifdef BCM_CNIC
0793f83f
DK		 8405 /* iSCSI NPAR MAC */
8406 if (IS_MF_SI(bp)) {
8407 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8408 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8409 val2 = MF_CFG_RD(bp, func_ext_config[func].
8410 iscsi_mac_addr_upper);
8411 val = MF_CFG_RD(bp, func_ext_config[func].
8412 iscsi_mac_addr_lower);
8413 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8414 }
8415 }
37b091ba 8416#endif
0793f83f
DK		 8417 } else {
8418 /* in SF read MACs from port configuration */
8419 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8420 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8421 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8422
8423#ifdef BCM_CNIC
8424 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8425 iscsi_mac_upper);
8426 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8427 iscsi_mac_lower);
8428 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8429#endif
8430 }
8431
8432 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8433 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8434
ec6ba945
VZ		 8435#ifdef BCM_CNIC
8436 /* Inform the upper layers about FCoE MAC */
8437 if (!CHIP_IS_E1x(bp)) {
8438 if (IS_MF_SD(bp))
8439 memcpy(bp->fip_mac, bp->dev->dev_addr,
8440 sizeof(bp->fip_mac));
8441 else
8442 memcpy(bp->fip_mac, bp->iscsi_mac,
8443 sizeof(bp->fip_mac));
8444 }
8445#endif
34f80b04
EG		 8446}
8447
8448static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8449{
0793f83f
DK		 8450 int /*abs*/func = BP_ABS_FUNC(bp);
8451 int vn, port;
8452 u32 val = 0;
34f80b04 8453 int rc = 0;
a2fbb9ea 8454
34f80b04 8455 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 8456
f2e0899f
DK		 8457 if (CHIP_IS_E1x(bp)) {
8458 bp->common.int_block = INT_BLOCK_HC;
8459
8460 bp->igu_dsb_id = DEF_SB_IGU_ID;
8461 bp->igu_base_sb = 0;
ec6ba945
VZ		 8462 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8463 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
f2e0899f
DK		 8464 } else {
8465 bp->common.int_block = INT_BLOCK_IGU;
8466 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8467 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8468 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8469 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8470 } else
8471 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
523224a3 8472
f2e0899f
DK		 8473 bnx2x_get_igu_cam_info(bp);
8474
8475 }
8476 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8477 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8478
8479 /*
8480 * Initialize MF configuration
8481 */
523224a3 8482
fb3bff17
DK		 8483 bp->mf_ov = 0;
8484 bp->mf_mode = 0;
f2e0899f 8485 vn = BP_E1HVN(bp);
0793f83f
DK		 8486 port = BP_PORT(bp);
8487
f2e0899f 8488 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
0793f83f
DK		 8489 DP(NETIF_MSG_PROBE,
8490 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8491 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8492 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
f2e0899f
DK		 8493 if (SHMEM2_HAS(bp, mf_cfg_addr))
8494 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8495 else
8496 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 8497 offsetof(struct shmem_region, func_mb) +
8498 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 8499 /*
8500 * get mf configuration:
8501 * 1. existance of MF configuration
8502 * 2. MAC address must be legal (check only upper bytes)
8503 * for Switch-Independent mode;
8504 * OVLAN must be legal for Switch-Dependent mode
8505 * 3. SF_MODE configures specific MF mode
8506 */
8507 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8508 /* get mf configuration */
8509 val = SHMEM_RD(bp,
8510 dev_info.shared_feature_config.config);
8511 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8512
8513 switch (val) {
8514 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8515 val = MF_CFG_RD(bp, func_mf_config[func].
8516 mac_upper);
8517 /* check for legal mac (upper bytes)*/
8518 if (val != 0xffff) {
8519 bp->mf_mode = MULTI_FUNCTION_SI;
8520 bp->mf_config[vn] = MF_CFG_RD(bp,
8521 func_mf_config[func].config);
8522 } else
8523 DP(NETIF_MSG_PROBE, "illegal MAC "
8524 "address for SI\n");
8525 break;
8526 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8527 /* get OV configuration */
8528 val = MF_CFG_RD(bp,
8529 func_mf_config[FUNC_0].e1hov_tag);
8530 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8531
8532 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8533 bp->mf_mode = MULTI_FUNCTION_SD;
8534 bp->mf_config[vn] = MF_CFG_RD(bp,
8535 func_mf_config[func].config);
8536 } else
8537 DP(NETIF_MSG_PROBE, "illegal OV for "
8538 "SD\n");
8539 break;
8540 default:
8541 /* Unknown configuration: reset mf_config */
8542 bp->mf_config[vn] = 0;
8543 DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",
8544 val);
8545 }
8546 }
a2fbb9ea 8547
2691d51d 8548 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 8549 IS_MF(bp) ? "multi" : "single");
2691d51d 8550
0793f83f
DK		 8551 switch (bp->mf_mode) {
8552 case MULTI_FUNCTION_SD:
8553 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8554 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 8555 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 8556 bp->mf_ov = val;
0793f83f
DK		 8557 BNX2X_DEV_INFO("MF OV for func %d is %d"
8558 " (0x%04x)\n", func,
8559 bp->mf_ov, bp->mf_ov);
2691d51d 8560 } else {
0793f83f
DK		 8561 BNX2X_ERR("No valid MF OV for func %d,"
8562 " aborting\n", func);
34f80b04
EG		 8563 rc = -EPERM;
8564 }
0793f83f
DK		 8565 break;
8566 case MULTI_FUNCTION_SI:
8567 BNX2X_DEV_INFO("func %d is in MF "
8568 "switch-independent mode\n", func);
8569 break;
8570 default:
8571 if (vn) {
8572 BNX2X_ERR("VN %d in single function mode,"
8573 " aborting\n", vn);
2691d51d
EG		 8574 rc = -EPERM;
8575 }
0793f83f 8576 break;
34f80b04 8577 }
0793f83f 8578
34f80b04 8579 }
a2fbb9ea 8580
f2e0899f
DK		 8581 /* adjust igu_sb_cnt to MF for E1x */
8582 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 8583 bp->igu_sb_cnt /= E1HVN_MAX;
8584
f2e0899f
DK		 8585 /*
8586 * adjust E2 sb count: to be removed when FW will support
8587 * more then 16 L2 clients
8588 */
8589#define MAX_L2_CLIENTS 16
8590 if (CHIP_IS_E2(bp))
8591 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8592 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8593
34f80b04
EG		 8594 if (!BP_NOMCP(bp)) {
8595 bnx2x_get_port_hwinfo(bp);
8596
f2e0899f
DK		 8597 bp->fw_seq =
8598 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8599 DRV_MSG_SEQ_NUMBER_MASK);
34f80b04
EG		 8600 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8601 }
8602
0793f83f
DK		 8603 /* Get MAC addresses */
8604 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 8605
34f80b04
EG		 8606 return rc;
8607}
8608
34f24c7f
VZ		 8609static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8610{
8611 int cnt, i, block_end, rodi;
8612 char vpd_data[BNX2X_VPD_LEN+1];
8613 char str_id_reg[VENDOR_ID_LEN+1];
8614 char str_id_cap[VENDOR_ID_LEN+1];
8615 u8 len;
8616
8617 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8618 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8619
8620 if (cnt < BNX2X_VPD_LEN)
8621 goto out_not_found;
8622
8623 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8624 PCI_VPD_LRDT_RO_DATA);
8625 if (i < 0)
8626 goto out_not_found;
8627
8628
8629 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8630 pci_vpd_lrdt_size(&vpd_data[i]);
8631
8632 i += PCI_VPD_LRDT_TAG_SIZE;
8633
8634 if (block_end > BNX2X_VPD_LEN)
8635 goto out_not_found;
8636
8637 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8638 PCI_VPD_RO_KEYWORD_MFR_ID);
8639 if (rodi < 0)
8640 goto out_not_found;
8641
8642 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8643
8644 if (len != VENDOR_ID_LEN)
8645 goto out_not_found;
8646
8647 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8648
8649 /* vendor specific info */
8650 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8651 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8652 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8653 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8654
8655 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8656 PCI_VPD_RO_KEYWORD_VENDOR0);
8657 if (rodi >= 0) {
8658 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8659
8660 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8661
8662 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8663 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8664 bp->fw_ver[len] = ' ';
8665 }
8666 }
8667 return;
8668 }
8669out_not_found:
8670 return;
8671}
8672
34f80b04
EG		 8673static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8674{
f2e0899f 8675 int func;
87942b46 8676 int timer_interval;
34f80b04
EG		 8677 int rc;
8678
da5a662a
VZ		 8679 /* Disable interrupt handling until HW is initialized */
8680 atomic_set(&bp->intr_sem, 1);
e1510706 8681 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
da5a662a 8682
34f80b04 8683 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 8684 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 8685 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 8686#ifdef BCM_CNIC
8687 mutex_init(&bp->cnic_mutex);
8688#endif
a2fbb9ea 8689
1cf167f2 8690 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
72fd0718 8691 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
34f80b04
EG		 8692
8693 rc = bnx2x_get_hwinfo(bp);
8694
523224a3
DK		 8695 if (!rc)
8696 rc = bnx2x_alloc_mem_bp(bp);
8697
34f24c7f 8698 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 8699
8700 func = BP_FUNC(bp);
8701
34f80b04
EG		 8702 /* need to reset chip if undi was active */
8703 if (!BP_NOMCP(bp))
8704 bnx2x_undi_unload(bp);
8705
8706 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 8707 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 8708
8709 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 8710 dev_err(&bp->pdev->dev, "MCP disabled, "
8711 "must load devices in order!\n");
34f80b04 8712
555f6c78 8713 bp->multi_mode = multi_mode;
5d7cd496 8714 bp->int_mode = int_mode;
555f6c78 8715
4fd89b7a
DK		 8716 bp->dev->features |= NETIF_F_GRO;
8717
7a9b2557
VZ		 8718 /* Set TPA flags */
8719 if (disable_tpa) {
8720 bp->flags &= ~TPA_ENABLE_FLAG;
8721 bp->dev->features &= ~NETIF_F_LRO;
8722 } else {
8723 bp->flags |= TPA_ENABLE_FLAG;
8724 bp->dev->features |= NETIF_F_LRO;
8725 }
5d7cd496 8726 bp->disable_tpa = disable_tpa;
7a9b2557 8727
a18f5128
EG		 8728 if (CHIP_IS_E1(bp))
8729 bp->dropless_fc = 0;
8730 else
8731 bp->dropless_fc = dropless_fc;
8732
8d5726c4 8733 bp->mrrs = mrrs;
7a9b2557 8734
34f80b04 8735 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04
EG		 8736
8737 bp->rx_csum = 1;
34f80b04 8738
7d323bfd 8739 /* make sure that the numbers are in the right granularity */
523224a3
DK		 8740 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8741 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 8742
87942b46
EG		 8743 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8744 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 8745
8746 init_timer(&bp->timer);
8747 bp->timer.expires = jiffies + bp->current_interval;
8748 bp->timer.data = (unsigned long) bp;
8749 bp->timer.function = bnx2x_timer;
8750
785b9b1a 8751 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 8752 bnx2x_dcbx_init_params(bp);
8753
34f80b04 8754 return rc;
a2fbb9ea
ET		 8755}
8756
a2fbb9ea 8757
de0c62db
DK		 8758/****************************************************************************
8759* General service functions
8760****************************************************************************/
a2fbb9ea 8761
bb2a0f7a 8762/* called with rtnl_lock */
a2fbb9ea
ET		 8763static int bnx2x_open(struct net_device *dev)
8764{
8765 struct bnx2x *bp = netdev_priv(dev);
8766
6eccabb3
EG		 8767 netif_carrier_off(dev);
8768
a2fbb9ea
ET		 8769 bnx2x_set_power_state(bp, PCI_D0);
8770
72fd0718
VZ		 8771 if (!bnx2x_reset_is_done(bp)) {
8772 do {
8773 /* Reset MCP mail box sequence if there is on going
8774 * recovery
8775 */
8776 bp->fw_seq = 0;
8777
8778 /* If it's the first function to load and reset done
8779 * is still not cleared it may mean that. We don't
8780 * check the attention state here because it may have
8781 * already been cleared by a "common" reset but we
8782 * shell proceed with "process kill" anyway.
8783 */
8784 if ((bnx2x_get_load_cnt(bp) == 0) &&
8785 bnx2x_trylock_hw_lock(bp,
8786 HW_LOCK_RESOURCE_RESERVED_08) &&
8787 (!bnx2x_leader_reset(bp))) {
8788 DP(NETIF_MSG_HW, "Recovered in open\n");
8789 break;
8790 }
8791
8792 bnx2x_set_power_state(bp, PCI_D3hot);
8793
8794 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8795 " completed yet. Try again later. If u still see this"
8796 " message after a few retries then power cycle is"
8797 " required.\n", bp->dev->name);
8798
8799 return -EAGAIN;
8800 } while (0);
8801 }
8802
8803 bp->recovery_state = BNX2X_RECOVERY_DONE;
8804
bb2a0f7a 8805 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 8806}
8807
bb2a0f7a 8808/* called with rtnl_lock */
a2fbb9ea
ET		 8809static int bnx2x_close(struct net_device *dev)
8810{
a2fbb9ea
ET		 8811 struct bnx2x *bp = netdev_priv(dev);
8812
8813 /* Unload the driver, release IRQs */
bb2a0f7a 8814 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
d3dbfee0 8815 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 8816
8817 return 0;
8818}
8819
f5372251 8820/* called with netif_tx_lock from dev_mcast.c */
9f6c9258 8821void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 8822{
8823 struct bnx2x *bp = netdev_priv(dev);
8824 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
8825 int port = BP_PORT(bp);
8826
8827 if (bp->state != BNX2X_STATE_OPEN) {
8828 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
8829 return;
8830 }
8831
8832 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
8833
8834 if (dev->flags & IFF_PROMISC)
8835 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04 8836 else if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf
JP		 8837 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
8838 CHIP_IS_E1(bp)))
34f80b04 8839 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04
EG		 8840 else { /* some multicasts */
8841 if (CHIP_IS_E1(bp)) {
523224a3
DK		 8842 /*
8843 * set mc list, do not wait as wait implies sleep
8844 * and set_rx_mode can be invoked from non-sleepable
8845 * context
8846 */
8847 u8 offset = (CHIP_REV_IS_SLOW(bp) ?
8848 BNX2X_MAX_EMUL_MULTI*(1 + port) :
8849 BNX2X_MAX_MULTICAST*(1 + port));
e665bfda 8850
523224a3 8851 bnx2x_set_e1_mc_list(bp, offset);
34f80b04
EG		 8852 } else { /* E1H */
8853 /* Accept one or more multicasts */
22bedad3 8854 struct netdev_hw_addr *ha;
34f80b04
EG		 8855 u32 mc_filter[MC_HASH_SIZE];
8856 u32 crc, bit, regidx;
8857 int i;
8858
8859 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
8860
22bedad3 8861 netdev_for_each_mc_addr(ha, dev) {
7c510e4b 8862 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
523224a3 8863 bnx2x_mc_addr(ha));
34f80b04 8864
523224a3
DK		 8865 crc = crc32c_le(0, bnx2x_mc_addr(ha),
8866 ETH_ALEN);
34f80b04
EG		 8867 bit = (crc >> 24) & 0xff;
8868 regidx = bit >> 5;
8869 bit &= 0x1f;
8870 mc_filter[regidx] |= (1 << bit);
8871 }
8872
8873 for (i = 0; i < MC_HASH_SIZE; i++)
8874 REG_WR(bp, MC_HASH_OFFSET(bp, i),
8875 mc_filter[i]);
8876 }
8877 }
8878
8879 bp->rx_mode = rx_mode;
8880 bnx2x_set_storm_rx_mode(bp);
8881}
8882
c18487ee 8883/* called with rtnl_lock */
01cd4528
EG		 8884static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
8885 int devad, u16 addr)
a2fbb9ea 8886{
01cd4528
EG		 8887 struct bnx2x *bp = netdev_priv(netdev);
8888 u16 value;
8889 int rc;
a2fbb9ea 8890
01cd4528
EG		 8891 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
8892 prtad, devad, addr);
a2fbb9ea 8893
01cd4528
EG		 8894 /* The HW expects different devad if CL22 is used */
8895 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 8896
01cd4528 8897 bnx2x_acquire_phy_lock(bp);
e10bc84d 8898 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 8899 bnx2x_release_phy_lock(bp);
8900 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 8901
01cd4528
EG		 8902 if (!rc)
8903 rc = value;
8904 return rc;
8905}
a2fbb9ea 8906
01cd4528
EG		 8907/* called with rtnl_lock */
8908static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
8909 u16 addr, u16 value)
8910{
8911 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 8912 int rc;
8913
8914 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
8915 " value 0x%x\n", prtad, devad, addr, value);
8916
01cd4528
EG		 8917 /* The HW expects different devad if CL22 is used */
8918 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 8919
01cd4528 8920 bnx2x_acquire_phy_lock(bp);
e10bc84d 8921 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 8922 bnx2x_release_phy_lock(bp);
8923 return rc;
8924}
c18487ee 8925
01cd4528
EG		 8926/* called with rtnl_lock */
8927static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8928{
8929 struct bnx2x *bp = netdev_priv(dev);
8930 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 8931
01cd4528
EG		 8932 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
8933 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 8934
01cd4528
EG		 8935 if (!netif_running(dev))
8936 return -EAGAIN;
8937
8938 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 8939}
8940
257ddbda 8941#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 8942static void poll_bnx2x(struct net_device *dev)
8943{
8944 struct bnx2x *bp = netdev_priv(dev);
8945
8946 disable_irq(bp->pdev->irq);
8947 bnx2x_interrupt(bp->pdev->irq, dev);
8948 enable_irq(bp->pdev->irq);
8949}
8950#endif
8951
c64213cd
SH		 8952static const struct net_device_ops bnx2x_netdev_ops = {
8953 .ndo_open = bnx2x_open,
8954 .ndo_stop = bnx2x_close,
8955 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 8956 .ndo_select_queue = bnx2x_select_queue,
356e2385 8957 .ndo_set_multicast_list = bnx2x_set_rx_mode,
c64213cd
SH		 8958 .ndo_set_mac_address = bnx2x_change_mac_addr,
8959 .ndo_validate_addr = eth_validate_addr,
8960 .ndo_do_ioctl = bnx2x_ioctl,
8961 .ndo_change_mtu = bnx2x_change_mtu,
8962 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 8963#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 8964 .ndo_poll_controller = poll_bnx2x,
8965#endif
8966};
8967
34f80b04
EG		 8968static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
8969 struct net_device *dev)
a2fbb9ea
ET		 8970{
8971 struct bnx2x *bp;
8972 int rc;
8973
8974 SET_NETDEV_DEV(dev, &pdev->dev);
8975 bp = netdev_priv(dev);
8976
34f80b04
EG		 8977 bp->dev = dev;
8978 bp->pdev = pdev;
a2fbb9ea 8979 bp->flags = 0;
f2e0899f 8980 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 8981
8982 rc = pci_enable_device(pdev);
8983 if (rc) {
cdaa7cb8
VZ		 8984 dev_err(&bp->pdev->dev,
8985 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 8986 goto err_out;
8987 }
8988
8989 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 8990 dev_err(&bp->pdev->dev,
8991 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 8992 rc = -ENODEV;
8993 goto err_out_disable;
8994 }
8995
8996 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 8997 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
8998 " base address, aborting\n");
a2fbb9ea
ET		 8999 rc = -ENODEV;
9000 goto err_out_disable;
9001 }
9002
34f80b04
EG		 9003 if (atomic_read(&pdev->enable_cnt) == 1) {
9004 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9005 if (rc) {
cdaa7cb8
VZ		 9006 dev_err(&bp->pdev->dev,
9007 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 9008 goto err_out_disable;
9009 }
a2fbb9ea 9010
34f80b04
EG		 9011 pci_set_master(pdev);
9012 pci_save_state(pdev);
9013 }
a2fbb9ea
ET		 9014
9015 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9016 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 9017 dev_err(&bp->pdev->dev,
9018 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 9019 rc = -EIO;
9020 goto err_out_release;
9021 }
9022
9023 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9024 if (bp->pcie_cap == 0) {
cdaa7cb8
VZ		 9025 dev_err(&bp->pdev->dev,
9026 "Cannot find PCI Express capability, aborting\n");
a2fbb9ea
ET		 9027 rc = -EIO;
9028 goto err_out_release;
9029 }
9030
1a983142 9031 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
a2fbb9ea 9032 bp->flags |= USING_DAC_FLAG;
1a983142 9033 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
cdaa7cb8
VZ		 9034 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9035 " failed, aborting\n");
a2fbb9ea
ET		 9036 rc = -EIO;
9037 goto err_out_release;
9038 }
9039
1a983142 9040 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
cdaa7cb8
VZ		 9041 dev_err(&bp->pdev->dev,
9042 "System does not support DMA, aborting\n");
a2fbb9ea
ET		 9043 rc = -EIO;
9044 goto err_out_release;
9045 }
9046
34f80b04
EG		 9047 dev->mem_start = pci_resource_start(pdev, 0);
9048 dev->base_addr = dev->mem_start;
9049 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 9050
9051 dev->irq = pdev->irq;
9052
275f165f 9053 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 9054 if (!bp->regview) {
cdaa7cb8
VZ		 9055 dev_err(&bp->pdev->dev,
9056 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 9057 rc = -ENOMEM;
9058 goto err_out_release;
9059 }
9060
34f80b04 9061 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
523224a3 9062 min_t(u64, BNX2X_DB_SIZE(bp),
34f80b04 9063 pci_resource_len(pdev, 2)));
a2fbb9ea 9064 if (!bp->doorbells) {
cdaa7cb8
VZ		 9065 dev_err(&bp->pdev->dev,
9066 "Cannot map doorbell space, aborting\n");
a2fbb9ea
ET		 9067 rc = -ENOMEM;
9068 goto err_out_unmap;
9069 }
9070
9071 bnx2x_set_power_state(bp, PCI_D0);
9072
34f80b04
EG		 9073 /* clean indirect addresses */
9074 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9075 PCICFG_VENDOR_ID_OFFSET);
9076 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9077 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9078 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9079 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
a2fbb9ea 9080
72fd0718
VZ		 9081 /* Reset the load counter */
9082 bnx2x_clear_load_cnt(bp);
9083
34f80b04 9084 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 9085
c64213cd 9086 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 9087 bnx2x_set_ethtool_ops(dev);
34f80b04 9088 dev->features |= NETIF_F_SG;
79032644 9089 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
34f80b04
EG		 9090 if (bp->flags & USING_DAC_FLAG)
9091 dev->features |= NETIF_F_HIGHDMA;
5316bc0b
EG		 9092 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9093 dev->features |= NETIF_F_TSO6;
34f80b04 9094 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
5316bc0b
EG		 9095
9096 dev->vlan_features |= NETIF_F_SG;
79032644 9097 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
5316bc0b
EG		 9098 if (bp->flags & USING_DAC_FLAG)
9099 dev->vlan_features |= NETIF_F_HIGHDMA;
9100 dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9101 dev->vlan_features |= NETIF_F_TSO6;
a2fbb9ea 9102
785b9b1a
SR		 9103#ifdef BCM_DCB
9104 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9105#endif
9106
01cd4528
EG		 9107 /* get_port_hwinfo() will set prtad and mmds properly */
9108 bp->mdio.prtad = MDIO_PRTAD_NONE;
9109 bp->mdio.mmds = 0;
9110 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9111 bp->mdio.dev = dev;
9112 bp->mdio.mdio_read = bnx2x_mdio_read;
9113 bp->mdio.mdio_write = bnx2x_mdio_write;
9114
a2fbb9ea
ET		 9115 return 0;
9116
9117err_out_unmap:
9118 if (bp->regview) {
9119 iounmap(bp->regview);
9120 bp->regview = NULL;
9121 }
a2fbb9ea
ET		 9122 if (bp->doorbells) {
9123 iounmap(bp->doorbells);
9124 bp->doorbells = NULL;
9125 }
9126
9127err_out_release:
34f80b04
EG		 9128 if (atomic_read(&pdev->enable_cnt) == 1)
9129 pci_release_regions(pdev);
a2fbb9ea
ET		 9130
9131err_out_disable:
9132 pci_disable_device(pdev);
9133 pci_set_drvdata(pdev, NULL);
9134
9135err_out:
9136 return rc;
9137}
9138
37f9ce62
EG		 9139static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9140 int *width, int *speed)
25047950
ET		 9141{
9142 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9143
37f9ce62 9144 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 9145
37f9ce62
EG		 9146 /* return value of 1=2.5GHz 2=5GHz */
9147 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 9148}
37f9ce62 9149
6891dd25 9150static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 9151{
37f9ce62 9152 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 9153 struct bnx2x_fw_file_hdr *fw_hdr;
9154 struct bnx2x_fw_file_section *sections;
94a78b79 9155 u32 offset, len, num_ops;
37f9ce62 9156 u16 *ops_offsets;
94a78b79 9157 int i;
37f9ce62 9158 const u8 *fw_ver;
94a78b79
VZ		 9159
9160 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9161 return -EINVAL;
9162
9163 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9164 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9165
9166 /* Make sure none of the offsets and sizes make us read beyond
9167 * the end of the firmware data */
9168 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9169 offset = be32_to_cpu(sections[i].offset);
9170 len = be32_to_cpu(sections[i].len);
9171 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 9172 dev_err(&bp->pdev->dev,
9173 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 9174 return -EINVAL;
9175 }
9176 }
9177
9178 /* Likewise for the init_ops offsets */
9179 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9180 ops_offsets = (u16 *)(firmware->data + offset);
9181 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9182
9183 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9184 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 9185 dev_err(&bp->pdev->dev,
9186 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 9187 return -EINVAL;
9188 }
9189 }
9190
9191 /* Check FW version */
9192 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9193 fw_ver = firmware->data + offset;
9194 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9195 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9196 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9197 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 9198 dev_err(&bp->pdev->dev,
9199 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 9200 fw_ver[0], fw_ver[1], fw_ver[2],
9201 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9202 BCM_5710_FW_MINOR_VERSION,
9203 BCM_5710_FW_REVISION_VERSION,
9204 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 9205 return -EINVAL;
94a78b79
VZ		 9206 }
9207
9208 return 0;
9209}
9210
ab6ad5a4 9211static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9212{
ab6ad5a4
EG		 9213 const __be32 *source = (const __be32 *)_source;
9214 u32 *target = (u32 *)_target;
94a78b79 9215 u32 i;
94a78b79
VZ		 9216
9217 for (i = 0; i < n/4; i++)
9218 target[i] = be32_to_cpu(source[i]);
9219}
9220
9221/*
9222 Ops array is stored in the following format:
9223 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9224 */
ab6ad5a4 9225static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 9226{
ab6ad5a4
EG		 9227 const __be32 *source = (const __be32 *)_source;
9228 struct raw_op *target = (struct raw_op *)_target;
94a78b79 9229 u32 i, j, tmp;
94a78b79 9230
ab6ad5a4 9231 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 9232 tmp = be32_to_cpu(source[j]);
9233 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 9234 target[i].offset = tmp & 0xffffff;
9235 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 9236 }
9237}
ab6ad5a4 9238
523224a3
DK		 9239/**
9240 * IRO array is stored in the following format:
9241 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9242 */
9243static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9244{
9245 const __be32 *source = (const __be32 *)_source;
9246 struct iro *target = (struct iro *)_target;
9247 u32 i, j, tmp;
9248
9249 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9250 target[i].base = be32_to_cpu(source[j]);
9251 j++;
9252 tmp = be32_to_cpu(source[j]);
9253 target[i].m1 = (tmp >> 16) & 0xffff;
9254 target[i].m2 = tmp & 0xffff;
9255 j++;
9256 tmp = be32_to_cpu(source[j]);
9257 target[i].m3 = (tmp >> 16) & 0xffff;
9258 target[i].size = tmp & 0xffff;
9259 j++;
9260 }
9261}
9262
ab6ad5a4 9263static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 9264{
ab6ad5a4
EG		 9265 const __be16 *source = (const __be16 *)_source;
9266 u16 *target = (u16 *)_target;
94a78b79 9267 u32 i;
94a78b79
VZ		 9268
9269 for (i = 0; i < n/2; i++)
9270 target[i] = be16_to_cpu(source[i]);
9271}
9272
7995c64e
JP		 9273#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9274do { \
9275 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9276 bp->arr = kmalloc(len, GFP_KERNEL); \
9277 if (!bp->arr) { \
9278 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9279 goto lbl; \
9280 } \
9281 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9282 (u8 *)bp->arr, len); \
9283} while (0)
94a78b79 9284
6891dd25 9285int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 9286{
45229b42 9287 const char *fw_file_name;
94a78b79 9288 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 9289 int rc;
94a78b79 9290
94a78b79 9291 if (CHIP_IS_E1(bp))
45229b42 9292 fw_file_name = FW_FILE_NAME_E1;
cdaa7cb8 9293 else if (CHIP_IS_E1H(bp))
45229b42 9294 fw_file_name = FW_FILE_NAME_E1H;
f2e0899f
DK		 9295 else if (CHIP_IS_E2(bp))
9296 fw_file_name = FW_FILE_NAME_E2;
cdaa7cb8 9297 else {
6891dd25 9298 BNX2X_ERR("Unsupported chip revision\n");
cdaa7cb8
VZ		 9299 return -EINVAL;
9300 }
94a78b79 9301
6891dd25 9302 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 9303
6891dd25 9304 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
94a78b79 9305 if (rc) {
6891dd25 9306 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
94a78b79
VZ		 9307 goto request_firmware_exit;
9308 }
9309
9310 rc = bnx2x_check_firmware(bp);
9311 if (rc) {
6891dd25 9312 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
94a78b79
VZ		 9313 goto request_firmware_exit;
9314 }
9315
9316 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9317
9318 /* Initialize the pointers to the init arrays */
9319 /* Blob */
9320 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9321
9322 /* Opcodes */
9323 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9324
9325 /* Offsets */
ab6ad5a4
EG		 9326 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9327 be16_to_cpu_n);
94a78b79
VZ		 9328
9329 /* STORMs firmware */
573f2035
EG		 9330 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9331 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9332 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9333 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9334 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9335 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9336 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9337 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9338 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9339 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9340 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9341 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9342 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9343 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9344 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9345 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 9346 /* IRO */
9347 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 9348
9349 return 0;
ab6ad5a4 9350
523224a3
DK		 9351iro_alloc_err:
9352 kfree(bp->init_ops_offsets);
94a78b79
VZ		 9353init_offsets_alloc_err:
9354 kfree(bp->init_ops);
9355init_ops_alloc_err:
9356 kfree(bp->init_data);
9357request_firmware_exit:
9358 release_firmware(bp->firmware);
9359
9360 return rc;
9361}
9362
523224a3
DK		 9363static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9364{
9365 int cid_count = L2_FP_COUNT(l2_cid_count);
94a78b79 9366
523224a3
DK		 9367#ifdef BCM_CNIC
9368 cid_count += CNIC_CID_MAX;
9369#endif
9370 return roundup(cid_count, QM_CID_ROUND);
9371}
f85582f8 9372
a2fbb9ea
ET		 9373static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9374 const struct pci_device_id *ent)
9375{
a2fbb9ea
ET		 9376 struct net_device *dev = NULL;
9377 struct bnx2x *bp;
37f9ce62 9378 int pcie_width, pcie_speed;
523224a3
DK		 9379 int rc, cid_count;
9380
f2e0899f
DK		 9381 switch (ent->driver_data) {
9382 case BCM57710:
9383 case BCM57711:
9384 case BCM57711E:
9385 cid_count = FP_SB_MAX_E1x;
9386 break;
9387
9388 case BCM57712:
9389 case BCM57712E:
9390 cid_count = FP_SB_MAX_E2;
9391 break;
a2fbb9ea 9392
f2e0899f
DK		 9393 default:
9394 pr_err("Unknown board_type (%ld), aborting\n",
9395 ent->driver_data);
870634b0 9396 return -ENODEV;
f2e0899f
DK		 9397 }
9398
ec6ba945 9399 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
f85582f8 9400
a2fbb9ea 9401 /* dev zeroed in init_etherdev */
523224a3 9402 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
34f80b04 9403 if (!dev) {
cdaa7cb8 9404 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 9405 return -ENOMEM;
34f80b04 9406 }
a2fbb9ea 9407
a2fbb9ea 9408 bp = netdev_priv(dev);
7995c64e 9409 bp->msg_enable = debug;
a2fbb9ea 9410
df4770de
EG		 9411 pci_set_drvdata(pdev, dev);
9412
523224a3
DK		 9413 bp->l2_cid_count = cid_count;
9414
34f80b04 9415 rc = bnx2x_init_dev(pdev, dev);
a2fbb9ea
ET		 9416 if (rc < 0) {
9417 free_netdev(dev);
9418 return rc;
9419 }
9420
34f80b04 9421 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 9422 if (rc)
9423 goto init_one_exit;
9424
523224a3
DK		 9425 /* calc qm_cid_count */
9426 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9427
ec6ba945
VZ		 9428#ifdef BCM_CNIC
9429 /* disable FCOE L2 queue for E1x*/
9430 if (CHIP_IS_E1x(bp))
9431 bp->flags |= NO_FCOE_FLAG;
9432
9433#endif
9434
d6214d7a
DK		 9435 /* Configure interupt mode: try to enable MSI-X/MSI if
9436 * needed, set bp->num_queues appropriately.
9437 */
9438 bnx2x_set_int_mode(bp);
9439
9440 /* Add all NAPI objects */
9441 bnx2x_add_all_napi(bp);
9442
b340007f
VZ		 9443 rc = register_netdev(dev);
9444 if (rc) {
9445 dev_err(&pdev->dev, "Cannot register net device\n");
9446 goto init_one_exit;
9447 }
9448
ec6ba945
VZ		 9449#ifdef BCM_CNIC
9450 if (!NO_FCOE(bp)) {
9451 /* Add storage MAC address */
9452 rtnl_lock();
9453 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9454 rtnl_unlock();
9455 }
9456#endif
9457
37f9ce62 9458 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 9459
cdaa7cb8
VZ		 9460 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9461 " IRQ %d, ", board_info[ent->driver_data].name,
9462 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
f2e0899f
DK		 9463 pcie_width,
9464 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9465 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9466 "5GHz (Gen2)" : "2.5GHz",
cdaa7cb8
VZ		 9467 dev->base_addr, bp->pdev->irq);
9468 pr_cont("node addr %pM\n", dev->dev_addr);
c016201c 9469
a2fbb9ea 9470 return 0;
34f80b04
EG		 9471
9472init_one_exit:
9473 if (bp->regview)
9474 iounmap(bp->regview);
9475
9476 if (bp->doorbells)
9477 iounmap(bp->doorbells);
9478
9479 free_netdev(dev);
9480
9481 if (atomic_read(&pdev->enable_cnt) == 1)
9482 pci_release_regions(pdev);
9483
9484 pci_disable_device(pdev);
9485 pci_set_drvdata(pdev, NULL);
9486
9487 return rc;
a2fbb9ea
ET		 9488}
9489
9490static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9491{
9492 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 9493 struct bnx2x *bp;
9494
9495 if (!dev) {
cdaa7cb8 9496 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 9497 return;
9498 }
228241eb 9499 bp = netdev_priv(dev);
a2fbb9ea 9500
ec6ba945
VZ		 9501#ifdef BCM_CNIC
9502 /* Delete storage MAC address */
9503 if (!NO_FCOE(bp)) {
9504 rtnl_lock();
9505 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9506 rtnl_unlock();
9507 }
9508#endif
9509
a2fbb9ea
ET		 9510 unregister_netdev(dev);
9511
d6214d7a
DK		 9512 /* Delete all NAPI objects */
9513 bnx2x_del_all_napi(bp);
9514
084d6cbb
VZ		 9515 /* Power on: we can't let PCI layer write to us while we are in D3 */
9516 bnx2x_set_power_state(bp, PCI_D0);
9517
d6214d7a
DK		 9518 /* Disable MSI/MSI-X */
9519 bnx2x_disable_msi(bp);
f85582f8 9520
084d6cbb
VZ		 9521 /* Power off */
9522 bnx2x_set_power_state(bp, PCI_D3hot);
9523
72fd0718
VZ		 9524 /* Make sure RESET task is not scheduled before continuing */
9525 cancel_delayed_work_sync(&bp->reset_task);
9526
a2fbb9ea
ET		 9527 if (bp->regview)
9528 iounmap(bp->regview);
9529
9530 if (bp->doorbells)
9531 iounmap(bp->doorbells);
9532
523224a3
DK		 9533 bnx2x_free_mem_bp(bp);
9534
a2fbb9ea 9535 free_netdev(dev);
34f80b04
EG		 9536
9537 if (atomic_read(&pdev->enable_cnt) == 1)
9538 pci_release_regions(pdev);
9539
a2fbb9ea
ET		 9540 pci_disable_device(pdev);
9541 pci_set_drvdata(pdev, NULL);
9542}
9543
f8ef6e44
YG		 9544static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9545{
9546 int i;
9547
9548 bp->state = BNX2X_STATE_ERROR;
9549
9550 bp->rx_mode = BNX2X_RX_MODE_NONE;
9551
9552 bnx2x_netif_stop(bp, 0);
c89af1a3 9553 netif_carrier_off(bp->dev);
f8ef6e44
YG		 9554
9555 del_timer_sync(&bp->timer);
9556 bp->stats_state = STATS_STATE_DISABLED;
9557 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9558
9559 /* Release IRQs */
d6214d7a 9560 bnx2x_free_irq(bp);
f8ef6e44 9561
f8ef6e44
YG		 9562 /* Free SKBs, SGEs, TPA pool and driver internals */
9563 bnx2x_free_skbs(bp);
523224a3 9564
ec6ba945 9565 for_each_rx_queue(bp, i)
f8ef6e44 9566 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 9567
f8ef6e44
YG		 9568 bnx2x_free_mem(bp);
9569
9570 bp->state = BNX2X_STATE_CLOSED;
9571
f8ef6e44
YG		 9572 return 0;
9573}
9574
9575static void bnx2x_eeh_recover(struct bnx2x *bp)
9576{
9577 u32 val;
9578
9579 mutex_init(&bp->port.phy_mutex);
9580
9581 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9582 bp->link_params.shmem_base = bp->common.shmem_base;
9583 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9584
9585 if (!bp->common.shmem_base ||
9586 (bp->common.shmem_base < 0xA0000) ||
9587 (bp->common.shmem_base >= 0xC0000)) {
9588 BNX2X_DEV_INFO("MCP not active\n");
9589 bp->flags |= NO_MCP_FLAG;
9590 return;
9591 }
9592
9593 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9594 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9595 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9596 BNX2X_ERR("BAD MCP validity signature\n");
9597
9598 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 9599 bp->fw_seq =
9600 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9601 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 9602 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9603 }
9604}
9605
493adb1f
WX		 9606/**
9607 * bnx2x_io_error_detected - called when PCI error is detected
9608 * @pdev: Pointer to PCI device
9609 * @state: The current pci connection state
9610 *
9611 * This function is called after a PCI bus error affecting
9612 * this device has been detected.
9613 */
9614static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9615 pci_channel_state_t state)
9616{
9617 struct net_device *dev = pci_get_drvdata(pdev);
9618 struct bnx2x *bp = netdev_priv(dev);
9619
9620 rtnl_lock();
9621
9622 netif_device_detach(dev);
9623
07ce50e4
DN		 9624 if (state == pci_channel_io_perm_failure) {
9625 rtnl_unlock();
9626 return PCI_ERS_RESULT_DISCONNECT;
9627 }
9628
493adb1f 9629 if (netif_running(dev))
f8ef6e44 9630 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 9631
9632 pci_disable_device(pdev);
9633
9634 rtnl_unlock();
9635
9636 /* Request a slot reset */
9637 return PCI_ERS_RESULT_NEED_RESET;
9638}
9639
9640/**
9641 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9642 * @pdev: Pointer to PCI device
9643 *
9644 * Restart the card from scratch, as if from a cold-boot.
9645 */
9646static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9647{
9648 struct net_device *dev = pci_get_drvdata(pdev);
9649 struct bnx2x *bp = netdev_priv(dev);
9650
9651 rtnl_lock();
9652
9653 if (pci_enable_device(pdev)) {
9654 dev_err(&pdev->dev,
9655 "Cannot re-enable PCI device after reset\n");
9656 rtnl_unlock();
9657 return PCI_ERS_RESULT_DISCONNECT;
9658 }
9659
9660 pci_set_master(pdev);
9661 pci_restore_state(pdev);
9662
9663 if (netif_running(dev))
9664 bnx2x_set_power_state(bp, PCI_D0);
9665
9666 rtnl_unlock();
9667
9668 return PCI_ERS_RESULT_RECOVERED;
9669}
9670
9671/**
9672 * bnx2x_io_resume - called when traffic can start flowing again
9673 * @pdev: Pointer to PCI device
9674 *
9675 * This callback is called when the error recovery driver tells us that
9676 * its OK to resume normal operation.
9677 */
9678static void bnx2x_io_resume(struct pci_dev *pdev)
9679{
9680 struct net_device *dev = pci_get_drvdata(pdev);
9681 struct bnx2x *bp = netdev_priv(dev);
9682
72fd0718 9683 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
f2e0899f
DK		 9684 printk(KERN_ERR "Handling parity error recovery. "
9685 "Try again later\n");
72fd0718
VZ		 9686 return;
9687 }
9688
493adb1f
WX		 9689 rtnl_lock();
9690
f8ef6e44
YG		 9691 bnx2x_eeh_recover(bp);
9692
493adb1f 9693 if (netif_running(dev))
f8ef6e44 9694 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 9695
9696 netif_device_attach(dev);
9697
9698 rtnl_unlock();
9699}
9700
9701static struct pci_error_handlers bnx2x_err_handler = {
9702 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 9703 .slot_reset = bnx2x_io_slot_reset,
9704 .resume = bnx2x_io_resume,
493adb1f
WX		 9705};
9706
a2fbb9ea 9707static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 9708 .name = DRV_MODULE_NAME,
9709 .id_table = bnx2x_pci_tbl,
9710 .probe = bnx2x_init_one,
9711 .remove = __devexit_p(bnx2x_remove_one),
9712 .suspend = bnx2x_suspend,
9713 .resume = bnx2x_resume,
9714 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 9715};
9716
9717static int __init bnx2x_init(void)
9718{
dd21ca6d
SG		 9719 int ret;
9720
7995c64e 9721 pr_info("%s", version);
938cf541 9722
1cf167f2
EG		 9723 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9724 if (bnx2x_wq == NULL) {
7995c64e 9725 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 9726 return -ENOMEM;
9727 }
9728
dd21ca6d
SG		 9729 ret = pci_register_driver(&bnx2x_pci_driver);
9730 if (ret) {
7995c64e 9731 pr_err("Cannot register driver\n");
dd21ca6d
SG		 9732 destroy_workqueue(bnx2x_wq);
9733 }
9734 return ret;
a2fbb9ea
ET		 9735}
9736
9737static void __exit bnx2x_cleanup(void)
9738{
9739 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 9740
9741 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 9742}
9743
9744module_init(bnx2x_init);
9745module_exit(bnx2x_cleanup);
9746
993ac7b5
MC		 9747#ifdef BCM_CNIC
9748
9749/* count denotes the number of new completions we have seen */
9750static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9751{
9752 struct eth_spe *spe;
9753
9754#ifdef BNX2X_STOP_ON_ERROR
9755 if (unlikely(bp->panic))
9756 return;
9757#endif
9758
9759 spin_lock_bh(&bp->spq_lock);
c2bff63f 9760 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 9761 bp->cnic_spq_pending -= count;
9762
993ac7b5 9763
c2bff63f
DK		 9764 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9765 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9766 & SPE_HDR_CONN_TYPE) >>
9767 SPE_HDR_CONN_TYPE_SHIFT;
9768
9769 /* Set validation for iSCSI L2 client before sending SETUP
9770 * ramrod
9771 */
9772 if (type == ETH_CONNECTION_TYPE) {
9773 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9774 hdr.conn_and_cmd_data) >>
9775 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9776
9777 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9778 bnx2x_set_ctx_validation(&bp->context.
9779 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9780 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9781 }
9782
9783 /* There may be not more than 8 L2 and COMMON SPEs and not more
9784 * than 8 L5 SPEs in the air.
9785 */
9786 if ((type == NONE_CONNECTION_TYPE) ||
9787 (type == ETH_CONNECTION_TYPE)) {
9788 if (!atomic_read(&bp->spq_left))
9789 break;
9790 else
9791 atomic_dec(&bp->spq_left);
ec6ba945
VZ		 9792 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9793 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 9794 if (bp->cnic_spq_pending >=
9795 bp->cnic_eth_dev.max_kwqe_pending)
9796 break;
9797 else
9798 bp->cnic_spq_pending++;
9799 } else {
9800 BNX2X_ERR("Unknown SPE type: %d\n", type);
9801 bnx2x_panic();
993ac7b5 9802 break;
c2bff63f 9803 }
993ac7b5
MC		 9804
9805 spe = bnx2x_sp_get_next(bp);
9806 *spe = *bp->cnic_kwq_cons;
9807
993ac7b5
MC		 9808 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9809 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9810
9811 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9812 bp->cnic_kwq_cons = bp->cnic_kwq;
9813 else
9814 bp->cnic_kwq_cons++;
9815 }
9816 bnx2x_sp_prod_update(bp);
9817 spin_unlock_bh(&bp->spq_lock);
9818}
9819
9820static int bnx2x_cnic_sp_queue(struct net_device *dev,
9821 struct kwqe_16 *kwqes[], u32 count)
9822{
9823 struct bnx2x *bp = netdev_priv(dev);
9824 int i;
9825
9826#ifdef BNX2X_STOP_ON_ERROR
9827 if (unlikely(bp->panic))
9828 return -EIO;
9829#endif
9830
9831 spin_lock_bh(&bp->spq_lock);
9832
9833 for (i = 0; i < count; i++) {
9834 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
9835
9836 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
9837 break;
9838
9839 *bp->cnic_kwq_prod = *spe;
9840
9841 bp->cnic_kwq_pending++;
9842
9843 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
9844 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 9845 spe->data.update_data_addr.hi,
9846 spe->data.update_data_addr.lo,
993ac7b5
MC		 9847 bp->cnic_kwq_pending);
9848
9849 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
9850 bp->cnic_kwq_prod = bp->cnic_kwq;
9851 else
9852 bp->cnic_kwq_prod++;
9853 }
9854
9855 spin_unlock_bh(&bp->spq_lock);
9856
9857 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
9858 bnx2x_cnic_sp_post(bp, 0);
9859
9860 return i;
9861}
9862
9863static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9864{
9865 struct cnic_ops *c_ops;
9866 int rc = 0;
9867
9868 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 9869 c_ops = rcu_dereference_protected(bp->cnic_ops,
9870 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 9871 if (c_ops)
9872 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9873 mutex_unlock(&bp->cnic_mutex);
9874
9875 return rc;
9876}
9877
9878static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9879{
9880 struct cnic_ops *c_ops;
9881 int rc = 0;
9882
9883 rcu_read_lock();
9884 c_ops = rcu_dereference(bp->cnic_ops);
9885 if (c_ops)
9886 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9887 rcu_read_unlock();
9888
9889 return rc;
9890}
9891
9892/*
9893 * for commands that have no data
9894 */
9f6c9258 9895int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 9896{
9897 struct cnic_ctl_info ctl = {0};
9898
9899 ctl.cmd = cmd;
9900
9901 return bnx2x_cnic_ctl_send(bp, &ctl);
9902}
9903
9904static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
9905{
9906 struct cnic_ctl_info ctl;
9907
9908 /* first we tell CNIC and only then we count this as a completion */
9909 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
9910 ctl.data.comp.cid = cid;
9911
9912 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 9913 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 9914}
9915
9916static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
9917{
9918 struct bnx2x *bp = netdev_priv(dev);
9919 int rc = 0;
9920
9921 switch (ctl->cmd) {
9922 case DRV_CTL_CTXTBL_WR_CMD: {
9923 u32 index = ctl->data.io.offset;
9924 dma_addr_t addr = ctl->data.io.dma_addr;
9925
9926 bnx2x_ilt_wr(bp, index, addr);
9927 break;
9928 }
9929
c2bff63f
DK		 9930 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
9931 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 9932
9933 bnx2x_cnic_sp_post(bp, count);
9934 break;
9935 }
9936
9937 /* rtnl_lock is held. */
9938 case DRV_CTL_START_L2_CMD: {
9939 u32 cli = ctl->data.ring.client_id;
9940
ec6ba945
VZ		 9941 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
9942 bnx2x_del_fcoe_eth_macs(bp);
9943
523224a3
DK		 9944 /* Set iSCSI MAC address */
9945 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
9946
9947 mmiowb();
9948 barrier();
9949
9950 /* Start accepting on iSCSI L2 ring. Accept all multicasts
9951 * because it's the only way for UIO Client to accept
9952 * multicasts (in non-promiscuous mode only one Client per
9953 * function will receive multicast packets (leading in our
9954 * case).
9955 */
9956 bnx2x_rxq_set_mac_filters(bp, cli,
9957 BNX2X_ACCEPT_UNICAST |
9958 BNX2X_ACCEPT_BROADCAST |
9959 BNX2X_ACCEPT_ALL_MULTICAST);
9960 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
9961
993ac7b5
MC		 9962 break;
9963 }
9964
9965 /* rtnl_lock is held. */
9966 case DRV_CTL_STOP_L2_CMD: {
9967 u32 cli = ctl->data.ring.client_id;
9968
523224a3
DK		 9969 /* Stop accepting on iSCSI L2 ring */
9970 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
9971 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
9972
9973 mmiowb();
9974 barrier();
9975
9976 /* Unset iSCSI L2 MAC */
9977 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
993ac7b5
MC		 9978 break;
9979 }
c2bff63f
DK		 9980 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
9981 int count = ctl->data.credit.credit_count;
9982
9983 smp_mb__before_atomic_inc();
9984 atomic_add(count, &bp->spq_left);
9985 smp_mb__after_atomic_inc();
9986 break;
9987 }
993ac7b5
MC		 9988
9989 default:
9990 BNX2X_ERR("unknown command %x\n", ctl->cmd);
9991 rc = -EINVAL;
9992 }
9993
9994 return rc;
9995}
9996
9f6c9258 9997void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 9998{
9999 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10000
10001 if (bp->flags & USING_MSIX_FLAG) {
10002 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10003 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10004 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10005 } else {
10006 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10007 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10008 }
f2e0899f
DK		 10009 if (CHIP_IS_E2(bp))
10010 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10011 else
10012 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10013
993ac7b5 10014 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
523224a3 10015 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
993ac7b5
MC		 10016 cp->irq_arr[1].status_blk = bp->def_status_blk;
10017 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 10018 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 10019
10020 cp->num_irq = 2;
10021}
10022
10023static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10024 void *data)
10025{
10026 struct bnx2x *bp = netdev_priv(dev);
10027 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10028
10029 if (ops == NULL)
10030 return -EINVAL;
10031
10032 if (atomic_read(&bp->intr_sem) != 0)
10033 return -EBUSY;
10034
10035 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10036 if (!bp->cnic_kwq)
10037 return -ENOMEM;
10038
10039 bp->cnic_kwq_cons = bp->cnic_kwq;
10040 bp->cnic_kwq_prod = bp->cnic_kwq;
10041 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10042
10043 bp->cnic_spq_pending = 0;
10044 bp->cnic_kwq_pending = 0;
10045
10046 bp->cnic_data = data;
10047
10048 cp->num_irq = 0;
10049 cp->drv_state = CNIC_DRV_STATE_REGD;
523224a3 10050 cp->iro_arr = bp->iro_arr;
993ac7b5 10051
993ac7b5 10052 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 10053
993ac7b5
MC		 10054 rcu_assign_pointer(bp->cnic_ops, ops);
10055
10056 return 0;
10057}
10058
10059static int bnx2x_unregister_cnic(struct net_device *dev)
10060{
10061 struct bnx2x *bp = netdev_priv(dev);
10062 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10063
10064 mutex_lock(&bp->cnic_mutex);
993ac7b5
MC		 10065 cp->drv_state = 0;
10066 rcu_assign_pointer(bp->cnic_ops, NULL);
10067 mutex_unlock(&bp->cnic_mutex);
10068 synchronize_rcu();
10069 kfree(bp->cnic_kwq);
10070 bp->cnic_kwq = NULL;
10071
10072 return 0;
10073}
10074
10075struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10076{
10077 struct bnx2x *bp = netdev_priv(dev);
10078 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10079
10080 cp->drv_owner = THIS_MODULE;
10081 cp->chip_id = CHIP_ID(bp);
10082 cp->pdev = bp->pdev;
10083 cp->io_base = bp->regview;
10084 cp->io_base2 = bp->doorbells;
10085 cp->max_kwqe_pending = 8;
523224a3 10086 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 10087 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10088 bnx2x_cid_ilt_lines(bp);
993ac7b5 10089 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 10090 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 10091 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10092 cp->drv_ctl = bnx2x_drv_ctl;
10093 cp->drv_register_cnic = bnx2x_register_cnic;
10094 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945
VZ		 10095 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10096 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10097 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
c2bff63f
DK		 10098 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10099
10100 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10101 "starting cid %d\n",
10102 cp->ctx_blk_size,
10103 cp->ctx_tbl_offset,
10104 cp->ctx_tbl_len,
10105 cp->starting_cid);
993ac7b5
MC		 10106 return cp;
10107}
10108EXPORT_SYMBOL(bnx2x_cnic_probe);
10109
10110#endif /* BCM_CNIC */
94a78b79 10111
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