[people/ms/u-boot.git] / drivers / net / cs8900.c

/*
 * Cirrus Logic CS8900A Ethernet
 *
 * (C) 2009 Ben Warren , biggerbadderben@gmail.com
 *     Converted to use CONFIG_NET_MULTI API
 *
 * (C) 2003 Wolfgang Denk, wd@denx.de
 *     Extension to synchronize ethaddr environment variable
 *     against value in EEPROM
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is loaded into SRAM in bootstrap mode, where it waits
 * for commands on UART1 to read and write memory, jump to code etc.
 * A design goal for this program is to be entirely independent of the
 * target board.  Anything with a CL-PS7111 or EP7211 should be able to run
 * this code in bootstrap mode.  All the board specifics can be handled on
 * the host.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <net.h>
#include <malloc.h>
#include "cs8900.h"

#undef DEBUG

/* packet page register access functions */

#ifdef CONFIG_CS8900_BUS32

#define REG_WRITE(v, a) writel((v),(a))
#define REG_READ(a) readl((a))

/* we don't need 16 bit initialisation on 32 bit bus */
#define get_reg_init_bus(r,d) get_reg((r),(d))

#else

#define REG_WRITE(v, a) writew((v),(a))
#define REG_READ(a) readw((a))

static u16 get_reg_init_bus(struct eth_device *dev, int regno)
{
	/* force 16 bit busmode */
	volatile u8 c;
	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
	uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;

	c = readb(iob);
	c = readb(iob + 1);
	c = readb(iob);
	c = readb(iob + 1);
	c = readb(iob);

	REG_WRITE(regno, &priv->regs->pptr);
	return REG_READ(&priv->regs->pdata);
}
#endif

static u16 get_reg(struct eth_device *dev, int regno)
{
	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
	REG_WRITE(regno, &priv->regs->pptr);
	return REG_READ(&priv->regs->pdata);
}


static void put_reg(struct eth_device *dev, int regno, u16 val)
{
	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
	REG_WRITE(regno, &priv->regs->pptr);
	REG_WRITE(val, &priv->regs->pdata);
}

static void cs8900_reset(struct eth_device *dev)
{
	int tmo;
	u16 us;

	/* reset NIC */
	put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);

	/* wait for 200ms */
	udelay(200000);
	/* Wait until the chip is reset */

	tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
	while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
		PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
		/*NOP*/;
}

static void cs8900_reginit(struct eth_device *dev)
{
	/* receive only error free packets addressed to this card */
	put_reg(dev, PP_RxCTL,
		PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
	/* do not generate any interrupts on receive operations */
	put_reg(dev, PP_RxCFG, 0);
	/* do not generate any interrupts on transmit operations */
	put_reg(dev, PP_TxCFG, 0);
	/* do not generate any interrupts on buffer operations */
	put_reg(dev, PP_BufCFG, 0);
	/* enable transmitter/receiver mode */
	put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
}

void cs8900_get_enetaddr(struct eth_device *dev)
{
	int i;

	/* verify chip id */
	if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
		return;
	cs8900_reset(dev);
	if ((get_reg(dev, PP_SelfSTAT) &
		(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
		(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {

		/* Load the MAC from EEPROM */
		for (i = 0; i < 3; i++) {
			u32 Addr;

			Addr = get_reg(dev, PP_IA + i * 2);
			dev->enetaddr[i * 2] = Addr & 0xFF;
			dev->enetaddr[i * 2 + 1] = Addr >> 8;
		}
	}
}

void cs8900_halt(struct eth_device *dev)
{
	/* disable transmitter/receiver mode */
	put_reg(dev, PP_LineCTL, 0);

	/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
	get_reg_init_bus(dev, PP_ChipID);
}

static int cs8900_init(struct eth_device *dev, bd_t * bd)
{
	uchar *enetaddr = dev->enetaddr;
	u16 id;

	/* verify chip id */
	id = get_reg_init_bus(dev, PP_ChipID);
	if (id != 0x630e) {
		printf ("CS8900 Ethernet chip not found: "
			"ID=0x%04x instead 0x%04x\n", id, 0x630e);
		return 1;
	}

	cs8900_reset (dev);
	/* set the ethernet address */
	put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
	put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
	put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));

	cs8900_reginit(dev);
	return 0;
}

/* Get a data block via Ethernet */
static int cs8900_recv(struct eth_device *dev)
{
	int i;
	u16 rxlen;
	u16 *addr;
	u16 status;

	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);

	status = get_reg(dev, PP_RER);

	if ((status & PP_RER_RxOK) == 0)
		return 0;

	status = REG_READ(&priv->regs->rtdata);
	rxlen = REG_READ(&priv->regs->rtdata);

	if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
		debug("packet too big!\n");
	for (addr = (u16 *) NetRxPackets[0], i = rxlen >> 1; i > 0;
		 i--)
		*addr++ = REG_READ(&priv->regs->rtdata);
	if (rxlen & 1)
		*addr++ = REG_READ(&priv->regs->rtdata);

	/* Pass the packet up to the protocol layers. */
	NetReceive (NetRxPackets[0], rxlen);
	return rxlen;
}

/* Send a data block via Ethernet. */
static int cs8900_send(struct eth_device *dev,
			volatile void *packet, int length)
{
	volatile u16 *addr;
	int tmo;
	u16 s;
	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);

retry:
	/* initiate a transmit sequence */
	REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
	REG_WRITE(length, &priv->regs->txlen);

	/* Test to see if the chip has allocated memory for the packet */
	if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
		/* Oops... this should not happen! */
		debug("cs: unable to send packet; retrying...\n");
		for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
			get_timer(0) < tmo;)
			/*NOP*/;
		cs8900_reset(dev);
		cs8900_reginit(dev);
		goto retry;
	}

	/* Write the contents of the packet */
	/* assume even number of bytes */
	for (addr = packet; length > 0; length -= 2)
		REG_WRITE(*addr++, &priv->regs->rtdata);

	/* wait for transfer to succeed */
	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
		if (get_timer(0) >= tmo)
			break;
	}

	/* nothing */ ;
	if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
		debug("\ntransmission error %#x\n", s);
	}

	return 0;
}

static void cs8900_e2prom_ready(struct eth_device *dev)
{
	while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
		;
}

/***********************************************************/
/* read a 16-bit word out of the EEPROM                    */
/***********************************************************/

int cs8900_e2prom_read(struct eth_device *dev,
			u8 addr, u16 *value)
{
	cs8900_e2prom_ready(dev);
	put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
	cs8900_e2prom_ready(dev);
	*value = get_reg(dev, PP_EEData);

	return 0;
}


/***********************************************************/
/* write a 16-bit word into the EEPROM                     */
/***********************************************************/

int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
{
	cs8900_e2prom_ready(dev);
	put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
	cs8900_e2prom_ready(dev);
	put_reg(dev, PP_EEData, value);
	put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
	cs8900_e2prom_ready(dev);
	put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
	cs8900_e2prom_ready(dev);

	return 0;
}

int cs8900_initialize(u8 dev_num, int base_addr)
{
	struct eth_device *dev;
	struct cs8900_priv *priv;

	dev = malloc(sizeof(*dev));
	if (!dev) {
		return 0;
	}
	memset(dev, 0, sizeof(*dev));

	priv = malloc(sizeof(*priv));
	if (!priv) {
		free(dev);
		return 0;
	}
	memset(priv, 0, sizeof(*priv));
	priv->regs = (struct cs8900_regs *)base_addr;

	dev->iobase = base_addr;
	dev->priv = priv;
	dev->init = cs8900_init;
	dev->halt = cs8900_halt;
	dev->send = cs8900_send;
	dev->recv = cs8900_recv;

	/* Load MAC address from EEPROM */
	cs8900_get_enetaddr(dev);

	sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);

	eth_register(dev);
	return 0;
}
Commit	Line	Data
c609719b WD	1	/*
	2	* Cirrus Logic CS8900A Ethernet
	3	*
b1c0eaac BW	4	* (C) 2009 Ben Warren , biggerbadderben@gmail.com
	5	* Converted to use CONFIG_NET_MULTI API
	6	*
6069ff26 WD	7	* (C) 2003 Wolfgang Denk, wd@denx.de
	8	* Extension to synchronize ethaddr environment variable
	9	* against value in EEPROM
	10	*
c609719b WD	11	* (C) Copyright 2002
	12	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	13	* Marius Groeger <mgroeger@sysgo.de>
	14	*
	15	* Copyright (C) 1999 Ben Williamson <benw@pobox.com>
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is loaded into SRAM in bootstrap mode, where it waits
	21	* for commands on UART1 to read and write memory, jump to code etc.
	22	* A design goal for this program is to be entirely independent of the
	23	* target board. Anything with a CL-PS7111 or EP7211 should be able to run
	24	* this code in bootstrap mode. All the board specifics can be handled on
	25	* the host.
	26	*
	27	* This program is free software; you can redistribute it and/or modify
	28	* it under the terms of the GNU General Public License as published by
	29	* the Free Software Foundation; either version 2 of the License, or
	30	* (at your option) any later version.
	31	*
	32	* This program is distributed in the hope that it will be useful,
	33	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	34	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	35	* GNU General Public License for more details.
	36	*
	37	* You should have received a copy of the GNU General Public License
	38	* along with this program; if not, write to the Free Software
	39	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	40	*/
	41
	42	#include <common.h>
	43	#include <command.h>
b1c0eaac	44	#include <asm/io.h>
c609719b	45	#include <net.h>
b1c0eaac BW	46	#include <malloc.h>
b1c0eaac BW	47	#include "cs8900.h"
c609719b	48
a2663ea4	49	#undef DEBUG
c609719b WD	50
	51	/* packet page register access functions */
	52
b1c0eaac BW	53	#ifdef CONFIG_CS8900_BUS32
	54
	55	#define REG_WRITE(v, a) writel((v),(a))
	56	#define REG_READ(a) readl((a))
	57
c609719b	58	/* we don't need 16 bit initialisation on 32 bit bus */
830c7b67	59	#define get_reg_init_bus(r,d) get_reg((r),(d))
b1c0eaac	60
c609719b	61	#else
6069ff26	62
b1c0eaac BW	63	#define REG_WRITE(v, a) writew((v),(a))
b1c0eaac BW	64	#define REG_READ(a) readw((a))
6069ff26	65
b1c0eaac BW	66	static u16 get_reg_init_bus(struct eth_device *dev, int regno)
	67	{
	68	/* force 16 bit busmode */
	69	volatile u8 c;
	70	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
	71	uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
	72
	73	c = readb(iob);
	74	c = readb(iob + 1);
	75	c = readb(iob);
	76	c = readb(iob + 1);
	77	c = readb(iob);
	78
	79	REG_WRITE(regno, &priv->regs->pptr);
	80	return REG_READ(&priv->regs->pdata);
c609719b WD	81	}
	82	#endif
	83
b1c0eaac	84	static u16 get_reg(struct eth_device *dev, int regno)
c609719b	85	{
b1c0eaac BW	86	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
	87	REG_WRITE(regno, &priv->regs->pptr);
	88	return REG_READ(&priv->regs->pdata);
c609719b WD	89	}
	90
	91
b1c0eaac	92	static void put_reg(struct eth_device *dev, int regno, u16 val)
c609719b	93	{
b1c0eaac BW	94	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
	95	REG_WRITE(regno, &priv->regs->pptr);
	96	REG_WRITE(val, &priv->regs->pdata);
c609719b WD	97	}
c609719b WD	98
b1c0eaac	99	static void cs8900_reset(struct eth_device *dev)
c609719b	100	{
6069ff26	101	int tmo;
b1c0eaac	102	u16 us;
c609719b	103
6069ff26	104	/* reset NIC */
b1c0eaac	105	put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) \| PP_SelfCTL_Reset);
c609719b	106
6069ff26	107	/* wait for 200ms */
b1c0eaac	108	udelay(200000);
6069ff26	109	/* Wait until the chip is reset */
c609719b	110
b1c0eaac BW	111	tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
	112	while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
	113	PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
6069ff26	114	/NOP/;
c609719b WD	115	}
c609719b WD	116
b1c0eaac	117	static void cs8900_reginit(struct eth_device *dev)
a2663ea4 WD	118	{
a2663ea4 WD	119	/* receive only error free packets addressed to this card */
b1c0eaac BW	120	put_reg(dev, PP_RxCTL,
b1c0eaac BW	121	PP_RxCTL_IA \| PP_RxCTL_Broadcast \| PP_RxCTL_RxOK);
a2663ea4	122	/* do not generate any interrupts on receive operations */
b1c0eaac	123	put_reg(dev, PP_RxCFG, 0);
a2663ea4	124	/* do not generate any interrupts on transmit operations */
b1c0eaac	125	put_reg(dev, PP_TxCFG, 0);
a2663ea4	126	/* do not generate any interrupts on buffer operations */
b1c0eaac	127	put_reg(dev, PP_BufCFG, 0);
a2663ea4	128	/* enable transmitter/receiver mode */
b1c0eaac	129	put_reg(dev, PP_LineCTL, PP_LineCTL_Rx \| PP_LineCTL_Tx);
a2663ea4 WD	130	}
a2663ea4 WD	131
b1c0eaac	132	void cs8900_get_enetaddr(struct eth_device *dev)
c609719b	133	{
6069ff26	134	int i;
6069ff26 WD	135
6069ff26 WD	136	/* verify chip id */
b1c0eaac	137	if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
6069ff26	138	return;
b1c0eaac BW	139	cs8900_reset(dev);
	140	if ((get_reg(dev, PP_SelfSTAT) &
	141	(PP_SelfSTAT_EEPROM \| PP_SelfSTAT_EEPROM_OK)) ==
	142	(PP_SelfSTAT_EEPROM \| PP_SelfSTAT_EEPROM_OK)) {
6069ff26 WD	143
6069ff26 WD	144	/* Load the MAC from EEPROM */
b1c0eaac BW	145	for (i = 0; i < 3; i++) {
b1c0eaac BW	146	u32 Addr;
6069ff26	147
b1c0eaac BW	148	Addr = get_reg(dev, PP_IA + i * 2);
	149	dev->enetaddr[i * 2] = Addr & 0xFF;
	150	dev->enetaddr[i * 2 + 1] = Addr >> 8;
6069ff26	151	}
c609719b	152	}
c609719b WD	153	}
c609719b WD	154
b1c0eaac	155	void cs8900_halt(struct eth_device *dev)
c609719b	156	{
6069ff26	157	/* disable transmitter/receiver mode */
b1c0eaac	158	put_reg(dev, PP_LineCTL, 0);
c609719b	159
6069ff26	160	/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
b1c0eaac	161	get_reg_init_bus(dev, PP_ChipID);
c609719b WD	162	}
c609719b WD	163
b1c0eaac	164	static int cs8900_init(struct eth_device dev, bd_t bd)
c609719b	165	{
b1c0eaac BW	166	uchar *enetaddr = dev->enetaddr;
b1c0eaac BW	167	u16 id;
0a5238ce	168
6069ff26	169	/* verify chip id */
b1c0eaac BW	170	id = get_reg_init_bus(dev, PP_ChipID);
	171	if (id != 0x630e) {
	172	printf ("CS8900 Ethernet chip not found: "
	173	"ID=0x%04x instead 0x%04x\n", id, 0x630e);
	174	return 1;
6069ff26	175	}
c609719b	176
b1c0eaac	177	cs8900_reset (dev);
6069ff26	178	/* set the ethernet address */
b1c0eaac BW	179	put_reg(dev, PP_IA + 0, enetaddr[0] \| (enetaddr[1] << 8));
	180	put_reg(dev, PP_IA + 2, enetaddr[2] \| (enetaddr[3] << 8));
	181	put_reg(dev, PP_IA + 4, enetaddr[4] \| (enetaddr[5] << 8));
c609719b	182
b1c0eaac	183	cs8900_reginit(dev);
6069ff26	184	return 0;
c609719b WD	185	}
	186
	187	/* Get a data block via Ethernet */
b1c0eaac	188	static int cs8900_recv(struct eth_device *dev)
c609719b	189	{
6069ff26	190	int i;
b1c0eaac BW	191	u16 rxlen;
	192	u16 *addr;
	193	u16 status;
c609719b	194
b1c0eaac BW	195	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
	196
	197	status = get_reg(dev, PP_RER);
c609719b	198
6069ff26 WD	199	if ((status & PP_RER_RxOK) == 0)
6069ff26 WD	200	return 0;
c609719b	201
b1c0eaac BW	202	status = REG_READ(&priv->regs->rtdata);
b1c0eaac BW	203	rxlen = REG_READ(&priv->regs->rtdata);
c609719b	204
6069ff26	205	if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
b1c0eaac BW	206	debug("packet too big!\n");
b1c0eaac BW	207	for (addr = (u16 *) NetRxPackets[0], i = rxlen >> 1; i > 0;
6069ff26	208	i--)
b1c0eaac	209	*addr++ = REG_READ(&priv->regs->rtdata);
6069ff26	210	if (rxlen & 1)
b1c0eaac	211	*addr++ = REG_READ(&priv->regs->rtdata);
c609719b	212
6069ff26 WD	213	/* Pass the packet up to the protocol layers. */
6069ff26 WD	214	NetReceive (NetRxPackets[0], rxlen);
6069ff26	215	return rxlen;
c609719b WD	216	}
	217
	218	/* Send a data block via Ethernet. */
b1c0eaac BW	219	static int cs8900_send(struct eth_device *dev,
b1c0eaac BW	220	volatile void *packet, int length)
c609719b	221	{
b1c0eaac	222	volatile u16 *addr;
6069ff26	223	int tmo;
b1c0eaac BW	224	u16 s;
b1c0eaac BW	225	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
c609719b WD	226
c609719b WD	227	retry:
6069ff26	228	/* initiate a transmit sequence */
b1c0eaac BW	229	REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
b1c0eaac BW	230	REG_WRITE(length, &priv->regs->txlen);
6069ff26 WD	231
6069ff26 WD	232	/* Test to see if the chip has allocated memory for the packet */
b1c0eaac	233	if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
6069ff26	234	/* Oops... this should not happen! */
b1c0eaac BW	235	debug("cs: unable to send packet; retrying...\n");
	236	for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	237	get_timer(0) < tmo;)
6069ff26	238	/NOP/;
b1c0eaac BW	239	cs8900_reset(dev);
b1c0eaac BW	240	cs8900_reginit(dev);
6069ff26 WD	241	goto retry;
	242	}
	243
	244	/* Write the contents of the packet */
	245	/* assume even number of bytes */
	246	for (addr = packet; length > 0; length -= 2)
b1c0eaac	247	REG_WRITE(*addr++, &priv->regs->rtdata);
6069ff26 WD	248
6069ff26 WD	249	/* wait for transfer to succeed */
b1c0eaac BW	250	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	251	while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
	252	if (get_timer(0) >= tmo)
6069ff26 WD	253	break;
	254	}
	255
	256	/* nothing */ ;
b1c0eaac BW	257	if((s & (PP_TER_CRS \| PP_TER_TxOK)) != PP_TER_TxOK) {
b1c0eaac BW	258	debug("\ntransmission error %#x\n", s);
6069ff26 WD	259	}
	260
	261	return 0;
c609719b WD	262	}
c609719b WD	263
b1c0eaac	264	static void cs8900_e2prom_ready(struct eth_device *dev)
1cb8e980	265	{
b1c0eaac	266	while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
13e0b8f7	267	;
1cb8e980 WD	268	}
	269
	270	/***********************************************************/
	271	/* read a 16-bit word out of the EEPROM */
	272	/***********************************************************/
	273
b1c0eaac BW	274	int cs8900_e2prom_read(struct eth_device *dev,
b1c0eaac BW	275	u8 addr, u16 *value)
1cb8e980	276	{
b1c0eaac BW	277	cs8900_e2prom_ready(dev);
	278	put_reg(dev, PP_EECMD, EEPROM_READ_CMD \| addr);
	279	cs8900_e2prom_ready(dev);
	280	*value = get_reg(dev, PP_EEData);
1cb8e980 WD	281
	282	return 0;
	283	}
	284
	285
	286	/***********************************************************/
	287	/* write a 16-bit word into the EEPROM */
	288	/***********************************************************/
	289
b1c0eaac BW	290	int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
	291	{
	292	cs8900_e2prom_ready(dev);
	293	put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
	294	cs8900_e2prom_ready(dev);
	295	put_reg(dev, PP_EEData, value);
	296	put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD \| addr);
	297	cs8900_e2prom_ready(dev);
	298	put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
	299	cs8900_e2prom_ready(dev);
	300
	301	return 0;
	302	}
	303
	304	int cs8900_initialize(u8 dev_num, int base_addr)
1cb8e980	305	{
b1c0eaac BW	306	struct eth_device *dev;
	307	struct cs8900_priv *priv;
	308
	309	dev = malloc(sizeof(*dev));
	310	if (!dev) {
b1c0eaac BW	311	return 0;
	312	}
	313	memset(dev, 0, sizeof(*dev));
	314
	315	priv = malloc(sizeof(*priv));
	316	if (!priv) {
07c96606	317	free(dev);
b1c0eaac BW	318	return 0;
	319	}
	320	memset(priv, 0, sizeof(*priv));
	321	priv->regs = (struct cs8900_regs *)base_addr;
	322
b1c0eaac BW	323	dev->iobase = base_addr;
	324	dev->priv = priv;
	325	dev->init = cs8900_init;
	326	dev->halt = cs8900_halt;
	327	dev->send = cs8900_send;
	328	dev->recv = cs8900_recv;
497ab0ee HT	329
	330	/* Load MAC address from EEPROM */
	331	cs8900_get_enetaddr(dev);
	332
b1c0eaac	333	sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
1cb8e980	334
b1c0eaac	335	eth_register(dev);
06d01dbe	336	return 0;
1cb8e980	337	}