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Commit | Line | Data |
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c74b2108 SK |
1 | /* |
2 | * Ethernet driver for TI TMS320DM644x (DaVinci) chips. | |
3 | * | |
4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
5 | * | |
6 | * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright | |
7 | * follows: | |
8 | * | |
9 | * ---------------------------------------------------------------------------- | |
10 | * | |
11 | * dm644x_emac.c | |
12 | * | |
13 | * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM | |
14 | * | |
15 | * Copyright (C) 2005 Texas Instruments. | |
16 | * | |
17 | * ---------------------------------------------------------------------------- | |
18 | * | |
1a459660 | 19 | * SPDX-License-Identifier: GPL-2.0+ |
c74b2108 | 20 | * |
c74b2108 SK |
21 | * Modifications: |
22 | * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. | |
23 | * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors | |
c74b2108 SK |
24 | */ |
25 | #include <common.h> | |
26 | #include <command.h> | |
27 | #include <net.h> | |
28 | #include <miiphy.h> | |
8453587e | 29 | #include <malloc.h> |
ee3fad87 | 30 | #include <netdev.h> |
2aa87202 | 31 | #include <linux/compiler.h> |
c74b2108 | 32 | #include <asm/arch/emac_defs.h> |
d7e35437 | 33 | #include <asm/io.h> |
7c587d32 | 34 | #include "davinci_emac.h" |
c74b2108 | 35 | |
c74b2108 SK |
36 | unsigned int emac_dbg = 0; |
37 | #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) | |
38 | ||
82b77217 IY |
39 | #ifdef EMAC_HW_RAM_ADDR |
40 | static inline unsigned long BD_TO_HW(unsigned long x) | |
41 | { | |
42 | if (x == 0) | |
43 | return 0; | |
44 | ||
45 | return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; | |
46 | } | |
47 | ||
48 | static inline unsigned long HW_TO_BD(unsigned long x) | |
49 | { | |
50 | if (x == 0) | |
51 | return 0; | |
52 | ||
53 | return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; | |
54 | } | |
55 | #else | |
56 | #define BD_TO_HW(x) (x) | |
57 | #define HW_TO_BD(x) (x) | |
58 | #endif | |
59 | ||
d7e35437 | 60 | #ifdef DAVINCI_EMAC_GIG_ENABLE |
fb1d6332 | 61 | #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) |
d7e35437 | 62 | #else |
fb1d6332 | 63 | #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ |
d7e35437 NT |
64 | #endif |
65 | ||
882ecfa3 HS |
66 | #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) |
67 | #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ | |
68 | EMAC_MDIO_CLOCK_FREQ) - 1) | |
69 | #endif | |
70 | ||
fcaac589 | 71 | static void davinci_eth_mdio_enable(void); |
c74b2108 SK |
72 | |
73 | static int gen_init_phy(int phy_addr); | |
74 | static int gen_is_phy_connected(int phy_addr); | |
75 | static int gen_get_link_speed(int phy_addr); | |
76 | static int gen_auto_negotiate(int phy_addr); | |
77 | ||
c74b2108 SK |
78 | void eth_mdio_enable(void) |
79 | { | |
fcaac589 | 80 | davinci_eth_mdio_enable(); |
c74b2108 | 81 | } |
c74b2108 | 82 | |
c74b2108 SK |
83 | /* EMAC Addresses */ |
84 | static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; | |
85 | static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; | |
86 | static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; | |
87 | ||
88 | /* EMAC descriptors */ | |
89 | static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); | |
90 | static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); | |
91 | static volatile emac_desc *emac_rx_active_head = 0; | |
92 | static volatile emac_desc *emac_rx_active_tail = 0; | |
93 | static int emac_rx_queue_active = 0; | |
94 | ||
95 | /* Receive packet buffers */ | |
2aa87202 IY |
96 | static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] |
97 | __aligned(ARCH_DMA_MINALIGN); | |
c74b2108 | 98 | |
dc02bada HS |
99 | #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT |
100 | #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 | |
101 | #endif | |
062fe7d3 | 102 | |
c74b2108 | 103 | /* PHY address for a discovered PHY (0xff - not found) */ |
dc02bada | 104 | static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; |
062fe7d3 MH |
105 | |
106 | /* number of PHY found active */ | |
107 | static u_int8_t num_phy; | |
c74b2108 | 108 | |
dc02bada | 109 | phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; |
c74b2108 | 110 | |
7b37a27e BG |
111 | static int davinci_eth_set_mac_addr(struct eth_device *dev) |
112 | { | |
113 | unsigned long mac_hi; | |
114 | unsigned long mac_lo; | |
115 | ||
116 | /* | |
117 | * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast | |
118 | * receive) | |
119 | * Using channel 0 only - other channels are disabled | |
120 | * */ | |
121 | writel(0, &adap_emac->MACINDEX); | |
122 | mac_hi = (dev->enetaddr[3] << 24) | | |
123 | (dev->enetaddr[2] << 16) | | |
124 | (dev->enetaddr[1] << 8) | | |
125 | (dev->enetaddr[0]); | |
126 | mac_lo = (dev->enetaddr[5] << 8) | | |
127 | (dev->enetaddr[4]); | |
128 | ||
129 | writel(mac_hi, &adap_emac->MACADDRHI); | |
130 | #if defined(DAVINCI_EMAC_VERSION2) | |
131 | writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, | |
132 | &adap_emac->MACADDRLO); | |
133 | #else | |
134 | writel(mac_lo, &adap_emac->MACADDRLO); | |
135 | #endif | |
136 | ||
137 | writel(0, &adap_emac->MACHASH1); | |
138 | writel(0, &adap_emac->MACHASH2); | |
139 | ||
140 | /* Set source MAC address - REQUIRED */ | |
141 | writel(mac_hi, &adap_emac->MACSRCADDRHI); | |
142 | writel(mac_lo, &adap_emac->MACSRCADDRLO); | |
143 | ||
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
fcaac589 | 148 | static void davinci_eth_mdio_enable(void) |
c74b2108 SK |
149 | { |
150 | u_int32_t clkdiv; | |
151 | ||
882ecfa3 | 152 | clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; |
c74b2108 | 153 | |
d7e35437 NT |
154 | writel((clkdiv & 0xff) | |
155 | MDIO_CONTROL_ENABLE | | |
156 | MDIO_CONTROL_FAULT | | |
157 | MDIO_CONTROL_FAULT_ENABLE, | |
158 | &adap_mdio->CONTROL); | |
c74b2108 | 159 | |
d7e35437 NT |
160 | while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) |
161 | ; | |
c74b2108 SK |
162 | } |
163 | ||
164 | /* | |
165 | * Tries to find an active connected PHY. Returns 1 if address if found. | |
166 | * If no active PHY (or more than one PHY) found returns 0. | |
167 | * Sets active_phy_addr variable. | |
168 | */ | |
fcaac589 | 169 | static int davinci_eth_phy_detect(void) |
c74b2108 SK |
170 | { |
171 | u_int32_t phy_act_state; | |
172 | int i; | |
062fe7d3 MH |
173 | int j; |
174 | unsigned int count = 0; | |
175 | ||
dc02bada HS |
176 | for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) |
177 | active_phy_addr[i] = 0xff; | |
c74b2108 | 178 | |
062fe7d3 MH |
179 | udelay(1000); |
180 | phy_act_state = readl(&adap_mdio->ALIVE); | |
c74b2108 | 181 | |
d7e35437 | 182 | if (phy_act_state == 0) |
062fe7d3 | 183 | return 0; /* No active PHYs */ |
c74b2108 | 184 | |
fcaac589 | 185 | debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); |
c74b2108 | 186 | |
062fe7d3 | 187 | for (i = 0, j = 0; i < 32; i++) |
c74b2108 | 188 | if (phy_act_state & (1 << i)) { |
062fe7d3 | 189 | count++; |
b6090098 | 190 | if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { |
dc02bada HS |
191 | active_phy_addr[j++] = i; |
192 | } else { | |
193 | printf("%s: to many PHYs detected.\n", | |
194 | __func__); | |
195 | count = 0; | |
196 | break; | |
197 | } | |
c74b2108 | 198 | } |
c74b2108 | 199 | |
062fe7d3 MH |
200 | num_phy = count; |
201 | ||
202 | return count; | |
c74b2108 SK |
203 | } |
204 | ||
205 | ||
206 | /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ | |
fcaac589 | 207 | int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) |
c74b2108 SK |
208 | { |
209 | int tmp; | |
210 | ||
d7e35437 NT |
211 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
212 | ; | |
c74b2108 | 213 | |
d7e35437 NT |
214 | writel(MDIO_USERACCESS0_GO | |
215 | MDIO_USERACCESS0_WRITE_READ | | |
216 | ((reg_num & 0x1f) << 21) | | |
217 | ((phy_addr & 0x1f) << 16), | |
218 | &adap_mdio->USERACCESS0); | |
c74b2108 SK |
219 | |
220 | /* Wait for command to complete */ | |
d7e35437 NT |
221 | while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) |
222 | ; | |
c74b2108 SK |
223 | |
224 | if (tmp & MDIO_USERACCESS0_ACK) { | |
225 | *data = tmp & 0xffff; | |
05237f73 | 226 | return 1; |
c74b2108 SK |
227 | } |
228 | ||
05237f73 | 229 | return 0; |
c74b2108 SK |
230 | } |
231 | ||
232 | /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ | |
fcaac589 | 233 | int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) |
c74b2108 SK |
234 | { |
235 | ||
d7e35437 NT |
236 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
237 | ; | |
c74b2108 | 238 | |
d7e35437 NT |
239 | writel(MDIO_USERACCESS0_GO | |
240 | MDIO_USERACCESS0_WRITE_WRITE | | |
241 | ((reg_num & 0x1f) << 21) | | |
242 | ((phy_addr & 0x1f) << 16) | | |
243 | (data & 0xffff), | |
244 | &adap_mdio->USERACCESS0); | |
c74b2108 SK |
245 | |
246 | /* Wait for command to complete */ | |
d7e35437 NT |
247 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
248 | ; | |
c74b2108 | 249 | |
05237f73 | 250 | return 1; |
c74b2108 SK |
251 | } |
252 | ||
253 | /* PHY functions for a generic PHY */ | |
254 | static int gen_init_phy(int phy_addr) | |
255 | { | |
256 | int ret = 1; | |
257 | ||
258 | if (gen_get_link_speed(phy_addr)) { | |
259 | /* Try another time */ | |
260 | ret = gen_get_link_speed(phy_addr); | |
261 | } | |
262 | ||
263 | return(ret); | |
264 | } | |
265 | ||
266 | static int gen_is_phy_connected(int phy_addr) | |
267 | { | |
268 | u_int16_t dummy; | |
269 | ||
062fe7d3 MH |
270 | return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); |
271 | } | |
272 | ||
273 | static int get_active_phy(void) | |
274 | { | |
275 | int i; | |
276 | ||
277 | for (i = 0; i < num_phy; i++) | |
278 | if (phy[i].get_link_speed(active_phy_addr[i])) | |
279 | return i; | |
280 | ||
281 | return -1; /* Return error if no link */ | |
c74b2108 SK |
282 | } |
283 | ||
284 | static int gen_get_link_speed(int phy_addr) | |
285 | { | |
286 | u_int16_t tmp; | |
287 | ||
d2607401 SR |
288 | if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && |
289 | (tmp & 0x04)) { | |
290 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ | |
291 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
7d2fade7 | 292 | davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); |
d2607401 SR |
293 | |
294 | /* Speed doesn't matter, there is no setting for it in EMAC. */ | |
7d2fade7 | 295 | if (tmp & (LPA_100FULL | LPA_10FULL)) { |
d2607401 SR |
296 | /* set EMAC for Full Duplex */ |
297 | writel(EMAC_MACCONTROL_MIIEN_ENABLE | | |
298 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE, | |
299 | &adap_emac->MACCONTROL); | |
300 | } else { | |
301 | /*set EMAC for Half Duplex */ | |
302 | writel(EMAC_MACCONTROL_MIIEN_ENABLE, | |
303 | &adap_emac->MACCONTROL); | |
304 | } | |
305 | ||
7d2fade7 | 306 | if (tmp & (LPA_100FULL | LPA_100HALF)) |
d2607401 SR |
307 | writel(readl(&adap_emac->MACCONTROL) | |
308 | EMAC_MACCONTROL_RMIISPEED_100, | |
309 | &adap_emac->MACCONTROL); | |
310 | else | |
311 | writel(readl(&adap_emac->MACCONTROL) & | |
312 | ~EMAC_MACCONTROL_RMIISPEED_100, | |
313 | &adap_emac->MACCONTROL); | |
314 | #endif | |
c74b2108 | 315 | return(1); |
d2607401 | 316 | } |
c74b2108 SK |
317 | |
318 | return(0); | |
319 | } | |
320 | ||
321 | static int gen_auto_negotiate(int phy_addr) | |
322 | { | |
323 | u_int16_t tmp; | |
cc4bd47f MH |
324 | u_int16_t val; |
325 | unsigned long cntr = 0; | |
326 | ||
327 | if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) | |
328 | return 0; | |
329 | ||
330 | val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | | |
331 | BMCR_SPEED100; | |
332 | davinci_eth_phy_write(phy_addr, MII_BMCR, val); | |
333 | ||
334 | if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) | |
335 | return 0; | |
336 | ||
337 | val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | | |
338 | ADVERTISE_10HALF); | |
339 | davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); | |
c74b2108 | 340 | |
8ef583a0 | 341 | if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) |
c74b2108 SK |
342 | return(0); |
343 | ||
de820365 TR |
344 | #ifdef DAVINCI_EMAC_GIG_ENABLE |
345 | davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val); | |
346 | val |= PHY_1000BTCR_1000FD; | |
347 | val &= ~PHY_1000BTCR_1000HD; | |
348 | davinci_eth_phy_write(phy_addr, MII_CTRL1000, val); | |
349 | davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val); | |
350 | #endif | |
351 | ||
c74b2108 | 352 | /* Restart Auto_negotiation */ |
cc4bd47f | 353 | tmp |= BMCR_ANRESTART; |
8ef583a0 | 354 | davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); |
c74b2108 SK |
355 | |
356 | /*check AutoNegotiate complete */ | |
cc4bd47f MH |
357 | do { |
358 | udelay(40000); | |
359 | if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) | |
360 | return 0; | |
361 | ||
362 | if (tmp & BMSR_ANEGCOMPLETE) | |
363 | break; | |
364 | ||
365 | cntr++; | |
366 | } while (cntr < 200); | |
367 | ||
8ef583a0 | 368 | if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) |
c74b2108 SK |
369 | return(0); |
370 | ||
8ef583a0 | 371 | if (!(tmp & BMSR_ANEGCOMPLETE)) |
c74b2108 SK |
372 | return(0); |
373 | ||
374 | return(gen_get_link_speed(phy_addr)); | |
375 | } | |
376 | /* End of generic PHY functions */ | |
377 | ||
378 | ||
afaac86f | 379 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
5a49f174 JH |
380 | static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad, |
381 | int reg) | |
c74b2108 | 382 | { |
5a49f174 | 383 | unsigned short value = 0; |
875e0bc6 | 384 | int retval = davinci_eth_phy_read(addr, reg, &value); |
05237f73 | 385 | |
386 | return retval ? value : -EIO; | |
c74b2108 SK |
387 | } |
388 | ||
5a49f174 JH |
389 | static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad, |
390 | int reg, u16 value) | |
c74b2108 | 391 | { |
05237f73 | 392 | return davinci_eth_phy_write(addr, reg, value) ? 0 : 1; |
c74b2108 | 393 | } |
c74b2108 SK |
394 | #endif |
395 | ||
fb1d6332 | 396 | static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) |
d7e35437 NT |
397 | { |
398 | u_int16_t data; | |
399 | ||
fb1d6332 | 400 | if (davinci_eth_phy_read(phy_addr, 0, &data)) { |
d7e35437 NT |
401 | if (data & (1 << 6)) { /* speed selection MSB */ |
402 | /* | |
403 | * Check if link detected is giga-bit | |
404 | * If Gigabit mode detected, enable gigbit in MAC | |
405 | */ | |
4b9b9e7c SP |
406 | writel(readl(&adap_emac->MACCONTROL) | |
407 | EMAC_MACCONTROL_GIGFORCE | | |
408 | EMAC_MACCONTROL_GIGABIT_ENABLE, | |
409 | &adap_emac->MACCONTROL); | |
d7e35437 NT |
410 | } |
411 | } | |
412 | } | |
c74b2108 SK |
413 | |
414 | /* Eth device open */ | |
8453587e | 415 | static int davinci_eth_open(struct eth_device *dev, bd_t *bis) |
c74b2108 SK |
416 | { |
417 | dv_reg_p addr; | |
de820365 TR |
418 | u_int32_t clkdiv, cnt, mac_control; |
419 | uint16_t __maybe_unused lpa_val; | |
c74b2108 | 420 | volatile emac_desc *rx_desc; |
062fe7d3 | 421 | int index; |
c74b2108 SK |
422 | |
423 | debug_emac("+ emac_open\n"); | |
424 | ||
425 | /* Reset EMAC module and disable interrupts in wrapper */ | |
d7e35437 NT |
426 | writel(1, &adap_emac->SOFTRESET); |
427 | while (readl(&adap_emac->SOFTRESET) != 0) | |
428 | ; | |
429 | #if defined(DAVINCI_EMAC_VERSION2) | |
430 | writel(1, &adap_ewrap->softrst); | |
431 | while (readl(&adap_ewrap->softrst) != 0) | |
432 | ; | |
433 | #else | |
434 | writel(0, &adap_ewrap->EWCTL); | |
c74b2108 | 435 | for (cnt = 0; cnt < 5; cnt++) { |
d7e35437 | 436 | clkdiv = readl(&adap_ewrap->EWCTL); |
c74b2108 | 437 | } |
d7e35437 | 438 | #endif |
c74b2108 | 439 | |
d2607401 SR |
440 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ |
441 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
442 | adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; | |
443 | adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; | |
444 | adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; | |
445 | #endif | |
c74b2108 SK |
446 | rx_desc = emac_rx_desc; |
447 | ||
d7e35437 NT |
448 | writel(1, &adap_emac->TXCONTROL); |
449 | writel(1, &adap_emac->RXCONTROL); | |
c74b2108 | 450 | |
7b37a27e | 451 | davinci_eth_set_mac_addr(dev); |
c74b2108 SK |
452 | |
453 | /* Set DMA 8 TX / 8 RX Head pointers to 0 */ | |
454 | addr = &adap_emac->TX0HDP; | |
abbf2d9b | 455 | for (cnt = 0; cnt < 8; cnt++) |
d7e35437 | 456 | writel(0, addr++); |
c74b2108 SK |
457 | |
458 | addr = &adap_emac->RX0HDP; | |
abbf2d9b | 459 | for (cnt = 0; cnt < 8; cnt++) |
d7e35437 | 460 | writel(0, addr++); |
c74b2108 SK |
461 | |
462 | /* Clear Statistics (do this before setting MacControl register) */ | |
463 | addr = &adap_emac->RXGOODFRAMES; | |
464 | for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) | |
d7e35437 | 465 | writel(0, addr++); |
c74b2108 SK |
466 | |
467 | /* No multicast addressing */ | |
d7e35437 NT |
468 | writel(0, &adap_emac->MACHASH1); |
469 | writel(0, &adap_emac->MACHASH2); | |
c74b2108 SK |
470 | |
471 | /* Create RX queue and set receive process in place */ | |
472 | emac_rx_active_head = emac_rx_desc; | |
473 | for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { | |
82b77217 | 474 | rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); |
2aa87202 | 475 | rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; |
c74b2108 SK |
476 | rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; |
477 | rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; | |
478 | rx_desc++; | |
479 | } | |
480 | ||
d7e35437 | 481 | /* Finalize the rx desc list */ |
c74b2108 SK |
482 | rx_desc--; |
483 | rx_desc->next = 0; | |
484 | emac_rx_active_tail = rx_desc; | |
485 | emac_rx_queue_active = 1; | |
486 | ||
487 | /* Enable TX/RX */ | |
d7e35437 NT |
488 | writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); |
489 | writel(0, &adap_emac->RXBUFFEROFFSET); | |
c74b2108 | 490 | |
d7e35437 NT |
491 | /* |
492 | * No fancy configs - Use this for promiscous debug | |
493 | * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE | |
494 | */ | |
495 | writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); | |
c74b2108 SK |
496 | |
497 | /* Enable ch 0 only */ | |
d7e35437 | 498 | writel(1, &adap_emac->RXUNICASTSET); |
c74b2108 | 499 | |
c74b2108 | 500 | /* Init MDIO & get link state */ |
882ecfa3 | 501 | clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; |
d7e35437 NT |
502 | writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, |
503 | &adap_mdio->CONTROL); | |
504 | ||
505 | /* We need to wait for MDIO to start */ | |
506 | udelay(1000); | |
c74b2108 | 507 | |
062fe7d3 MH |
508 | index = get_active_phy(); |
509 | if (index == -1) | |
c74b2108 SK |
510 | return(0); |
511 | ||
de820365 TR |
512 | /* Enable MII interface */ |
513 | mac_control = EMAC_MACCONTROL_MIIEN_ENABLE; | |
514 | #ifdef DAVINCI_EMAC_GIG_ENABLE | |
515 | davinci_eth_phy_read(active_phy_addr[index], MII_STAT1000, &lpa_val); | |
516 | if (lpa_val & PHY_1000BTSR_1000FD) { | |
517 | debug_emac("eth_open : gigabit negotiated\n"); | |
518 | mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE; | |
519 | mac_control |= EMAC_MACCONTROL_GIGABIT_ENABLE; | |
520 | } | |
521 | #endif | |
d7e35437 | 522 | |
de820365 TR |
523 | davinci_eth_phy_read(active_phy_addr[index], MII_LPA, &lpa_val); |
524 | if (lpa_val & (LPA_100FULL | LPA_10FULL)) | |
525 | /* set EMAC for Full Duplex */ | |
526 | mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE; | |
527 | #if defined(CONFIG_SOC_DA8XX) || \ | |
528 | (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)) | |
529 | mac_control |= EMAC_MACCONTROL_RMIISPEED_100; | |
530 | #endif | |
531 | writel(mac_control, &adap_emac->MACCONTROL); | |
c74b2108 | 532 | /* Start receive process */ |
82b77217 | 533 | writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); |
c74b2108 SK |
534 | |
535 | debug_emac("- emac_open\n"); | |
536 | ||
537 | return(1); | |
538 | } | |
539 | ||
540 | /* EMAC Channel Teardown */ | |
fcaac589 | 541 | static void davinci_eth_ch_teardown(int ch) |
c74b2108 SK |
542 | { |
543 | dv_reg dly = 0xff; | |
544 | dv_reg cnt; | |
545 | ||
546 | debug_emac("+ emac_ch_teardown\n"); | |
547 | ||
548 | if (ch == EMAC_CH_TX) { | |
549 | /* Init TX channel teardown */ | |
ba511f77 | 550 | writel(0, &adap_emac->TXTEARDOWN); |
d7e35437 NT |
551 | do { |
552 | /* | |
553 | * Wait here for Tx teardown completion interrupt to | |
554 | * occur. Note: A task delay can be called here to pend | |
555 | * rather than occupying CPU cycles - anyway it has | |
556 | * been found that teardown takes very few cpu cycles | |
557 | * and does not affect functionality | |
558 | */ | |
559 | dly--; | |
560 | udelay(1); | |
561 | if (dly == 0) | |
53677ef1 | 562 | break; |
d7e35437 NT |
563 | cnt = readl(&adap_emac->TX0CP); |
564 | } while (cnt != 0xfffffffc); | |
565 | writel(cnt, &adap_emac->TX0CP); | |
566 | writel(0, &adap_emac->TX0HDP); | |
c74b2108 SK |
567 | } else { |
568 | /* Init RX channel teardown */ | |
ba511f77 | 569 | writel(0, &adap_emac->RXTEARDOWN); |
d7e35437 NT |
570 | do { |
571 | /* | |
572 | * Wait here for Rx teardown completion interrupt to | |
573 | * occur. Note: A task delay can be called here to pend | |
574 | * rather than occupying CPU cycles - anyway it has | |
575 | * been found that teardown takes very few cpu cycles | |
576 | * and does not affect functionality | |
577 | */ | |
578 | dly--; | |
579 | udelay(1); | |
580 | if (dly == 0) | |
53677ef1 | 581 | break; |
d7e35437 NT |
582 | cnt = readl(&adap_emac->RX0CP); |
583 | } while (cnt != 0xfffffffc); | |
584 | writel(cnt, &adap_emac->RX0CP); | |
585 | writel(0, &adap_emac->RX0HDP); | |
c74b2108 SK |
586 | } |
587 | ||
588 | debug_emac("- emac_ch_teardown\n"); | |
589 | } | |
590 | ||
591 | /* Eth device close */ | |
8453587e | 592 | static void davinci_eth_close(struct eth_device *dev) |
c74b2108 SK |
593 | { |
594 | debug_emac("+ emac_close\n"); | |
595 | ||
fcaac589 | 596 | davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ |
0b830198 JH |
597 | if (readl(&adap_emac->RXCONTROL) & 1) |
598 | davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ | |
c74b2108 SK |
599 | |
600 | /* Reset EMAC module and disable interrupts in wrapper */ | |
d7e35437 NT |
601 | writel(1, &adap_emac->SOFTRESET); |
602 | #if defined(DAVINCI_EMAC_VERSION2) | |
603 | writel(1, &adap_ewrap->softrst); | |
604 | #else | |
605 | writel(0, &adap_ewrap->EWCTL); | |
606 | #endif | |
c74b2108 | 607 | |
d2607401 SR |
608 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ |
609 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
610 | adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; | |
611 | adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; | |
612 | adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; | |
613 | #endif | |
c74b2108 | 614 | debug_emac("- emac_close\n"); |
c74b2108 SK |
615 | } |
616 | ||
617 | static int tx_send_loop = 0; | |
618 | ||
619 | /* | |
620 | * This function sends a single packet on the network and returns | |
621 | * positive number (number of bytes transmitted) or negative for error | |
622 | */ | |
8453587e | 623 | static int davinci_eth_send_packet (struct eth_device *dev, |
bbcdefb3 | 624 | void *packet, int length) |
c74b2108 SK |
625 | { |
626 | int ret_status = -1; | |
062fe7d3 | 627 | int index; |
c74b2108 SK |
628 | tx_send_loop = 0; |
629 | ||
062fe7d3 MH |
630 | index = get_active_phy(); |
631 | if (index == -1) { | |
632 | printf(" WARN: emac_send_packet: No link\n"); | |
c74b2108 SK |
633 | return (ret_status); |
634 | } | |
635 | ||
636 | /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ | |
53677ef1 | 637 | if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { |
c74b2108 SK |
638 | length = EMAC_MIN_ETHERNET_PKT_SIZE; |
639 | } | |
640 | ||
641 | /* Populate the TX descriptor */ | |
53677ef1 WD |
642 | emac_tx_desc->next = 0; |
643 | emac_tx_desc->buffer = (u_int8_t *) packet; | |
c74b2108 SK |
644 | emac_tx_desc->buff_off_len = (length & 0xffff); |
645 | emac_tx_desc->pkt_flag_len = ((length & 0xffff) | | |
53677ef1 WD |
646 | EMAC_CPPI_SOP_BIT | |
647 | EMAC_CPPI_OWNERSHIP_BIT | | |
648 | EMAC_CPPI_EOP_BIT); | |
2aa87202 IY |
649 | |
650 | flush_dcache_range((unsigned long)packet, | |
6202b8f2 | 651 | (unsigned long)packet + ALIGN(length, PKTALIGN)); |
2aa87202 | 652 | |
c74b2108 | 653 | /* Send the packet */ |
82b77217 | 654 | writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); |
c74b2108 SK |
655 | |
656 | /* Wait for packet to complete or link down */ | |
657 | while (1) { | |
062fe7d3 | 658 | if (!phy[index].get_link_speed(active_phy_addr[index])) { |
fcaac589 | 659 | davinci_eth_ch_teardown (EMAC_CH_TX); |
53677ef1 WD |
660 | return (ret_status); |
661 | } | |
d7e35437 | 662 | |
d7e35437 | 663 | if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { |
53677ef1 WD |
664 | ret_status = length; |
665 | break; | |
c74b2108 | 666 | } |
53677ef1 | 667 | tx_send_loop++; |
c74b2108 SK |
668 | } |
669 | ||
53677ef1 | 670 | return (ret_status); |
c74b2108 SK |
671 | } |
672 | ||
673 | /* | |
674 | * This function handles receipt of a packet from the network | |
675 | */ | |
8453587e | 676 | static int davinci_eth_rcv_packet (struct eth_device *dev) |
c74b2108 | 677 | { |
53677ef1 WD |
678 | volatile emac_desc *rx_curr_desc; |
679 | volatile emac_desc *curr_desc; | |
680 | volatile emac_desc *tail_desc; | |
681 | int status, ret = -1; | |
c74b2108 SK |
682 | |
683 | rx_curr_desc = emac_rx_active_head; | |
2300184f VS |
684 | if (!rx_curr_desc) |
685 | return 0; | |
c74b2108 | 686 | status = rx_curr_desc->pkt_flag_len; |
2300184f | 687 | if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) { |
53677ef1 WD |
688 | if (status & EMAC_CPPI_RX_ERROR_FRAME) { |
689 | /* Error in packet - discard it and requeue desc */ | |
690 | printf ("WARN: emac_rcv_pkt: Error in packet\n"); | |
c74b2108 | 691 | } else { |
2aa87202 | 692 | unsigned long tmp = (unsigned long)rx_curr_desc->buffer; |
a51897b6 | 693 | unsigned short len = |
694 | rx_curr_desc->buff_off_len & 0xffff; | |
2aa87202 | 695 | |
a51897b6 | 696 | invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN)); |
697 | net_process_received_packet(rx_curr_desc->buffer, len); | |
698 | ret = len; | |
53677ef1 | 699 | } |
c74b2108 | 700 | |
53677ef1 | 701 | /* Ack received packet descriptor */ |
82b77217 | 702 | writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); |
53677ef1 WD |
703 | curr_desc = rx_curr_desc; |
704 | emac_rx_active_head = | |
82b77217 | 705 | (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); |
c74b2108 | 706 | |
53677ef1 WD |
707 | if (status & EMAC_CPPI_EOQ_BIT) { |
708 | if (emac_rx_active_head) { | |
82b77217 | 709 | writel(BD_TO_HW((ulong)emac_rx_active_head), |
d7e35437 | 710 | &adap_emac->RX0HDP); |
c74b2108 SK |
711 | } else { |
712 | emac_rx_queue_active = 0; | |
53677ef1 | 713 | printf ("INFO:emac_rcv_packet: RX Queue not active\n"); |
c74b2108 SK |
714 | } |
715 | } | |
716 | ||
717 | /* Recycle RX descriptor */ | |
718 | rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; | |
719 | rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; | |
720 | rx_curr_desc->next = 0; | |
721 | ||
722 | if (emac_rx_active_head == 0) { | |
53677ef1 | 723 | printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); |
c74b2108 SK |
724 | emac_rx_active_head = curr_desc; |
725 | emac_rx_active_tail = curr_desc; | |
726 | if (emac_rx_queue_active != 0) { | |
82b77217 | 727 | writel(BD_TO_HW((ulong)emac_rx_active_head), |
d7e35437 | 728 | &adap_emac->RX0HDP); |
53677ef1 | 729 | printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); |
c74b2108 SK |
730 | emac_rx_queue_active = 1; |
731 | } | |
732 | } else { | |
733 | tail_desc = emac_rx_active_tail; | |
734 | emac_rx_active_tail = curr_desc; | |
82b77217 | 735 | tail_desc->next = BD_TO_HW((ulong) curr_desc); |
c74b2108 SK |
736 | status = tail_desc->pkt_flag_len; |
737 | if (status & EMAC_CPPI_EOQ_BIT) { | |
82b77217 | 738 | writel(BD_TO_HW((ulong)curr_desc), |
d7e35437 | 739 | &adap_emac->RX0HDP); |
c74b2108 SK |
740 | status &= ~EMAC_CPPI_EOQ_BIT; |
741 | tail_desc->pkt_flag_len = status; | |
742 | } | |
743 | } | |
53677ef1 | 744 | return (ret); |
c74b2108 | 745 | } |
53677ef1 | 746 | return (0); |
c74b2108 SK |
747 | } |
748 | ||
8cc13c13 BW |
749 | /* |
750 | * This function initializes the emac hardware. It does NOT initialize | |
751 | * EMAC modules power or pin multiplexors, that is done by board_init() | |
752 | * much earlier in bootup process. Returns 1 on success, 0 otherwise. | |
753 | */ | |
8453587e | 754 | int davinci_emac_initialize(void) |
8cc13c13 BW |
755 | { |
756 | u_int32_t phy_id; | |
757 | u_int16_t tmp; | |
758 | int i; | |
062fe7d3 | 759 | int ret; |
8453587e BW |
760 | struct eth_device *dev; |
761 | ||
762 | dev = malloc(sizeof *dev); | |
763 | ||
764 | if (dev == NULL) | |
765 | return -1; | |
766 | ||
767 | memset(dev, 0, sizeof *dev); | |
192bc694 | 768 | strcpy(dev->name, "DaVinci-EMAC"); |
8453587e BW |
769 | |
770 | dev->iobase = 0; | |
771 | dev->init = davinci_eth_open; | |
772 | dev->halt = davinci_eth_close; | |
773 | dev->send = davinci_eth_send_packet; | |
774 | dev->recv = davinci_eth_rcv_packet; | |
7b37a27e | 775 | dev->write_hwaddr = davinci_eth_set_mac_addr; |
8453587e BW |
776 | |
777 | eth_register(dev); | |
8cc13c13 BW |
778 | |
779 | davinci_eth_mdio_enable(); | |
780 | ||
19fdf9a1 HS |
781 | /* let the EMAC detect the PHYs */ |
782 | udelay(5000); | |
783 | ||
8cc13c13 | 784 | for (i = 0; i < 256; i++) { |
d7e35437 | 785 | if (readl(&adap_mdio->ALIVE)) |
8cc13c13 | 786 | break; |
062fe7d3 | 787 | udelay(1000); |
8cc13c13 BW |
788 | } |
789 | ||
790 | if (i >= 256) { | |
791 | printf("No ETH PHY detected!!!\n"); | |
792 | return(0); | |
793 | } | |
794 | ||
062fe7d3 MH |
795 | /* Find if PHY(s) is/are connected */ |
796 | ret = davinci_eth_phy_detect(); | |
797 | if (!ret) | |
8cc13c13 | 798 | return(0); |
062fe7d3 | 799 | else |
dc02bada | 800 | debug_emac(" %d ETH PHY detected\n", ret); |
8cc13c13 BW |
801 | |
802 | /* Get PHY ID and initialize phy_ops for a detected PHY */ | |
062fe7d3 MH |
803 | for (i = 0; i < num_phy; i++) { |
804 | if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, | |
805 | &tmp)) { | |
806 | active_phy_addr[i] = 0xff; | |
807 | continue; | |
808 | } | |
c74b2108 | 809 | |
062fe7d3 | 810 | phy_id = (tmp << 16) & 0xffff0000; |
8cc13c13 | 811 | |
062fe7d3 MH |
812 | if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, |
813 | &tmp)) { | |
814 | active_phy_addr[i] = 0xff; | |
815 | continue; | |
816 | } | |
8cc13c13 | 817 | |
062fe7d3 | 818 | phy_id |= tmp & 0x0000ffff; |
8cc13c13 | 819 | |
062fe7d3 | 820 | switch (phy_id) { |
918588cf | 821 | #ifdef PHY_KSZ8873 |
062fe7d3 MH |
822 | case PHY_KSZ8873: |
823 | sprintf(phy[i].name, "KSZ8873 @ 0x%02x", | |
824 | active_phy_addr[i]); | |
825 | phy[i].init = ksz8873_init_phy; | |
826 | phy[i].is_phy_connected = ksz8873_is_phy_connected; | |
827 | phy[i].get_link_speed = ksz8873_get_link_speed; | |
828 | phy[i].auto_negotiate = ksz8873_auto_negotiate; | |
829 | break; | |
918588cf IY |
830 | #endif |
831 | #ifdef PHY_LXT972 | |
8cc13c13 | 832 | case PHY_LXT972: |
062fe7d3 MH |
833 | sprintf(phy[i].name, "LXT972 @ 0x%02x", |
834 | active_phy_addr[i]); | |
835 | phy[i].init = lxt972_init_phy; | |
836 | phy[i].is_phy_connected = lxt972_is_phy_connected; | |
837 | phy[i].get_link_speed = lxt972_get_link_speed; | |
838 | phy[i].auto_negotiate = lxt972_auto_negotiate; | |
8cc13c13 | 839 | break; |
918588cf IY |
840 | #endif |
841 | #ifdef PHY_DP83848 | |
8cc13c13 | 842 | case PHY_DP83848: |
062fe7d3 MH |
843 | sprintf(phy[i].name, "DP83848 @ 0x%02x", |
844 | active_phy_addr[i]); | |
845 | phy[i].init = dp83848_init_phy; | |
846 | phy[i].is_phy_connected = dp83848_is_phy_connected; | |
847 | phy[i].get_link_speed = dp83848_get_link_speed; | |
848 | phy[i].auto_negotiate = dp83848_auto_negotiate; | |
8cc13c13 | 849 | break; |
918588cf IY |
850 | #endif |
851 | #ifdef PHY_ET1011C | |
840f8923 | 852 | case PHY_ET1011C: |
062fe7d3 MH |
853 | sprintf(phy[i].name, "ET1011C @ 0x%02x", |
854 | active_phy_addr[i]); | |
855 | phy[i].init = gen_init_phy; | |
856 | phy[i].is_phy_connected = gen_is_phy_connected; | |
857 | phy[i].get_link_speed = et1011c_get_link_speed; | |
858 | phy[i].auto_negotiate = gen_auto_negotiate; | |
840f8923 | 859 | break; |
918588cf | 860 | #endif |
8cc13c13 | 861 | default: |
062fe7d3 MH |
862 | sprintf(phy[i].name, "GENERIC @ 0x%02x", |
863 | active_phy_addr[i]); | |
864 | phy[i].init = gen_init_phy; | |
865 | phy[i].is_phy_connected = gen_is_phy_connected; | |
866 | phy[i].get_link_speed = gen_get_link_speed; | |
867 | phy[i].auto_negotiate = gen_auto_negotiate; | |
868 | } | |
8cc13c13 | 869 | |
e0297a55 | 870 | debug("Ethernet PHY: %s\n", phy[i].name); |
8cc13c13 | 871 | |
5a49f174 JH |
872 | int retval; |
873 | struct mii_dev *mdiodev = mdio_alloc(); | |
874 | if (!mdiodev) | |
875 | return -ENOMEM; | |
876 | strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN); | |
877 | mdiodev->read = davinci_mii_phy_read; | |
878 | mdiodev->write = davinci_mii_phy_write; | |
879 | ||
880 | retval = mdio_register(mdiodev); | |
881 | if (retval < 0) | |
882 | return retval; | |
de820365 TR |
883 | #ifdef DAVINCI_EMAC_GIG_ENABLE |
884 | #define PHY_CONF_REG 22 | |
885 | /* Enable PHY to clock out TX_CLK */ | |
886 | davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp); | |
887 | tmp |= PHY_CONF_TXCLKEN; | |
888 | davinci_eth_phy_write(active_phy_addr[i], PHY_CONF_REG, tmp); | |
889 | davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp); | |
890 | #endif | |
062fe7d3 | 891 | } |
b78375a8 | 892 | |
de820365 | 893 | #if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ |
de575502 | 894 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \ |
de820365 | 895 | !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)) |
b78375a8 RS |
896 | for (i = 0; i < num_phy; i++) { |
897 | if (phy[i].is_phy_connected(i)) | |
898 | phy[i].auto_negotiate(i); | |
899 | } | |
900 | #endif | |
8cc13c13 BW |
901 | return(1); |
902 | } |