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c74b2108 SK |
1 | /* |
2 | * Ethernet driver for TI TMS320DM644x (DaVinci) chips. | |
3 | * | |
4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
5 | * | |
6 | * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright | |
7 | * follows: | |
8 | * | |
9 | * ---------------------------------------------------------------------------- | |
10 | * | |
11 | * dm644x_emac.c | |
12 | * | |
13 | * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM | |
14 | * | |
15 | * Copyright (C) 2005 Texas Instruments. | |
16 | * | |
17 | * ---------------------------------------------------------------------------- | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify | |
20 | * it under the terms of the GNU General Public License as published by | |
21 | * the Free Software Foundation; either version 2 of the License, or | |
22 | * (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
32 | * ---------------------------------------------------------------------------- | |
33 | ||
34 | * Modifications: | |
35 | * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. | |
36 | * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors | |
37 | * | |
38 | */ | |
39 | #include <common.h> | |
40 | #include <command.h> | |
41 | #include <net.h> | |
42 | #include <miiphy.h> | |
8453587e | 43 | #include <malloc.h> |
c74b2108 | 44 | #include <asm/arch/emac_defs.h> |
d7e35437 | 45 | #include <asm/io.h> |
c74b2108 | 46 | |
c74b2108 SK |
47 | unsigned int emac_dbg = 0; |
48 | #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) | |
49 | ||
d7e35437 NT |
50 | #ifdef DAVINCI_EMAC_GIG_ENABLE |
51 | #define emac_gigabit_enable() davinci_eth_gigabit_enable() | |
52 | #else | |
53 | #define emac_gigabit_enable() /* no gigabit to enable */ | |
54 | #endif | |
55 | ||
fcaac589 | 56 | static void davinci_eth_mdio_enable(void); |
c74b2108 SK |
57 | |
58 | static int gen_init_phy(int phy_addr); | |
59 | static int gen_is_phy_connected(int phy_addr); | |
60 | static int gen_get_link_speed(int phy_addr); | |
61 | static int gen_auto_negotiate(int phy_addr); | |
62 | ||
c74b2108 SK |
63 | void eth_mdio_enable(void) |
64 | { | |
fcaac589 | 65 | davinci_eth_mdio_enable(); |
c74b2108 | 66 | } |
c74b2108 | 67 | |
fcaac589 | 68 | static u_int8_t davinci_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
c74b2108 SK |
69 | |
70 | /* | |
71 | * This function must be called before emac_open() if you want to override | |
72 | * the default mac address. | |
73 | */ | |
fcaac589 | 74 | void davinci_eth_set_mac_addr(const u_int8_t *addr) |
c74b2108 SK |
75 | { |
76 | int i; | |
77 | ||
fcaac589 SP |
78 | for (i = 0; i < sizeof (davinci_eth_mac_addr); i++) { |
79 | davinci_eth_mac_addr[i] = addr[i]; | |
c74b2108 SK |
80 | } |
81 | } | |
82 | ||
83 | /* EMAC Addresses */ | |
84 | static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; | |
85 | static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; | |
86 | static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; | |
87 | ||
88 | /* EMAC descriptors */ | |
89 | static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); | |
90 | static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); | |
91 | static volatile emac_desc *emac_rx_active_head = 0; | |
92 | static volatile emac_desc *emac_rx_active_tail = 0; | |
93 | static int emac_rx_queue_active = 0; | |
94 | ||
95 | /* Receive packet buffers */ | |
96 | static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; | |
97 | ||
98 | /* PHY address for a discovered PHY (0xff - not found) */ | |
99 | static volatile u_int8_t active_phy_addr = 0xff; | |
100 | ||
101 | phy_t phy; | |
102 | ||
fcaac589 | 103 | static void davinci_eth_mdio_enable(void) |
c74b2108 SK |
104 | { |
105 | u_int32_t clkdiv; | |
106 | ||
107 | clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; | |
108 | ||
d7e35437 NT |
109 | writel((clkdiv & 0xff) | |
110 | MDIO_CONTROL_ENABLE | | |
111 | MDIO_CONTROL_FAULT | | |
112 | MDIO_CONTROL_FAULT_ENABLE, | |
113 | &adap_mdio->CONTROL); | |
c74b2108 | 114 | |
d7e35437 NT |
115 | while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) |
116 | ; | |
c74b2108 SK |
117 | } |
118 | ||
119 | /* | |
120 | * Tries to find an active connected PHY. Returns 1 if address if found. | |
121 | * If no active PHY (or more than one PHY) found returns 0. | |
122 | * Sets active_phy_addr variable. | |
123 | */ | |
fcaac589 | 124 | static int davinci_eth_phy_detect(void) |
c74b2108 SK |
125 | { |
126 | u_int32_t phy_act_state; | |
127 | int i; | |
128 | ||
129 | active_phy_addr = 0xff; | |
130 | ||
d7e35437 NT |
131 | phy_act_state = readl(&adap_mdio->ALIVE) & EMAC_MDIO_PHY_MASK; |
132 | if (phy_act_state == 0) | |
c74b2108 SK |
133 | return(0); /* No active PHYs */ |
134 | ||
fcaac589 | 135 | debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); |
c74b2108 SK |
136 | |
137 | for (i = 0; i < 32; i++) { | |
138 | if (phy_act_state & (1 << i)) { | |
139 | if (phy_act_state & ~(1 << i)) | |
140 | return(0); /* More than one PHY */ | |
141 | else { | |
142 | active_phy_addr = i; | |
143 | return(1); | |
144 | } | |
145 | } | |
146 | } | |
147 | ||
148 | return(0); /* Just to make GCC happy */ | |
149 | } | |
150 | ||
151 | ||
152 | /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ | |
fcaac589 | 153 | int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) |
c74b2108 SK |
154 | { |
155 | int tmp; | |
156 | ||
d7e35437 NT |
157 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
158 | ; | |
c74b2108 | 159 | |
d7e35437 NT |
160 | writel(MDIO_USERACCESS0_GO | |
161 | MDIO_USERACCESS0_WRITE_READ | | |
162 | ((reg_num & 0x1f) << 21) | | |
163 | ((phy_addr & 0x1f) << 16), | |
164 | &adap_mdio->USERACCESS0); | |
c74b2108 SK |
165 | |
166 | /* Wait for command to complete */ | |
d7e35437 NT |
167 | while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) |
168 | ; | |
c74b2108 SK |
169 | |
170 | if (tmp & MDIO_USERACCESS0_ACK) { | |
171 | *data = tmp & 0xffff; | |
172 | return(1); | |
173 | } | |
174 | ||
175 | *data = -1; | |
176 | return(0); | |
177 | } | |
178 | ||
179 | /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ | |
fcaac589 | 180 | int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) |
c74b2108 SK |
181 | { |
182 | ||
d7e35437 NT |
183 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
184 | ; | |
c74b2108 | 185 | |
d7e35437 NT |
186 | writel(MDIO_USERACCESS0_GO | |
187 | MDIO_USERACCESS0_WRITE_WRITE | | |
188 | ((reg_num & 0x1f) << 21) | | |
189 | ((phy_addr & 0x1f) << 16) | | |
190 | (data & 0xffff), | |
191 | &adap_mdio->USERACCESS0); | |
c74b2108 SK |
192 | |
193 | /* Wait for command to complete */ | |
d7e35437 NT |
194 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
195 | ; | |
c74b2108 SK |
196 | |
197 | return(1); | |
198 | } | |
199 | ||
200 | /* PHY functions for a generic PHY */ | |
201 | static int gen_init_phy(int phy_addr) | |
202 | { | |
203 | int ret = 1; | |
204 | ||
205 | if (gen_get_link_speed(phy_addr)) { | |
206 | /* Try another time */ | |
207 | ret = gen_get_link_speed(phy_addr); | |
208 | } | |
209 | ||
210 | return(ret); | |
211 | } | |
212 | ||
213 | static int gen_is_phy_connected(int phy_addr) | |
214 | { | |
215 | u_int16_t dummy; | |
216 | ||
fcaac589 | 217 | return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); |
c74b2108 SK |
218 | } |
219 | ||
220 | static int gen_get_link_speed(int phy_addr) | |
221 | { | |
222 | u_int16_t tmp; | |
223 | ||
fcaac589 | 224 | if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04)) |
c74b2108 SK |
225 | return(1); |
226 | ||
227 | return(0); | |
228 | } | |
229 | ||
230 | static int gen_auto_negotiate(int phy_addr) | |
231 | { | |
232 | u_int16_t tmp; | |
233 | ||
fcaac589 | 234 | if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) |
c74b2108 SK |
235 | return(0); |
236 | ||
237 | /* Restart Auto_negotiation */ | |
238 | tmp |= PHY_BMCR_AUTON; | |
fcaac589 | 239 | davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp); |
c74b2108 SK |
240 | |
241 | /*check AutoNegotiate complete */ | |
242 | udelay (10000); | |
fcaac589 | 243 | if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) |
c74b2108 SK |
244 | return(0); |
245 | ||
246 | if (!(tmp & PHY_BMSR_AUTN_COMP)) | |
247 | return(0); | |
248 | ||
249 | return(gen_get_link_speed(phy_addr)); | |
250 | } | |
251 | /* End of generic PHY functions */ | |
252 | ||
253 | ||
afaac86f | 254 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
5700bb63 | 255 | static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) |
c74b2108 | 256 | { |
fcaac589 | 257 | return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); |
c74b2108 SK |
258 | } |
259 | ||
5700bb63 | 260 | static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) |
c74b2108 | 261 | { |
fcaac589 | 262 | return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); |
c74b2108 | 263 | } |
c74b2108 SK |
264 | #endif |
265 | ||
d7e35437 NT |
266 | static void __attribute__((unused)) davinci_eth_gigabit_enable(void) |
267 | { | |
268 | u_int16_t data; | |
269 | ||
270 | if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) { | |
271 | if (data & (1 << 6)) { /* speed selection MSB */ | |
272 | /* | |
273 | * Check if link detected is giga-bit | |
274 | * If Gigabit mode detected, enable gigbit in MAC | |
275 | */ | |
276 | writel(EMAC_MACCONTROL_GIGFORCE | | |
277 | EMAC_MACCONTROL_GIGABIT_ENABLE, | |
278 | &adap_emac->MACCONTROL); | |
279 | } | |
280 | } | |
281 | } | |
c74b2108 SK |
282 | |
283 | /* Eth device open */ | |
8453587e | 284 | static int davinci_eth_open(struct eth_device *dev, bd_t *bis) |
c74b2108 SK |
285 | { |
286 | dv_reg_p addr; | |
287 | u_int32_t clkdiv, cnt; | |
288 | volatile emac_desc *rx_desc; | |
d7e35437 NT |
289 | unsigned long mac_hi; |
290 | unsigned long mac_lo; | |
c74b2108 SK |
291 | |
292 | debug_emac("+ emac_open\n"); | |
293 | ||
294 | /* Reset EMAC module and disable interrupts in wrapper */ | |
d7e35437 NT |
295 | writel(1, &adap_emac->SOFTRESET); |
296 | while (readl(&adap_emac->SOFTRESET) != 0) | |
297 | ; | |
298 | #if defined(DAVINCI_EMAC_VERSION2) | |
299 | writel(1, &adap_ewrap->softrst); | |
300 | while (readl(&adap_ewrap->softrst) != 0) | |
301 | ; | |
302 | #else | |
303 | writel(0, &adap_ewrap->EWCTL); | |
c74b2108 | 304 | for (cnt = 0; cnt < 5; cnt++) { |
d7e35437 | 305 | clkdiv = readl(&adap_ewrap->EWCTL); |
c74b2108 | 306 | } |
d7e35437 | 307 | #endif |
c74b2108 SK |
308 | |
309 | rx_desc = emac_rx_desc; | |
310 | ||
d7e35437 NT |
311 | writel(1, &adap_emac->TXCONTROL); |
312 | writel(1, &adap_emac->RXCONTROL); | |
c74b2108 SK |
313 | |
314 | /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ | |
315 | /* Using channel 0 only - other channels are disabled */ | |
d7e35437 NT |
316 | writel(0, &adap_emac->MACINDEX); |
317 | mac_hi = (davinci_eth_mac_addr[3] << 24) | | |
318 | (davinci_eth_mac_addr[2] << 16) | | |
319 | (davinci_eth_mac_addr[1] << 8) | | |
320 | (davinci_eth_mac_addr[0]); | |
321 | mac_lo = (davinci_eth_mac_addr[5] << 8) | | |
322 | (davinci_eth_mac_addr[4]); | |
323 | ||
324 | writel(mac_hi, &adap_emac->MACADDRHI); | |
325 | #if defined(DAVINCI_EMAC_VERSION2) | |
326 | writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, | |
327 | &adap_emac->MACADDRLO); | |
328 | #else | |
329 | writel(mac_lo, &adap_emac->MACADDRLO); | |
330 | #endif | |
331 | ||
332 | writel(0, &adap_emac->MACHASH1); | |
333 | writel(0, &adap_emac->MACHASH2); | |
c74b2108 SK |
334 | |
335 | /* Set source MAC address - REQUIRED */ | |
d7e35437 NT |
336 | writel(mac_hi, &adap_emac->MACSRCADDRHI); |
337 | writel(mac_lo, &adap_emac->MACSRCADDRLO); | |
c74b2108 SK |
338 | |
339 | /* Set DMA 8 TX / 8 RX Head pointers to 0 */ | |
340 | addr = &adap_emac->TX0HDP; | |
341 | for(cnt = 0; cnt < 16; cnt++) | |
d7e35437 | 342 | writel(0, addr++); |
c74b2108 SK |
343 | |
344 | addr = &adap_emac->RX0HDP; | |
345 | for(cnt = 0; cnt < 16; cnt++) | |
d7e35437 | 346 | writel(0, addr++); |
c74b2108 SK |
347 | |
348 | /* Clear Statistics (do this before setting MacControl register) */ | |
349 | addr = &adap_emac->RXGOODFRAMES; | |
350 | for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) | |
d7e35437 | 351 | writel(0, addr++); |
c74b2108 SK |
352 | |
353 | /* No multicast addressing */ | |
d7e35437 NT |
354 | writel(0, &adap_emac->MACHASH1); |
355 | writel(0, &adap_emac->MACHASH2); | |
c74b2108 SK |
356 | |
357 | /* Create RX queue and set receive process in place */ | |
358 | emac_rx_active_head = emac_rx_desc; | |
359 | for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { | |
360 | rx_desc->next = (u_int32_t)(rx_desc + 1); | |
361 | rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; | |
362 | rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; | |
363 | rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; | |
364 | rx_desc++; | |
365 | } | |
366 | ||
d7e35437 | 367 | /* Finalize the rx desc list */ |
c74b2108 SK |
368 | rx_desc--; |
369 | rx_desc->next = 0; | |
370 | emac_rx_active_tail = rx_desc; | |
371 | emac_rx_queue_active = 1; | |
372 | ||
373 | /* Enable TX/RX */ | |
d7e35437 NT |
374 | writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); |
375 | writel(0, &adap_emac->RXBUFFEROFFSET); | |
c74b2108 | 376 | |
d7e35437 NT |
377 | /* |
378 | * No fancy configs - Use this for promiscous debug | |
379 | * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE | |
380 | */ | |
381 | writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); | |
c74b2108 SK |
382 | |
383 | /* Enable ch 0 only */ | |
d7e35437 | 384 | writel(1, &adap_emac->RXUNICASTSET); |
c74b2108 SK |
385 | |
386 | /* Enable MII interface and Full duplex mode */ | |
d7e35437 NT |
387 | #ifdef CONFIG_SOC_DA8XX |
388 | writel((EMAC_MACCONTROL_MIIEN_ENABLE | | |
389 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE | | |
390 | EMAC_MACCONTROL_RMIISPEED_100), | |
391 | &adap_emac->MACCONTROL); | |
392 | #else | |
393 | writel((EMAC_MACCONTROL_MIIEN_ENABLE | | |
394 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE), | |
395 | &adap_emac->MACCONTROL); | |
396 | #endif | |
c74b2108 SK |
397 | |
398 | /* Init MDIO & get link state */ | |
399 | clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; | |
d7e35437 NT |
400 | writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, |
401 | &adap_mdio->CONTROL); | |
402 | ||
403 | /* We need to wait for MDIO to start */ | |
404 | udelay(1000); | |
c74b2108 SK |
405 | |
406 | if (!phy.get_link_speed(active_phy_addr)) | |
407 | return(0); | |
408 | ||
d7e35437 NT |
409 | emac_gigabit_enable(); |
410 | ||
c74b2108 | 411 | /* Start receive process */ |
d7e35437 | 412 | writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); |
c74b2108 SK |
413 | |
414 | debug_emac("- emac_open\n"); | |
415 | ||
416 | return(1); | |
417 | } | |
418 | ||
419 | /* EMAC Channel Teardown */ | |
fcaac589 | 420 | static void davinci_eth_ch_teardown(int ch) |
c74b2108 SK |
421 | { |
422 | dv_reg dly = 0xff; | |
423 | dv_reg cnt; | |
424 | ||
425 | debug_emac("+ emac_ch_teardown\n"); | |
426 | ||
427 | if (ch == EMAC_CH_TX) { | |
428 | /* Init TX channel teardown */ | |
d7e35437 NT |
429 | writel(1, &adap_emac->TXTEARDOWN); |
430 | do { | |
431 | /* | |
432 | * Wait here for Tx teardown completion interrupt to | |
433 | * occur. Note: A task delay can be called here to pend | |
434 | * rather than occupying CPU cycles - anyway it has | |
435 | * been found that teardown takes very few cpu cycles | |
436 | * and does not affect functionality | |
437 | */ | |
438 | dly--; | |
439 | udelay(1); | |
440 | if (dly == 0) | |
53677ef1 | 441 | break; |
d7e35437 NT |
442 | cnt = readl(&adap_emac->TX0CP); |
443 | } while (cnt != 0xfffffffc); | |
444 | writel(cnt, &adap_emac->TX0CP); | |
445 | writel(0, &adap_emac->TX0HDP); | |
c74b2108 SK |
446 | } else { |
447 | /* Init RX channel teardown */ | |
d7e35437 NT |
448 | writel(1, &adap_emac->RXTEARDOWN); |
449 | do { | |
450 | /* | |
451 | * Wait here for Rx teardown completion interrupt to | |
452 | * occur. Note: A task delay can be called here to pend | |
453 | * rather than occupying CPU cycles - anyway it has | |
454 | * been found that teardown takes very few cpu cycles | |
455 | * and does not affect functionality | |
456 | */ | |
457 | dly--; | |
458 | udelay(1); | |
459 | if (dly == 0) | |
53677ef1 | 460 | break; |
d7e35437 NT |
461 | cnt = readl(&adap_emac->RX0CP); |
462 | } while (cnt != 0xfffffffc); | |
463 | writel(cnt, &adap_emac->RX0CP); | |
464 | writel(0, &adap_emac->RX0HDP); | |
c74b2108 SK |
465 | } |
466 | ||
467 | debug_emac("- emac_ch_teardown\n"); | |
468 | } | |
469 | ||
470 | /* Eth device close */ | |
8453587e | 471 | static void davinci_eth_close(struct eth_device *dev) |
c74b2108 SK |
472 | { |
473 | debug_emac("+ emac_close\n"); | |
474 | ||
fcaac589 SP |
475 | davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ |
476 | davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ | |
c74b2108 SK |
477 | |
478 | /* Reset EMAC module and disable interrupts in wrapper */ | |
d7e35437 NT |
479 | writel(1, &adap_emac->SOFTRESET); |
480 | #if defined(DAVINCI_EMAC_VERSION2) | |
481 | writel(1, &adap_ewrap->softrst); | |
482 | #else | |
483 | writel(0, &adap_ewrap->EWCTL); | |
484 | #endif | |
c74b2108 SK |
485 | |
486 | debug_emac("- emac_close\n"); | |
c74b2108 SK |
487 | } |
488 | ||
489 | static int tx_send_loop = 0; | |
490 | ||
491 | /* | |
492 | * This function sends a single packet on the network and returns | |
493 | * positive number (number of bytes transmitted) or negative for error | |
494 | */ | |
8453587e BW |
495 | static int davinci_eth_send_packet (struct eth_device *dev, |
496 | volatile void *packet, int length) | |
c74b2108 SK |
497 | { |
498 | int ret_status = -1; | |
53677ef1 | 499 | |
c74b2108 SK |
500 | tx_send_loop = 0; |
501 | ||
502 | /* Return error if no link */ | |
53677ef1 WD |
503 | if (!phy.get_link_speed (active_phy_addr)) { |
504 | printf ("WARN: emac_send_packet: No link\n"); | |
c74b2108 SK |
505 | return (ret_status); |
506 | } | |
507 | ||
d7e35437 NT |
508 | emac_gigabit_enable(); |
509 | ||
c74b2108 | 510 | /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ |
53677ef1 | 511 | if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { |
c74b2108 SK |
512 | length = EMAC_MIN_ETHERNET_PKT_SIZE; |
513 | } | |
514 | ||
515 | /* Populate the TX descriptor */ | |
53677ef1 WD |
516 | emac_tx_desc->next = 0; |
517 | emac_tx_desc->buffer = (u_int8_t *) packet; | |
c74b2108 SK |
518 | emac_tx_desc->buff_off_len = (length & 0xffff); |
519 | emac_tx_desc->pkt_flag_len = ((length & 0xffff) | | |
53677ef1 WD |
520 | EMAC_CPPI_SOP_BIT | |
521 | EMAC_CPPI_OWNERSHIP_BIT | | |
522 | EMAC_CPPI_EOP_BIT); | |
c74b2108 | 523 | /* Send the packet */ |
d7e35437 | 524 | writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); |
c74b2108 SK |
525 | |
526 | /* Wait for packet to complete or link down */ | |
527 | while (1) { | |
53677ef1 | 528 | if (!phy.get_link_speed (active_phy_addr)) { |
fcaac589 | 529 | davinci_eth_ch_teardown (EMAC_CH_TX); |
53677ef1 WD |
530 | return (ret_status); |
531 | } | |
d7e35437 NT |
532 | |
533 | emac_gigabit_enable(); | |
534 | ||
535 | if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { | |
53677ef1 WD |
536 | ret_status = length; |
537 | break; | |
c74b2108 | 538 | } |
53677ef1 | 539 | tx_send_loop++; |
c74b2108 SK |
540 | } |
541 | ||
53677ef1 | 542 | return (ret_status); |
c74b2108 SK |
543 | } |
544 | ||
545 | /* | |
546 | * This function handles receipt of a packet from the network | |
547 | */ | |
8453587e | 548 | static int davinci_eth_rcv_packet (struct eth_device *dev) |
c74b2108 | 549 | { |
53677ef1 WD |
550 | volatile emac_desc *rx_curr_desc; |
551 | volatile emac_desc *curr_desc; | |
552 | volatile emac_desc *tail_desc; | |
553 | int status, ret = -1; | |
c74b2108 SK |
554 | |
555 | rx_curr_desc = emac_rx_active_head; | |
556 | status = rx_curr_desc->pkt_flag_len; | |
557 | if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { | |
53677ef1 WD |
558 | if (status & EMAC_CPPI_RX_ERROR_FRAME) { |
559 | /* Error in packet - discard it and requeue desc */ | |
560 | printf ("WARN: emac_rcv_pkt: Error in packet\n"); | |
c74b2108 | 561 | } else { |
53677ef1 WD |
562 | NetReceive (rx_curr_desc->buffer, |
563 | (rx_curr_desc->buff_off_len & 0xffff)); | |
c74b2108 | 564 | ret = rx_curr_desc->buff_off_len & 0xffff; |
53677ef1 | 565 | } |
c74b2108 | 566 | |
53677ef1 | 567 | /* Ack received packet descriptor */ |
d7e35437 | 568 | writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); |
53677ef1 WD |
569 | curr_desc = rx_curr_desc; |
570 | emac_rx_active_head = | |
571 | (volatile emac_desc *) rx_curr_desc->next; | |
c74b2108 | 572 | |
53677ef1 WD |
573 | if (status & EMAC_CPPI_EOQ_BIT) { |
574 | if (emac_rx_active_head) { | |
d7e35437 NT |
575 | writel((unsigned long)emac_rx_active_head, |
576 | &adap_emac->RX0HDP); | |
c74b2108 SK |
577 | } else { |
578 | emac_rx_queue_active = 0; | |
53677ef1 | 579 | printf ("INFO:emac_rcv_packet: RX Queue not active\n"); |
c74b2108 SK |
580 | } |
581 | } | |
582 | ||
583 | /* Recycle RX descriptor */ | |
584 | rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; | |
585 | rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; | |
586 | rx_curr_desc->next = 0; | |
587 | ||
588 | if (emac_rx_active_head == 0) { | |
53677ef1 | 589 | printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); |
c74b2108 SK |
590 | emac_rx_active_head = curr_desc; |
591 | emac_rx_active_tail = curr_desc; | |
592 | if (emac_rx_queue_active != 0) { | |
d7e35437 NT |
593 | writel((unsigned long)emac_rx_active_head, |
594 | &adap_emac->RX0HDP); | |
53677ef1 | 595 | printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); |
c74b2108 SK |
596 | emac_rx_queue_active = 1; |
597 | } | |
598 | } else { | |
599 | tail_desc = emac_rx_active_tail; | |
600 | emac_rx_active_tail = curr_desc; | |
53677ef1 | 601 | tail_desc->next = (unsigned int) curr_desc; |
c74b2108 SK |
602 | status = tail_desc->pkt_flag_len; |
603 | if (status & EMAC_CPPI_EOQ_BIT) { | |
d7e35437 NT |
604 | writel((unsigned long)curr_desc, |
605 | &adap_emac->RX0HDP); | |
c74b2108 SK |
606 | status &= ~EMAC_CPPI_EOQ_BIT; |
607 | tail_desc->pkt_flag_len = status; | |
608 | } | |
609 | } | |
53677ef1 | 610 | return (ret); |
c74b2108 | 611 | } |
53677ef1 | 612 | return (0); |
c74b2108 SK |
613 | } |
614 | ||
8cc13c13 BW |
615 | /* |
616 | * This function initializes the emac hardware. It does NOT initialize | |
617 | * EMAC modules power or pin multiplexors, that is done by board_init() | |
618 | * much earlier in bootup process. Returns 1 on success, 0 otherwise. | |
619 | */ | |
8453587e | 620 | int davinci_emac_initialize(void) |
8cc13c13 BW |
621 | { |
622 | u_int32_t phy_id; | |
623 | u_int16_t tmp; | |
624 | int i; | |
8453587e BW |
625 | struct eth_device *dev; |
626 | ||
627 | dev = malloc(sizeof *dev); | |
628 | ||
629 | if (dev == NULL) | |
630 | return -1; | |
631 | ||
632 | memset(dev, 0, sizeof *dev); | |
633 | ||
634 | dev->iobase = 0; | |
635 | dev->init = davinci_eth_open; | |
636 | dev->halt = davinci_eth_close; | |
637 | dev->send = davinci_eth_send_packet; | |
638 | dev->recv = davinci_eth_rcv_packet; | |
639 | ||
640 | eth_register(dev); | |
8cc13c13 BW |
641 | |
642 | davinci_eth_mdio_enable(); | |
643 | ||
644 | for (i = 0; i < 256; i++) { | |
d7e35437 | 645 | if (readl(&adap_mdio->ALIVE)) |
8cc13c13 BW |
646 | break; |
647 | udelay(10); | |
648 | } | |
649 | ||
650 | if (i >= 256) { | |
651 | printf("No ETH PHY detected!!!\n"); | |
652 | return(0); | |
653 | } | |
654 | ||
655 | /* Find if a PHY is connected and get it's address */ | |
656 | if (!davinci_eth_phy_detect()) | |
657 | return(0); | |
658 | ||
659 | /* Get PHY ID and initialize phy_ops for a detected PHY */ | |
660 | if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { | |
661 | active_phy_addr = 0xff; | |
662 | return(0); | |
663 | } | |
c74b2108 | 664 | |
8cc13c13 BW |
665 | phy_id = (tmp << 16) & 0xffff0000; |
666 | ||
667 | if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { | |
668 | active_phy_addr = 0xff; | |
669 | return(0); | |
670 | } | |
671 | ||
672 | phy_id |= tmp & 0x0000ffff; | |
673 | ||
674 | switch (phy_id) { | |
675 | case PHY_LXT972: | |
676 | sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); | |
677 | phy.init = lxt972_init_phy; | |
678 | phy.is_phy_connected = lxt972_is_phy_connected; | |
679 | phy.get_link_speed = lxt972_get_link_speed; | |
680 | phy.auto_negotiate = lxt972_auto_negotiate; | |
681 | break; | |
682 | case PHY_DP83848: | |
683 | sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); | |
684 | phy.init = dp83848_init_phy; | |
685 | phy.is_phy_connected = dp83848_is_phy_connected; | |
686 | phy.get_link_speed = dp83848_get_link_speed; | |
687 | phy.auto_negotiate = dp83848_auto_negotiate; | |
688 | break; | |
689 | default: | |
690 | sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); | |
691 | phy.init = gen_init_phy; | |
692 | phy.is_phy_connected = gen_is_phy_connected; | |
693 | phy.get_link_speed = gen_get_link_speed; | |
694 | phy.auto_negotiate = gen_auto_negotiate; | |
695 | } | |
696 | ||
697 | printf("Ethernet PHY: %s\n", phy.name); | |
698 | ||
8453587e | 699 | miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write); |
8cc13c13 BW |
700 | return(1); |
701 | } |