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c74b2108 SK |
1 | /* |
2 | * Ethernet driver for TI TMS320DM644x (DaVinci) chips. | |
3 | * | |
4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
5 | * | |
6 | * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright | |
7 | * follows: | |
8 | * | |
9 | * ---------------------------------------------------------------------------- | |
10 | * | |
11 | * dm644x_emac.c | |
12 | * | |
13 | * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM | |
14 | * | |
15 | * Copyright (C) 2005 Texas Instruments. | |
16 | * | |
17 | * ---------------------------------------------------------------------------- | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify | |
20 | * it under the terms of the GNU General Public License as published by | |
21 | * the Free Software Foundation; either version 2 of the License, or | |
22 | * (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
32 | * ---------------------------------------------------------------------------- | |
33 | ||
34 | * Modifications: | |
35 | * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. | |
36 | * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors | |
37 | * | |
38 | */ | |
39 | #include <common.h> | |
40 | #include <command.h> | |
41 | #include <net.h> | |
42 | #include <miiphy.h> | |
8453587e | 43 | #include <malloc.h> |
c74b2108 | 44 | #include <asm/arch/emac_defs.h> |
d7e35437 | 45 | #include <asm/io.h> |
c74b2108 | 46 | |
c74b2108 SK |
47 | unsigned int emac_dbg = 0; |
48 | #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) | |
49 | ||
d7e35437 | 50 | #ifdef DAVINCI_EMAC_GIG_ENABLE |
fb1d6332 | 51 | #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) |
d7e35437 | 52 | #else |
fb1d6332 | 53 | #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ |
d7e35437 NT |
54 | #endif |
55 | ||
882ecfa3 HS |
56 | #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) |
57 | #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ | |
58 | EMAC_MDIO_CLOCK_FREQ) - 1) | |
59 | #endif | |
60 | ||
fcaac589 | 61 | static void davinci_eth_mdio_enable(void); |
c74b2108 SK |
62 | |
63 | static int gen_init_phy(int phy_addr); | |
64 | static int gen_is_phy_connected(int phy_addr); | |
65 | static int gen_get_link_speed(int phy_addr); | |
66 | static int gen_auto_negotiate(int phy_addr); | |
67 | ||
c74b2108 SK |
68 | void eth_mdio_enable(void) |
69 | { | |
fcaac589 | 70 | davinci_eth_mdio_enable(); |
c74b2108 | 71 | } |
c74b2108 | 72 | |
c74b2108 SK |
73 | /* EMAC Addresses */ |
74 | static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; | |
75 | static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; | |
76 | static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; | |
77 | ||
78 | /* EMAC descriptors */ | |
79 | static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); | |
80 | static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); | |
81 | static volatile emac_desc *emac_rx_active_head = 0; | |
82 | static volatile emac_desc *emac_rx_active_tail = 0; | |
83 | static int emac_rx_queue_active = 0; | |
84 | ||
85 | /* Receive packet buffers */ | |
86 | static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; | |
87 | ||
dc02bada HS |
88 | #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT |
89 | #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 | |
90 | #endif | |
062fe7d3 | 91 | |
c74b2108 | 92 | /* PHY address for a discovered PHY (0xff - not found) */ |
dc02bada | 93 | static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; |
062fe7d3 MH |
94 | |
95 | /* number of PHY found active */ | |
96 | static u_int8_t num_phy; | |
c74b2108 | 97 | |
dc02bada | 98 | phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; |
c74b2108 | 99 | |
7b37a27e BG |
100 | static int davinci_eth_set_mac_addr(struct eth_device *dev) |
101 | { | |
102 | unsigned long mac_hi; | |
103 | unsigned long mac_lo; | |
104 | ||
105 | /* | |
106 | * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast | |
107 | * receive) | |
108 | * Using channel 0 only - other channels are disabled | |
109 | * */ | |
110 | writel(0, &adap_emac->MACINDEX); | |
111 | mac_hi = (dev->enetaddr[3] << 24) | | |
112 | (dev->enetaddr[2] << 16) | | |
113 | (dev->enetaddr[1] << 8) | | |
114 | (dev->enetaddr[0]); | |
115 | mac_lo = (dev->enetaddr[5] << 8) | | |
116 | (dev->enetaddr[4]); | |
117 | ||
118 | writel(mac_hi, &adap_emac->MACADDRHI); | |
119 | #if defined(DAVINCI_EMAC_VERSION2) | |
120 | writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, | |
121 | &adap_emac->MACADDRLO); | |
122 | #else | |
123 | writel(mac_lo, &adap_emac->MACADDRLO); | |
124 | #endif | |
125 | ||
126 | writel(0, &adap_emac->MACHASH1); | |
127 | writel(0, &adap_emac->MACHASH2); | |
128 | ||
129 | /* Set source MAC address - REQUIRED */ | |
130 | writel(mac_hi, &adap_emac->MACSRCADDRHI); | |
131 | writel(mac_lo, &adap_emac->MACSRCADDRLO); | |
132 | ||
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
fcaac589 | 137 | static void davinci_eth_mdio_enable(void) |
c74b2108 SK |
138 | { |
139 | u_int32_t clkdiv; | |
140 | ||
882ecfa3 | 141 | clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; |
c74b2108 | 142 | |
d7e35437 NT |
143 | writel((clkdiv & 0xff) | |
144 | MDIO_CONTROL_ENABLE | | |
145 | MDIO_CONTROL_FAULT | | |
146 | MDIO_CONTROL_FAULT_ENABLE, | |
147 | &adap_mdio->CONTROL); | |
c74b2108 | 148 | |
d7e35437 NT |
149 | while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) |
150 | ; | |
c74b2108 SK |
151 | } |
152 | ||
153 | /* | |
154 | * Tries to find an active connected PHY. Returns 1 if address if found. | |
155 | * If no active PHY (or more than one PHY) found returns 0. | |
156 | * Sets active_phy_addr variable. | |
157 | */ | |
fcaac589 | 158 | static int davinci_eth_phy_detect(void) |
c74b2108 SK |
159 | { |
160 | u_int32_t phy_act_state; | |
161 | int i; | |
062fe7d3 MH |
162 | int j; |
163 | unsigned int count = 0; | |
164 | ||
dc02bada HS |
165 | for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) |
166 | active_phy_addr[i] = 0xff; | |
c74b2108 | 167 | |
062fe7d3 MH |
168 | udelay(1000); |
169 | phy_act_state = readl(&adap_mdio->ALIVE); | |
c74b2108 | 170 | |
d7e35437 | 171 | if (phy_act_state == 0) |
062fe7d3 | 172 | return 0; /* No active PHYs */ |
c74b2108 | 173 | |
fcaac589 | 174 | debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); |
c74b2108 | 175 | |
062fe7d3 | 176 | for (i = 0, j = 0; i < 32; i++) |
c74b2108 | 177 | if (phy_act_state & (1 << i)) { |
062fe7d3 | 178 | count++; |
dc02bada HS |
179 | if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { |
180 | active_phy_addr[j++] = i; | |
181 | } else { | |
182 | printf("%s: to many PHYs detected.\n", | |
183 | __func__); | |
184 | count = 0; | |
185 | break; | |
186 | } | |
c74b2108 | 187 | } |
c74b2108 | 188 | |
062fe7d3 MH |
189 | num_phy = count; |
190 | ||
191 | return count; | |
c74b2108 SK |
192 | } |
193 | ||
194 | ||
195 | /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ | |
fcaac589 | 196 | int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) |
c74b2108 SK |
197 | { |
198 | int tmp; | |
199 | ||
d7e35437 NT |
200 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
201 | ; | |
c74b2108 | 202 | |
d7e35437 NT |
203 | writel(MDIO_USERACCESS0_GO | |
204 | MDIO_USERACCESS0_WRITE_READ | | |
205 | ((reg_num & 0x1f) << 21) | | |
206 | ((phy_addr & 0x1f) << 16), | |
207 | &adap_mdio->USERACCESS0); | |
c74b2108 SK |
208 | |
209 | /* Wait for command to complete */ | |
d7e35437 NT |
210 | while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) |
211 | ; | |
c74b2108 SK |
212 | |
213 | if (tmp & MDIO_USERACCESS0_ACK) { | |
214 | *data = tmp & 0xffff; | |
215 | return(1); | |
216 | } | |
217 | ||
218 | *data = -1; | |
219 | return(0); | |
220 | } | |
221 | ||
222 | /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ | |
fcaac589 | 223 | int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) |
c74b2108 SK |
224 | { |
225 | ||
d7e35437 NT |
226 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
227 | ; | |
c74b2108 | 228 | |
d7e35437 NT |
229 | writel(MDIO_USERACCESS0_GO | |
230 | MDIO_USERACCESS0_WRITE_WRITE | | |
231 | ((reg_num & 0x1f) << 21) | | |
232 | ((phy_addr & 0x1f) << 16) | | |
233 | (data & 0xffff), | |
234 | &adap_mdio->USERACCESS0); | |
c74b2108 SK |
235 | |
236 | /* Wait for command to complete */ | |
d7e35437 NT |
237 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
238 | ; | |
c74b2108 SK |
239 | |
240 | return(1); | |
241 | } | |
242 | ||
243 | /* PHY functions for a generic PHY */ | |
244 | static int gen_init_phy(int phy_addr) | |
245 | { | |
246 | int ret = 1; | |
247 | ||
248 | if (gen_get_link_speed(phy_addr)) { | |
249 | /* Try another time */ | |
250 | ret = gen_get_link_speed(phy_addr); | |
251 | } | |
252 | ||
253 | return(ret); | |
254 | } | |
255 | ||
256 | static int gen_is_phy_connected(int phy_addr) | |
257 | { | |
258 | u_int16_t dummy; | |
259 | ||
062fe7d3 MH |
260 | return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); |
261 | } | |
262 | ||
263 | static int get_active_phy(void) | |
264 | { | |
265 | int i; | |
266 | ||
267 | for (i = 0; i < num_phy; i++) | |
268 | if (phy[i].get_link_speed(active_phy_addr[i])) | |
269 | return i; | |
270 | ||
271 | return -1; /* Return error if no link */ | |
c74b2108 SK |
272 | } |
273 | ||
274 | static int gen_get_link_speed(int phy_addr) | |
275 | { | |
276 | u_int16_t tmp; | |
277 | ||
d2607401 SR |
278 | if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && |
279 | (tmp & 0x04)) { | |
280 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ | |
281 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
7d2fade7 | 282 | davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); |
d2607401 SR |
283 | |
284 | /* Speed doesn't matter, there is no setting for it in EMAC. */ | |
7d2fade7 | 285 | if (tmp & (LPA_100FULL | LPA_10FULL)) { |
d2607401 SR |
286 | /* set EMAC for Full Duplex */ |
287 | writel(EMAC_MACCONTROL_MIIEN_ENABLE | | |
288 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE, | |
289 | &adap_emac->MACCONTROL); | |
290 | } else { | |
291 | /*set EMAC for Half Duplex */ | |
292 | writel(EMAC_MACCONTROL_MIIEN_ENABLE, | |
293 | &adap_emac->MACCONTROL); | |
294 | } | |
295 | ||
7d2fade7 | 296 | if (tmp & (LPA_100FULL | LPA_100HALF)) |
d2607401 SR |
297 | writel(readl(&adap_emac->MACCONTROL) | |
298 | EMAC_MACCONTROL_RMIISPEED_100, | |
299 | &adap_emac->MACCONTROL); | |
300 | else | |
301 | writel(readl(&adap_emac->MACCONTROL) & | |
302 | ~EMAC_MACCONTROL_RMIISPEED_100, | |
303 | &adap_emac->MACCONTROL); | |
304 | #endif | |
c74b2108 | 305 | return(1); |
d2607401 | 306 | } |
c74b2108 SK |
307 | |
308 | return(0); | |
309 | } | |
310 | ||
311 | static int gen_auto_negotiate(int phy_addr) | |
312 | { | |
313 | u_int16_t tmp; | |
cc4bd47f MH |
314 | u_int16_t val; |
315 | unsigned long cntr = 0; | |
316 | ||
317 | if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) | |
318 | return 0; | |
319 | ||
320 | val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | | |
321 | BMCR_SPEED100; | |
322 | davinci_eth_phy_write(phy_addr, MII_BMCR, val); | |
323 | ||
324 | if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) | |
325 | return 0; | |
326 | ||
327 | val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | | |
328 | ADVERTISE_10HALF); | |
329 | davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); | |
c74b2108 | 330 | |
8ef583a0 | 331 | if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) |
c74b2108 SK |
332 | return(0); |
333 | ||
334 | /* Restart Auto_negotiation */ | |
cc4bd47f | 335 | tmp |= BMCR_ANRESTART; |
8ef583a0 | 336 | davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); |
c74b2108 SK |
337 | |
338 | /*check AutoNegotiate complete */ | |
cc4bd47f MH |
339 | do { |
340 | udelay(40000); | |
341 | if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) | |
342 | return 0; | |
343 | ||
344 | if (tmp & BMSR_ANEGCOMPLETE) | |
345 | break; | |
346 | ||
347 | cntr++; | |
348 | } while (cntr < 200); | |
349 | ||
8ef583a0 | 350 | if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) |
c74b2108 SK |
351 | return(0); |
352 | ||
8ef583a0 | 353 | if (!(tmp & BMSR_ANEGCOMPLETE)) |
c74b2108 SK |
354 | return(0); |
355 | ||
356 | return(gen_get_link_speed(phy_addr)); | |
357 | } | |
358 | /* End of generic PHY functions */ | |
359 | ||
360 | ||
afaac86f | 361 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
5700bb63 | 362 | static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) |
c74b2108 | 363 | { |
fcaac589 | 364 | return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); |
c74b2108 SK |
365 | } |
366 | ||
5700bb63 | 367 | static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) |
c74b2108 | 368 | { |
fcaac589 | 369 | return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); |
c74b2108 | 370 | } |
c74b2108 SK |
371 | #endif |
372 | ||
fb1d6332 | 373 | static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) |
d7e35437 NT |
374 | { |
375 | u_int16_t data; | |
376 | ||
fb1d6332 | 377 | if (davinci_eth_phy_read(phy_addr, 0, &data)) { |
d7e35437 NT |
378 | if (data & (1 << 6)) { /* speed selection MSB */ |
379 | /* | |
380 | * Check if link detected is giga-bit | |
381 | * If Gigabit mode detected, enable gigbit in MAC | |
382 | */ | |
4b9b9e7c SP |
383 | writel(readl(&adap_emac->MACCONTROL) | |
384 | EMAC_MACCONTROL_GIGFORCE | | |
385 | EMAC_MACCONTROL_GIGABIT_ENABLE, | |
386 | &adap_emac->MACCONTROL); | |
d7e35437 NT |
387 | } |
388 | } | |
389 | } | |
c74b2108 SK |
390 | |
391 | /* Eth device open */ | |
8453587e | 392 | static int davinci_eth_open(struct eth_device *dev, bd_t *bis) |
c74b2108 SK |
393 | { |
394 | dv_reg_p addr; | |
395 | u_int32_t clkdiv, cnt; | |
396 | volatile emac_desc *rx_desc; | |
062fe7d3 | 397 | int index; |
c74b2108 SK |
398 | |
399 | debug_emac("+ emac_open\n"); | |
400 | ||
401 | /* Reset EMAC module and disable interrupts in wrapper */ | |
d7e35437 NT |
402 | writel(1, &adap_emac->SOFTRESET); |
403 | while (readl(&adap_emac->SOFTRESET) != 0) | |
404 | ; | |
405 | #if defined(DAVINCI_EMAC_VERSION2) | |
406 | writel(1, &adap_ewrap->softrst); | |
407 | while (readl(&adap_ewrap->softrst) != 0) | |
408 | ; | |
409 | #else | |
410 | writel(0, &adap_ewrap->EWCTL); | |
c74b2108 | 411 | for (cnt = 0; cnt < 5; cnt++) { |
d7e35437 | 412 | clkdiv = readl(&adap_ewrap->EWCTL); |
c74b2108 | 413 | } |
d7e35437 | 414 | #endif |
c74b2108 | 415 | |
d2607401 SR |
416 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ |
417 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
418 | adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; | |
419 | adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; | |
420 | adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; | |
421 | #endif | |
c74b2108 SK |
422 | rx_desc = emac_rx_desc; |
423 | ||
d7e35437 NT |
424 | writel(1, &adap_emac->TXCONTROL); |
425 | writel(1, &adap_emac->RXCONTROL); | |
c74b2108 | 426 | |
7b37a27e | 427 | davinci_eth_set_mac_addr(dev); |
c74b2108 SK |
428 | |
429 | /* Set DMA 8 TX / 8 RX Head pointers to 0 */ | |
430 | addr = &adap_emac->TX0HDP; | |
431 | for(cnt = 0; cnt < 16; cnt++) | |
d7e35437 | 432 | writel(0, addr++); |
c74b2108 SK |
433 | |
434 | addr = &adap_emac->RX0HDP; | |
435 | for(cnt = 0; cnt < 16; cnt++) | |
d7e35437 | 436 | writel(0, addr++); |
c74b2108 SK |
437 | |
438 | /* Clear Statistics (do this before setting MacControl register) */ | |
439 | addr = &adap_emac->RXGOODFRAMES; | |
440 | for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) | |
d7e35437 | 441 | writel(0, addr++); |
c74b2108 SK |
442 | |
443 | /* No multicast addressing */ | |
d7e35437 NT |
444 | writel(0, &adap_emac->MACHASH1); |
445 | writel(0, &adap_emac->MACHASH2); | |
c74b2108 SK |
446 | |
447 | /* Create RX queue and set receive process in place */ | |
448 | emac_rx_active_head = emac_rx_desc; | |
449 | for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { | |
450 | rx_desc->next = (u_int32_t)(rx_desc + 1); | |
451 | rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; | |
452 | rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; | |
453 | rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; | |
454 | rx_desc++; | |
455 | } | |
456 | ||
d7e35437 | 457 | /* Finalize the rx desc list */ |
c74b2108 SK |
458 | rx_desc--; |
459 | rx_desc->next = 0; | |
460 | emac_rx_active_tail = rx_desc; | |
461 | emac_rx_queue_active = 1; | |
462 | ||
463 | /* Enable TX/RX */ | |
d7e35437 NT |
464 | writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); |
465 | writel(0, &adap_emac->RXBUFFEROFFSET); | |
c74b2108 | 466 | |
d7e35437 NT |
467 | /* |
468 | * No fancy configs - Use this for promiscous debug | |
469 | * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE | |
470 | */ | |
471 | writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); | |
c74b2108 SK |
472 | |
473 | /* Enable ch 0 only */ | |
d7e35437 | 474 | writel(1, &adap_emac->RXUNICASTSET); |
c74b2108 SK |
475 | |
476 | /* Enable MII interface and Full duplex mode */ | |
d7e35437 NT |
477 | #ifdef CONFIG_SOC_DA8XX |
478 | writel((EMAC_MACCONTROL_MIIEN_ENABLE | | |
479 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE | | |
480 | EMAC_MACCONTROL_RMIISPEED_100), | |
481 | &adap_emac->MACCONTROL); | |
482 | #else | |
483 | writel((EMAC_MACCONTROL_MIIEN_ENABLE | | |
484 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE), | |
485 | &adap_emac->MACCONTROL); | |
486 | #endif | |
c74b2108 SK |
487 | |
488 | /* Init MDIO & get link state */ | |
882ecfa3 | 489 | clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; |
d7e35437 NT |
490 | writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, |
491 | &adap_mdio->CONTROL); | |
492 | ||
493 | /* We need to wait for MDIO to start */ | |
494 | udelay(1000); | |
c74b2108 | 495 | |
062fe7d3 MH |
496 | index = get_active_phy(); |
497 | if (index == -1) | |
c74b2108 SK |
498 | return(0); |
499 | ||
fb1d6332 | 500 | emac_gigabit_enable(active_phy_addr[index]); |
d7e35437 | 501 | |
c74b2108 | 502 | /* Start receive process */ |
d7e35437 | 503 | writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); |
c74b2108 SK |
504 | |
505 | debug_emac("- emac_open\n"); | |
506 | ||
507 | return(1); | |
508 | } | |
509 | ||
510 | /* EMAC Channel Teardown */ | |
fcaac589 | 511 | static void davinci_eth_ch_teardown(int ch) |
c74b2108 SK |
512 | { |
513 | dv_reg dly = 0xff; | |
514 | dv_reg cnt; | |
515 | ||
516 | debug_emac("+ emac_ch_teardown\n"); | |
517 | ||
518 | if (ch == EMAC_CH_TX) { | |
519 | /* Init TX channel teardown */ | |
ba511f77 | 520 | writel(0, &adap_emac->TXTEARDOWN); |
d7e35437 NT |
521 | do { |
522 | /* | |
523 | * Wait here for Tx teardown completion interrupt to | |
524 | * occur. Note: A task delay can be called here to pend | |
525 | * rather than occupying CPU cycles - anyway it has | |
526 | * been found that teardown takes very few cpu cycles | |
527 | * and does not affect functionality | |
528 | */ | |
529 | dly--; | |
530 | udelay(1); | |
531 | if (dly == 0) | |
53677ef1 | 532 | break; |
d7e35437 NT |
533 | cnt = readl(&adap_emac->TX0CP); |
534 | } while (cnt != 0xfffffffc); | |
535 | writel(cnt, &adap_emac->TX0CP); | |
536 | writel(0, &adap_emac->TX0HDP); | |
c74b2108 SK |
537 | } else { |
538 | /* Init RX channel teardown */ | |
ba511f77 | 539 | writel(0, &adap_emac->RXTEARDOWN); |
d7e35437 NT |
540 | do { |
541 | /* | |
542 | * Wait here for Rx teardown completion interrupt to | |
543 | * occur. Note: A task delay can be called here to pend | |
544 | * rather than occupying CPU cycles - anyway it has | |
545 | * been found that teardown takes very few cpu cycles | |
546 | * and does not affect functionality | |
547 | */ | |
548 | dly--; | |
549 | udelay(1); | |
550 | if (dly == 0) | |
53677ef1 | 551 | break; |
d7e35437 NT |
552 | cnt = readl(&adap_emac->RX0CP); |
553 | } while (cnt != 0xfffffffc); | |
554 | writel(cnt, &adap_emac->RX0CP); | |
555 | writel(0, &adap_emac->RX0HDP); | |
c74b2108 SK |
556 | } |
557 | ||
558 | debug_emac("- emac_ch_teardown\n"); | |
559 | } | |
560 | ||
561 | /* Eth device close */ | |
8453587e | 562 | static void davinci_eth_close(struct eth_device *dev) |
c74b2108 SK |
563 | { |
564 | debug_emac("+ emac_close\n"); | |
565 | ||
fcaac589 SP |
566 | davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ |
567 | davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ | |
c74b2108 SK |
568 | |
569 | /* Reset EMAC module and disable interrupts in wrapper */ | |
d7e35437 NT |
570 | writel(1, &adap_emac->SOFTRESET); |
571 | #if defined(DAVINCI_EMAC_VERSION2) | |
572 | writel(1, &adap_ewrap->softrst); | |
573 | #else | |
574 | writel(0, &adap_ewrap->EWCTL); | |
575 | #endif | |
c74b2108 | 576 | |
d2607401 SR |
577 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ |
578 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
579 | adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; | |
580 | adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; | |
581 | adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; | |
582 | #endif | |
c74b2108 | 583 | debug_emac("- emac_close\n"); |
c74b2108 SK |
584 | } |
585 | ||
586 | static int tx_send_loop = 0; | |
587 | ||
588 | /* | |
589 | * This function sends a single packet on the network and returns | |
590 | * positive number (number of bytes transmitted) or negative for error | |
591 | */ | |
8453587e BW |
592 | static int davinci_eth_send_packet (struct eth_device *dev, |
593 | volatile void *packet, int length) | |
c74b2108 SK |
594 | { |
595 | int ret_status = -1; | |
062fe7d3 | 596 | int index; |
c74b2108 SK |
597 | tx_send_loop = 0; |
598 | ||
062fe7d3 MH |
599 | index = get_active_phy(); |
600 | if (index == -1) { | |
601 | printf(" WARN: emac_send_packet: No link\n"); | |
c74b2108 SK |
602 | return (ret_status); |
603 | } | |
604 | ||
fb1d6332 | 605 | emac_gigabit_enable(active_phy_addr[index]); |
d7e35437 | 606 | |
c74b2108 | 607 | /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ |
53677ef1 | 608 | if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { |
c74b2108 SK |
609 | length = EMAC_MIN_ETHERNET_PKT_SIZE; |
610 | } | |
611 | ||
612 | /* Populate the TX descriptor */ | |
53677ef1 WD |
613 | emac_tx_desc->next = 0; |
614 | emac_tx_desc->buffer = (u_int8_t *) packet; | |
c74b2108 SK |
615 | emac_tx_desc->buff_off_len = (length & 0xffff); |
616 | emac_tx_desc->pkt_flag_len = ((length & 0xffff) | | |
53677ef1 WD |
617 | EMAC_CPPI_SOP_BIT | |
618 | EMAC_CPPI_OWNERSHIP_BIT | | |
619 | EMAC_CPPI_EOP_BIT); | |
c74b2108 | 620 | /* Send the packet */ |
d7e35437 | 621 | writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); |
c74b2108 SK |
622 | |
623 | /* Wait for packet to complete or link down */ | |
624 | while (1) { | |
062fe7d3 | 625 | if (!phy[index].get_link_speed(active_phy_addr[index])) { |
fcaac589 | 626 | davinci_eth_ch_teardown (EMAC_CH_TX); |
53677ef1 WD |
627 | return (ret_status); |
628 | } | |
d7e35437 | 629 | |
fb1d6332 | 630 | emac_gigabit_enable(active_phy_addr[index]); |
d7e35437 NT |
631 | |
632 | if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { | |
53677ef1 WD |
633 | ret_status = length; |
634 | break; | |
c74b2108 | 635 | } |
53677ef1 | 636 | tx_send_loop++; |
c74b2108 SK |
637 | } |
638 | ||
53677ef1 | 639 | return (ret_status); |
c74b2108 SK |
640 | } |
641 | ||
642 | /* | |
643 | * This function handles receipt of a packet from the network | |
644 | */ | |
8453587e | 645 | static int davinci_eth_rcv_packet (struct eth_device *dev) |
c74b2108 | 646 | { |
53677ef1 WD |
647 | volatile emac_desc *rx_curr_desc; |
648 | volatile emac_desc *curr_desc; | |
649 | volatile emac_desc *tail_desc; | |
650 | int status, ret = -1; | |
c74b2108 SK |
651 | |
652 | rx_curr_desc = emac_rx_active_head; | |
653 | status = rx_curr_desc->pkt_flag_len; | |
654 | if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { | |
53677ef1 WD |
655 | if (status & EMAC_CPPI_RX_ERROR_FRAME) { |
656 | /* Error in packet - discard it and requeue desc */ | |
657 | printf ("WARN: emac_rcv_pkt: Error in packet\n"); | |
c74b2108 | 658 | } else { |
53677ef1 WD |
659 | NetReceive (rx_curr_desc->buffer, |
660 | (rx_curr_desc->buff_off_len & 0xffff)); | |
c74b2108 | 661 | ret = rx_curr_desc->buff_off_len & 0xffff; |
53677ef1 | 662 | } |
c74b2108 | 663 | |
53677ef1 | 664 | /* Ack received packet descriptor */ |
d7e35437 | 665 | writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); |
53677ef1 WD |
666 | curr_desc = rx_curr_desc; |
667 | emac_rx_active_head = | |
668 | (volatile emac_desc *) rx_curr_desc->next; | |
c74b2108 | 669 | |
53677ef1 WD |
670 | if (status & EMAC_CPPI_EOQ_BIT) { |
671 | if (emac_rx_active_head) { | |
d7e35437 NT |
672 | writel((unsigned long)emac_rx_active_head, |
673 | &adap_emac->RX0HDP); | |
c74b2108 SK |
674 | } else { |
675 | emac_rx_queue_active = 0; | |
53677ef1 | 676 | printf ("INFO:emac_rcv_packet: RX Queue not active\n"); |
c74b2108 SK |
677 | } |
678 | } | |
679 | ||
680 | /* Recycle RX descriptor */ | |
681 | rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; | |
682 | rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; | |
683 | rx_curr_desc->next = 0; | |
684 | ||
685 | if (emac_rx_active_head == 0) { | |
53677ef1 | 686 | printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); |
c74b2108 SK |
687 | emac_rx_active_head = curr_desc; |
688 | emac_rx_active_tail = curr_desc; | |
689 | if (emac_rx_queue_active != 0) { | |
d7e35437 NT |
690 | writel((unsigned long)emac_rx_active_head, |
691 | &adap_emac->RX0HDP); | |
53677ef1 | 692 | printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); |
c74b2108 SK |
693 | emac_rx_queue_active = 1; |
694 | } | |
695 | } else { | |
696 | tail_desc = emac_rx_active_tail; | |
697 | emac_rx_active_tail = curr_desc; | |
53677ef1 | 698 | tail_desc->next = (unsigned int) curr_desc; |
c74b2108 SK |
699 | status = tail_desc->pkt_flag_len; |
700 | if (status & EMAC_CPPI_EOQ_BIT) { | |
d7e35437 NT |
701 | writel((unsigned long)curr_desc, |
702 | &adap_emac->RX0HDP); | |
c74b2108 SK |
703 | status &= ~EMAC_CPPI_EOQ_BIT; |
704 | tail_desc->pkt_flag_len = status; | |
705 | } | |
706 | } | |
53677ef1 | 707 | return (ret); |
c74b2108 | 708 | } |
53677ef1 | 709 | return (0); |
c74b2108 SK |
710 | } |
711 | ||
8cc13c13 BW |
712 | /* |
713 | * This function initializes the emac hardware. It does NOT initialize | |
714 | * EMAC modules power or pin multiplexors, that is done by board_init() | |
715 | * much earlier in bootup process. Returns 1 on success, 0 otherwise. | |
716 | */ | |
8453587e | 717 | int davinci_emac_initialize(void) |
8cc13c13 BW |
718 | { |
719 | u_int32_t phy_id; | |
720 | u_int16_t tmp; | |
721 | int i; | |
062fe7d3 | 722 | int ret; |
8453587e BW |
723 | struct eth_device *dev; |
724 | ||
725 | dev = malloc(sizeof *dev); | |
726 | ||
727 | if (dev == NULL) | |
728 | return -1; | |
729 | ||
730 | memset(dev, 0, sizeof *dev); | |
2a7d603f | 731 | sprintf(dev->name, "DaVinci-EMAC"); |
8453587e BW |
732 | |
733 | dev->iobase = 0; | |
734 | dev->init = davinci_eth_open; | |
735 | dev->halt = davinci_eth_close; | |
736 | dev->send = davinci_eth_send_packet; | |
737 | dev->recv = davinci_eth_rcv_packet; | |
7b37a27e | 738 | dev->write_hwaddr = davinci_eth_set_mac_addr; |
8453587e BW |
739 | |
740 | eth_register(dev); | |
8cc13c13 BW |
741 | |
742 | davinci_eth_mdio_enable(); | |
743 | ||
19fdf9a1 HS |
744 | /* let the EMAC detect the PHYs */ |
745 | udelay(5000); | |
746 | ||
8cc13c13 | 747 | for (i = 0; i < 256; i++) { |
d7e35437 | 748 | if (readl(&adap_mdio->ALIVE)) |
8cc13c13 | 749 | break; |
062fe7d3 | 750 | udelay(1000); |
8cc13c13 BW |
751 | } |
752 | ||
753 | if (i >= 256) { | |
754 | printf("No ETH PHY detected!!!\n"); | |
755 | return(0); | |
756 | } | |
757 | ||
062fe7d3 MH |
758 | /* Find if PHY(s) is/are connected */ |
759 | ret = davinci_eth_phy_detect(); | |
760 | if (!ret) | |
8cc13c13 | 761 | return(0); |
062fe7d3 | 762 | else |
dc02bada | 763 | debug_emac(" %d ETH PHY detected\n", ret); |
8cc13c13 BW |
764 | |
765 | /* Get PHY ID and initialize phy_ops for a detected PHY */ | |
062fe7d3 MH |
766 | for (i = 0; i < num_phy; i++) { |
767 | if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, | |
768 | &tmp)) { | |
769 | active_phy_addr[i] = 0xff; | |
770 | continue; | |
771 | } | |
c74b2108 | 772 | |
062fe7d3 | 773 | phy_id = (tmp << 16) & 0xffff0000; |
8cc13c13 | 774 | |
062fe7d3 MH |
775 | if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, |
776 | &tmp)) { | |
777 | active_phy_addr[i] = 0xff; | |
778 | continue; | |
779 | } | |
8cc13c13 | 780 | |
062fe7d3 | 781 | phy_id |= tmp & 0x0000ffff; |
8cc13c13 | 782 | |
062fe7d3 MH |
783 | switch (phy_id) { |
784 | case PHY_KSZ8873: | |
785 | sprintf(phy[i].name, "KSZ8873 @ 0x%02x", | |
786 | active_phy_addr[i]); | |
787 | phy[i].init = ksz8873_init_phy; | |
788 | phy[i].is_phy_connected = ksz8873_is_phy_connected; | |
789 | phy[i].get_link_speed = ksz8873_get_link_speed; | |
790 | phy[i].auto_negotiate = ksz8873_auto_negotiate; | |
791 | break; | |
8cc13c13 | 792 | case PHY_LXT972: |
062fe7d3 MH |
793 | sprintf(phy[i].name, "LXT972 @ 0x%02x", |
794 | active_phy_addr[i]); | |
795 | phy[i].init = lxt972_init_phy; | |
796 | phy[i].is_phy_connected = lxt972_is_phy_connected; | |
797 | phy[i].get_link_speed = lxt972_get_link_speed; | |
798 | phy[i].auto_negotiate = lxt972_auto_negotiate; | |
8cc13c13 BW |
799 | break; |
800 | case PHY_DP83848: | |
062fe7d3 MH |
801 | sprintf(phy[i].name, "DP83848 @ 0x%02x", |
802 | active_phy_addr[i]); | |
803 | phy[i].init = dp83848_init_phy; | |
804 | phy[i].is_phy_connected = dp83848_is_phy_connected; | |
805 | phy[i].get_link_speed = dp83848_get_link_speed; | |
806 | phy[i].auto_negotiate = dp83848_auto_negotiate; | |
8cc13c13 | 807 | break; |
840f8923 | 808 | case PHY_ET1011C: |
062fe7d3 MH |
809 | sprintf(phy[i].name, "ET1011C @ 0x%02x", |
810 | active_phy_addr[i]); | |
811 | phy[i].init = gen_init_phy; | |
812 | phy[i].is_phy_connected = gen_is_phy_connected; | |
813 | phy[i].get_link_speed = et1011c_get_link_speed; | |
814 | phy[i].auto_negotiate = gen_auto_negotiate; | |
840f8923 | 815 | break; |
8cc13c13 | 816 | default: |
062fe7d3 MH |
817 | sprintf(phy[i].name, "GENERIC @ 0x%02x", |
818 | active_phy_addr[i]); | |
819 | phy[i].init = gen_init_phy; | |
820 | phy[i].is_phy_connected = gen_is_phy_connected; | |
821 | phy[i].get_link_speed = gen_get_link_speed; | |
822 | phy[i].auto_negotiate = gen_auto_negotiate; | |
823 | } | |
8cc13c13 | 824 | |
e0297a55 | 825 | debug("Ethernet PHY: %s\n", phy[i].name); |
8cc13c13 | 826 | |
062fe7d3 MH |
827 | miiphy_register(phy[i].name, davinci_mii_phy_read, |
828 | davinci_mii_phy_write); | |
829 | } | |
8cc13c13 BW |
830 | return(1); |
831 | } |