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Commit | Line | Data |
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5b1b1883 VK |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5b1b1883 VK |
6 | */ |
7 | ||
8 | /* | |
64dcd25f | 9 | * Designware ethernet IP driver for U-Boot |
5b1b1883 VK |
10 | */ |
11 | ||
12 | #include <common.h> | |
75577ba4 | 13 | #include <dm.h> |
64dcd25f | 14 | #include <errno.h> |
5b1b1883 VK |
15 | #include <miiphy.h> |
16 | #include <malloc.h> | |
8b7ee66c | 17 | #include <pci.h> |
ef76025a | 18 | #include <linux/compiler.h> |
5b1b1883 VK |
19 | #include <linux/err.h> |
20 | #include <asm/io.h> | |
6ec922fa | 21 | #include <power/regulator.h> |
5b1b1883 VK |
22 | #include "designware.h" |
23 | ||
75577ba4 SG |
24 | DECLARE_GLOBAL_DATA_PTR; |
25 | ||
92a190aa AB |
26 | static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
27 | { | |
90b7fc92 SS |
28 | #ifdef CONFIG_DM_ETH |
29 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); | |
30 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
31 | #else | |
92a190aa | 32 | struct eth_mac_regs *mac_p = bus->priv; |
90b7fc92 | 33 | #endif |
92a190aa AB |
34 | ulong start; |
35 | u16 miiaddr; | |
36 | int timeout = CONFIG_MDIO_TIMEOUT; | |
37 | ||
38 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | | |
39 | ((reg << MIIREGSHIFT) & MII_REGMSK); | |
40 | ||
41 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); | |
42 | ||
43 | start = get_timer(0); | |
44 | while (get_timer(start) < timeout) { | |
45 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) | |
46 | return readl(&mac_p->miidata); | |
47 | udelay(10); | |
48 | }; | |
49 | ||
64dcd25f | 50 | return -ETIMEDOUT; |
92a190aa AB |
51 | } |
52 | ||
53 | static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, | |
54 | u16 val) | |
55 | { | |
90b7fc92 SS |
56 | #ifdef CONFIG_DM_ETH |
57 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); | |
58 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
59 | #else | |
92a190aa | 60 | struct eth_mac_regs *mac_p = bus->priv; |
90b7fc92 | 61 | #endif |
92a190aa AB |
62 | ulong start; |
63 | u16 miiaddr; | |
64dcd25f | 64 | int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; |
92a190aa AB |
65 | |
66 | writel(val, &mac_p->miidata); | |
67 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | | |
68 | ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; | |
69 | ||
70 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); | |
71 | ||
72 | start = get_timer(0); | |
73 | while (get_timer(start) < timeout) { | |
74 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { | |
75 | ret = 0; | |
76 | break; | |
77 | } | |
78 | udelay(10); | |
79 | }; | |
80 | ||
81 | return ret; | |
82 | } | |
83 | ||
66d027e2 | 84 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) |
90b7fc92 SS |
85 | static int dw_mdio_reset(struct mii_dev *bus) |
86 | { | |
87 | struct udevice *dev = bus->priv; | |
88 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
89 | struct dw_eth_pdata *pdata = dev_get_platdata(dev); | |
90 | int ret; | |
91 | ||
92 | if (!dm_gpio_is_valid(&priv->reset_gpio)) | |
93 | return 0; | |
94 | ||
95 | /* reset the phy */ | |
96 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); | |
97 | if (ret) | |
98 | return ret; | |
99 | ||
100 | udelay(pdata->reset_delays[0]); | |
101 | ||
102 | ret = dm_gpio_set_value(&priv->reset_gpio, 1); | |
103 | if (ret) | |
104 | return ret; | |
105 | ||
106 | udelay(pdata->reset_delays[1]); | |
107 | ||
108 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); | |
109 | if (ret) | |
110 | return ret; | |
111 | ||
112 | udelay(pdata->reset_delays[2]); | |
113 | ||
114 | return 0; | |
115 | } | |
116 | #endif | |
117 | ||
118 | static int dw_mdio_init(const char *name, void *priv) | |
92a190aa AB |
119 | { |
120 | struct mii_dev *bus = mdio_alloc(); | |
121 | ||
122 | if (!bus) { | |
123 | printf("Failed to allocate MDIO bus\n"); | |
64dcd25f | 124 | return -ENOMEM; |
92a190aa AB |
125 | } |
126 | ||
127 | bus->read = dw_mdio_read; | |
128 | bus->write = dw_mdio_write; | |
192bc694 | 129 | snprintf(bus->name, sizeof(bus->name), "%s", name); |
66d027e2 | 130 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) |
90b7fc92 SS |
131 | bus->reset = dw_mdio_reset; |
132 | #endif | |
92a190aa | 133 | |
90b7fc92 | 134 | bus->priv = priv; |
92a190aa AB |
135 | |
136 | return mdio_register(bus); | |
137 | } | |
13edd170 | 138 | |
64dcd25f | 139 | static void tx_descs_init(struct dw_eth_dev *priv) |
5b1b1883 | 140 | { |
5b1b1883 VK |
141 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
142 | struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; | |
143 | char *txbuffs = &priv->txbuffs[0]; | |
144 | struct dmamacdescr *desc_p; | |
145 | u32 idx; | |
146 | ||
147 | for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { | |
148 | desc_p = &desc_table_p[idx]; | |
0e1a3e30 BG |
149 | desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; |
150 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; | |
5b1b1883 VK |
151 | |
152 | #if defined(CONFIG_DW_ALTDESCRIPTOR) | |
153 | desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | | |
2b261092 MV |
154 | DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | |
155 | DESC_TXSTS_TXCHECKINSCTRL | | |
5b1b1883 VK |
156 | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); |
157 | ||
158 | desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; | |
159 | desc_p->dmamac_cntl = 0; | |
160 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); | |
161 | #else | |
162 | desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; | |
163 | desc_p->txrx_status = 0; | |
164 | #endif | |
165 | } | |
166 | ||
167 | /* Correcting the last pointer of the chain */ | |
0e1a3e30 | 168 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
5b1b1883 | 169 | |
50b0df81 | 170 | /* Flush all Tx buffer descriptors at once */ |
0e1a3e30 BG |
171 | flush_dcache_range((ulong)priv->tx_mac_descrtable, |
172 | (ulong)priv->tx_mac_descrtable + | |
50b0df81 AB |
173 | sizeof(priv->tx_mac_descrtable)); |
174 | ||
5b1b1883 | 175 | writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); |
74cb708d | 176 | priv->tx_currdescnum = 0; |
5b1b1883 VK |
177 | } |
178 | ||
64dcd25f | 179 | static void rx_descs_init(struct dw_eth_dev *priv) |
5b1b1883 | 180 | { |
5b1b1883 VK |
181 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
182 | struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; | |
183 | char *rxbuffs = &priv->rxbuffs[0]; | |
184 | struct dmamacdescr *desc_p; | |
185 | u32 idx; | |
186 | ||
50b0df81 AB |
187 | /* Before passing buffers to GMAC we need to make sure zeros |
188 | * written there right after "priv" structure allocation were | |
189 | * flushed into RAM. | |
190 | * Otherwise there's a chance to get some of them flushed in RAM when | |
191 | * GMAC is already pushing data to RAM via DMA. This way incoming from | |
192 | * GMAC data will be corrupted. */ | |
0e1a3e30 | 193 | flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); |
50b0df81 | 194 | |
5b1b1883 VK |
195 | for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { |
196 | desc_p = &desc_table_p[idx]; | |
0e1a3e30 BG |
197 | desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; |
198 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; | |
5b1b1883 VK |
199 | |
200 | desc_p->dmamac_cntl = | |
2b261092 | 201 | (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | |
5b1b1883 VK |
202 | DESC_RXCTRL_RXCHAIN; |
203 | ||
204 | desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; | |
205 | } | |
206 | ||
207 | /* Correcting the last pointer of the chain */ | |
0e1a3e30 | 208 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
5b1b1883 | 209 | |
50b0df81 | 210 | /* Flush all Rx buffer descriptors at once */ |
0e1a3e30 BG |
211 | flush_dcache_range((ulong)priv->rx_mac_descrtable, |
212 | (ulong)priv->rx_mac_descrtable + | |
50b0df81 AB |
213 | sizeof(priv->rx_mac_descrtable)); |
214 | ||
5b1b1883 | 215 | writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); |
74cb708d | 216 | priv->rx_currdescnum = 0; |
5b1b1883 VK |
217 | } |
218 | ||
64dcd25f | 219 | static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) |
5b1b1883 | 220 | { |
92a190aa AB |
221 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
222 | u32 macid_lo, macid_hi; | |
92a190aa AB |
223 | |
224 | macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + | |
225 | (mac_id[3] << 24); | |
226 | macid_hi = mac_id[4] + (mac_id[5] << 8); | |
227 | ||
228 | writel(macid_hi, &mac_p->macaddr0hi); | |
229 | writel(macid_lo, &mac_p->macaddr0lo); | |
230 | ||
231 | return 0; | |
5b1b1883 VK |
232 | } |
233 | ||
0ea38db9 SG |
234 | static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, |
235 | struct phy_device *phydev) | |
5b1b1883 | 236 | { |
92a190aa | 237 | u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; |
5b1b1883 | 238 | |
92a190aa AB |
239 | if (!phydev->link) { |
240 | printf("%s: No link.\n", phydev->dev->name); | |
0ea38db9 | 241 | return 0; |
92a190aa | 242 | } |
5b1b1883 | 243 | |
92a190aa AB |
244 | if (phydev->speed != 1000) |
245 | conf |= MII_PORTSELECT; | |
b884c3fe AB |
246 | else |
247 | conf &= ~MII_PORTSELECT; | |
7091915a | 248 | |
92a190aa AB |
249 | if (phydev->speed == 100) |
250 | conf |= FES_100; | |
5b1b1883 | 251 | |
92a190aa AB |
252 | if (phydev->duplex) |
253 | conf |= FULLDPLXMODE; | |
cafabe19 | 254 | |
92a190aa | 255 | writel(conf, &mac_p->conf); |
5b1b1883 | 256 | |
92a190aa AB |
257 | printf("Speed: %d, %s duplex%s\n", phydev->speed, |
258 | (phydev->duplex) ? "full" : "half", | |
259 | (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); | |
0ea38db9 SG |
260 | |
261 | return 0; | |
5b1b1883 VK |
262 | } |
263 | ||
64dcd25f | 264 | static void _dw_eth_halt(struct dw_eth_dev *priv) |
5b1b1883 | 265 | { |
5b1b1883 | 266 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
92a190aa | 267 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
5b1b1883 | 268 | |
92a190aa AB |
269 | writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); |
270 | writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); | |
5b1b1883 | 271 | |
92a190aa | 272 | phy_shutdown(priv->phydev); |
5b1b1883 VK |
273 | } |
274 | ||
e72ced23 | 275 | int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) |
5b1b1883 | 276 | { |
5b1b1883 VK |
277 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
278 | struct eth_dma_regs *dma_p = priv->dma_regs_p; | |
92a190aa | 279 | unsigned int start; |
64dcd25f | 280 | int ret; |
5b1b1883 | 281 | |
92a190aa | 282 | writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); |
13edd170 | 283 | |
92a190aa AB |
284 | start = get_timer(0); |
285 | while (readl(&dma_p->busmode) & DMAMAC_SRST) { | |
875143f3 AB |
286 | if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { |
287 | printf("DMA reset timeout\n"); | |
64dcd25f | 288 | return -ETIMEDOUT; |
875143f3 | 289 | } |
ef76025a | 290 | |
92a190aa AB |
291 | mdelay(100); |
292 | }; | |
5b1b1883 | 293 | |
f3edfd30 BM |
294 | /* |
295 | * Soft reset above clears HW address registers. | |
296 | * So we have to set it here once again. | |
297 | */ | |
298 | _dw_write_hwaddr(priv, enetaddr); | |
299 | ||
64dcd25f SG |
300 | rx_descs_init(priv); |
301 | tx_descs_init(priv); | |
5b1b1883 | 302 | |
49692c5f | 303 | writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); |
5b1b1883 | 304 | |
d2279221 | 305 | #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE |
92a190aa AB |
306 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, |
307 | &dma_p->opmode); | |
d2279221 SZ |
308 | #else |
309 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO, | |
310 | &dma_p->opmode); | |
311 | #endif | |
5b1b1883 | 312 | |
92a190aa | 313 | writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); |
9afc1af0 | 314 | |
2ddaf13b SZ |
315 | #ifdef CONFIG_DW_AXI_BURST_LEN |
316 | writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); | |
317 | #endif | |
318 | ||
92a190aa | 319 | /* Start up the PHY */ |
64dcd25f SG |
320 | ret = phy_startup(priv->phydev); |
321 | if (ret) { | |
92a190aa AB |
322 | printf("Could not initialize PHY %s\n", |
323 | priv->phydev->dev->name); | |
64dcd25f | 324 | return ret; |
9afc1af0 VK |
325 | } |
326 | ||
0ea38db9 SG |
327 | ret = dw_adjust_link(priv, mac_p, priv->phydev); |
328 | if (ret) | |
329 | return ret; | |
5b1b1883 | 330 | |
f63f28ee SG |
331 | return 0; |
332 | } | |
333 | ||
e72ced23 | 334 | int designware_eth_enable(struct dw_eth_dev *priv) |
f63f28ee SG |
335 | { |
336 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
337 | ||
92a190aa | 338 | if (!priv->phydev->link) |
64dcd25f | 339 | return -EIO; |
5b1b1883 | 340 | |
aa51005c | 341 | writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); |
5b1b1883 VK |
342 | |
343 | return 0; | |
344 | } | |
345 | ||
64dcd25f | 346 | static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) |
5b1b1883 | 347 | { |
5b1b1883 VK |
348 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
349 | u32 desc_num = priv->tx_currdescnum; | |
350 | struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; | |
0e1a3e30 BG |
351 | ulong desc_start = (ulong)desc_p; |
352 | ulong desc_end = desc_start + | |
96cec17d | 353 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
0e1a3e30 BG |
354 | ulong data_start = desc_p->dmamac_addr; |
355 | ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); | |
964ea7c1 IC |
356 | /* |
357 | * Strictly we only need to invalidate the "txrx_status" field | |
358 | * for the following check, but on some platforms we cannot | |
96cec17d MV |
359 | * invalidate only 4 bytes, so we flush the entire descriptor, |
360 | * which is 16 bytes in total. This is safe because the | |
361 | * individual descriptors in the array are each aligned to | |
362 | * ARCH_DMA_MINALIGN and padded appropriately. | |
964ea7c1 | 363 | */ |
96cec17d | 364 | invalidate_dcache_range(desc_start, desc_end); |
50b0df81 | 365 | |
5b1b1883 VK |
366 | /* Check if the descriptor is owned by CPU */ |
367 | if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { | |
368 | printf("CPU not owner of tx frame\n"); | |
64dcd25f | 369 | return -EPERM; |
5b1b1883 VK |
370 | } |
371 | ||
0e1a3e30 | 372 | memcpy((void *)data_start, packet, length); |
5b1b1883 | 373 | |
50b0df81 | 374 | /* Flush data to be sent */ |
96cec17d | 375 | flush_dcache_range(data_start, data_end); |
50b0df81 | 376 | |
5b1b1883 VK |
377 | #if defined(CONFIG_DW_ALTDESCRIPTOR) |
378 | desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; | |
2b261092 | 379 | desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & |
5b1b1883 VK |
380 | DESC_TXCTRL_SIZE1MASK; |
381 | ||
382 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK); | |
383 | desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; | |
384 | #else | |
2b261092 MV |
385 | desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & |
386 | DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | | |
5b1b1883 VK |
387 | DESC_TXCTRL_TXFIRST; |
388 | ||
389 | desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; | |
390 | #endif | |
391 | ||
50b0df81 | 392 | /* Flush modified buffer descriptor */ |
96cec17d | 393 | flush_dcache_range(desc_start, desc_end); |
50b0df81 | 394 | |
5b1b1883 VK |
395 | /* Test the wrap-around condition. */ |
396 | if (++desc_num >= CONFIG_TX_DESCR_NUM) | |
397 | desc_num = 0; | |
398 | ||
399 | priv->tx_currdescnum = desc_num; | |
400 | ||
401 | /* Start the transmission */ | |
402 | writel(POLL_DATA, &dma_p->txpolldemand); | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
75577ba4 | 407 | static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) |
5b1b1883 | 408 | { |
50b0df81 | 409 | u32 status, desc_num = priv->rx_currdescnum; |
5b1b1883 | 410 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; |
75577ba4 | 411 | int length = -EAGAIN; |
0e1a3e30 BG |
412 | ulong desc_start = (ulong)desc_p; |
413 | ulong desc_end = desc_start + | |
96cec17d | 414 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
0e1a3e30 BG |
415 | ulong data_start = desc_p->dmamac_addr; |
416 | ulong data_end; | |
5b1b1883 | 417 | |
50b0df81 | 418 | /* Invalidate entire buffer descriptor */ |
96cec17d | 419 | invalidate_dcache_range(desc_start, desc_end); |
50b0df81 AB |
420 | |
421 | status = desc_p->txrx_status; | |
422 | ||
5b1b1883 VK |
423 | /* Check if the owner is the CPU */ |
424 | if (!(status & DESC_RXSTS_OWNBYDMA)) { | |
425 | ||
2b261092 | 426 | length = (status & DESC_RXSTS_FRMLENMSK) >> |
5b1b1883 VK |
427 | DESC_RXSTS_FRMLENSHFT; |
428 | ||
50b0df81 | 429 | /* Invalidate received data */ |
96cec17d MV |
430 | data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); |
431 | invalidate_dcache_range(data_start, data_end); | |
0e1a3e30 | 432 | *packetp = (uchar *)(ulong)desc_p->dmamac_addr; |
75577ba4 | 433 | } |
50b0df81 | 434 | |
75577ba4 SG |
435 | return length; |
436 | } | |
5b1b1883 | 437 | |
75577ba4 SG |
438 | static int _dw_free_pkt(struct dw_eth_dev *priv) |
439 | { | |
440 | u32 desc_num = priv->rx_currdescnum; | |
441 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; | |
0e1a3e30 BG |
442 | ulong desc_start = (ulong)desc_p; |
443 | ulong desc_end = desc_start + | |
75577ba4 | 444 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
5b1b1883 | 445 | |
75577ba4 SG |
446 | /* |
447 | * Make the current descriptor valid again and go to | |
448 | * the next one | |
449 | */ | |
450 | desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; | |
50b0df81 | 451 | |
75577ba4 SG |
452 | /* Flush only status field - others weren't changed */ |
453 | flush_dcache_range(desc_start, desc_end); | |
5b1b1883 | 454 | |
75577ba4 SG |
455 | /* Test the wrap-around condition. */ |
456 | if (++desc_num >= CONFIG_RX_DESCR_NUM) | |
457 | desc_num = 0; | |
5b1b1883 VK |
458 | priv->rx_currdescnum = desc_num; |
459 | ||
75577ba4 | 460 | return 0; |
5b1b1883 VK |
461 | } |
462 | ||
64dcd25f | 463 | static int dw_phy_init(struct dw_eth_dev *priv, void *dev) |
5b1b1883 | 464 | { |
92a190aa | 465 | struct phy_device *phydev; |
6968ec92 | 466 | int mask = 0xffffffff, ret; |
cafabe19 | 467 | |
92a190aa AB |
468 | #ifdef CONFIG_PHY_ADDR |
469 | mask = 1 << CONFIG_PHY_ADDR; | |
5b1b1883 VK |
470 | #endif |
471 | ||
92a190aa AB |
472 | phydev = phy_find_by_mask(priv->bus, mask, priv->interface); |
473 | if (!phydev) | |
64dcd25f | 474 | return -ENODEV; |
5b1b1883 | 475 | |
15e82e53 IC |
476 | phy_connect_dev(phydev, dev); |
477 | ||
92a190aa | 478 | phydev->supported &= PHY_GBIT_FEATURES; |
6968ec92 AB |
479 | if (priv->max_speed) { |
480 | ret = phy_set_supported(phydev, priv->max_speed); | |
481 | if (ret) | |
482 | return ret; | |
483 | } | |
92a190aa | 484 | phydev->advertising = phydev->supported; |
5b1b1883 | 485 | |
92a190aa AB |
486 | priv->phydev = phydev; |
487 | phy_config(phydev); | |
ef76025a | 488 | |
64dcd25f SG |
489 | return 0; |
490 | } | |
491 | ||
75577ba4 | 492 | #ifndef CONFIG_DM_ETH |
64dcd25f SG |
493 | static int dw_eth_init(struct eth_device *dev, bd_t *bis) |
494 | { | |
f63f28ee SG |
495 | int ret; |
496 | ||
e72ced23 | 497 | ret = designware_eth_init(dev->priv, dev->enetaddr); |
f63f28ee SG |
498 | if (!ret) |
499 | ret = designware_eth_enable(dev->priv); | |
500 | ||
501 | return ret; | |
64dcd25f SG |
502 | } |
503 | ||
504 | static int dw_eth_send(struct eth_device *dev, void *packet, int length) | |
505 | { | |
506 | return _dw_eth_send(dev->priv, packet, length); | |
507 | } | |
508 | ||
509 | static int dw_eth_recv(struct eth_device *dev) | |
510 | { | |
75577ba4 SG |
511 | uchar *packet; |
512 | int length; | |
513 | ||
514 | length = _dw_eth_recv(dev->priv, &packet); | |
515 | if (length == -EAGAIN) | |
516 | return 0; | |
517 | net_process_received_packet(packet, length); | |
518 | ||
519 | _dw_free_pkt(dev->priv); | |
520 | ||
521 | return 0; | |
64dcd25f SG |
522 | } |
523 | ||
524 | static void dw_eth_halt(struct eth_device *dev) | |
525 | { | |
526 | return _dw_eth_halt(dev->priv); | |
527 | } | |
528 | ||
529 | static int dw_write_hwaddr(struct eth_device *dev) | |
530 | { | |
531 | return _dw_write_hwaddr(dev->priv, dev->enetaddr); | |
5b1b1883 | 532 | } |
5b1b1883 | 533 | |
92a190aa | 534 | int designware_initialize(ulong base_addr, u32 interface) |
5b1b1883 VK |
535 | { |
536 | struct eth_device *dev; | |
537 | struct dw_eth_dev *priv; | |
538 | ||
539 | dev = (struct eth_device *) malloc(sizeof(struct eth_device)); | |
540 | if (!dev) | |
541 | return -ENOMEM; | |
542 | ||
543 | /* | |
544 | * Since the priv structure contains the descriptors which need a strict | |
545 | * buswidth alignment, memalign is used to allocate memory | |
546 | */ | |
1c848a25 IC |
547 | priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, |
548 | sizeof(struct dw_eth_dev)); | |
5b1b1883 VK |
549 | if (!priv) { |
550 | free(dev); | |
551 | return -ENOMEM; | |
552 | } | |
553 | ||
0e1a3e30 BG |
554 | if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { |
555 | printf("designware: buffers are outside DMA memory\n"); | |
556 | return -EINVAL; | |
557 | } | |
558 | ||
5b1b1883 VK |
559 | memset(dev, 0, sizeof(struct eth_device)); |
560 | memset(priv, 0, sizeof(struct dw_eth_dev)); | |
561 | ||
92a190aa | 562 | sprintf(dev->name, "dwmac.%lx", base_addr); |
5b1b1883 VK |
563 | dev->iobase = (int)base_addr; |
564 | dev->priv = priv; | |
565 | ||
5b1b1883 VK |
566 | priv->dev = dev; |
567 | priv->mac_regs_p = (struct eth_mac_regs *)base_addr; | |
568 | priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + | |
569 | DW_DMA_BASE_OFFSET); | |
5b1b1883 | 570 | |
5b1b1883 VK |
571 | dev->init = dw_eth_init; |
572 | dev->send = dw_eth_send; | |
573 | dev->recv = dw_eth_recv; | |
574 | dev->halt = dw_eth_halt; | |
575 | dev->write_hwaddr = dw_write_hwaddr; | |
576 | ||
577 | eth_register(dev); | |
578 | ||
92a190aa AB |
579 | priv->interface = interface; |
580 | ||
581 | dw_mdio_init(dev->name, priv->mac_regs_p); | |
582 | priv->bus = miiphy_get_dev_by_name(dev->name); | |
583 | ||
64dcd25f | 584 | return dw_phy_init(priv, dev); |
5b1b1883 | 585 | } |
75577ba4 SG |
586 | #endif |
587 | ||
588 | #ifdef CONFIG_DM_ETH | |
589 | static int designware_eth_start(struct udevice *dev) | |
590 | { | |
591 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
f63f28ee SG |
592 | struct dw_eth_dev *priv = dev_get_priv(dev); |
593 | int ret; | |
75577ba4 | 594 | |
e72ced23 | 595 | ret = designware_eth_init(priv, pdata->enetaddr); |
f63f28ee SG |
596 | if (ret) |
597 | return ret; | |
598 | ret = designware_eth_enable(priv); | |
599 | if (ret) | |
600 | return ret; | |
601 | ||
602 | return 0; | |
75577ba4 SG |
603 | } |
604 | ||
e72ced23 | 605 | int designware_eth_send(struct udevice *dev, void *packet, int length) |
75577ba4 SG |
606 | { |
607 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
608 | ||
609 | return _dw_eth_send(priv, packet, length); | |
610 | } | |
611 | ||
e72ced23 | 612 | int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
75577ba4 SG |
613 | { |
614 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
615 | ||
616 | return _dw_eth_recv(priv, packetp); | |
617 | } | |
618 | ||
e72ced23 | 619 | int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) |
75577ba4 SG |
620 | { |
621 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
622 | ||
623 | return _dw_free_pkt(priv); | |
624 | } | |
625 | ||
e72ced23 | 626 | void designware_eth_stop(struct udevice *dev) |
75577ba4 SG |
627 | { |
628 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
629 | ||
630 | return _dw_eth_halt(priv); | |
631 | } | |
632 | ||
e72ced23 | 633 | int designware_eth_write_hwaddr(struct udevice *dev) |
75577ba4 SG |
634 | { |
635 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
636 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
637 | ||
638 | return _dw_write_hwaddr(priv, pdata->enetaddr); | |
639 | } | |
640 | ||
8b7ee66c BM |
641 | static int designware_eth_bind(struct udevice *dev) |
642 | { | |
643 | #ifdef CONFIG_DM_PCI | |
644 | static int num_cards; | |
645 | char name[20]; | |
646 | ||
647 | /* Create a unique device name for PCI type devices */ | |
648 | if (device_is_on_pci_bus(dev)) { | |
649 | sprintf(name, "eth_designware#%u", num_cards++); | |
650 | device_set_name(dev, name); | |
651 | } | |
652 | #endif | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
b9e08d0e | 657 | int designware_eth_probe(struct udevice *dev) |
75577ba4 SG |
658 | { |
659 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
660 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
f0dc73c0 | 661 | u32 iobase = pdata->iobase; |
0e1a3e30 | 662 | ulong ioaddr; |
75577ba4 SG |
663 | int ret; |
664 | ||
6ec922fa JC |
665 | #if defined(CONFIG_DM_REGULATOR) |
666 | struct udevice *phy_supply; | |
667 | ||
668 | ret = device_get_supply_regulator(dev, "phy-supply", | |
669 | &phy_supply); | |
670 | if (ret) { | |
671 | debug("%s: No phy supply\n", dev->name); | |
672 | } else { | |
673 | ret = regulator_set_enable(phy_supply, true); | |
674 | if (ret) { | |
675 | puts("Error enabling phy supply\n"); | |
676 | return ret; | |
677 | } | |
678 | } | |
679 | #endif | |
680 | ||
8b7ee66c BM |
681 | #ifdef CONFIG_DM_PCI |
682 | /* | |
683 | * If we are on PCI bus, either directly attached to a PCI root port, | |
684 | * or via a PCI bridge, fill in platdata before we probe the hardware. | |
685 | */ | |
686 | if (device_is_on_pci_bus(dev)) { | |
8b7ee66c BM |
687 | dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); |
688 | iobase &= PCI_BASE_ADDRESS_MEM_MASK; | |
6758a6cc | 689 | iobase = dm_pci_mem_to_phys(dev, iobase); |
8b7ee66c BM |
690 | |
691 | pdata->iobase = iobase; | |
692 | pdata->phy_interface = PHY_INTERFACE_MODE_RMII; | |
693 | } | |
694 | #endif | |
695 | ||
f0dc73c0 | 696 | debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); |
0e1a3e30 BG |
697 | ioaddr = iobase; |
698 | priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; | |
699 | priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); | |
75577ba4 | 700 | priv->interface = pdata->phy_interface; |
6968ec92 | 701 | priv->max_speed = pdata->max_speed; |
75577ba4 | 702 | |
90b7fc92 | 703 | dw_mdio_init(dev->name, dev); |
75577ba4 SG |
704 | priv->bus = miiphy_get_dev_by_name(dev->name); |
705 | ||
706 | ret = dw_phy_init(priv, dev); | |
707 | debug("%s, ret=%d\n", __func__, ret); | |
708 | ||
709 | return ret; | |
710 | } | |
711 | ||
5d2459fd BM |
712 | static int designware_eth_remove(struct udevice *dev) |
713 | { | |
714 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
715 | ||
716 | free(priv->phydev); | |
717 | mdio_unregister(priv->bus); | |
718 | mdio_free(priv->bus); | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
b9e08d0e | 723 | const struct eth_ops designware_eth_ops = { |
75577ba4 SG |
724 | .start = designware_eth_start, |
725 | .send = designware_eth_send, | |
726 | .recv = designware_eth_recv, | |
727 | .free_pkt = designware_eth_free_pkt, | |
728 | .stop = designware_eth_stop, | |
729 | .write_hwaddr = designware_eth_write_hwaddr, | |
730 | }; | |
731 | ||
b9e08d0e | 732 | int designware_eth_ofdata_to_platdata(struct udevice *dev) |
75577ba4 | 733 | { |
90b7fc92 | 734 | struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); |
66d027e2 | 735 | #ifdef CONFIG_DM_GPIO |
90b7fc92 | 736 | struct dw_eth_dev *priv = dev_get_priv(dev); |
66d027e2 | 737 | #endif |
90b7fc92 | 738 | struct eth_pdata *pdata = &dw_pdata->eth_pdata; |
75577ba4 | 739 | const char *phy_mode; |
6968ec92 | 740 | const fdt32_t *cell; |
66d027e2 | 741 | #ifdef CONFIG_DM_GPIO |
90b7fc92 | 742 | int reset_flags = GPIOD_IS_OUT; |
66d027e2 | 743 | #endif |
90b7fc92 | 744 | int ret = 0; |
75577ba4 | 745 | |
a821c4af | 746 | pdata->iobase = devfdt_get_addr(dev); |
75577ba4 | 747 | pdata->phy_interface = -1; |
e160f7d4 SG |
748 | phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", |
749 | NULL); | |
75577ba4 SG |
750 | if (phy_mode) |
751 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
752 | if (pdata->phy_interface == -1) { | |
753 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
754 | return -EINVAL; | |
755 | } | |
756 | ||
6968ec92 | 757 | pdata->max_speed = 0; |
e160f7d4 | 758 | cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); |
6968ec92 AB |
759 | if (cell) |
760 | pdata->max_speed = fdt32_to_cpu(*cell); | |
761 | ||
66d027e2 | 762 | #ifdef CONFIG_DM_GPIO |
7ad326a9 | 763 | if (dev_read_bool(dev, "snps,reset-active-low")) |
90b7fc92 SS |
764 | reset_flags |= GPIOD_ACTIVE_LOW; |
765 | ||
766 | ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, | |
767 | &priv->reset_gpio, reset_flags); | |
768 | if (ret == 0) { | |
7ad326a9 PT |
769 | ret = dev_read_u32_array(dev, "snps,reset-delays-us", |
770 | dw_pdata->reset_delays, 3); | |
90b7fc92 SS |
771 | } else if (ret == -ENOENT) { |
772 | ret = 0; | |
773 | } | |
66d027e2 | 774 | #endif |
90b7fc92 SS |
775 | |
776 | return ret; | |
75577ba4 SG |
777 | } |
778 | ||
779 | static const struct udevice_id designware_eth_ids[] = { | |
780 | { .compatible = "allwinner,sun7i-a20-gmac" }, | |
b9628595 | 781 | { .compatible = "altr,socfpga-stmmac" }, |
cfe25561 | 782 | { .compatible = "amlogic,meson6-dwmac" }, |
655217d9 | 783 | { .compatible = "amlogic,meson-gx-dwmac" }, |
b20b70fc | 784 | { .compatible = "st,stm32-dwmac" }, |
75577ba4 SG |
785 | { } |
786 | }; | |
787 | ||
9f76f105 | 788 | U_BOOT_DRIVER(eth_designware) = { |
75577ba4 SG |
789 | .name = "eth_designware", |
790 | .id = UCLASS_ETH, | |
791 | .of_match = designware_eth_ids, | |
792 | .ofdata_to_platdata = designware_eth_ofdata_to_platdata, | |
8b7ee66c | 793 | .bind = designware_eth_bind, |
75577ba4 | 794 | .probe = designware_eth_probe, |
5d2459fd | 795 | .remove = designware_eth_remove, |
75577ba4 SG |
796 | .ops = &designware_eth_ops, |
797 | .priv_auto_alloc_size = sizeof(struct dw_eth_dev), | |
90b7fc92 | 798 | .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), |
75577ba4 SG |
799 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
800 | }; | |
8b7ee66c BM |
801 | |
802 | static struct pci_device_id supported[] = { | |
803 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, | |
804 | { } | |
805 | }; | |
806 | ||
807 | U_BOOT_PCI_DEVICE(eth_designware, supported); | |
75577ba4 | 808 | #endif |