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Commit | Line | Data |
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5b1b1883 VK |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5b1b1883 VK |
6 | */ |
7 | ||
8 | /* | |
64dcd25f | 9 | * Designware ethernet IP driver for U-Boot |
5b1b1883 VK |
10 | */ |
11 | ||
12 | #include <common.h> | |
ba1f9667 | 13 | #include <clk.h> |
75577ba4 | 14 | #include <dm.h> |
64dcd25f | 15 | #include <errno.h> |
5b1b1883 VK |
16 | #include <miiphy.h> |
17 | #include <malloc.h> | |
8b7ee66c | 18 | #include <pci.h> |
ef76025a | 19 | #include <linux/compiler.h> |
5b1b1883 | 20 | #include <linux/err.h> |
7a9ca9db | 21 | #include <linux/kernel.h> |
5b1b1883 | 22 | #include <asm/io.h> |
6ec922fa | 23 | #include <power/regulator.h> |
5b1b1883 VK |
24 | #include "designware.h" |
25 | ||
75577ba4 SG |
26 | DECLARE_GLOBAL_DATA_PTR; |
27 | ||
92a190aa AB |
28 | static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
29 | { | |
90b7fc92 SS |
30 | #ifdef CONFIG_DM_ETH |
31 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); | |
32 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
33 | #else | |
92a190aa | 34 | struct eth_mac_regs *mac_p = bus->priv; |
90b7fc92 | 35 | #endif |
92a190aa AB |
36 | ulong start; |
37 | u16 miiaddr; | |
38 | int timeout = CONFIG_MDIO_TIMEOUT; | |
39 | ||
40 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | | |
41 | ((reg << MIIREGSHIFT) & MII_REGMSK); | |
42 | ||
43 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); | |
44 | ||
45 | start = get_timer(0); | |
46 | while (get_timer(start) < timeout) { | |
47 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) | |
48 | return readl(&mac_p->miidata); | |
49 | udelay(10); | |
50 | }; | |
51 | ||
64dcd25f | 52 | return -ETIMEDOUT; |
92a190aa AB |
53 | } |
54 | ||
55 | static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, | |
56 | u16 val) | |
57 | { | |
90b7fc92 SS |
58 | #ifdef CONFIG_DM_ETH |
59 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); | |
60 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
61 | #else | |
92a190aa | 62 | struct eth_mac_regs *mac_p = bus->priv; |
90b7fc92 | 63 | #endif |
92a190aa AB |
64 | ulong start; |
65 | u16 miiaddr; | |
64dcd25f | 66 | int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; |
92a190aa AB |
67 | |
68 | writel(val, &mac_p->miidata); | |
69 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | | |
70 | ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; | |
71 | ||
72 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); | |
73 | ||
74 | start = get_timer(0); | |
75 | while (get_timer(start) < timeout) { | |
76 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { | |
77 | ret = 0; | |
78 | break; | |
79 | } | |
80 | udelay(10); | |
81 | }; | |
82 | ||
83 | return ret; | |
84 | } | |
85 | ||
66d027e2 | 86 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) |
90b7fc92 SS |
87 | static int dw_mdio_reset(struct mii_dev *bus) |
88 | { | |
89 | struct udevice *dev = bus->priv; | |
90 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
91 | struct dw_eth_pdata *pdata = dev_get_platdata(dev); | |
92 | int ret; | |
93 | ||
94 | if (!dm_gpio_is_valid(&priv->reset_gpio)) | |
95 | return 0; | |
96 | ||
97 | /* reset the phy */ | |
98 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); | |
99 | if (ret) | |
100 | return ret; | |
101 | ||
102 | udelay(pdata->reset_delays[0]); | |
103 | ||
104 | ret = dm_gpio_set_value(&priv->reset_gpio, 1); | |
105 | if (ret) | |
106 | return ret; | |
107 | ||
108 | udelay(pdata->reset_delays[1]); | |
109 | ||
110 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); | |
111 | if (ret) | |
112 | return ret; | |
113 | ||
114 | udelay(pdata->reset_delays[2]); | |
115 | ||
116 | return 0; | |
117 | } | |
118 | #endif | |
119 | ||
120 | static int dw_mdio_init(const char *name, void *priv) | |
92a190aa AB |
121 | { |
122 | struct mii_dev *bus = mdio_alloc(); | |
123 | ||
124 | if (!bus) { | |
125 | printf("Failed to allocate MDIO bus\n"); | |
64dcd25f | 126 | return -ENOMEM; |
92a190aa AB |
127 | } |
128 | ||
129 | bus->read = dw_mdio_read; | |
130 | bus->write = dw_mdio_write; | |
192bc694 | 131 | snprintf(bus->name, sizeof(bus->name), "%s", name); |
66d027e2 | 132 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) |
90b7fc92 SS |
133 | bus->reset = dw_mdio_reset; |
134 | #endif | |
92a190aa | 135 | |
90b7fc92 | 136 | bus->priv = priv; |
92a190aa AB |
137 | |
138 | return mdio_register(bus); | |
139 | } | |
13edd170 | 140 | |
64dcd25f | 141 | static void tx_descs_init(struct dw_eth_dev *priv) |
5b1b1883 | 142 | { |
5b1b1883 VK |
143 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
144 | struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; | |
145 | char *txbuffs = &priv->txbuffs[0]; | |
146 | struct dmamacdescr *desc_p; | |
147 | u32 idx; | |
148 | ||
149 | for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { | |
150 | desc_p = &desc_table_p[idx]; | |
0e1a3e30 BG |
151 | desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; |
152 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; | |
5b1b1883 VK |
153 | |
154 | #if defined(CONFIG_DW_ALTDESCRIPTOR) | |
155 | desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | | |
2b261092 MV |
156 | DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | |
157 | DESC_TXSTS_TXCHECKINSCTRL | | |
5b1b1883 VK |
158 | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); |
159 | ||
160 | desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; | |
161 | desc_p->dmamac_cntl = 0; | |
162 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); | |
163 | #else | |
164 | desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; | |
165 | desc_p->txrx_status = 0; | |
166 | #endif | |
167 | } | |
168 | ||
169 | /* Correcting the last pointer of the chain */ | |
0e1a3e30 | 170 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
5b1b1883 | 171 | |
50b0df81 | 172 | /* Flush all Tx buffer descriptors at once */ |
0e1a3e30 BG |
173 | flush_dcache_range((ulong)priv->tx_mac_descrtable, |
174 | (ulong)priv->tx_mac_descrtable + | |
50b0df81 AB |
175 | sizeof(priv->tx_mac_descrtable)); |
176 | ||
5b1b1883 | 177 | writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); |
74cb708d | 178 | priv->tx_currdescnum = 0; |
5b1b1883 VK |
179 | } |
180 | ||
64dcd25f | 181 | static void rx_descs_init(struct dw_eth_dev *priv) |
5b1b1883 | 182 | { |
5b1b1883 VK |
183 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
184 | struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; | |
185 | char *rxbuffs = &priv->rxbuffs[0]; | |
186 | struct dmamacdescr *desc_p; | |
187 | u32 idx; | |
188 | ||
50b0df81 AB |
189 | /* Before passing buffers to GMAC we need to make sure zeros |
190 | * written there right after "priv" structure allocation were | |
191 | * flushed into RAM. | |
192 | * Otherwise there's a chance to get some of them flushed in RAM when | |
193 | * GMAC is already pushing data to RAM via DMA. This way incoming from | |
194 | * GMAC data will be corrupted. */ | |
0e1a3e30 | 195 | flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); |
50b0df81 | 196 | |
5b1b1883 VK |
197 | for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { |
198 | desc_p = &desc_table_p[idx]; | |
0e1a3e30 BG |
199 | desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; |
200 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; | |
5b1b1883 VK |
201 | |
202 | desc_p->dmamac_cntl = | |
2b261092 | 203 | (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | |
5b1b1883 VK |
204 | DESC_RXCTRL_RXCHAIN; |
205 | ||
206 | desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; | |
207 | } | |
208 | ||
209 | /* Correcting the last pointer of the chain */ | |
0e1a3e30 | 210 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
5b1b1883 | 211 | |
50b0df81 | 212 | /* Flush all Rx buffer descriptors at once */ |
0e1a3e30 BG |
213 | flush_dcache_range((ulong)priv->rx_mac_descrtable, |
214 | (ulong)priv->rx_mac_descrtable + | |
50b0df81 AB |
215 | sizeof(priv->rx_mac_descrtable)); |
216 | ||
5b1b1883 | 217 | writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); |
74cb708d | 218 | priv->rx_currdescnum = 0; |
5b1b1883 VK |
219 | } |
220 | ||
64dcd25f | 221 | static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) |
5b1b1883 | 222 | { |
92a190aa AB |
223 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
224 | u32 macid_lo, macid_hi; | |
92a190aa AB |
225 | |
226 | macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + | |
227 | (mac_id[3] << 24); | |
228 | macid_hi = mac_id[4] + (mac_id[5] << 8); | |
229 | ||
230 | writel(macid_hi, &mac_p->macaddr0hi); | |
231 | writel(macid_lo, &mac_p->macaddr0lo); | |
232 | ||
233 | return 0; | |
5b1b1883 VK |
234 | } |
235 | ||
0ea38db9 SG |
236 | static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, |
237 | struct phy_device *phydev) | |
5b1b1883 | 238 | { |
92a190aa | 239 | u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; |
5b1b1883 | 240 | |
92a190aa AB |
241 | if (!phydev->link) { |
242 | printf("%s: No link.\n", phydev->dev->name); | |
0ea38db9 | 243 | return 0; |
92a190aa | 244 | } |
5b1b1883 | 245 | |
92a190aa AB |
246 | if (phydev->speed != 1000) |
247 | conf |= MII_PORTSELECT; | |
b884c3fe AB |
248 | else |
249 | conf &= ~MII_PORTSELECT; | |
7091915a | 250 | |
92a190aa AB |
251 | if (phydev->speed == 100) |
252 | conf |= FES_100; | |
5b1b1883 | 253 | |
92a190aa AB |
254 | if (phydev->duplex) |
255 | conf |= FULLDPLXMODE; | |
cafabe19 | 256 | |
92a190aa | 257 | writel(conf, &mac_p->conf); |
5b1b1883 | 258 | |
92a190aa AB |
259 | printf("Speed: %d, %s duplex%s\n", phydev->speed, |
260 | (phydev->duplex) ? "full" : "half", | |
261 | (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); | |
0ea38db9 SG |
262 | |
263 | return 0; | |
5b1b1883 VK |
264 | } |
265 | ||
64dcd25f | 266 | static void _dw_eth_halt(struct dw_eth_dev *priv) |
5b1b1883 | 267 | { |
5b1b1883 | 268 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
92a190aa | 269 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
5b1b1883 | 270 | |
92a190aa AB |
271 | writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); |
272 | writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); | |
5b1b1883 | 273 | |
92a190aa | 274 | phy_shutdown(priv->phydev); |
5b1b1883 VK |
275 | } |
276 | ||
e72ced23 | 277 | int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) |
5b1b1883 | 278 | { |
5b1b1883 VK |
279 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
280 | struct eth_dma_regs *dma_p = priv->dma_regs_p; | |
92a190aa | 281 | unsigned int start; |
64dcd25f | 282 | int ret; |
5b1b1883 | 283 | |
92a190aa | 284 | writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); |
13edd170 | 285 | |
92a190aa AB |
286 | start = get_timer(0); |
287 | while (readl(&dma_p->busmode) & DMAMAC_SRST) { | |
875143f3 AB |
288 | if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { |
289 | printf("DMA reset timeout\n"); | |
64dcd25f | 290 | return -ETIMEDOUT; |
875143f3 | 291 | } |
ef76025a | 292 | |
92a190aa AB |
293 | mdelay(100); |
294 | }; | |
5b1b1883 | 295 | |
f3edfd30 BM |
296 | /* |
297 | * Soft reset above clears HW address registers. | |
298 | * So we have to set it here once again. | |
299 | */ | |
300 | _dw_write_hwaddr(priv, enetaddr); | |
301 | ||
64dcd25f SG |
302 | rx_descs_init(priv); |
303 | tx_descs_init(priv); | |
5b1b1883 | 304 | |
49692c5f | 305 | writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); |
5b1b1883 | 306 | |
d2279221 | 307 | #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE |
92a190aa AB |
308 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, |
309 | &dma_p->opmode); | |
d2279221 SZ |
310 | #else |
311 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO, | |
312 | &dma_p->opmode); | |
313 | #endif | |
5b1b1883 | 314 | |
92a190aa | 315 | writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); |
9afc1af0 | 316 | |
2ddaf13b SZ |
317 | #ifdef CONFIG_DW_AXI_BURST_LEN |
318 | writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); | |
319 | #endif | |
320 | ||
92a190aa | 321 | /* Start up the PHY */ |
64dcd25f SG |
322 | ret = phy_startup(priv->phydev); |
323 | if (ret) { | |
92a190aa AB |
324 | printf("Could not initialize PHY %s\n", |
325 | priv->phydev->dev->name); | |
64dcd25f | 326 | return ret; |
9afc1af0 VK |
327 | } |
328 | ||
0ea38db9 SG |
329 | ret = dw_adjust_link(priv, mac_p, priv->phydev); |
330 | if (ret) | |
331 | return ret; | |
5b1b1883 | 332 | |
f63f28ee SG |
333 | return 0; |
334 | } | |
335 | ||
e72ced23 | 336 | int designware_eth_enable(struct dw_eth_dev *priv) |
f63f28ee SG |
337 | { |
338 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
339 | ||
92a190aa | 340 | if (!priv->phydev->link) |
64dcd25f | 341 | return -EIO; |
5b1b1883 | 342 | |
aa51005c | 343 | writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); |
5b1b1883 VK |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
7a9ca9db FF |
348 | #define ETH_ZLEN 60 |
349 | ||
64dcd25f | 350 | static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) |
5b1b1883 | 351 | { |
5b1b1883 VK |
352 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
353 | u32 desc_num = priv->tx_currdescnum; | |
354 | struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; | |
0e1a3e30 BG |
355 | ulong desc_start = (ulong)desc_p; |
356 | ulong desc_end = desc_start + | |
96cec17d | 357 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
0e1a3e30 BG |
358 | ulong data_start = desc_p->dmamac_addr; |
359 | ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); | |
964ea7c1 IC |
360 | /* |
361 | * Strictly we only need to invalidate the "txrx_status" field | |
362 | * for the following check, but on some platforms we cannot | |
96cec17d MV |
363 | * invalidate only 4 bytes, so we flush the entire descriptor, |
364 | * which is 16 bytes in total. This is safe because the | |
365 | * individual descriptors in the array are each aligned to | |
366 | * ARCH_DMA_MINALIGN and padded appropriately. | |
964ea7c1 | 367 | */ |
96cec17d | 368 | invalidate_dcache_range(desc_start, desc_end); |
50b0df81 | 369 | |
5b1b1883 VK |
370 | /* Check if the descriptor is owned by CPU */ |
371 | if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { | |
372 | printf("CPU not owner of tx frame\n"); | |
64dcd25f | 373 | return -EPERM; |
5b1b1883 VK |
374 | } |
375 | ||
7a9ca9db FF |
376 | length = max(length, ETH_ZLEN); |
377 | ||
0e1a3e30 | 378 | memcpy((void *)data_start, packet, length); |
5b1b1883 | 379 | |
50b0df81 | 380 | /* Flush data to be sent */ |
96cec17d | 381 | flush_dcache_range(data_start, data_end); |
50b0df81 | 382 | |
5b1b1883 VK |
383 | #if defined(CONFIG_DW_ALTDESCRIPTOR) |
384 | desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; | |
2b261092 | 385 | desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & |
5b1b1883 VK |
386 | DESC_TXCTRL_SIZE1MASK; |
387 | ||
388 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK); | |
389 | desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; | |
390 | #else | |
2b261092 MV |
391 | desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & |
392 | DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | | |
5b1b1883 VK |
393 | DESC_TXCTRL_TXFIRST; |
394 | ||
395 | desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; | |
396 | #endif | |
397 | ||
50b0df81 | 398 | /* Flush modified buffer descriptor */ |
96cec17d | 399 | flush_dcache_range(desc_start, desc_end); |
50b0df81 | 400 | |
5b1b1883 VK |
401 | /* Test the wrap-around condition. */ |
402 | if (++desc_num >= CONFIG_TX_DESCR_NUM) | |
403 | desc_num = 0; | |
404 | ||
405 | priv->tx_currdescnum = desc_num; | |
406 | ||
407 | /* Start the transmission */ | |
408 | writel(POLL_DATA, &dma_p->txpolldemand); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
75577ba4 | 413 | static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) |
5b1b1883 | 414 | { |
50b0df81 | 415 | u32 status, desc_num = priv->rx_currdescnum; |
5b1b1883 | 416 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; |
75577ba4 | 417 | int length = -EAGAIN; |
0e1a3e30 BG |
418 | ulong desc_start = (ulong)desc_p; |
419 | ulong desc_end = desc_start + | |
96cec17d | 420 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
0e1a3e30 BG |
421 | ulong data_start = desc_p->dmamac_addr; |
422 | ulong data_end; | |
5b1b1883 | 423 | |
50b0df81 | 424 | /* Invalidate entire buffer descriptor */ |
96cec17d | 425 | invalidate_dcache_range(desc_start, desc_end); |
50b0df81 AB |
426 | |
427 | status = desc_p->txrx_status; | |
428 | ||
5b1b1883 VK |
429 | /* Check if the owner is the CPU */ |
430 | if (!(status & DESC_RXSTS_OWNBYDMA)) { | |
431 | ||
2b261092 | 432 | length = (status & DESC_RXSTS_FRMLENMSK) >> |
5b1b1883 VK |
433 | DESC_RXSTS_FRMLENSHFT; |
434 | ||
50b0df81 | 435 | /* Invalidate received data */ |
96cec17d MV |
436 | data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); |
437 | invalidate_dcache_range(data_start, data_end); | |
0e1a3e30 | 438 | *packetp = (uchar *)(ulong)desc_p->dmamac_addr; |
75577ba4 | 439 | } |
50b0df81 | 440 | |
75577ba4 SG |
441 | return length; |
442 | } | |
5b1b1883 | 443 | |
75577ba4 SG |
444 | static int _dw_free_pkt(struct dw_eth_dev *priv) |
445 | { | |
446 | u32 desc_num = priv->rx_currdescnum; | |
447 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; | |
0e1a3e30 BG |
448 | ulong desc_start = (ulong)desc_p; |
449 | ulong desc_end = desc_start + | |
75577ba4 | 450 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
5b1b1883 | 451 | |
75577ba4 SG |
452 | /* |
453 | * Make the current descriptor valid again and go to | |
454 | * the next one | |
455 | */ | |
456 | desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; | |
50b0df81 | 457 | |
75577ba4 SG |
458 | /* Flush only status field - others weren't changed */ |
459 | flush_dcache_range(desc_start, desc_end); | |
5b1b1883 | 460 | |
75577ba4 SG |
461 | /* Test the wrap-around condition. */ |
462 | if (++desc_num >= CONFIG_RX_DESCR_NUM) | |
463 | desc_num = 0; | |
5b1b1883 VK |
464 | priv->rx_currdescnum = desc_num; |
465 | ||
75577ba4 | 466 | return 0; |
5b1b1883 VK |
467 | } |
468 | ||
64dcd25f | 469 | static int dw_phy_init(struct dw_eth_dev *priv, void *dev) |
5b1b1883 | 470 | { |
92a190aa | 471 | struct phy_device *phydev; |
6968ec92 | 472 | int mask = 0xffffffff, ret; |
cafabe19 | 473 | |
92a190aa AB |
474 | #ifdef CONFIG_PHY_ADDR |
475 | mask = 1 << CONFIG_PHY_ADDR; | |
5b1b1883 VK |
476 | #endif |
477 | ||
92a190aa AB |
478 | phydev = phy_find_by_mask(priv->bus, mask, priv->interface); |
479 | if (!phydev) | |
64dcd25f | 480 | return -ENODEV; |
5b1b1883 | 481 | |
15e82e53 IC |
482 | phy_connect_dev(phydev, dev); |
483 | ||
92a190aa | 484 | phydev->supported &= PHY_GBIT_FEATURES; |
6968ec92 AB |
485 | if (priv->max_speed) { |
486 | ret = phy_set_supported(phydev, priv->max_speed); | |
487 | if (ret) | |
488 | return ret; | |
489 | } | |
92a190aa | 490 | phydev->advertising = phydev->supported; |
5b1b1883 | 491 | |
92a190aa AB |
492 | priv->phydev = phydev; |
493 | phy_config(phydev); | |
ef76025a | 494 | |
64dcd25f SG |
495 | return 0; |
496 | } | |
497 | ||
75577ba4 | 498 | #ifndef CONFIG_DM_ETH |
64dcd25f SG |
499 | static int dw_eth_init(struct eth_device *dev, bd_t *bis) |
500 | { | |
f63f28ee SG |
501 | int ret; |
502 | ||
e72ced23 | 503 | ret = designware_eth_init(dev->priv, dev->enetaddr); |
f63f28ee SG |
504 | if (!ret) |
505 | ret = designware_eth_enable(dev->priv); | |
506 | ||
507 | return ret; | |
64dcd25f SG |
508 | } |
509 | ||
510 | static int dw_eth_send(struct eth_device *dev, void *packet, int length) | |
511 | { | |
512 | return _dw_eth_send(dev->priv, packet, length); | |
513 | } | |
514 | ||
515 | static int dw_eth_recv(struct eth_device *dev) | |
516 | { | |
75577ba4 SG |
517 | uchar *packet; |
518 | int length; | |
519 | ||
520 | length = _dw_eth_recv(dev->priv, &packet); | |
521 | if (length == -EAGAIN) | |
522 | return 0; | |
523 | net_process_received_packet(packet, length); | |
524 | ||
525 | _dw_free_pkt(dev->priv); | |
526 | ||
527 | return 0; | |
64dcd25f SG |
528 | } |
529 | ||
530 | static void dw_eth_halt(struct eth_device *dev) | |
531 | { | |
532 | return _dw_eth_halt(dev->priv); | |
533 | } | |
534 | ||
535 | static int dw_write_hwaddr(struct eth_device *dev) | |
536 | { | |
537 | return _dw_write_hwaddr(dev->priv, dev->enetaddr); | |
5b1b1883 | 538 | } |
5b1b1883 | 539 | |
92a190aa | 540 | int designware_initialize(ulong base_addr, u32 interface) |
5b1b1883 VK |
541 | { |
542 | struct eth_device *dev; | |
543 | struct dw_eth_dev *priv; | |
544 | ||
545 | dev = (struct eth_device *) malloc(sizeof(struct eth_device)); | |
546 | if (!dev) | |
547 | return -ENOMEM; | |
548 | ||
549 | /* | |
550 | * Since the priv structure contains the descriptors which need a strict | |
551 | * buswidth alignment, memalign is used to allocate memory | |
552 | */ | |
1c848a25 IC |
553 | priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, |
554 | sizeof(struct dw_eth_dev)); | |
5b1b1883 VK |
555 | if (!priv) { |
556 | free(dev); | |
557 | return -ENOMEM; | |
558 | } | |
559 | ||
0e1a3e30 BG |
560 | if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { |
561 | printf("designware: buffers are outside DMA memory\n"); | |
562 | return -EINVAL; | |
563 | } | |
564 | ||
5b1b1883 VK |
565 | memset(dev, 0, sizeof(struct eth_device)); |
566 | memset(priv, 0, sizeof(struct dw_eth_dev)); | |
567 | ||
92a190aa | 568 | sprintf(dev->name, "dwmac.%lx", base_addr); |
5b1b1883 VK |
569 | dev->iobase = (int)base_addr; |
570 | dev->priv = priv; | |
571 | ||
5b1b1883 VK |
572 | priv->dev = dev; |
573 | priv->mac_regs_p = (struct eth_mac_regs *)base_addr; | |
574 | priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + | |
575 | DW_DMA_BASE_OFFSET); | |
5b1b1883 | 576 | |
5b1b1883 VK |
577 | dev->init = dw_eth_init; |
578 | dev->send = dw_eth_send; | |
579 | dev->recv = dw_eth_recv; | |
580 | dev->halt = dw_eth_halt; | |
581 | dev->write_hwaddr = dw_write_hwaddr; | |
582 | ||
583 | eth_register(dev); | |
584 | ||
92a190aa AB |
585 | priv->interface = interface; |
586 | ||
587 | dw_mdio_init(dev->name, priv->mac_regs_p); | |
588 | priv->bus = miiphy_get_dev_by_name(dev->name); | |
589 | ||
64dcd25f | 590 | return dw_phy_init(priv, dev); |
5b1b1883 | 591 | } |
75577ba4 SG |
592 | #endif |
593 | ||
594 | #ifdef CONFIG_DM_ETH | |
595 | static int designware_eth_start(struct udevice *dev) | |
596 | { | |
597 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
f63f28ee SG |
598 | struct dw_eth_dev *priv = dev_get_priv(dev); |
599 | int ret; | |
75577ba4 | 600 | |
e72ced23 | 601 | ret = designware_eth_init(priv, pdata->enetaddr); |
f63f28ee SG |
602 | if (ret) |
603 | return ret; | |
604 | ret = designware_eth_enable(priv); | |
605 | if (ret) | |
606 | return ret; | |
607 | ||
608 | return 0; | |
75577ba4 SG |
609 | } |
610 | ||
e72ced23 | 611 | int designware_eth_send(struct udevice *dev, void *packet, int length) |
75577ba4 SG |
612 | { |
613 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
614 | ||
615 | return _dw_eth_send(priv, packet, length); | |
616 | } | |
617 | ||
e72ced23 | 618 | int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
75577ba4 SG |
619 | { |
620 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
621 | ||
622 | return _dw_eth_recv(priv, packetp); | |
623 | } | |
624 | ||
e72ced23 | 625 | int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) |
75577ba4 SG |
626 | { |
627 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
628 | ||
629 | return _dw_free_pkt(priv); | |
630 | } | |
631 | ||
e72ced23 | 632 | void designware_eth_stop(struct udevice *dev) |
75577ba4 SG |
633 | { |
634 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
635 | ||
636 | return _dw_eth_halt(priv); | |
637 | } | |
638 | ||
e72ced23 | 639 | int designware_eth_write_hwaddr(struct udevice *dev) |
75577ba4 SG |
640 | { |
641 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
642 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
643 | ||
644 | return _dw_write_hwaddr(priv, pdata->enetaddr); | |
645 | } | |
646 | ||
8b7ee66c BM |
647 | static int designware_eth_bind(struct udevice *dev) |
648 | { | |
649 | #ifdef CONFIG_DM_PCI | |
650 | static int num_cards; | |
651 | char name[20]; | |
652 | ||
653 | /* Create a unique device name for PCI type devices */ | |
654 | if (device_is_on_pci_bus(dev)) { | |
655 | sprintf(name, "eth_designware#%u", num_cards++); | |
656 | device_set_name(dev, name); | |
657 | } | |
658 | #endif | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
b9e08d0e | 663 | int designware_eth_probe(struct udevice *dev) |
75577ba4 SG |
664 | { |
665 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
666 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
f0dc73c0 | 667 | u32 iobase = pdata->iobase; |
0e1a3e30 | 668 | ulong ioaddr; |
75577ba4 | 669 | int ret; |
ba1f9667 PC |
670 | #ifdef CONFIG_CLK |
671 | int i, err, clock_nb; | |
672 | ||
673 | priv->clock_count = 0; | |
674 | clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); | |
675 | if (clock_nb > 0) { | |
676 | priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), | |
677 | GFP_KERNEL); | |
678 | if (!priv->clocks) | |
679 | return -ENOMEM; | |
680 | ||
681 | for (i = 0; i < clock_nb; i++) { | |
682 | err = clk_get_by_index(dev, i, &priv->clocks[i]); | |
683 | if (err < 0) | |
684 | break; | |
685 | ||
686 | err = clk_enable(&priv->clocks[i]); | |
687 | if (err) { | |
688 | pr_err("failed to enable clock %d\n", i); | |
689 | clk_free(&priv->clocks[i]); | |
690 | goto clk_err; | |
691 | } | |
692 | priv->clock_count++; | |
693 | } | |
694 | } else if (clock_nb != -ENOENT) { | |
695 | pr_err("failed to get clock phandle(%d)\n", clock_nb); | |
696 | return clock_nb; | |
697 | } | |
698 | #endif | |
75577ba4 | 699 | |
6ec922fa JC |
700 | #if defined(CONFIG_DM_REGULATOR) |
701 | struct udevice *phy_supply; | |
702 | ||
703 | ret = device_get_supply_regulator(dev, "phy-supply", | |
704 | &phy_supply); | |
705 | if (ret) { | |
706 | debug("%s: No phy supply\n", dev->name); | |
707 | } else { | |
708 | ret = regulator_set_enable(phy_supply, true); | |
709 | if (ret) { | |
710 | puts("Error enabling phy supply\n"); | |
711 | return ret; | |
712 | } | |
713 | } | |
714 | #endif | |
715 | ||
8b7ee66c BM |
716 | #ifdef CONFIG_DM_PCI |
717 | /* | |
718 | * If we are on PCI bus, either directly attached to a PCI root port, | |
719 | * or via a PCI bridge, fill in platdata before we probe the hardware. | |
720 | */ | |
721 | if (device_is_on_pci_bus(dev)) { | |
8b7ee66c BM |
722 | dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); |
723 | iobase &= PCI_BASE_ADDRESS_MEM_MASK; | |
6758a6cc | 724 | iobase = dm_pci_mem_to_phys(dev, iobase); |
8b7ee66c BM |
725 | |
726 | pdata->iobase = iobase; | |
727 | pdata->phy_interface = PHY_INTERFACE_MODE_RMII; | |
728 | } | |
729 | #endif | |
730 | ||
f0dc73c0 | 731 | debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); |
0e1a3e30 BG |
732 | ioaddr = iobase; |
733 | priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; | |
734 | priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); | |
75577ba4 | 735 | priv->interface = pdata->phy_interface; |
6968ec92 | 736 | priv->max_speed = pdata->max_speed; |
75577ba4 | 737 | |
90b7fc92 | 738 | dw_mdio_init(dev->name, dev); |
75577ba4 SG |
739 | priv->bus = miiphy_get_dev_by_name(dev->name); |
740 | ||
741 | ret = dw_phy_init(priv, dev); | |
742 | debug("%s, ret=%d\n", __func__, ret); | |
743 | ||
744 | return ret; | |
ba1f9667 PC |
745 | |
746 | #ifdef CONFIG_CLK | |
747 | clk_err: | |
748 | ret = clk_release_all(priv->clocks, priv->clock_count); | |
749 | if (ret) | |
750 | pr_err("failed to disable all clocks\n"); | |
751 | ||
752 | return err; | |
753 | #endif | |
75577ba4 SG |
754 | } |
755 | ||
5d2459fd BM |
756 | static int designware_eth_remove(struct udevice *dev) |
757 | { | |
758 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
759 | ||
760 | free(priv->phydev); | |
761 | mdio_unregister(priv->bus); | |
762 | mdio_free(priv->bus); | |
763 | ||
ba1f9667 PC |
764 | #ifdef CONFIG_CLK |
765 | return clk_release_all(priv->clocks, priv->clock_count); | |
766 | #else | |
5d2459fd | 767 | return 0; |
ba1f9667 | 768 | #endif |
5d2459fd BM |
769 | } |
770 | ||
b9e08d0e | 771 | const struct eth_ops designware_eth_ops = { |
75577ba4 SG |
772 | .start = designware_eth_start, |
773 | .send = designware_eth_send, | |
774 | .recv = designware_eth_recv, | |
775 | .free_pkt = designware_eth_free_pkt, | |
776 | .stop = designware_eth_stop, | |
777 | .write_hwaddr = designware_eth_write_hwaddr, | |
778 | }; | |
779 | ||
b9e08d0e | 780 | int designware_eth_ofdata_to_platdata(struct udevice *dev) |
75577ba4 | 781 | { |
90b7fc92 | 782 | struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); |
66d027e2 | 783 | #ifdef CONFIG_DM_GPIO |
90b7fc92 | 784 | struct dw_eth_dev *priv = dev_get_priv(dev); |
66d027e2 | 785 | #endif |
90b7fc92 | 786 | struct eth_pdata *pdata = &dw_pdata->eth_pdata; |
75577ba4 | 787 | const char *phy_mode; |
66d027e2 | 788 | #ifdef CONFIG_DM_GPIO |
90b7fc92 | 789 | int reset_flags = GPIOD_IS_OUT; |
66d027e2 | 790 | #endif |
90b7fc92 | 791 | int ret = 0; |
75577ba4 | 792 | |
15050f1c | 793 | pdata->iobase = dev_read_addr(dev); |
75577ba4 | 794 | pdata->phy_interface = -1; |
15050f1c | 795 | phy_mode = dev_read_string(dev, "phy-mode"); |
75577ba4 SG |
796 | if (phy_mode) |
797 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
798 | if (pdata->phy_interface == -1) { | |
799 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
800 | return -EINVAL; | |
801 | } | |
802 | ||
15050f1c | 803 | pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); |
6968ec92 | 804 | |
66d027e2 | 805 | #ifdef CONFIG_DM_GPIO |
7ad326a9 | 806 | if (dev_read_bool(dev, "snps,reset-active-low")) |
90b7fc92 SS |
807 | reset_flags |= GPIOD_ACTIVE_LOW; |
808 | ||
809 | ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, | |
810 | &priv->reset_gpio, reset_flags); | |
811 | if (ret == 0) { | |
7ad326a9 PT |
812 | ret = dev_read_u32_array(dev, "snps,reset-delays-us", |
813 | dw_pdata->reset_delays, 3); | |
90b7fc92 SS |
814 | } else if (ret == -ENOENT) { |
815 | ret = 0; | |
816 | } | |
66d027e2 | 817 | #endif |
90b7fc92 SS |
818 | |
819 | return ret; | |
75577ba4 SG |
820 | } |
821 | ||
822 | static const struct udevice_id designware_eth_ids[] = { | |
823 | { .compatible = "allwinner,sun7i-a20-gmac" }, | |
b9628595 | 824 | { .compatible = "altr,socfpga-stmmac" }, |
cfe25561 | 825 | { .compatible = "amlogic,meson6-dwmac" }, |
655217d9 | 826 | { .compatible = "amlogic,meson-gx-dwmac" }, |
b20b70fc | 827 | { .compatible = "st,stm32-dwmac" }, |
75577ba4 SG |
828 | { } |
829 | }; | |
830 | ||
9f76f105 | 831 | U_BOOT_DRIVER(eth_designware) = { |
75577ba4 SG |
832 | .name = "eth_designware", |
833 | .id = UCLASS_ETH, | |
834 | .of_match = designware_eth_ids, | |
835 | .ofdata_to_platdata = designware_eth_ofdata_to_platdata, | |
8b7ee66c | 836 | .bind = designware_eth_bind, |
75577ba4 | 837 | .probe = designware_eth_probe, |
5d2459fd | 838 | .remove = designware_eth_remove, |
75577ba4 SG |
839 | .ops = &designware_eth_ops, |
840 | .priv_auto_alloc_size = sizeof(struct dw_eth_dev), | |
90b7fc92 | 841 | .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), |
75577ba4 SG |
842 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
843 | }; | |
8b7ee66c BM |
844 | |
845 | static struct pci_device_id supported[] = { | |
846 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, | |
847 | { } | |
848 | }; | |
849 | ||
850 | U_BOOT_PCI_DEVICE(eth_designware, supported); | |
75577ba4 | 851 | #endif |