[people/ms/u-boot.git] / drivers / net / designware.c

/*
 * (C) Copyright 2010
 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Designware ethernet IP driver for u-boot
 */

#include <common.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/compiler.h>
#include <linux/err.h>
#include <asm/io.h>
#include "designware.h"

static int configure_phy(struct eth_device *dev);

static void tx_descs_init(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
	char *txbuffs = &priv->txbuffs[0];
	struct dmamacdescr *desc_p;
	u32 idx;

	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
		desc_p = &desc_table_p[idx];
		desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
		desc_p->dmamac_next = &desc_table_p[idx + 1];

#if defined(CONFIG_DW_ALTDESCRIPTOR)
		desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
				DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
				DESC_TXSTS_TXCHECKINSCTRL | \
				DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);

		desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
		desc_p->dmamac_cntl = 0;
		desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
#else
		desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
		desc_p->txrx_status = 0;
#endif
	}

	/* Correcting the last pointer of the chain */
	desc_p->dmamac_next = &desc_table_p[0];

	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
}

static void rx_descs_init(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
	char *rxbuffs = &priv->rxbuffs[0];
	struct dmamacdescr *desc_p;
	u32 idx;

	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
		desc_p = &desc_table_p[idx];
		desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
		desc_p->dmamac_next = &desc_table_p[idx + 1];

		desc_p->dmamac_cntl =
			(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
				      DESC_RXCTRL_RXCHAIN;

		desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
	}

	/* Correcting the last pointer of the chain */
	desc_p->dmamac_next = &desc_table_p[0];

	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
}

static void descs_init(struct eth_device *dev)
{
	tx_descs_init(dev);
	rx_descs_init(dev);
}

static int mac_reset(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;

	ulong start;
	int timeout = CONFIG_MACRESET_TIMEOUT;

	writel(DMAMAC_SRST, &dma_p->busmode);
	writel(MII_PORTSELECT, &mac_p->conf);

	start = get_timer(0);
	while (get_timer(start) < timeout) {
		if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
			return 0;

		/* Try again after 10usec */
		udelay(10);
	};

	return -1;
}

static int dw_write_hwaddr(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	u32 macid_lo, macid_hi;
	u8 *mac_id = &dev->enetaddr[0];

	macid_lo = mac_id[0] + (mac_id[1] << 8) + \
		   (mac_id[2] << 16) + (mac_id[3] << 24);
	macid_hi = mac_id[4] + (mac_id[5] << 8);

	writel(macid_hi, &mac_p->macaddr0hi);
	writel(macid_lo, &mac_p->macaddr0lo);

	return 0;
}

static int dw_eth_init(struct eth_device *dev, bd_t *bis)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	u32 conf;

	if (priv->phy_configured != 1)
		configure_phy(dev);

	/* Print link status only once */
	if (!priv->link_printed) {
		printf("ENET Speed is %d Mbps - %s duplex connection\n",
		       priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
		priv->link_printed = 1;
	}

	/* Reset ethernet hardware */
	if (mac_reset(dev) < 0)
		return -1;

	/* Resore the HW MAC address as it has been lost during MAC reset */
	dw_write_hwaddr(dev);

	writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
			&dma_p->busmode);

	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
		TXSECONDFRAME, &dma_p->opmode);

	conf = FRAMEBURSTENABLE | DISABLERXOWN;

	if (priv->speed != 1000)
		conf |= MII_PORTSELECT;

	if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
		(priv->interface != PHY_INTERFACE_MODE_GMII)) {

		if (priv->speed == 100)
			conf |= FES_100;
	}

	if (priv->duplex == FULL)
		conf |= FULLDPLXMODE;

	writel(conf, &mac_p->conf);

	descs_init(dev);

	/*
	 * Start/Enable xfer at dma as well as mac level
	 */
	writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
	writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);

	writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);

	return 0;
}

static int dw_eth_send(struct eth_device *dev, void *packet, int length)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	u32 desc_num = priv->tx_currdescnum;
	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];

	/* Check if the descriptor is owned by CPU */
	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
		printf("CPU not owner of tx frame\n");
		return -1;
	}

	memcpy((void *)desc_p->dmamac_addr, packet, length);

#if defined(CONFIG_DW_ALTDESCRIPTOR)
	desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
	desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
			       DESC_TXCTRL_SIZE1MASK;

	desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
	desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
	desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
			       DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
			       DESC_TXCTRL_TXFIRST;

	desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif

	/* Test the wrap-around condition. */
	if (++desc_num >= CONFIG_TX_DESCR_NUM)
		desc_num = 0;

	priv->tx_currdescnum = desc_num;

	/* Start the transmission */
	writel(POLL_DATA, &dma_p->txpolldemand);

	return 0;
}

static int dw_eth_recv(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	u32 desc_num = priv->rx_currdescnum;
	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];

	u32 status = desc_p->txrx_status;
	int length = 0;

	/* Check  if the owner is the CPU */
	if (!(status & DESC_RXSTS_OWNBYDMA)) {

		length = (status & DESC_RXSTS_FRMLENMSK) >> \
			 DESC_RXSTS_FRMLENSHFT;

		NetReceive(desc_p->dmamac_addr, length);

		/*
		 * Make the current descriptor valid again and go to
		 * the next one
		 */
		desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;

		/* Test the wrap-around condition. */
		if (++desc_num >= CONFIG_RX_DESCR_NUM)
			desc_num = 0;
	}

	priv->rx_currdescnum = desc_num;

	return length;
}

static void dw_eth_halt(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;

	mac_reset(dev);
	priv->tx_currdescnum = priv->rx_currdescnum = 0;
}

static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	ulong start;
	u32 miiaddr;
	int timeout = CONFIG_MDIO_TIMEOUT;

	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
		  ((reg << MIIREGSHIFT) & MII_REGMSK);

	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);

	start = get_timer(0);
	while (get_timer(start) < timeout) {
		if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
			*val = readl(&mac_p->miidata);
			return 0;
		}

		/* Try again after 10usec */
		udelay(10);
	};

	return -1;
}

static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	ulong start;
	u32 miiaddr;
	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
	u16 value;

	writel(val, &mac_p->miidata);
	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
		  ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;

	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);

	start = get_timer(0);
	while (get_timer(start) < timeout) {
		if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
			ret = 0;
			break;
		}

		/* Try again after 10usec */
		udelay(10);
	};

	/* Needed as a fix for ST-Phy */
	eth_mdio_read(dev, addr, reg, &value);

	return ret;
}

#if defined(CONFIG_DW_SEARCH_PHY)
static int find_phy(struct eth_device *dev)
{
	int phy_addr = 0;
	u16 ctrl, oldctrl;

	do {
		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
		oldctrl = ctrl & BMCR_ANENABLE;

		ctrl ^= BMCR_ANENABLE;
		eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
		ctrl &= BMCR_ANENABLE;

		if (ctrl == oldctrl) {
			phy_addr++;
		} else {
			ctrl ^= BMCR_ANENABLE;
			eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);

			return phy_addr;
		}
	} while (phy_addr < 32);

	return -1;
}
#endif

static int dw_reset_phy(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	u16 ctrl;
	ulong start;
	int timeout = CONFIG_PHYRESET_TIMEOUT;
	u32 phy_addr = priv->address;

	eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);

	start = get_timer(0);
	while (get_timer(start) < timeout) {
		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
		if (!(ctrl & BMCR_RESET))
			break;

		/* Try again after 10usec */
		udelay(10);
	};

	if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
		return -1;

#ifdef CONFIG_PHY_RESET_DELAY
	udelay(CONFIG_PHY_RESET_DELAY);
#endif
	return 0;
}

/*
 * Add weak default function for board specific PHY configuration
 */
int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
		int (*mii_write)(struct eth_device *, u8, u8, u16),
		int dw_reset_phy(struct eth_device *))
{
	return 0;
}

static int configure_phy(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	int phy_addr;
	u16 bmcr;
#if defined(CONFIG_DW_AUTONEG)
	u16 bmsr;
	u32 timeout;
	ulong start;
#endif

#if defined(CONFIG_DW_SEARCH_PHY)
	phy_addr = find_phy(dev);
	if (phy_addr >= 0)
		priv->address = phy_addr;
	else
		return -1;
#else
	phy_addr = priv->address;
#endif

	/*
	 * Some boards need board specific PHY initialization. This is
	 * after the main driver init code but before the auto negotiation
	 * is run.
	 */
	if (designware_board_phy_init(dev, phy_addr,
				      eth_mdio_write, dw_reset_phy) < 0)
		return -1;

	if (dw_reset_phy(dev) < 0)
		return -1;

#if defined(CONFIG_DW_AUTONEG)
	/* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
	eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);

	bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
#else
	bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;

#if defined(CONFIG_DW_SPEED10M)
	bmcr &= ~BMCR_SPEED100;
#endif
#if defined(CONFIG_DW_DUPLEXHALF)
	bmcr &= ~BMCR_FULLDPLX;
#endif
#endif
	if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
		return -1;

	/* Read the phy status register and populate priv structure */
#if defined(CONFIG_DW_AUTONEG)
	timeout = CONFIG_AUTONEG_TIMEOUT;
	start = get_timer(0);
	puts("Waiting for PHY auto negotiation to complete");
	while (get_timer(start) < timeout) {
		eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
		if (bmsr & BMSR_ANEGCOMPLETE) {
			priv->phy_configured = 1;
			break;
		}

		/* Print dot all 1s to show progress */
		if ((get_timer(start) % 1000) == 0)
			putc('.');

		/* Try again after 1msec */
		udelay(1000);
	};

	if (!(bmsr & BMSR_ANEGCOMPLETE))
		puts(" TIMEOUT!\n");
	else
		puts(" done\n");
#else
	priv->phy_configured = 1;
#endif

	priv->speed = miiphy_speed(dev->name, phy_addr);
	priv->duplex = miiphy_duplex(dev->name, phy_addr);

	return 0;
}

#if defined(CONFIG_MII)
static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
{
	struct eth_device *dev;

	dev = eth_get_dev_by_name(devname);
	if (dev)
		eth_mdio_read(dev, addr, reg, val);

	return 0;
}

static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
{
	struct eth_device *dev;

	dev = eth_get_dev_by_name(devname);
	if (dev)
		eth_mdio_write(dev, addr, reg, val);

	return 0;
}
#endif

int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
{
	struct eth_device *dev;
	struct dw_eth_dev *priv;

	dev = (struct eth_device *) malloc(sizeof(struct eth_device));
	if (!dev)
		return -ENOMEM;

	/*
	 * Since the priv structure contains the descriptors which need a strict
	 * buswidth alignment, memalign is used to allocate memory
	 */
	priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
	if (!priv) {
		free(dev);
		return -ENOMEM;
	}

	memset(dev, 0, sizeof(struct eth_device));
	memset(priv, 0, sizeof(struct dw_eth_dev));

	sprintf(dev->name, "mii%d", id);
	dev->iobase = (int)base_addr;
	dev->priv = priv;

	eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);

	priv->dev = dev;
	priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
	priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
			DW_DMA_BASE_OFFSET);
	priv->address = phy_addr;
	priv->phy_configured = 0;
	priv->interface = interface;

	dev->init = dw_eth_init;
	dev->send = dw_eth_send;
	dev->recv = dw_eth_recv;
	dev->halt = dw_eth_halt;
	dev->write_hwaddr = dw_write_hwaddr;

	eth_register(dev);

#if defined(CONFIG_MII)
	miiphy_register(dev->name, dw_mii_read, dw_mii_write);
#endif
	return 1;
}
Commit	Line	Data
5b1b1883 VK	1	/*
	2	* (C) Copyright 2010
	3	* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Designware ethernet IP driver for u-boot
	26	*/
	27
	28	#include <common.h>
	29	#include <miiphy.h>
	30	#include <malloc.h>
ef76025a	31	#include <linux/compiler.h>
5b1b1883 VK	32	#include <linux/err.h>
	33	#include <asm/io.h>
	34	#include "designware.h"
	35
13edd170 VK	36	static int configure_phy(struct eth_device *dev);
13edd170 VK	37
5b1b1883 VK	38	static void tx_descs_init(struct eth_device *dev)
	39	{
	40	struct dw_eth_dev *priv = dev->priv;
	41	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	42	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
	43	char *txbuffs = &priv->txbuffs[0];
	44	struct dmamacdescr *desc_p;
	45	u32 idx;
	46
	47	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
	48	desc_p = &desc_table_p[idx];
	49	desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
	50	desc_p->dmamac_next = &desc_table_p[idx + 1];
	51
	52	#if defined(CONFIG_DW_ALTDESCRIPTOR)
	53	desc_p->txrx_status &= ~(DESC_TXSTS_TXINT \| DESC_TXSTS_TXLAST \|
	54	DESC_TXSTS_TXFIRST \| DESC_TXSTS_TXCRCDIS \| \
	55	DESC_TXSTS_TXCHECKINSCTRL \| \
	56	DESC_TXSTS_TXRINGEND \| DESC_TXSTS_TXPADDIS);
	57
	58	desc_p->txrx_status \|= DESC_TXSTS_TXCHAIN;
	59	desc_p->dmamac_cntl = 0;
	60	desc_p->txrx_status &= ~(DESC_TXSTS_MSK \| DESC_TXSTS_OWNBYDMA);
	61	#else
	62	desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
	63	desc_p->txrx_status = 0;
	64	#endif
	65	}
	66
	67	/* Correcting the last pointer of the chain */
	68	desc_p->dmamac_next = &desc_table_p[0];
	69
	70	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
	71	}
	72
	73	static void rx_descs_init(struct eth_device *dev)
	74	{
	75	struct dw_eth_dev *priv = dev->priv;
	76	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	77	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
	78	char *rxbuffs = &priv->rxbuffs[0];
	79	struct dmamacdescr *desc_p;
	80	u32 idx;
	81
	82	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
	83	desc_p = &desc_table_p[idx];
	84	desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
	85	desc_p->dmamac_next = &desc_table_p[idx + 1];
	86
	87	desc_p->dmamac_cntl =
	88	(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) \| \
	89	DESC_RXCTRL_RXCHAIN;
	90
	91	desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
	92	}
	93
	94	/* Correcting the last pointer of the chain */
	95	desc_p->dmamac_next = &desc_table_p[0];
	96
	97	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
	98	}
	99
	100	static void descs_init(struct eth_device *dev)
	101	{
102	tx_descs_init(dev);
103	rx_descs_init(dev);
104	}
105
106	static int mac_reset(struct eth_device *dev)
107	{
108	struct dw_eth_dev *priv = dev->priv;
109	struct eth_mac_regs *mac_p = priv->mac_regs_p;
110	struct eth_dma_regs *dma_p = priv->dma_regs_p;
111
cafabe19	112	ulong start;
5b1b1883 VK	113	int timeout = CONFIG_MACRESET_TIMEOUT;
	114
	115	writel(DMAMAC_SRST, &dma_p->busmode);
	116	writel(MII_PORTSELECT, &mac_p->conf);
	117
cafabe19 AV	118	start = get_timer(0);
cafabe19 AV	119	while (get_timer(start) < timeout) {
5b1b1883 VK	120	if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
5b1b1883 VK	121	return 0;
cafabe19 AV	122
	123	/* Try again after 10usec */
	124	udelay(10);
	125	};
5b1b1883 VK	126
	127	return -1;
	128	}
	129
	130	static int dw_write_hwaddr(struct eth_device *dev)
	131	{
	132	struct dw_eth_dev *priv = dev->priv;
	133	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	134	u32 macid_lo, macid_hi;
	135	u8 *mac_id = &dev->enetaddr[0];
	136
	137	macid_lo = mac_id[0] + (mac_id[1] << 8) + \
	138	(mac_id[2] << 16) + (mac_id[3] << 24);
	139	macid_hi = mac_id[4] + (mac_id[5] << 8);
	140
	141	writel(macid_hi, &mac_p->macaddr0hi);
	142	writel(macid_lo, &mac_p->macaddr0lo);
	143
	144	return 0;
	145	}
	146
	147	static int dw_eth_init(struct eth_device dev, bd_t bis)
	148	{
	149	struct dw_eth_dev *priv = dev->priv;
	150	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	151	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	152	u32 conf;
	153
13edd170 VK	154	if (priv->phy_configured != 1)
	155	configure_phy(dev);
	156
ef76025a SR	157	/* Print link status only once */
	158	if (!priv->link_printed) {
	159	printf("ENET Speed is %d Mbps - %s duplex connection\n",
	160	priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
	161	priv->link_printed = 1;
	162	}
	163
5b1b1883 VK	164	/* Reset ethernet hardware */
	165	if (mac_reset(dev) < 0)
	166	return -1;
	167
c7f6dbe7 VK	168	/* Resore the HW MAC address as it has been lost during MAC reset */
	169	dw_write_hwaddr(dev);
	170
5b1b1883 VK	171	writel(FIXEDBURST \| PRIORXTX_41 \| BURST_16,
	172	&dma_p->busmode);
	173
66f119e5 DN	174	writel(readl(&dma_p->opmode) \| FLUSHTXFIFO \| STOREFORWARD \|
66f119e5 DN	175	TXSECONDFRAME, &dma_p->opmode);
5b1b1883 VK	176
	177	conf = FRAMEBURSTENABLE \| DISABLERXOWN;
	178
ef76025a	179	if (priv->speed != 1000)
5b1b1883 VK	180	conf \|= MII_PORTSELECT;
5b1b1883 VK	181
9afc1af0 VK	182	if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
	183	(priv->interface != PHY_INTERFACE_MODE_GMII)) {
	184
ef76025a	185	if (priv->speed == 100)
9afc1af0 VK	186	conf \|= FES_100;
	187	}
	188
ef76025a	189	if (priv->duplex == FULL)
5b1b1883 VK	190	conf \|= FULLDPLXMODE;
	191
	192	writel(conf, &mac_p->conf);
	193
	194	descs_init(dev);
	195
	196	/*
	197	* Start/Enable xfer at dma as well as mac level
	198	*/
	199	writel(readl(&dma_p->opmode) \| RXSTART, &dma_p->opmode);
	200	writel(readl(&dma_p->opmode) \| TXSTART, &dma_p->opmode);
	201
aa51005c	202	writel(readl(&mac_p->conf) \| RXENABLE \| TXENABLE, &mac_p->conf);
5b1b1883 VK	203
	204	return 0;
	205	}
	206
10cbe3b6	207	static int dw_eth_send(struct eth_device dev, void packet, int length)
5b1b1883 VK	208	{
	209	struct dw_eth_dev *priv = dev->priv;
	210	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	211	u32 desc_num = priv->tx_currdescnum;
	212	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
	213
	214	/* Check if the descriptor is owned by CPU */
	215	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
	216	printf("CPU not owner of tx frame\n");
	217	return -1;
	218	}
	219
10cbe3b6	220	memcpy((void *)desc_p->dmamac_addr, packet, length);
5b1b1883 VK	221
	222	#if defined(CONFIG_DW_ALTDESCRIPTOR)
	223	desc_p->txrx_status \|= DESC_TXSTS_TXFIRST \| DESC_TXSTS_TXLAST;
	224	desc_p->dmamac_cntl \|= (length << DESC_TXCTRL_SIZE1SHFT) & \
	225	DESC_TXCTRL_SIZE1MASK;
	226
	227	desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
	228	desc_p->txrx_status \|= DESC_TXSTS_OWNBYDMA;
	229	#else
	230	desc_p->dmamac_cntl \|= ((length << DESC_TXCTRL_SIZE1SHFT) & \
	231	DESC_TXCTRL_SIZE1MASK) \| DESC_TXCTRL_TXLAST \| \
	232	DESC_TXCTRL_TXFIRST;
	233
	234	desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
	235	#endif
	236
	237	/* Test the wrap-around condition. */
	238	if (++desc_num >= CONFIG_TX_DESCR_NUM)
	239	desc_num = 0;
	240
	241	priv->tx_currdescnum = desc_num;
	242
	243	/* Start the transmission */
	244	writel(POLL_DATA, &dma_p->txpolldemand);
	245
	246	return 0;
	247	}
	248
	249	static int dw_eth_recv(struct eth_device *dev)
	250	{
	251	struct dw_eth_dev *priv = dev->priv;
	252	u32 desc_num = priv->rx_currdescnum;
	253	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
	254
	255	u32 status = desc_p->txrx_status;
	256	int length = 0;
	257
	258	/* Check if the owner is the CPU */
	259	if (!(status & DESC_RXSTS_OWNBYDMA)) {
	260
	261	length = (status & DESC_RXSTS_FRMLENMSK) >> \
	262	DESC_RXSTS_FRMLENSHFT;
	263
	264	NetReceive(desc_p->dmamac_addr, length);
	265
	266	/*
	267	* Make the current descriptor valid again and go to
	268	* the next one
	269	*/
	270	desc_p->txrx_status \|= DESC_RXSTS_OWNBYDMA;
	271
	272	/* Test the wrap-around condition. */
	273	if (++desc_num >= CONFIG_RX_DESCR_NUM)
	274	desc_num = 0;
	275	}
	276
	277	priv->rx_currdescnum = desc_num;
	278
	279	return length;
	280	}
	281
	282	static void dw_eth_halt(struct eth_device *dev)
	283	{
	284	struct dw_eth_dev *priv = dev->priv;
285
286	mac_reset(dev);
287	priv->tx_currdescnum = priv->rx_currdescnum = 0;
288	}
289
290	static int eth_mdio_read(struct eth_device dev, u8 addr, u8 reg, u16 val)
291	{
292	struct dw_eth_dev *priv = dev->priv;
293	struct eth_mac_regs *mac_p = priv->mac_regs_p;
cafabe19	294	ulong start;
5b1b1883 VK	295	u32 miiaddr;
	296	int timeout = CONFIG_MDIO_TIMEOUT;
	297
	298	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) \| \
	299	((reg << MIIREGSHIFT) & MII_REGMSK);
	300
	301	writel(miiaddr \| MII_CLKRANGE_150_250M \| MII_BUSY, &mac_p->miiaddr);
	302
cafabe19 AV	303	start = get_timer(0);
cafabe19 AV	304	while (get_timer(start) < timeout) {
5b1b1883 VK	305	if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
	306	*val = readl(&mac_p->miidata);
	307	return 0;
	308	}
cafabe19 AV	309
	310	/* Try again after 10usec */
	311	udelay(10);
	312	};
5b1b1883 VK	313
	314	return -1;
	315	}
	316
	317	static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
	318	{
	319	struct dw_eth_dev *priv = dev->priv;
	320	struct eth_mac_regs *mac_p = priv->mac_regs_p;
cafabe19	321	ulong start;
5b1b1883 VK	322	u32 miiaddr;
	323	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
	324	u16 value;
	325
	326	writel(val, &mac_p->miidata);
	327	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) \| \
	328	((reg << MIIREGSHIFT) & MII_REGMSK) \| MII_WRITE;
	329
	330	writel(miiaddr \| MII_CLKRANGE_150_250M \| MII_BUSY, &mac_p->miiaddr);
	331
cafabe19 AV	332	start = get_timer(0);
cafabe19 AV	333	while (get_timer(start) < timeout) {
c7f6dbe7	334	if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
5b1b1883	335	ret = 0;
c7f6dbe7 VK	336	break;
c7f6dbe7 VK	337	}
cafabe19 AV	338
	339	/* Try again after 10usec */
	340	udelay(10);
	341	};
5b1b1883 VK	342
	343	/* Needed as a fix for ST-Phy */
	344	eth_mdio_read(dev, addr, reg, &value);
	345
	346	return ret;
	347	}
	348
	349	#if defined(CONFIG_DW_SEARCH_PHY)
	350	static int find_phy(struct eth_device *dev)
	351	{
	352	int phy_addr = 0;
	353	u16 ctrl, oldctrl;
	354
	355	do {
8ef583a0 MF	356	eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
8ef583a0 MF	357	oldctrl = ctrl & BMCR_ANENABLE;
5b1b1883	358
8ef583a0 MF	359	ctrl ^= BMCR_ANENABLE;
	360	eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
	361	eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
	362	ctrl &= BMCR_ANENABLE;
5b1b1883 VK	363
	364	if (ctrl == oldctrl) {
	365	phy_addr++;
	366	} else {
8ef583a0 MF	367	ctrl ^= BMCR_ANENABLE;
8ef583a0 MF	368	eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
5b1b1883 VK	369
	370	return phy_addr;
	371	}
	372	} while (phy_addr < 32);
	373
	374	return -1;
	375	}
	376	#endif
	377
	378	static int dw_reset_phy(struct eth_device *dev)
	379	{
	380	struct dw_eth_dev *priv = dev->priv;
	381	u16 ctrl;
cafabe19	382	ulong start;
5b1b1883 VK	383	int timeout = CONFIG_PHYRESET_TIMEOUT;
	384	u32 phy_addr = priv->address;
	385
8ef583a0	386	eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
cafabe19 AV	387
	388	start = get_timer(0);
	389	while (get_timer(start) < timeout) {
8ef583a0 MF	390	eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
8ef583a0 MF	391	if (!(ctrl & BMCR_RESET))
5b1b1883	392	break;
5b1b1883	393
cafabe19 AV	394	/* Try again after 10usec */
	395	udelay(10);
	396	};
	397
	398	if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
5b1b1883 VK	399	return -1;
	400
	401	#ifdef CONFIG_PHY_RESET_DELAY
	402	udelay(CONFIG_PHY_RESET_DELAY);
	403	#endif
	404	return 0;
	405	}
	406
ef76025a SR	407	/*
	408	* Add weak default function for board specific PHY configuration
	409	*/
	410	int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
	411	int (mii_write)(struct eth_device , u8, u8, u16),
	412	int dw_reset_phy(struct eth_device *))
	413	{
	414	return 0;
	415	}
	416
5b1b1883 VK	417	static int configure_phy(struct eth_device *dev)
	418	{
	419	struct dw_eth_dev *priv = dev->priv;
	420	int phy_addr;
ee7f5bfd	421	u16 bmcr;
5b1b1883 VK	422	#if defined(CONFIG_DW_AUTONEG)
	423	u16 bmsr;
	424	u32 timeout;
cafabe19	425	ulong start;
5b1b1883 VK	426	#endif
	427
	428	#if defined(CONFIG_DW_SEARCH_PHY)
	429	phy_addr = find_phy(dev);
024333c9	430	if (phy_addr >= 0)
5b1b1883 VK	431	priv->address = phy_addr;
	432	else
	433	return -1;
f0ece9e9 MF	434	#else
f0ece9e9 MF	435	phy_addr = priv->address;
5b1b1883	436	#endif
ef76025a SR	437
	438	/*
	439	* Some boards need board specific PHY initialization. This is
	440	* after the main driver init code but before the auto negotiation
	441	* is run.
	442	*/
	443	if (designware_board_phy_init(dev, phy_addr,
	444	eth_mdio_write, dw_reset_phy) < 0)
	445	return -1;
	446
5b1b1883 VK	447	if (dw_reset_phy(dev) < 0)
	448	return -1;
	449
	450	#if defined(CONFIG_DW_AUTONEG)
20a5dde1 AV	451	/* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
	452	eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
	453
e25c90b4	454	bmcr = BMCR_ANENABLE \| BMCR_ANRESTART;
5b1b1883	455	#else
8ef583a0	456	bmcr = BMCR_SPEED100 \| BMCR_FULLDPLX;
5b1b1883 VK	457
5b1b1883 VK	458	#if defined(CONFIG_DW_SPEED10M)
8ef583a0	459	bmcr &= ~BMCR_SPEED100;
5b1b1883 VK	460	#endif
5b1b1883 VK	461	#if defined(CONFIG_DW_DUPLEXHALF)
8ef583a0	462	bmcr &= ~BMCR_FULLDPLX;
5b1b1883 VK	463	#endif
5b1b1883 VK	464	#endif
8ef583a0	465	if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
5b1b1883 VK	466	return -1;
	467
	468	/* Read the phy status register and populate priv structure */
	469	#if defined(CONFIG_DW_AUTONEG)
	470	timeout = CONFIG_AUTONEG_TIMEOUT;
cafabe19	471	start = get_timer(0);
ef76025a	472	puts("Waiting for PHY auto negotiation to complete");
cafabe19	473	while (get_timer(start) < timeout) {
8ef583a0	474	eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
ef76025a SR	475	if (bmsr & BMSR_ANEGCOMPLETE) {
ef76025a SR	476	priv->phy_configured = 1;
5b1b1883	477	break;
13edd170	478	}
5b1b1883	479
ef76025a SR	480	/* Print dot all 1s to show progress */
	481	if ((get_timer(start) % 1000) == 0)
	482	putc('.');
	483
	484	/* Try again after 1msec */
	485	udelay(1000);
	486	};
5b1b1883	487
ef76025a SR	488	if (!(bmsr & BMSR_ANEGCOMPLETE))
ef76025a SR	489	puts(" TIMEOUT!\n");
5b1b1883	490	else
ef76025a SR	491	puts(" done\n");
ef76025a SR	492	#else
13edd170	493	priv->phy_configured = 1;
ef76025a SR	494	#endif
	495
	496	priv->speed = miiphy_speed(dev->name, phy_addr);
	497	priv->duplex = miiphy_duplex(dev->name, phy_addr);
13edd170	498
5b1b1883 VK	499	return 0;
	500	}
	501
	502	#if defined(CONFIG_MII)
5700bb63	503	static int dw_mii_read(const char devname, u8 addr, u8 reg, u16 val)
5b1b1883 VK	504	{
	505	struct eth_device *dev;
	506
	507	dev = eth_get_dev_by_name(devname);
	508	if (dev)
	509	eth_mdio_read(dev, addr, reg, val);
	510
	511	return 0;
	512	}
	513
5700bb63	514	static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
5b1b1883 VK	515	{
	516	struct eth_device *dev;
	517
	518	dev = eth_get_dev_by_name(devname);
	519	if (dev)
	520	eth_mdio_write(dev, addr, reg, val);
	521
	522	return 0;
	523	}
	524	#endif
	525
9afc1af0	526	int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
5b1b1883 VK	527	{
	528	struct eth_device *dev;
	529	struct dw_eth_dev *priv;
	530
	531	dev = (struct eth_device *) malloc(sizeof(struct eth_device));
	532	if (!dev)
	533	return -ENOMEM;
	534
	535	/*
	536	* Since the priv structure contains the descriptors which need a strict
	537	* buswidth alignment, memalign is used to allocate memory
	538	*/
	539	priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
	540	if (!priv) {
	541	free(dev);
	542	return -ENOMEM;
	543	}
	544
	545	memset(dev, 0, sizeof(struct eth_device));
	546	memset(priv, 0, sizeof(struct dw_eth_dev));
	547
	548	sprintf(dev->name, "mii%d", id);
	549	dev->iobase = (int)base_addr;
	550	dev->priv = priv;
	551
7616e785	552	eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
5b1b1883 VK	553
	554	priv->dev = dev;
	555	priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
	556	priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
	557	DW_DMA_BASE_OFFSET);
	558	priv->address = phy_addr;
13edd170	559	priv->phy_configured = 0;
9afc1af0	560	priv->interface = interface;
5b1b1883	561
5b1b1883 VK	562	dev->init = dw_eth_init;
	563	dev->send = dw_eth_send;
	564	dev->recv = dw_eth_recv;
	565	dev->halt = dw_eth_halt;
	566	dev->write_hwaddr = dw_write_hwaddr;
	567
	568	eth_register(dev);
	569
	570	#if defined(CONFIG_MII)
	571	miiphy_register(dev->name, dw_mii_read, dw_mii_write);
	572	#endif
	573	return 1;
	574	}