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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
5b1b1883 VK |
2 | /* |
3 | * (C) Copyright 2010 | |
4 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. | |
5b1b1883 VK |
5 | */ |
6 | ||
7 | /* | |
64dcd25f | 8 | * Designware ethernet IP driver for U-Boot |
5b1b1883 VK |
9 | */ |
10 | ||
11 | #include <common.h> | |
ba1f9667 | 12 | #include <clk.h> |
1eb69ae4 | 13 | #include <cpu_func.h> |
75577ba4 | 14 | #include <dm.h> |
64dcd25f | 15 | #include <errno.h> |
5b1b1883 VK |
16 | #include <miiphy.h> |
17 | #include <malloc.h> | |
90526e9f | 18 | #include <net.h> |
8b7ee66c | 19 | #include <pci.h> |
495c70f9 | 20 | #include <reset.h> |
90526e9f | 21 | #include <asm/cache.h> |
336d4615 | 22 | #include <dm/device_compat.h> |
61b29b82 | 23 | #include <dm/devres.h> |
ef76025a | 24 | #include <linux/compiler.h> |
5b1b1883 | 25 | #include <linux/err.h> |
7a9ca9db | 26 | #include <linux/kernel.h> |
5b1b1883 | 27 | #include <asm/io.h> |
6ec922fa | 28 | #include <power/regulator.h> |
5b1b1883 VK |
29 | #include "designware.h" |
30 | ||
92a190aa AB |
31 | static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
32 | { | |
90b7fc92 SS |
33 | #ifdef CONFIG_DM_ETH |
34 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); | |
35 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
36 | #else | |
92a190aa | 37 | struct eth_mac_regs *mac_p = bus->priv; |
90b7fc92 | 38 | #endif |
92a190aa AB |
39 | ulong start; |
40 | u16 miiaddr; | |
41 | int timeout = CONFIG_MDIO_TIMEOUT; | |
42 | ||
43 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | | |
44 | ((reg << MIIREGSHIFT) & MII_REGMSK); | |
45 | ||
46 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); | |
47 | ||
48 | start = get_timer(0); | |
49 | while (get_timer(start) < timeout) { | |
50 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) | |
51 | return readl(&mac_p->miidata); | |
52 | udelay(10); | |
53 | }; | |
54 | ||
64dcd25f | 55 | return -ETIMEDOUT; |
92a190aa AB |
56 | } |
57 | ||
58 | static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, | |
59 | u16 val) | |
60 | { | |
90b7fc92 SS |
61 | #ifdef CONFIG_DM_ETH |
62 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); | |
63 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
64 | #else | |
92a190aa | 65 | struct eth_mac_regs *mac_p = bus->priv; |
90b7fc92 | 66 | #endif |
92a190aa AB |
67 | ulong start; |
68 | u16 miiaddr; | |
64dcd25f | 69 | int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; |
92a190aa AB |
70 | |
71 | writel(val, &mac_p->miidata); | |
72 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | | |
73 | ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; | |
74 | ||
75 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); | |
76 | ||
77 | start = get_timer(0); | |
78 | while (get_timer(start) < timeout) { | |
79 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { | |
80 | ret = 0; | |
81 | break; | |
82 | } | |
83 | udelay(10); | |
84 | }; | |
85 | ||
86 | return ret; | |
87 | } | |
88 | ||
bcee8d67 | 89 | #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) |
90b7fc92 SS |
90 | static int dw_mdio_reset(struct mii_dev *bus) |
91 | { | |
92 | struct udevice *dev = bus->priv; | |
93 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
94 | struct dw_eth_pdata *pdata = dev_get_platdata(dev); | |
95 | int ret; | |
96 | ||
97 | if (!dm_gpio_is_valid(&priv->reset_gpio)) | |
98 | return 0; | |
99 | ||
100 | /* reset the phy */ | |
101 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); | |
102 | if (ret) | |
103 | return ret; | |
104 | ||
105 | udelay(pdata->reset_delays[0]); | |
106 | ||
107 | ret = dm_gpio_set_value(&priv->reset_gpio, 1); | |
108 | if (ret) | |
109 | return ret; | |
110 | ||
111 | udelay(pdata->reset_delays[1]); | |
112 | ||
113 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); | |
114 | if (ret) | |
115 | return ret; | |
116 | ||
117 | udelay(pdata->reset_delays[2]); | |
118 | ||
119 | return 0; | |
120 | } | |
121 | #endif | |
122 | ||
123 | static int dw_mdio_init(const char *name, void *priv) | |
92a190aa AB |
124 | { |
125 | struct mii_dev *bus = mdio_alloc(); | |
126 | ||
127 | if (!bus) { | |
128 | printf("Failed to allocate MDIO bus\n"); | |
64dcd25f | 129 | return -ENOMEM; |
92a190aa AB |
130 | } |
131 | ||
132 | bus->read = dw_mdio_read; | |
133 | bus->write = dw_mdio_write; | |
192bc694 | 134 | snprintf(bus->name, sizeof(bus->name), "%s", name); |
bcee8d67 | 135 | #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) |
90b7fc92 SS |
136 | bus->reset = dw_mdio_reset; |
137 | #endif | |
92a190aa | 138 | |
90b7fc92 | 139 | bus->priv = priv; |
92a190aa AB |
140 | |
141 | return mdio_register(bus); | |
142 | } | |
13edd170 | 143 | |
64dcd25f | 144 | static void tx_descs_init(struct dw_eth_dev *priv) |
5b1b1883 | 145 | { |
5b1b1883 VK |
146 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
147 | struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; | |
148 | char *txbuffs = &priv->txbuffs[0]; | |
149 | struct dmamacdescr *desc_p; | |
150 | u32 idx; | |
151 | ||
152 | for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { | |
153 | desc_p = &desc_table_p[idx]; | |
0e1a3e30 BG |
154 | desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; |
155 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; | |
5b1b1883 VK |
156 | |
157 | #if defined(CONFIG_DW_ALTDESCRIPTOR) | |
158 | desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | | |
2b261092 MV |
159 | DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | |
160 | DESC_TXSTS_TXCHECKINSCTRL | | |
5b1b1883 VK |
161 | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); |
162 | ||
163 | desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; | |
164 | desc_p->dmamac_cntl = 0; | |
165 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); | |
166 | #else | |
167 | desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; | |
168 | desc_p->txrx_status = 0; | |
169 | #endif | |
170 | } | |
171 | ||
172 | /* Correcting the last pointer of the chain */ | |
0e1a3e30 | 173 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
5b1b1883 | 174 | |
50b0df81 | 175 | /* Flush all Tx buffer descriptors at once */ |
0e1a3e30 BG |
176 | flush_dcache_range((ulong)priv->tx_mac_descrtable, |
177 | (ulong)priv->tx_mac_descrtable + | |
50b0df81 AB |
178 | sizeof(priv->tx_mac_descrtable)); |
179 | ||
5b1b1883 | 180 | writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); |
74cb708d | 181 | priv->tx_currdescnum = 0; |
5b1b1883 VK |
182 | } |
183 | ||
64dcd25f | 184 | static void rx_descs_init(struct dw_eth_dev *priv) |
5b1b1883 | 185 | { |
5b1b1883 VK |
186 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
187 | struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; | |
188 | char *rxbuffs = &priv->rxbuffs[0]; | |
189 | struct dmamacdescr *desc_p; | |
190 | u32 idx; | |
191 | ||
50b0df81 AB |
192 | /* Before passing buffers to GMAC we need to make sure zeros |
193 | * written there right after "priv" structure allocation were | |
194 | * flushed into RAM. | |
195 | * Otherwise there's a chance to get some of them flushed in RAM when | |
196 | * GMAC is already pushing data to RAM via DMA. This way incoming from | |
197 | * GMAC data will be corrupted. */ | |
0e1a3e30 | 198 | flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); |
50b0df81 | 199 | |
5b1b1883 VK |
200 | for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { |
201 | desc_p = &desc_table_p[idx]; | |
0e1a3e30 BG |
202 | desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; |
203 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; | |
5b1b1883 VK |
204 | |
205 | desc_p->dmamac_cntl = | |
2b261092 | 206 | (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | |
5b1b1883 VK |
207 | DESC_RXCTRL_RXCHAIN; |
208 | ||
209 | desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; | |
210 | } | |
211 | ||
212 | /* Correcting the last pointer of the chain */ | |
0e1a3e30 | 213 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
5b1b1883 | 214 | |
50b0df81 | 215 | /* Flush all Rx buffer descriptors at once */ |
0e1a3e30 BG |
216 | flush_dcache_range((ulong)priv->rx_mac_descrtable, |
217 | (ulong)priv->rx_mac_descrtable + | |
50b0df81 AB |
218 | sizeof(priv->rx_mac_descrtable)); |
219 | ||
5b1b1883 | 220 | writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); |
74cb708d | 221 | priv->rx_currdescnum = 0; |
5b1b1883 VK |
222 | } |
223 | ||
64dcd25f | 224 | static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) |
5b1b1883 | 225 | { |
92a190aa AB |
226 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
227 | u32 macid_lo, macid_hi; | |
92a190aa AB |
228 | |
229 | macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + | |
230 | (mac_id[3] << 24); | |
231 | macid_hi = mac_id[4] + (mac_id[5] << 8); | |
232 | ||
233 | writel(macid_hi, &mac_p->macaddr0hi); | |
234 | writel(macid_lo, &mac_p->macaddr0lo); | |
235 | ||
236 | return 0; | |
5b1b1883 VK |
237 | } |
238 | ||
0ea38db9 SG |
239 | static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, |
240 | struct phy_device *phydev) | |
5b1b1883 | 241 | { |
92a190aa | 242 | u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; |
5b1b1883 | 243 | |
92a190aa AB |
244 | if (!phydev->link) { |
245 | printf("%s: No link.\n", phydev->dev->name); | |
0ea38db9 | 246 | return 0; |
92a190aa | 247 | } |
5b1b1883 | 248 | |
92a190aa AB |
249 | if (phydev->speed != 1000) |
250 | conf |= MII_PORTSELECT; | |
b884c3fe AB |
251 | else |
252 | conf &= ~MII_PORTSELECT; | |
7091915a | 253 | |
92a190aa AB |
254 | if (phydev->speed == 100) |
255 | conf |= FES_100; | |
5b1b1883 | 256 | |
92a190aa AB |
257 | if (phydev->duplex) |
258 | conf |= FULLDPLXMODE; | |
cafabe19 | 259 | |
92a190aa | 260 | writel(conf, &mac_p->conf); |
5b1b1883 | 261 | |
92a190aa AB |
262 | printf("Speed: %d, %s duplex%s\n", phydev->speed, |
263 | (phydev->duplex) ? "full" : "half", | |
264 | (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); | |
0ea38db9 SG |
265 | |
266 | return 0; | |
5b1b1883 VK |
267 | } |
268 | ||
64dcd25f | 269 | static void _dw_eth_halt(struct dw_eth_dev *priv) |
5b1b1883 | 270 | { |
5b1b1883 | 271 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
92a190aa | 272 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
5b1b1883 | 273 | |
92a190aa AB |
274 | writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); |
275 | writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); | |
5b1b1883 | 276 | |
92a190aa | 277 | phy_shutdown(priv->phydev); |
5b1b1883 VK |
278 | } |
279 | ||
e72ced23 | 280 | int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) |
5b1b1883 | 281 | { |
5b1b1883 VK |
282 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
283 | struct eth_dma_regs *dma_p = priv->dma_regs_p; | |
92a190aa | 284 | unsigned int start; |
64dcd25f | 285 | int ret; |
5b1b1883 | 286 | |
92a190aa | 287 | writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); |
13edd170 | 288 | |
c6122194 QS |
289 | /* |
290 | * When a MII PHY is used, we must set the PS bit for the DMA | |
291 | * reset to succeed. | |
292 | */ | |
293 | if (priv->phydev->interface == PHY_INTERFACE_MODE_MII) | |
294 | writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf); | |
295 | else | |
296 | writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf); | |
297 | ||
92a190aa AB |
298 | start = get_timer(0); |
299 | while (readl(&dma_p->busmode) & DMAMAC_SRST) { | |
875143f3 AB |
300 | if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { |
301 | printf("DMA reset timeout\n"); | |
64dcd25f | 302 | return -ETIMEDOUT; |
875143f3 | 303 | } |
ef76025a | 304 | |
92a190aa AB |
305 | mdelay(100); |
306 | }; | |
5b1b1883 | 307 | |
f3edfd30 BM |
308 | /* |
309 | * Soft reset above clears HW address registers. | |
310 | * So we have to set it here once again. | |
311 | */ | |
312 | _dw_write_hwaddr(priv, enetaddr); | |
313 | ||
64dcd25f SG |
314 | rx_descs_init(priv); |
315 | tx_descs_init(priv); | |
5b1b1883 | 316 | |
49692c5f | 317 | writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); |
5b1b1883 | 318 | |
d2279221 | 319 | #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE |
92a190aa AB |
320 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, |
321 | &dma_p->opmode); | |
d2279221 SZ |
322 | #else |
323 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO, | |
324 | &dma_p->opmode); | |
325 | #endif | |
5b1b1883 | 326 | |
92a190aa | 327 | writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); |
9afc1af0 | 328 | |
2ddaf13b SZ |
329 | #ifdef CONFIG_DW_AXI_BURST_LEN |
330 | writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); | |
331 | #endif | |
332 | ||
92a190aa | 333 | /* Start up the PHY */ |
64dcd25f SG |
334 | ret = phy_startup(priv->phydev); |
335 | if (ret) { | |
92a190aa AB |
336 | printf("Could not initialize PHY %s\n", |
337 | priv->phydev->dev->name); | |
64dcd25f | 338 | return ret; |
9afc1af0 VK |
339 | } |
340 | ||
0ea38db9 SG |
341 | ret = dw_adjust_link(priv, mac_p, priv->phydev); |
342 | if (ret) | |
343 | return ret; | |
5b1b1883 | 344 | |
f63f28ee SG |
345 | return 0; |
346 | } | |
347 | ||
e72ced23 | 348 | int designware_eth_enable(struct dw_eth_dev *priv) |
f63f28ee SG |
349 | { |
350 | struct eth_mac_regs *mac_p = priv->mac_regs_p; | |
351 | ||
92a190aa | 352 | if (!priv->phydev->link) |
64dcd25f | 353 | return -EIO; |
5b1b1883 | 354 | |
aa51005c | 355 | writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); |
5b1b1883 VK |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
7a9ca9db FF |
360 | #define ETH_ZLEN 60 |
361 | ||
64dcd25f | 362 | static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) |
5b1b1883 | 363 | { |
5b1b1883 VK |
364 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
365 | u32 desc_num = priv->tx_currdescnum; | |
366 | struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; | |
0e1a3e30 BG |
367 | ulong desc_start = (ulong)desc_p; |
368 | ulong desc_end = desc_start + | |
96cec17d | 369 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
0e1a3e30 BG |
370 | ulong data_start = desc_p->dmamac_addr; |
371 | ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); | |
964ea7c1 IC |
372 | /* |
373 | * Strictly we only need to invalidate the "txrx_status" field | |
374 | * for the following check, but on some platforms we cannot | |
96cec17d MV |
375 | * invalidate only 4 bytes, so we flush the entire descriptor, |
376 | * which is 16 bytes in total. This is safe because the | |
377 | * individual descriptors in the array are each aligned to | |
378 | * ARCH_DMA_MINALIGN and padded appropriately. | |
964ea7c1 | 379 | */ |
96cec17d | 380 | invalidate_dcache_range(desc_start, desc_end); |
50b0df81 | 381 | |
5b1b1883 VK |
382 | /* Check if the descriptor is owned by CPU */ |
383 | if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { | |
384 | printf("CPU not owner of tx frame\n"); | |
64dcd25f | 385 | return -EPERM; |
5b1b1883 VK |
386 | } |
387 | ||
0e1a3e30 | 388 | memcpy((void *)data_start, packet, length); |
7efb75b1 SG |
389 | if (length < ETH_ZLEN) { |
390 | memset(&((char *)data_start)[length], 0, ETH_ZLEN - length); | |
391 | length = ETH_ZLEN; | |
392 | } | |
5b1b1883 | 393 | |
50b0df81 | 394 | /* Flush data to be sent */ |
96cec17d | 395 | flush_dcache_range(data_start, data_end); |
50b0df81 | 396 | |
5b1b1883 VK |
397 | #if defined(CONFIG_DW_ALTDESCRIPTOR) |
398 | desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; | |
ae8ac8d4 SG |
399 | desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) | |
400 | ((length << DESC_TXCTRL_SIZE1SHFT) & | |
401 | DESC_TXCTRL_SIZE1MASK); | |
5b1b1883 VK |
402 | |
403 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK); | |
404 | desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; | |
405 | #else | |
ae8ac8d4 SG |
406 | desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) | |
407 | ((length << DESC_TXCTRL_SIZE1SHFT) & | |
408 | DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | | |
409 | DESC_TXCTRL_TXFIRST; | |
5b1b1883 VK |
410 | |
411 | desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; | |
412 | #endif | |
413 | ||
50b0df81 | 414 | /* Flush modified buffer descriptor */ |
96cec17d | 415 | flush_dcache_range(desc_start, desc_end); |
50b0df81 | 416 | |
5b1b1883 VK |
417 | /* Test the wrap-around condition. */ |
418 | if (++desc_num >= CONFIG_TX_DESCR_NUM) | |
419 | desc_num = 0; | |
420 | ||
421 | priv->tx_currdescnum = desc_num; | |
422 | ||
423 | /* Start the transmission */ | |
424 | writel(POLL_DATA, &dma_p->txpolldemand); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
75577ba4 | 429 | static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) |
5b1b1883 | 430 | { |
50b0df81 | 431 | u32 status, desc_num = priv->rx_currdescnum; |
5b1b1883 | 432 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; |
75577ba4 | 433 | int length = -EAGAIN; |
0e1a3e30 BG |
434 | ulong desc_start = (ulong)desc_p; |
435 | ulong desc_end = desc_start + | |
96cec17d | 436 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
0e1a3e30 BG |
437 | ulong data_start = desc_p->dmamac_addr; |
438 | ulong data_end; | |
5b1b1883 | 439 | |
50b0df81 | 440 | /* Invalidate entire buffer descriptor */ |
96cec17d | 441 | invalidate_dcache_range(desc_start, desc_end); |
50b0df81 AB |
442 | |
443 | status = desc_p->txrx_status; | |
444 | ||
5b1b1883 VK |
445 | /* Check if the owner is the CPU */ |
446 | if (!(status & DESC_RXSTS_OWNBYDMA)) { | |
447 | ||
2b261092 | 448 | length = (status & DESC_RXSTS_FRMLENMSK) >> |
5b1b1883 VK |
449 | DESC_RXSTS_FRMLENSHFT; |
450 | ||
50b0df81 | 451 | /* Invalidate received data */ |
96cec17d MV |
452 | data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); |
453 | invalidate_dcache_range(data_start, data_end); | |
0e1a3e30 | 454 | *packetp = (uchar *)(ulong)desc_p->dmamac_addr; |
75577ba4 | 455 | } |
50b0df81 | 456 | |
75577ba4 SG |
457 | return length; |
458 | } | |
5b1b1883 | 459 | |
75577ba4 SG |
460 | static int _dw_free_pkt(struct dw_eth_dev *priv) |
461 | { | |
462 | u32 desc_num = priv->rx_currdescnum; | |
463 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; | |
0e1a3e30 BG |
464 | ulong desc_start = (ulong)desc_p; |
465 | ulong desc_end = desc_start + | |
75577ba4 | 466 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
5b1b1883 | 467 | |
75577ba4 SG |
468 | /* |
469 | * Make the current descriptor valid again and go to | |
470 | * the next one | |
471 | */ | |
472 | desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; | |
50b0df81 | 473 | |
75577ba4 SG |
474 | /* Flush only status field - others weren't changed */ |
475 | flush_dcache_range(desc_start, desc_end); | |
5b1b1883 | 476 | |
75577ba4 SG |
477 | /* Test the wrap-around condition. */ |
478 | if (++desc_num >= CONFIG_RX_DESCR_NUM) | |
479 | desc_num = 0; | |
5b1b1883 VK |
480 | priv->rx_currdescnum = desc_num; |
481 | ||
75577ba4 | 482 | return 0; |
5b1b1883 VK |
483 | } |
484 | ||
64dcd25f | 485 | static int dw_phy_init(struct dw_eth_dev *priv, void *dev) |
5b1b1883 | 486 | { |
92a190aa | 487 | struct phy_device *phydev; |
5dce9df0 | 488 | int phy_addr = -1, ret; |
cafabe19 | 489 | |
92a190aa | 490 | #ifdef CONFIG_PHY_ADDR |
5dce9df0 | 491 | phy_addr = CONFIG_PHY_ADDR; |
5b1b1883 VK |
492 | #endif |
493 | ||
5dce9df0 | 494 | phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface); |
92a190aa | 495 | if (!phydev) |
64dcd25f | 496 | return -ENODEV; |
5b1b1883 | 497 | |
92a190aa | 498 | phydev->supported &= PHY_GBIT_FEATURES; |
6968ec92 AB |
499 | if (priv->max_speed) { |
500 | ret = phy_set_supported(phydev, priv->max_speed); | |
501 | if (ret) | |
502 | return ret; | |
503 | } | |
92a190aa | 504 | phydev->advertising = phydev->supported; |
5b1b1883 | 505 | |
92a190aa AB |
506 | priv->phydev = phydev; |
507 | phy_config(phydev); | |
ef76025a | 508 | |
64dcd25f SG |
509 | return 0; |
510 | } | |
511 | ||
75577ba4 | 512 | #ifndef CONFIG_DM_ETH |
64dcd25f SG |
513 | static int dw_eth_init(struct eth_device *dev, bd_t *bis) |
514 | { | |
f63f28ee SG |
515 | int ret; |
516 | ||
e72ced23 | 517 | ret = designware_eth_init(dev->priv, dev->enetaddr); |
f63f28ee SG |
518 | if (!ret) |
519 | ret = designware_eth_enable(dev->priv); | |
520 | ||
521 | return ret; | |
64dcd25f SG |
522 | } |
523 | ||
524 | static int dw_eth_send(struct eth_device *dev, void *packet, int length) | |
525 | { | |
526 | return _dw_eth_send(dev->priv, packet, length); | |
527 | } | |
528 | ||
529 | static int dw_eth_recv(struct eth_device *dev) | |
530 | { | |
75577ba4 SG |
531 | uchar *packet; |
532 | int length; | |
533 | ||
534 | length = _dw_eth_recv(dev->priv, &packet); | |
535 | if (length == -EAGAIN) | |
536 | return 0; | |
537 | net_process_received_packet(packet, length); | |
538 | ||
539 | _dw_free_pkt(dev->priv); | |
540 | ||
541 | return 0; | |
64dcd25f SG |
542 | } |
543 | ||
544 | static void dw_eth_halt(struct eth_device *dev) | |
545 | { | |
546 | return _dw_eth_halt(dev->priv); | |
547 | } | |
548 | ||
549 | static int dw_write_hwaddr(struct eth_device *dev) | |
550 | { | |
551 | return _dw_write_hwaddr(dev->priv, dev->enetaddr); | |
5b1b1883 | 552 | } |
5b1b1883 | 553 | |
92a190aa | 554 | int designware_initialize(ulong base_addr, u32 interface) |
5b1b1883 VK |
555 | { |
556 | struct eth_device *dev; | |
557 | struct dw_eth_dev *priv; | |
558 | ||
559 | dev = (struct eth_device *) malloc(sizeof(struct eth_device)); | |
560 | if (!dev) | |
561 | return -ENOMEM; | |
562 | ||
563 | /* | |
564 | * Since the priv structure contains the descriptors which need a strict | |
565 | * buswidth alignment, memalign is used to allocate memory | |
566 | */ | |
1c848a25 IC |
567 | priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, |
568 | sizeof(struct dw_eth_dev)); | |
5b1b1883 VK |
569 | if (!priv) { |
570 | free(dev); | |
571 | return -ENOMEM; | |
572 | } | |
573 | ||
0e1a3e30 BG |
574 | if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { |
575 | printf("designware: buffers are outside DMA memory\n"); | |
576 | return -EINVAL; | |
577 | } | |
578 | ||
5b1b1883 VK |
579 | memset(dev, 0, sizeof(struct eth_device)); |
580 | memset(priv, 0, sizeof(struct dw_eth_dev)); | |
581 | ||
92a190aa | 582 | sprintf(dev->name, "dwmac.%lx", base_addr); |
5b1b1883 VK |
583 | dev->iobase = (int)base_addr; |
584 | dev->priv = priv; | |
585 | ||
5b1b1883 VK |
586 | priv->dev = dev; |
587 | priv->mac_regs_p = (struct eth_mac_regs *)base_addr; | |
588 | priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + | |
589 | DW_DMA_BASE_OFFSET); | |
5b1b1883 | 590 | |
5b1b1883 VK |
591 | dev->init = dw_eth_init; |
592 | dev->send = dw_eth_send; | |
593 | dev->recv = dw_eth_recv; | |
594 | dev->halt = dw_eth_halt; | |
595 | dev->write_hwaddr = dw_write_hwaddr; | |
596 | ||
597 | eth_register(dev); | |
598 | ||
92a190aa AB |
599 | priv->interface = interface; |
600 | ||
601 | dw_mdio_init(dev->name, priv->mac_regs_p); | |
602 | priv->bus = miiphy_get_dev_by_name(dev->name); | |
603 | ||
64dcd25f | 604 | return dw_phy_init(priv, dev); |
5b1b1883 | 605 | } |
75577ba4 SG |
606 | #endif |
607 | ||
608 | #ifdef CONFIG_DM_ETH | |
609 | static int designware_eth_start(struct udevice *dev) | |
610 | { | |
611 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
f63f28ee SG |
612 | struct dw_eth_dev *priv = dev_get_priv(dev); |
613 | int ret; | |
75577ba4 | 614 | |
e72ced23 | 615 | ret = designware_eth_init(priv, pdata->enetaddr); |
f63f28ee SG |
616 | if (ret) |
617 | return ret; | |
618 | ret = designware_eth_enable(priv); | |
619 | if (ret) | |
620 | return ret; | |
621 | ||
622 | return 0; | |
75577ba4 SG |
623 | } |
624 | ||
e72ced23 | 625 | int designware_eth_send(struct udevice *dev, void *packet, int length) |
75577ba4 SG |
626 | { |
627 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
628 | ||
629 | return _dw_eth_send(priv, packet, length); | |
630 | } | |
631 | ||
e72ced23 | 632 | int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
75577ba4 SG |
633 | { |
634 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
635 | ||
636 | return _dw_eth_recv(priv, packetp); | |
637 | } | |
638 | ||
e72ced23 | 639 | int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) |
75577ba4 SG |
640 | { |
641 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
642 | ||
643 | return _dw_free_pkt(priv); | |
644 | } | |
645 | ||
e72ced23 | 646 | void designware_eth_stop(struct udevice *dev) |
75577ba4 SG |
647 | { |
648 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
649 | ||
650 | return _dw_eth_halt(priv); | |
651 | } | |
652 | ||
e72ced23 | 653 | int designware_eth_write_hwaddr(struct udevice *dev) |
75577ba4 SG |
654 | { |
655 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
656 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
657 | ||
658 | return _dw_write_hwaddr(priv, pdata->enetaddr); | |
659 | } | |
660 | ||
8b7ee66c BM |
661 | static int designware_eth_bind(struct udevice *dev) |
662 | { | |
663 | #ifdef CONFIG_DM_PCI | |
664 | static int num_cards; | |
665 | char name[20]; | |
666 | ||
667 | /* Create a unique device name for PCI type devices */ | |
668 | if (device_is_on_pci_bus(dev)) { | |
669 | sprintf(name, "eth_designware#%u", num_cards++); | |
670 | device_set_name(dev, name); | |
671 | } | |
672 | #endif | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
b9e08d0e | 677 | int designware_eth_probe(struct udevice *dev) |
75577ba4 SG |
678 | { |
679 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
680 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
f0dc73c0 | 681 | u32 iobase = pdata->iobase; |
0e1a3e30 | 682 | ulong ioaddr; |
4ee587e2 | 683 | int ret, err; |
495c70f9 | 684 | struct reset_ctl_bulk reset_bulk; |
ba1f9667 | 685 | #ifdef CONFIG_CLK |
4ee587e2 | 686 | int i, clock_nb; |
ba1f9667 PC |
687 | |
688 | priv->clock_count = 0; | |
689 | clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); | |
690 | if (clock_nb > 0) { | |
691 | priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), | |
692 | GFP_KERNEL); | |
693 | if (!priv->clocks) | |
694 | return -ENOMEM; | |
695 | ||
696 | for (i = 0; i < clock_nb; i++) { | |
697 | err = clk_get_by_index(dev, i, &priv->clocks[i]); | |
698 | if (err < 0) | |
699 | break; | |
700 | ||
701 | err = clk_enable(&priv->clocks[i]); | |
1693a577 | 702 | if (err && err != -ENOSYS && err != -ENOTSUPP) { |
ba1f9667 PC |
703 | pr_err("failed to enable clock %d\n", i); |
704 | clk_free(&priv->clocks[i]); | |
705 | goto clk_err; | |
706 | } | |
707 | priv->clock_count++; | |
708 | } | |
709 | } else if (clock_nb != -ENOENT) { | |
710 | pr_err("failed to get clock phandle(%d)\n", clock_nb); | |
711 | return clock_nb; | |
712 | } | |
713 | #endif | |
75577ba4 | 714 | |
6ec922fa JC |
715 | #if defined(CONFIG_DM_REGULATOR) |
716 | struct udevice *phy_supply; | |
717 | ||
718 | ret = device_get_supply_regulator(dev, "phy-supply", | |
719 | &phy_supply); | |
720 | if (ret) { | |
721 | debug("%s: No phy supply\n", dev->name); | |
722 | } else { | |
723 | ret = regulator_set_enable(phy_supply, true); | |
724 | if (ret) { | |
725 | puts("Error enabling phy supply\n"); | |
726 | return ret; | |
727 | } | |
728 | } | |
729 | #endif | |
730 | ||
495c70f9 LFT |
731 | ret = reset_get_bulk(dev, &reset_bulk); |
732 | if (ret) | |
733 | dev_warn(dev, "Can't get reset: %d\n", ret); | |
734 | else | |
735 | reset_deassert_bulk(&reset_bulk); | |
736 | ||
8b7ee66c BM |
737 | #ifdef CONFIG_DM_PCI |
738 | /* | |
739 | * If we are on PCI bus, either directly attached to a PCI root port, | |
740 | * or via a PCI bridge, fill in platdata before we probe the hardware. | |
741 | */ | |
742 | if (device_is_on_pci_bus(dev)) { | |
8b7ee66c BM |
743 | dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); |
744 | iobase &= PCI_BASE_ADDRESS_MEM_MASK; | |
6758a6cc | 745 | iobase = dm_pci_mem_to_phys(dev, iobase); |
8b7ee66c BM |
746 | |
747 | pdata->iobase = iobase; | |
748 | pdata->phy_interface = PHY_INTERFACE_MODE_RMII; | |
749 | } | |
750 | #endif | |
751 | ||
f0dc73c0 | 752 | debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); |
0e1a3e30 BG |
753 | ioaddr = iobase; |
754 | priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; | |
755 | priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); | |
75577ba4 | 756 | priv->interface = pdata->phy_interface; |
6968ec92 | 757 | priv->max_speed = pdata->max_speed; |
75577ba4 | 758 | |
4ee587e2 SG |
759 | ret = dw_mdio_init(dev->name, dev); |
760 | if (ret) { | |
761 | err = ret; | |
762 | goto mdio_err; | |
763 | } | |
75577ba4 SG |
764 | priv->bus = miiphy_get_dev_by_name(dev->name); |
765 | ||
766 | ret = dw_phy_init(priv, dev); | |
767 | debug("%s, ret=%d\n", __func__, ret); | |
4ee587e2 SG |
768 | if (!ret) |
769 | return 0; | |
75577ba4 | 770 | |
4ee587e2 SG |
771 | /* continue here for cleanup if no PHY found */ |
772 | err = ret; | |
773 | mdio_unregister(priv->bus); | |
774 | mdio_free(priv->bus); | |
775 | mdio_err: | |
ba1f9667 PC |
776 | |
777 | #ifdef CONFIG_CLK | |
778 | clk_err: | |
779 | ret = clk_release_all(priv->clocks, priv->clock_count); | |
780 | if (ret) | |
781 | pr_err("failed to disable all clocks\n"); | |
782 | ||
ba1f9667 | 783 | #endif |
4ee587e2 | 784 | return err; |
75577ba4 SG |
785 | } |
786 | ||
5d2459fd BM |
787 | static int designware_eth_remove(struct udevice *dev) |
788 | { | |
789 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
790 | ||
791 | free(priv->phydev); | |
792 | mdio_unregister(priv->bus); | |
793 | mdio_free(priv->bus); | |
794 | ||
ba1f9667 PC |
795 | #ifdef CONFIG_CLK |
796 | return clk_release_all(priv->clocks, priv->clock_count); | |
797 | #else | |
5d2459fd | 798 | return 0; |
ba1f9667 | 799 | #endif |
5d2459fd BM |
800 | } |
801 | ||
b9e08d0e | 802 | const struct eth_ops designware_eth_ops = { |
75577ba4 SG |
803 | .start = designware_eth_start, |
804 | .send = designware_eth_send, | |
805 | .recv = designware_eth_recv, | |
806 | .free_pkt = designware_eth_free_pkt, | |
807 | .stop = designware_eth_stop, | |
808 | .write_hwaddr = designware_eth_write_hwaddr, | |
809 | }; | |
810 | ||
b9e08d0e | 811 | int designware_eth_ofdata_to_platdata(struct udevice *dev) |
75577ba4 | 812 | { |
90b7fc92 | 813 | struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); |
bcee8d67 | 814 | #if CONFIG_IS_ENABLED(DM_GPIO) |
90b7fc92 | 815 | struct dw_eth_dev *priv = dev_get_priv(dev); |
66d027e2 | 816 | #endif |
90b7fc92 | 817 | struct eth_pdata *pdata = &dw_pdata->eth_pdata; |
75577ba4 | 818 | const char *phy_mode; |
bcee8d67 | 819 | #if CONFIG_IS_ENABLED(DM_GPIO) |
90b7fc92 | 820 | int reset_flags = GPIOD_IS_OUT; |
66d027e2 | 821 | #endif |
90b7fc92 | 822 | int ret = 0; |
75577ba4 | 823 | |
15050f1c | 824 | pdata->iobase = dev_read_addr(dev); |
75577ba4 | 825 | pdata->phy_interface = -1; |
15050f1c | 826 | phy_mode = dev_read_string(dev, "phy-mode"); |
75577ba4 SG |
827 | if (phy_mode) |
828 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
829 | if (pdata->phy_interface == -1) { | |
830 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
831 | return -EINVAL; | |
832 | } | |
833 | ||
15050f1c | 834 | pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); |
6968ec92 | 835 | |
bcee8d67 | 836 | #if CONFIG_IS_ENABLED(DM_GPIO) |
7ad326a9 | 837 | if (dev_read_bool(dev, "snps,reset-active-low")) |
90b7fc92 SS |
838 | reset_flags |= GPIOD_ACTIVE_LOW; |
839 | ||
840 | ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, | |
841 | &priv->reset_gpio, reset_flags); | |
842 | if (ret == 0) { | |
7ad326a9 PT |
843 | ret = dev_read_u32_array(dev, "snps,reset-delays-us", |
844 | dw_pdata->reset_delays, 3); | |
90b7fc92 SS |
845 | } else if (ret == -ENOENT) { |
846 | ret = 0; | |
847 | } | |
66d027e2 | 848 | #endif |
90b7fc92 SS |
849 | |
850 | return ret; | |
75577ba4 SG |
851 | } |
852 | ||
853 | static const struct udevice_id designware_eth_ids[] = { | |
854 | { .compatible = "allwinner,sun7i-a20-gmac" }, | |
cfe25561 | 855 | { .compatible = "amlogic,meson6-dwmac" }, |
655217d9 | 856 | { .compatible = "amlogic,meson-gx-dwmac" }, |
ec353ad1 | 857 | { .compatible = "amlogic,meson-gxbb-dwmac" }, |
71a38a8e | 858 | { .compatible = "amlogic,meson-axg-dwmac" }, |
b20b70fc | 859 | { .compatible = "st,stm32-dwmac" }, |
2a723237 | 860 | { .compatible = "snps,arc-dwmac-3.70a" }, |
75577ba4 SG |
861 | { } |
862 | }; | |
863 | ||
9f76f105 | 864 | U_BOOT_DRIVER(eth_designware) = { |
75577ba4 SG |
865 | .name = "eth_designware", |
866 | .id = UCLASS_ETH, | |
867 | .of_match = designware_eth_ids, | |
868 | .ofdata_to_platdata = designware_eth_ofdata_to_platdata, | |
8b7ee66c | 869 | .bind = designware_eth_bind, |
75577ba4 | 870 | .probe = designware_eth_probe, |
5d2459fd | 871 | .remove = designware_eth_remove, |
75577ba4 SG |
872 | .ops = &designware_eth_ops, |
873 | .priv_auto_alloc_size = sizeof(struct dw_eth_dev), | |
90b7fc92 | 874 | .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), |
75577ba4 SG |
875 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
876 | }; | |
8b7ee66c BM |
877 | |
878 | static struct pci_device_id supported[] = { | |
879 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, | |
880 | { } | |
881 | }; | |
882 | ||
883 | U_BOOT_PCI_DEVICE(eth_designware, supported); | |
75577ba4 | 884 | #endif |