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Commit | Line | Data |
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5b1b1883 VK |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5b1b1883 VK |
6 | */ |
7 | ||
8 | /* | |
64dcd25f | 9 | * Designware ethernet IP driver for U-Boot |
5b1b1883 VK |
10 | */ |
11 | ||
12 | #include <common.h> | |
75577ba4 | 13 | #include <dm.h> |
64dcd25f | 14 | #include <errno.h> |
5b1b1883 VK |
15 | #include <miiphy.h> |
16 | #include <malloc.h> | |
ef76025a | 17 | #include <linux/compiler.h> |
5b1b1883 VK |
18 | #include <linux/err.h> |
19 | #include <asm/io.h> | |
20 | #include "designware.h" | |
21 | ||
75577ba4 SG |
22 | DECLARE_GLOBAL_DATA_PTR; |
23 | ||
92a190aa AB |
24 | #if !defined(CONFIG_PHYLIB) |
25 | # error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" | |
26 | #endif | |
27 | ||
28 | static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) | |
29 | { | |
30 | struct eth_mac_regs *mac_p = bus->priv; | |
31 | ulong start; | |
32 | u16 miiaddr; | |
33 | int timeout = CONFIG_MDIO_TIMEOUT; | |
34 | ||
35 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | | |
36 | ((reg << MIIREGSHIFT) & MII_REGMSK); | |
37 | ||
38 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); | |
39 | ||
40 | start = get_timer(0); | |
41 | while (get_timer(start) < timeout) { | |
42 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) | |
43 | return readl(&mac_p->miidata); | |
44 | udelay(10); | |
45 | }; | |
46 | ||
64dcd25f | 47 | return -ETIMEDOUT; |
92a190aa AB |
48 | } |
49 | ||
50 | static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, | |
51 | u16 val) | |
52 | { | |
53 | struct eth_mac_regs *mac_p = bus->priv; | |
54 | ulong start; | |
55 | u16 miiaddr; | |
64dcd25f | 56 | int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; |
92a190aa AB |
57 | |
58 | writel(val, &mac_p->miidata); | |
59 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | | |
60 | ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; | |
61 | ||
62 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); | |
63 | ||
64 | start = get_timer(0); | |
65 | while (get_timer(start) < timeout) { | |
66 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { | |
67 | ret = 0; | |
68 | break; | |
69 | } | |
70 | udelay(10); | |
71 | }; | |
72 | ||
73 | return ret; | |
74 | } | |
75 | ||
64dcd25f | 76 | static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p) |
92a190aa AB |
77 | { |
78 | struct mii_dev *bus = mdio_alloc(); | |
79 | ||
80 | if (!bus) { | |
81 | printf("Failed to allocate MDIO bus\n"); | |
64dcd25f | 82 | return -ENOMEM; |
92a190aa AB |
83 | } |
84 | ||
85 | bus->read = dw_mdio_read; | |
86 | bus->write = dw_mdio_write; | |
64dcd25f | 87 | snprintf(bus->name, sizeof(bus->name), name); |
92a190aa AB |
88 | |
89 | bus->priv = (void *)mac_regs_p; | |
90 | ||
91 | return mdio_register(bus); | |
92 | } | |
13edd170 | 93 | |
64dcd25f | 94 | static void tx_descs_init(struct dw_eth_dev *priv) |
5b1b1883 | 95 | { |
5b1b1883 VK |
96 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
97 | struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; | |
98 | char *txbuffs = &priv->txbuffs[0]; | |
99 | struct dmamacdescr *desc_p; | |
100 | u32 idx; | |
101 | ||
102 | for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { | |
103 | desc_p = &desc_table_p[idx]; | |
104 | desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; | |
105 | desc_p->dmamac_next = &desc_table_p[idx + 1]; | |
106 | ||
107 | #if defined(CONFIG_DW_ALTDESCRIPTOR) | |
108 | desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | | |
109 | DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ | |
110 | DESC_TXSTS_TXCHECKINSCTRL | \ | |
111 | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); | |
112 | ||
113 | desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; | |
114 | desc_p->dmamac_cntl = 0; | |
115 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); | |
116 | #else | |
117 | desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; | |
118 | desc_p->txrx_status = 0; | |
119 | #endif | |
120 | } | |
121 | ||
122 | /* Correcting the last pointer of the chain */ | |
123 | desc_p->dmamac_next = &desc_table_p[0]; | |
124 | ||
50b0df81 AB |
125 | /* Flush all Tx buffer descriptors at once */ |
126 | flush_dcache_range((unsigned int)priv->tx_mac_descrtable, | |
127 | (unsigned int)priv->tx_mac_descrtable + | |
128 | sizeof(priv->tx_mac_descrtable)); | |
129 | ||
5b1b1883 | 130 | writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); |
74cb708d | 131 | priv->tx_currdescnum = 0; |
5b1b1883 VK |
132 | } |
133 | ||
64dcd25f | 134 | static void rx_descs_init(struct dw_eth_dev *priv) |
5b1b1883 | 135 | { |
5b1b1883 VK |
136 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
137 | struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; | |
138 | char *rxbuffs = &priv->rxbuffs[0]; | |
139 | struct dmamacdescr *desc_p; | |
140 | u32 idx; | |
141 | ||
50b0df81 AB |
142 | /* Before passing buffers to GMAC we need to make sure zeros |
143 | * written there right after "priv" structure allocation were | |
144 | * flushed into RAM. | |
145 | * Otherwise there's a chance to get some of them flushed in RAM when | |
146 | * GMAC is already pushing data to RAM via DMA. This way incoming from | |
147 | * GMAC data will be corrupted. */ | |
148 | flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + | |
149 | RX_TOTAL_BUFSIZE); | |
150 | ||
5b1b1883 VK |
151 | for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { |
152 | desc_p = &desc_table_p[idx]; | |
153 | desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; | |
154 | desc_p->dmamac_next = &desc_table_p[idx + 1]; | |
155 | ||
156 | desc_p->dmamac_cntl = | |
157 | (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ | |
158 | DESC_RXCTRL_RXCHAIN; | |
159 | ||
160 | desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; | |
161 | } | |
162 | ||
163 | /* Correcting the last pointer of the chain */ | |
164 | desc_p->dmamac_next = &desc_table_p[0]; | |
165 | ||
50b0df81 AB |
166 | /* Flush all Rx buffer descriptors at once */ |
167 | flush_dcache_range((unsigned int)priv->rx_mac_descrtable, | |
168 | (unsigned int)priv->rx_mac_descrtable + | |
169 | sizeof(priv->rx_mac_descrtable)); | |
170 | ||
5b1b1883 | 171 | writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); |
74cb708d | 172 | priv->rx_currdescnum = 0; |
5b1b1883 VK |
173 | } |
174 | ||
64dcd25f | 175 | static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) |
5b1b1883 | 176 | { |
92a190aa AB |
177 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
178 | u32 macid_lo, macid_hi; | |
92a190aa AB |
179 | |
180 | macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + | |
181 | (mac_id[3] << 24); | |
182 | macid_hi = mac_id[4] + (mac_id[5] << 8); | |
183 | ||
184 | writel(macid_hi, &mac_p->macaddr0hi); | |
185 | writel(macid_lo, &mac_p->macaddr0lo); | |
186 | ||
187 | return 0; | |
5b1b1883 VK |
188 | } |
189 | ||
92a190aa AB |
190 | static void dw_adjust_link(struct eth_mac_regs *mac_p, |
191 | struct phy_device *phydev) | |
5b1b1883 | 192 | { |
92a190aa | 193 | u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; |
5b1b1883 | 194 | |
92a190aa AB |
195 | if (!phydev->link) { |
196 | printf("%s: No link.\n", phydev->dev->name); | |
197 | return; | |
198 | } | |
5b1b1883 | 199 | |
92a190aa AB |
200 | if (phydev->speed != 1000) |
201 | conf |= MII_PORTSELECT; | |
7091915a | 202 | |
92a190aa AB |
203 | if (phydev->speed == 100) |
204 | conf |= FES_100; | |
5b1b1883 | 205 | |
92a190aa AB |
206 | if (phydev->duplex) |
207 | conf |= FULLDPLXMODE; | |
cafabe19 | 208 | |
92a190aa | 209 | writel(conf, &mac_p->conf); |
5b1b1883 | 210 | |
92a190aa AB |
211 | printf("Speed: %d, %s duplex%s\n", phydev->speed, |
212 | (phydev->duplex) ? "full" : "half", | |
213 | (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); | |
5b1b1883 VK |
214 | } |
215 | ||
64dcd25f | 216 | static void _dw_eth_halt(struct dw_eth_dev *priv) |
5b1b1883 | 217 | { |
5b1b1883 | 218 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
92a190aa | 219 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
5b1b1883 | 220 | |
92a190aa AB |
221 | writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); |
222 | writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); | |
5b1b1883 | 223 | |
92a190aa | 224 | phy_shutdown(priv->phydev); |
5b1b1883 VK |
225 | } |
226 | ||
64dcd25f | 227 | static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) |
5b1b1883 | 228 | { |
5b1b1883 VK |
229 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
230 | struct eth_dma_regs *dma_p = priv->dma_regs_p; | |
92a190aa | 231 | unsigned int start; |
64dcd25f | 232 | int ret; |
5b1b1883 | 233 | |
92a190aa | 234 | writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); |
13edd170 | 235 | |
92a190aa AB |
236 | start = get_timer(0); |
237 | while (readl(&dma_p->busmode) & DMAMAC_SRST) { | |
875143f3 AB |
238 | if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { |
239 | printf("DMA reset timeout\n"); | |
64dcd25f | 240 | return -ETIMEDOUT; |
875143f3 | 241 | } |
ef76025a | 242 | |
92a190aa AB |
243 | mdelay(100); |
244 | }; | |
5b1b1883 | 245 | |
f3edfd30 BM |
246 | /* |
247 | * Soft reset above clears HW address registers. | |
248 | * So we have to set it here once again. | |
249 | */ | |
250 | _dw_write_hwaddr(priv, enetaddr); | |
251 | ||
64dcd25f SG |
252 | rx_descs_init(priv); |
253 | tx_descs_init(priv); | |
5b1b1883 | 254 | |
49692c5f | 255 | writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); |
5b1b1883 | 256 | |
d2279221 | 257 | #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE |
92a190aa AB |
258 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, |
259 | &dma_p->opmode); | |
d2279221 SZ |
260 | #else |
261 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO, | |
262 | &dma_p->opmode); | |
263 | #endif | |
5b1b1883 | 264 | |
92a190aa | 265 | writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); |
9afc1af0 | 266 | |
2ddaf13b SZ |
267 | #ifdef CONFIG_DW_AXI_BURST_LEN |
268 | writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); | |
269 | #endif | |
270 | ||
92a190aa | 271 | /* Start up the PHY */ |
64dcd25f SG |
272 | ret = phy_startup(priv->phydev); |
273 | if (ret) { | |
92a190aa AB |
274 | printf("Could not initialize PHY %s\n", |
275 | priv->phydev->dev->name); | |
64dcd25f | 276 | return ret; |
9afc1af0 VK |
277 | } |
278 | ||
92a190aa | 279 | dw_adjust_link(mac_p, priv->phydev); |
5b1b1883 | 280 | |
92a190aa | 281 | if (!priv->phydev->link) |
64dcd25f | 282 | return -EIO; |
5b1b1883 | 283 | |
aa51005c | 284 | writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); |
5b1b1883 VK |
285 | |
286 | return 0; | |
287 | } | |
288 | ||
64dcd25f | 289 | static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) |
5b1b1883 | 290 | { |
5b1b1883 VK |
291 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
292 | u32 desc_num = priv->tx_currdescnum; | |
293 | struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; | |
96cec17d MV |
294 | uint32_t desc_start = (uint32_t)desc_p; |
295 | uint32_t desc_end = desc_start + | |
296 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); | |
297 | uint32_t data_start = (uint32_t)desc_p->dmamac_addr; | |
298 | uint32_t data_end = data_start + | |
299 | roundup(length, ARCH_DMA_MINALIGN); | |
964ea7c1 IC |
300 | /* |
301 | * Strictly we only need to invalidate the "txrx_status" field | |
302 | * for the following check, but on some platforms we cannot | |
96cec17d MV |
303 | * invalidate only 4 bytes, so we flush the entire descriptor, |
304 | * which is 16 bytes in total. This is safe because the | |
305 | * individual descriptors in the array are each aligned to | |
306 | * ARCH_DMA_MINALIGN and padded appropriately. | |
964ea7c1 | 307 | */ |
96cec17d | 308 | invalidate_dcache_range(desc_start, desc_end); |
50b0df81 | 309 | |
5b1b1883 VK |
310 | /* Check if the descriptor is owned by CPU */ |
311 | if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { | |
312 | printf("CPU not owner of tx frame\n"); | |
64dcd25f | 313 | return -EPERM; |
5b1b1883 VK |
314 | } |
315 | ||
96cec17d | 316 | memcpy(desc_p->dmamac_addr, packet, length); |
5b1b1883 | 317 | |
50b0df81 | 318 | /* Flush data to be sent */ |
96cec17d | 319 | flush_dcache_range(data_start, data_end); |
50b0df81 | 320 | |
5b1b1883 VK |
321 | #if defined(CONFIG_DW_ALTDESCRIPTOR) |
322 | desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; | |
323 | desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ | |
324 | DESC_TXCTRL_SIZE1MASK; | |
325 | ||
326 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK); | |
327 | desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; | |
328 | #else | |
329 | desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ | |
330 | DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ | |
331 | DESC_TXCTRL_TXFIRST; | |
332 | ||
333 | desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; | |
334 | #endif | |
335 | ||
50b0df81 | 336 | /* Flush modified buffer descriptor */ |
96cec17d | 337 | flush_dcache_range(desc_start, desc_end); |
50b0df81 | 338 | |
5b1b1883 VK |
339 | /* Test the wrap-around condition. */ |
340 | if (++desc_num >= CONFIG_TX_DESCR_NUM) | |
341 | desc_num = 0; | |
342 | ||
343 | priv->tx_currdescnum = desc_num; | |
344 | ||
345 | /* Start the transmission */ | |
346 | writel(POLL_DATA, &dma_p->txpolldemand); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
75577ba4 | 351 | static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) |
5b1b1883 | 352 | { |
50b0df81 | 353 | u32 status, desc_num = priv->rx_currdescnum; |
5b1b1883 | 354 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; |
75577ba4 | 355 | int length = -EAGAIN; |
96cec17d MV |
356 | uint32_t desc_start = (uint32_t)desc_p; |
357 | uint32_t desc_end = desc_start + | |
358 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); | |
359 | uint32_t data_start = (uint32_t)desc_p->dmamac_addr; | |
360 | uint32_t data_end; | |
5b1b1883 | 361 | |
50b0df81 | 362 | /* Invalidate entire buffer descriptor */ |
96cec17d | 363 | invalidate_dcache_range(desc_start, desc_end); |
50b0df81 AB |
364 | |
365 | status = desc_p->txrx_status; | |
366 | ||
5b1b1883 VK |
367 | /* Check if the owner is the CPU */ |
368 | if (!(status & DESC_RXSTS_OWNBYDMA)) { | |
369 | ||
370 | length = (status & DESC_RXSTS_FRMLENMSK) >> \ | |
371 | DESC_RXSTS_FRMLENSHFT; | |
372 | ||
50b0df81 | 373 | /* Invalidate received data */ |
96cec17d MV |
374 | data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); |
375 | invalidate_dcache_range(data_start, data_end); | |
75577ba4 SG |
376 | *packetp = desc_p->dmamac_addr; |
377 | } | |
50b0df81 | 378 | |
75577ba4 SG |
379 | return length; |
380 | } | |
5b1b1883 | 381 | |
75577ba4 SG |
382 | static int _dw_free_pkt(struct dw_eth_dev *priv) |
383 | { | |
384 | u32 desc_num = priv->rx_currdescnum; | |
385 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; | |
386 | uint32_t desc_start = (uint32_t)desc_p; | |
387 | uint32_t desc_end = desc_start + | |
388 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); | |
5b1b1883 | 389 | |
75577ba4 SG |
390 | /* |
391 | * Make the current descriptor valid again and go to | |
392 | * the next one | |
393 | */ | |
394 | desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; | |
50b0df81 | 395 | |
75577ba4 SG |
396 | /* Flush only status field - others weren't changed */ |
397 | flush_dcache_range(desc_start, desc_end); | |
5b1b1883 | 398 | |
75577ba4 SG |
399 | /* Test the wrap-around condition. */ |
400 | if (++desc_num >= CONFIG_RX_DESCR_NUM) | |
401 | desc_num = 0; | |
5b1b1883 VK |
402 | priv->rx_currdescnum = desc_num; |
403 | ||
75577ba4 | 404 | return 0; |
5b1b1883 VK |
405 | } |
406 | ||
64dcd25f | 407 | static int dw_phy_init(struct dw_eth_dev *priv, void *dev) |
5b1b1883 | 408 | { |
92a190aa AB |
409 | struct phy_device *phydev; |
410 | int mask = 0xffffffff; | |
cafabe19 | 411 | |
92a190aa AB |
412 | #ifdef CONFIG_PHY_ADDR |
413 | mask = 1 << CONFIG_PHY_ADDR; | |
5b1b1883 VK |
414 | #endif |
415 | ||
92a190aa AB |
416 | phydev = phy_find_by_mask(priv->bus, mask, priv->interface); |
417 | if (!phydev) | |
64dcd25f | 418 | return -ENODEV; |
5b1b1883 | 419 | |
15e82e53 IC |
420 | phy_connect_dev(phydev, dev); |
421 | ||
92a190aa AB |
422 | phydev->supported &= PHY_GBIT_FEATURES; |
423 | phydev->advertising = phydev->supported; | |
5b1b1883 | 424 | |
92a190aa AB |
425 | priv->phydev = phydev; |
426 | phy_config(phydev); | |
ef76025a | 427 | |
64dcd25f SG |
428 | return 0; |
429 | } | |
430 | ||
75577ba4 | 431 | #ifndef CONFIG_DM_ETH |
64dcd25f SG |
432 | static int dw_eth_init(struct eth_device *dev, bd_t *bis) |
433 | { | |
434 | return _dw_eth_init(dev->priv, dev->enetaddr); | |
435 | } | |
436 | ||
437 | static int dw_eth_send(struct eth_device *dev, void *packet, int length) | |
438 | { | |
439 | return _dw_eth_send(dev->priv, packet, length); | |
440 | } | |
441 | ||
442 | static int dw_eth_recv(struct eth_device *dev) | |
443 | { | |
75577ba4 SG |
444 | uchar *packet; |
445 | int length; | |
446 | ||
447 | length = _dw_eth_recv(dev->priv, &packet); | |
448 | if (length == -EAGAIN) | |
449 | return 0; | |
450 | net_process_received_packet(packet, length); | |
451 | ||
452 | _dw_free_pkt(dev->priv); | |
453 | ||
454 | return 0; | |
64dcd25f SG |
455 | } |
456 | ||
457 | static void dw_eth_halt(struct eth_device *dev) | |
458 | { | |
459 | return _dw_eth_halt(dev->priv); | |
460 | } | |
461 | ||
462 | static int dw_write_hwaddr(struct eth_device *dev) | |
463 | { | |
464 | return _dw_write_hwaddr(dev->priv, dev->enetaddr); | |
5b1b1883 | 465 | } |
5b1b1883 | 466 | |
92a190aa | 467 | int designware_initialize(ulong base_addr, u32 interface) |
5b1b1883 VK |
468 | { |
469 | struct eth_device *dev; | |
470 | struct dw_eth_dev *priv; | |
471 | ||
472 | dev = (struct eth_device *) malloc(sizeof(struct eth_device)); | |
473 | if (!dev) | |
474 | return -ENOMEM; | |
475 | ||
476 | /* | |
477 | * Since the priv structure contains the descriptors which need a strict | |
478 | * buswidth alignment, memalign is used to allocate memory | |
479 | */ | |
1c848a25 IC |
480 | priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, |
481 | sizeof(struct dw_eth_dev)); | |
5b1b1883 VK |
482 | if (!priv) { |
483 | free(dev); | |
484 | return -ENOMEM; | |
485 | } | |
486 | ||
487 | memset(dev, 0, sizeof(struct eth_device)); | |
488 | memset(priv, 0, sizeof(struct dw_eth_dev)); | |
489 | ||
92a190aa | 490 | sprintf(dev->name, "dwmac.%lx", base_addr); |
5b1b1883 VK |
491 | dev->iobase = (int)base_addr; |
492 | dev->priv = priv; | |
493 | ||
5b1b1883 VK |
494 | priv->dev = dev; |
495 | priv->mac_regs_p = (struct eth_mac_regs *)base_addr; | |
496 | priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + | |
497 | DW_DMA_BASE_OFFSET); | |
5b1b1883 | 498 | |
5b1b1883 VK |
499 | dev->init = dw_eth_init; |
500 | dev->send = dw_eth_send; | |
501 | dev->recv = dw_eth_recv; | |
502 | dev->halt = dw_eth_halt; | |
503 | dev->write_hwaddr = dw_write_hwaddr; | |
504 | ||
505 | eth_register(dev); | |
506 | ||
92a190aa AB |
507 | priv->interface = interface; |
508 | ||
509 | dw_mdio_init(dev->name, priv->mac_regs_p); | |
510 | priv->bus = miiphy_get_dev_by_name(dev->name); | |
511 | ||
64dcd25f | 512 | return dw_phy_init(priv, dev); |
5b1b1883 | 513 | } |
75577ba4 SG |
514 | #endif |
515 | ||
516 | #ifdef CONFIG_DM_ETH | |
517 | static int designware_eth_start(struct udevice *dev) | |
518 | { | |
519 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
520 | ||
521 | return _dw_eth_init(dev->priv, pdata->enetaddr); | |
522 | } | |
523 | ||
524 | static int designware_eth_send(struct udevice *dev, void *packet, int length) | |
525 | { | |
526 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
527 | ||
528 | return _dw_eth_send(priv, packet, length); | |
529 | } | |
530 | ||
a1ca92ea | 531 | static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
75577ba4 SG |
532 | { |
533 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
534 | ||
535 | return _dw_eth_recv(priv, packetp); | |
536 | } | |
537 | ||
538 | static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, | |
539 | int length) | |
540 | { | |
541 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
542 | ||
543 | return _dw_free_pkt(priv); | |
544 | } | |
545 | ||
546 | static void designware_eth_stop(struct udevice *dev) | |
547 | { | |
548 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
549 | ||
550 | return _dw_eth_halt(priv); | |
551 | } | |
552 | ||
553 | static int designware_eth_write_hwaddr(struct udevice *dev) | |
554 | { | |
555 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
556 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
557 | ||
558 | return _dw_write_hwaddr(priv, pdata->enetaddr); | |
559 | } | |
560 | ||
561 | static int designware_eth_probe(struct udevice *dev) | |
562 | { | |
563 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
564 | struct dw_eth_dev *priv = dev_get_priv(dev); | |
565 | int ret; | |
566 | ||
567 | debug("%s, iobase=%lx, priv=%p\n", __func__, pdata->iobase, priv); | |
568 | priv->mac_regs_p = (struct eth_mac_regs *)pdata->iobase; | |
569 | priv->dma_regs_p = (struct eth_dma_regs *)(pdata->iobase + | |
570 | DW_DMA_BASE_OFFSET); | |
571 | priv->interface = pdata->phy_interface; | |
572 | ||
573 | dw_mdio_init(dev->name, priv->mac_regs_p); | |
574 | priv->bus = miiphy_get_dev_by_name(dev->name); | |
575 | ||
576 | ret = dw_phy_init(priv, dev); | |
577 | debug("%s, ret=%d\n", __func__, ret); | |
578 | ||
579 | return ret; | |
580 | } | |
581 | ||
582 | static const struct eth_ops designware_eth_ops = { | |
583 | .start = designware_eth_start, | |
584 | .send = designware_eth_send, | |
585 | .recv = designware_eth_recv, | |
586 | .free_pkt = designware_eth_free_pkt, | |
587 | .stop = designware_eth_stop, | |
588 | .write_hwaddr = designware_eth_write_hwaddr, | |
589 | }; | |
590 | ||
591 | static int designware_eth_ofdata_to_platdata(struct udevice *dev) | |
592 | { | |
593 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
594 | const char *phy_mode; | |
595 | ||
596 | pdata->iobase = dev_get_addr(dev); | |
597 | pdata->phy_interface = -1; | |
598 | phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); | |
599 | if (phy_mode) | |
600 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
601 | if (pdata->phy_interface == -1) { | |
602 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
603 | return -EINVAL; | |
604 | } | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
609 | static const struct udevice_id designware_eth_ids[] = { | |
610 | { .compatible = "allwinner,sun7i-a20-gmac" }, | |
b9628595 | 611 | { .compatible = "altr,socfpga-stmmac" }, |
75577ba4 SG |
612 | { } |
613 | }; | |
614 | ||
9f76f105 | 615 | U_BOOT_DRIVER(eth_designware) = { |
75577ba4 SG |
616 | .name = "eth_designware", |
617 | .id = UCLASS_ETH, | |
618 | .of_match = designware_eth_ids, | |
619 | .ofdata_to_platdata = designware_eth_ofdata_to_platdata, | |
620 | .probe = designware_eth_probe, | |
621 | .ops = &designware_eth_ops, | |
622 | .priv_auto_alloc_size = sizeof(struct dw_eth_dev), | |
623 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
624 | .flags = DM_FLAG_ALLOC_PRIV_DMA, | |
625 | }; | |
626 | #endif |