[people/ms/u-boot.git] / drivers / net / dm9000x.c

/*
  dm9000.c: Version 1.2 12/15/2003

	A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
	Copyright (C) 1997  Sten Wang

	This program is free software; you can redistribute it and/or
	modify it under the terms of the GNU General Public License
	as published by the Free Software Foundation; either version 2
	of the License, or (at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.

  (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.

V0.11	06/20/2001	REG_0A bit3=1, default enable BP with DA match
	06/22/2001	Support DM9801 progrmming
			E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
			E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
		R17 = (R17 & 0xfff0) | NF + 3
			E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
		R17 = (R17 & 0xfff0) | NF

v1.00			modify by simon 2001.9.5
	                change for kernel 2.4.x

v1.1   11/09/2001	fix force mode bug

v1.2   03/18/2003       Weilun Huang <weilun_huang@davicom.com.tw>:
			Fixed phy reset.
			Added tx/rx 32 bit mode.
			Cleaned up for kernel merge.

--------------------------------------

       12/15/2003       Initial port to u-boot by
       			Sascha Hauer <saschahauer@web.de>

       06/03/2008	Remy Bohmer <linux@bohmer.net>
			- Fixed the driver to work with DM9000A.
			  (check on ISR receive status bit before reading the
			  FIFO as described in DM9000 programming guide and
			  application notes)
			- Added autodetect of databus width.
			- Made debug code compile again.
			- Adapt eth_send such that it matches the DM9000*
			  application notes. Needed to make it work properly
			  for DM9000A.
			- Adapted reset procedure to match DM9000 application
			  notes (i.e. double reset)
			- some minor code cleanups
			These changes are tested with DM9000{A,EP,E} together
			with a 200MHz Atmel AT91SAM9261 core

TODO: external MII is not functional, only internal at the moment.
*/

#include <common.h>
#include <command.h>
#include <net.h>
#include <asm/io.h>
#include <dm9000.h>

#include "dm9000x.h"

/* Board/System/Debug information/definition ---------------- */

/* #define CONFIG_DM9000_DEBUG */

#ifdef CONFIG_DM9000_DEBUG
#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
#define DM9000_DMP_PACKET(func,packet,length)  \
	do { \
		int i; 							\
		printf("%s: length: %d\n", func, length);		\
		for (i = 0; i < length; i++) {				\
			if (i % 8 == 0)					\
				printf("\n%s: %02x: ", func, i);	\
			printf("%02x ", ((unsigned char *) packet)[i]);	\
		} printf("\n");						\
	} while(0)
#else
#define DM9000_DBG(fmt,args...)
#define DM9000_DMP_PACKET(func,packet,length)
#endif

/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
	u32 runt_length_counter;	/* counter: RX length < 64byte */
	u32 long_length_counter;	/* counter: RX length > 1514byte */
	u32 reset_counter;	/* counter: RESET */
	u32 reset_tx_timeout;	/* RESET caused by TX Timeout */
	u32 reset_rx_status;	/* RESET caused by RX Statsus wrong */
	u16 tx_pkt_cnt;
	u16 queue_start_addr;
	u16 dbug_cnt;
	u8 phy_addr;
	u8 device_wait_reset;	/* device state */
	unsigned char srom[128];
	void (*outblk)(volatile void *data_ptr, int count);
	void (*inblk)(void *data_ptr, int count);
	void (*rx_status)(u16 *RxStatus, u16 *RxLen);
	struct eth_device netdev;
} board_info_t;
static board_info_t dm9000_info;


/* function declaration ------------------------------------- */
static int dm9000_probe(void);
static u16 phy_read(int);
static void phy_write(int, u16);
static u8 DM9000_ior(int);
static void DM9000_iow(int reg, u8 value);

/* DM9000 network board routine ---------------------------- */

#define DM9000_outb(d,r) outb(d, r)
#define DM9000_outw(d,r) outw(d, r)
#define DM9000_outl(d,r) outl(d, r)
#define DM9000_inb(r) inb(r)
#define DM9000_inw(r) inw(r)
#define DM9000_inl(r) inl(r)

#ifdef CONFIG_DM9000_DEBUG
static void
dump_regs(void)
{
	DM9000_DBG("\n");
	DM9000_DBG("NCR   (0x00): %02x\n", DM9000_ior(0));
	DM9000_DBG("NSR   (0x01): %02x\n", DM9000_ior(1));
	DM9000_DBG("TCR   (0x02): %02x\n", DM9000_ior(2));
	DM9000_DBG("TSRI  (0x03): %02x\n", DM9000_ior(3));
	DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
	DM9000_DBG("RCR   (0x05): %02x\n", DM9000_ior(5));
	DM9000_DBG("RSR   (0x06): %02x\n", DM9000_ior(6));
	DM9000_DBG("ISR   (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
	DM9000_DBG("\n");
}
#endif

static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
{
	int i;
	for (i = 0; i < count; i++)
		DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
}

static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
{
	int i;
	u32 tmplen = (count + 1) / 2;

	for (i = 0; i < tmplen; i++)
		DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
}
static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
{
	int i;
	u32 tmplen = (count + 3) / 4;

	for (i = 0; i < tmplen; i++)
		DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
}

static void dm9000_inblk_8bit(void *data_ptr, int count)
{
	int i;
	for (i = 0; i < count; i++)
		((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
}

static void dm9000_inblk_16bit(void *data_ptr, int count)
{
	int i;
	u32 tmplen = (count + 1) / 2;

	for (i = 0; i < tmplen; i++)
		((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
}
static void dm9000_inblk_32bit(void *data_ptr, int count)
{
	int i;
	u32 tmplen = (count + 3) / 4;

	for (i = 0; i < tmplen; i++)
		((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
}

static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
{
	u32 tmpdata;

	DM9000_outb(DM9000_MRCMD, DM9000_IO);

	tmpdata = DM9000_inl(DM9000_DATA);
	*RxStatus = __le16_to_cpu(tmpdata);
	*RxLen = __le16_to_cpu(tmpdata >> 16);
}

static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
{
	DM9000_outb(DM9000_MRCMD, DM9000_IO);

	*RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
	*RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
}

static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
{
	DM9000_outb(DM9000_MRCMD, DM9000_IO);

	*RxStatus =
	    __le16_to_cpu(DM9000_inb(DM9000_DATA) +
			  (DM9000_inb(DM9000_DATA) << 8));
	*RxLen =
	    __le16_to_cpu(DM9000_inb(DM9000_DATA) +
			  (DM9000_inb(DM9000_DATA) << 8));
}

/*
  Search DM9000 board, allocate space and register it
*/
int
dm9000_probe(void)
{
	u32 id_val;
	id_val = DM9000_ior(DM9000_VIDL);
	id_val |= DM9000_ior(DM9000_VIDH) << 8;
	id_val |= DM9000_ior(DM9000_PIDL) << 16;
	id_val |= DM9000_ior(DM9000_PIDH) << 24;
	if (id_val == DM9000_ID) {
		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
		       id_val);
		return 0;
	} else {
		printf("dm9000 not found at 0x%08x id: 0x%08x\n",
		       CONFIG_DM9000_BASE, id_val);
		return -1;
	}
}

/* General Purpose dm9000 reset routine */
static void
dm9000_reset(void)
{
	DM9000_DBG("resetting DM9000\n");

	/* Reset DM9000,
	   see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */

	/* DEBUG: Make all GPIO0 outputs, all others inputs */
	DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
	/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
	DM9000_iow(DM9000_GPR, 0);
	/* Step 2: Software reset */
	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));

	do {
		DM9000_DBG("resetting the DM9000, 1st reset\n");
		udelay(25); /* Wait at least 20 us */
	} while (DM9000_ior(DM9000_NCR) & 1);

	DM9000_iow(DM9000_NCR, 0);
	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */

	do {
		DM9000_DBG("resetting the DM9000, 2nd reset\n");
		udelay(25); /* Wait at least 20 us */
	} while (DM9000_ior(DM9000_NCR) & 1);

	/* Check whether the ethernet controller is present */
	if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
	    (DM9000_ior(DM9000_PIDH) != 0x90))
		printf("ERROR: resetting DM9000 -> not responding\n");
}

/* Initialize dm9000 board
*/
static int dm9000_init(struct eth_device *dev, bd_t *bd)
{
	int i, oft, lnk;
	u8 io_mode;
	struct board_info *db = &dm9000_info;

	DM9000_DBG("%s\n", __func__);

	/* RESET device */
	dm9000_reset();

	if (dm9000_probe() < 0)
		return -1;

	/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
	io_mode = DM9000_ior(DM9000_ISR) >> 6;

	switch (io_mode) {
	case 0x0:  /* 16-bit mode */
		printf("DM9000: running in 16 bit mode\n");
		db->outblk    = dm9000_outblk_16bit;
		db->inblk     = dm9000_inblk_16bit;
		db->rx_status = dm9000_rx_status_16bit;
		break;
	case 0x01:  /* 32-bit mode */
		printf("DM9000: running in 32 bit mode\n");
		db->outblk    = dm9000_outblk_32bit;
		db->inblk     = dm9000_inblk_32bit;
		db->rx_status = dm9000_rx_status_32bit;
		break;
	case 0x02: /* 8 bit mode */
		printf("DM9000: running in 8 bit mode\n");
		db->outblk    = dm9000_outblk_8bit;
		db->inblk     = dm9000_inblk_8bit;
		db->rx_status = dm9000_rx_status_8bit;
		break;
	default:
		/* Assume 8 bit mode, will probably not work anyway */
		printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
		db->outblk    = dm9000_outblk_8bit;
		db->inblk     = dm9000_inblk_8bit;
		db->rx_status = dm9000_rx_status_8bit;
		break;
	}

	/* Program operating register, only internal phy supported */
	DM9000_iow(DM9000_NCR, 0x0);
	/* TX Polling clear */
	DM9000_iow(DM9000_TCR, 0);
	/* Less 3Kb, 200us */
	DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
	/* Flow Control : High/Low Water */
	DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
	/* SH FIXME: This looks strange! Flow Control */
	DM9000_iow(DM9000_FCR, 0x0);
	/* Special Mode */
	DM9000_iow(DM9000_SMCR, 0);
	/* clear TX status */
	DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
	/* Clear interrupt status */
	DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);

	printf("MAC: %pM\n", dev->enetaddr);

	/* fill device MAC address registers */
	for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
		DM9000_iow(oft, dev->enetaddr[i]);
	for (i = 0, oft = 0x16; i < 8; i++, oft++)
		DM9000_iow(oft, 0xff);

	/* read back mac, just to be sure */
	for (i = 0, oft = 0x10; i < 6; i++, oft++)
		DM9000_DBG("%02x:", DM9000_ior(oft));
	DM9000_DBG("\n");

	/* Activate DM9000 */
	/* RX enable */
	DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
	/* Enable TX/RX interrupt mask */
	DM9000_iow(DM9000_IMR, IMR_PAR);

	i = 0;
	while (!(phy_read(1) & 0x20)) {	/* autonegation complete bit */
		udelay(1000);
		i++;
		if (i == 10000) {
			printf("could not establish link\n");
			return 0;
		}
	}

	/* see what we've got */
	lnk = phy_read(17) >> 12;
	printf("operating at ");
	switch (lnk) {
	case 1:
		printf("10M half duplex ");
		break;
	case 2:
		printf("10M full duplex ");
		break;
	case 4:
		printf("100M half duplex ");
		break;
	case 8:
		printf("100M full duplex ");
		break;
	default:
		printf("unknown: %d ", lnk);
		break;
	}
	printf("mode\n");
	return 0;
}

/*
  Hardware start transmission.
  Send a packet to media from the upper layer.
*/
static int dm9000_send(struct eth_device *netdev, volatile void *packet,
		     int length)
{
	int tmo;
	struct board_info *db = &dm9000_info;

	DM9000_DMP_PACKET(__func__ , packet, length);

	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */

	/* Move data to DM9000 TX RAM */
	DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */

	/* push the data to the TX-fifo */
	(db->outblk)(packet, length);

	/* Set TX length to DM9000 */
	DM9000_iow(DM9000_TXPLL, length & 0xff);
	DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);

	/* Issue TX polling command */
	DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */

	/* wait for end of transmission */
	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
		!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
		if (get_timer(0) >= tmo) {
			printf("transmission timeout\n");
			break;
		}
	}
	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */

	DM9000_DBG("transmit done\n\n");
	return 0;
}

/*
  Stop the interface.
  The interface is stopped when it is brought.
*/
static void dm9000_halt(struct eth_device *netdev)
{
	DM9000_DBG("%s\n", __func__);

	/* RESET devie */
	phy_write(0, 0x8000);	/* PHY RESET */
	DM9000_iow(DM9000_GPR, 0x01);	/* Power-Down PHY */
	DM9000_iow(DM9000_IMR, 0x80);	/* Disable all interrupt */
	DM9000_iow(DM9000_RCR, 0x00);	/* Disable RX */
}

/*
  Received a packet and pass to upper layer
*/
static int dm9000_rx(struct eth_device *netdev)
{
	u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
	u16 RxStatus, RxLen = 0;
	struct board_info *db = &dm9000_info;

	/* Check packet ready or not, we must check
	   the ISR status first for DM9000A */
	if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
		return 0;

	DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */

	/* There is _at least_ 1 package in the fifo, read them all */
	for (;;) {
		DM9000_ior(DM9000_MRCMDX);	/* Dummy read */

		/* Get most updated data,
		   only look at bits 0:1, See application notes DM9000 */
		rxbyte = DM9000_inb(DM9000_DATA) & 0x03;

		/* Status check: this byte must be 0 or 1 */
		if (rxbyte > DM9000_PKT_RDY) {
			DM9000_iow(DM9000_RCR, 0x00);	/* Stop Device */
			DM9000_iow(DM9000_ISR, 0x80);	/* Stop INT request */
			printf("DM9000 error: status check fail: 0x%x\n",
				rxbyte);
			return 0;
		}

		if (rxbyte != DM9000_PKT_RDY)
			return 0; /* No packet received, ignore */

		DM9000_DBG("receiving packet\n");

		/* A packet ready now  & Get status/length */
		(db->rx_status)(&RxStatus, &RxLen);

		DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);

		/* Move data from DM9000 */
		/* Read received packet from RX SRAM */
		(db->inblk)(rdptr, RxLen);

		if ((RxStatus & 0xbf00) || (RxLen < 0x40)
			|| (RxLen > DM9000_PKT_MAX)) {
			if (RxStatus & 0x100) {
				printf("rx fifo error\n");
			}
			if (RxStatus & 0x200) {
				printf("rx crc error\n");
			}
			if (RxStatus & 0x8000) {
				printf("rx length error\n");
			}
			if (RxLen > DM9000_PKT_MAX) {
				printf("rx length too big\n");
				dm9000_reset();
			}
		} else {
			DM9000_DMP_PACKET(__func__ , rdptr, RxLen);

			DM9000_DBG("passing packet to upper layer\n");
			NetReceive(NetRxPackets[0], RxLen);
		}
	}
	return 0;
}

/*
  Read a word data from SROM
*/
#if !defined(CONFIG_DM9000_NO_SROM)
void dm9000_read_srom_word(int offset, u8 *to)
{
	DM9000_iow(DM9000_EPAR, offset);
	DM9000_iow(DM9000_EPCR, 0x4);
	udelay(8000);
	DM9000_iow(DM9000_EPCR, 0x0);
	to[0] = DM9000_ior(DM9000_EPDRL);
	to[1] = DM9000_ior(DM9000_EPDRH);
}

void dm9000_write_srom_word(int offset, u16 val)
{
	DM9000_iow(DM9000_EPAR, offset);
	DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
	DM9000_iow(DM9000_EPDRL, (val & 0xff));
	DM9000_iow(DM9000_EPCR, 0x12);
	udelay(8000);
	DM9000_iow(DM9000_EPCR, 0);
}
#endif

static void dm9000_get_enetaddr(struct eth_device *dev)
{
#if !defined(CONFIG_DM9000_NO_SROM)
	int i;
	for (i = 0; i < 3; i++)
		dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
#endif
}

/*
   Read a byte from I/O port
*/
static u8
DM9000_ior(int reg)
{
	DM9000_outb(reg, DM9000_IO);
	return DM9000_inb(DM9000_DATA);
}

/*
   Write a byte to I/O port
*/
static void
DM9000_iow(int reg, u8 value)
{
	DM9000_outb(reg, DM9000_IO);
	DM9000_outb(value, DM9000_DATA);
}

/*
   Read a word from phyxcer
*/
static u16
phy_read(int reg)
{
	u16 val;

	/* Fill the phyxcer register into REG_0C */
	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
	DM9000_iow(DM9000_EPCR, 0xc);	/* Issue phyxcer read command */
	udelay(100);			/* Wait read complete */
	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer read command */
	val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);

	/* The read data keeps on REG_0D & REG_0E */
	DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
	return val;
}

/*
   Write a word to phyxcer
*/
static void
phy_write(int reg, u16 value)
{

	/* Fill the phyxcer register into REG_0C */
	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);

	/* Fill the written data into REG_0D & REG_0E */
	DM9000_iow(DM9000_EPDRL, (value & 0xff));
	DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
	DM9000_iow(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
	udelay(500);			/* Wait write complete */
	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */
	DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
}

int dm9000_initialize(bd_t *bis)
{
	struct eth_device *dev = &(dm9000_info.netdev);

	/* Load MAC address from EEPROM */
	dm9000_get_enetaddr(dev);

	dev->init = dm9000_init;
	dev->halt = dm9000_halt;
	dev->send = dm9000_send;
	dev->recv = dm9000_rx;
	sprintf(dev->name, "dm9000");

	eth_register(dev);

	return 0;
}
Commit	Line	Data
281e00a3 WD	1	/*
	2	dm9000.c: Version 1.2 12/15/2003
	3
	4	A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
	5	Copyright (C) 1997 Sten Wang
	6
	7	This program is free software; you can redistribute it and/or
	8	modify it under the terms of the GNU General Public License
	9	as published by the Free Software Foundation; either version 2
	10	of the License, or (at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	(C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
	18
	19	V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
53677ef1 WD	20	06/22/2001 Support DM9801 progrmming
	21	E3: R25 = ((R24 + NF) & 0x00ff) \| 0xf000
	22	E4: R25 = ((R24 + NF) & 0x00ff) \| 0xc200
	23	R17 = (R17 & 0xfff0) \| NF + 3
	24	E5: R25 = ((R24 + NF - 3) & 0x00ff) \| 0xc200
	25	R17 = (R17 & 0xfff0) \| NF
	26
	27	v1.00 modify by simon 2001.9.5
281e00a3 WD	28	change for kernel 2.4.x
281e00a3 WD	29
53677ef1	30	v1.1 11/09/2001 fix force mode bug
281e00a3 WD	31
	32	v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
	33	Fixed phy reset.
	34	Added tx/rx 32 bit mode.
	35	Cleaned up for kernel merge.
	36
	37	--------------------------------------
	38
a101361b RB	39	12/15/2003 Initial port to u-boot by
	40	Sascha Hauer <saschahauer@web.de>
	41
	42	06/03/2008 Remy Bohmer <linux@bohmer.net>
850ba755 RB	43	- Fixed the driver to work with DM9000A.
	44	(check on ISR receive status bit before reading the
	45	FIFO as described in DM9000 programming guide and
	46	application notes)
a101361b	47	- Added autodetect of databus width.
134e2662	48	- Made debug code compile again.
acba3184 RB	49	- Adapt eth_send such that it matches the DM9000*
	50	application notes. Needed to make it work properly
	51	for DM9000A.
fbcb7ece RB	52	- Adapted reset procedure to match DM9000 application
fbcb7ece RB	53	notes (i.e. double reset)
98291e2e	54	- some minor code cleanups
a101361b	55	These changes are tested with DM9000{A,EP,E} together
e5a3bc24	56	with a 200MHz Atmel AT91SAM9261 core
281e00a3	57
d26b739a	58	TODO: external MII is not functional, only internal at the moment.
281e00a3 WD	59	*/
	60
	61	#include <common.h>
	62	#include <command.h>
	63	#include <net.h>
	64	#include <asm/io.h>
e5a3bc24	65	#include <dm9000.h>
281e00a3	66
281e00a3 WD	67	#include "dm9000x.h"
	68
	69	/* Board/System/Debug information/definition ---------------- */
	70
281e00a3 WD	71	/* #define CONFIG_DM9000_DEBUG */
	72
	73	#ifdef CONFIG_DM9000_DEBUG
134e2662 RB	74	#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
	75	#define DM9000_DMP_PACKET(func,packet,length) \
	76	do { \
	77	int i; \
076cd24c	78	printf("%s: length: %d\n", func, length); \
134e2662 RB	79	for (i = 0; i < length; i++) { \
	80	if (i % 8 == 0) \
	81	printf("\n%s: %02x: ", func, i); \
	82	printf("%02x ", ((unsigned char *) packet)[i]); \
	83	} printf("\n"); \
	84	} while(0)
	85	#else
281e00a3	86	#define DM9000_DBG(fmt,args...)
134e2662 RB	87	#define DM9000_DMP_PACKET(func,packet,length)
	88	#endif
	89
281e00a3 WD	90	/* Structure/enum declaration ------------------------------- */
	91	typedef struct board_info {
	92	u32 runt_length_counter; /* counter: RX length < 64byte */
	93	u32 long_length_counter; /* counter: RX length > 1514byte */
	94	u32 reset_counter; /* counter: RESET */
	95	u32 reset_tx_timeout; /* RESET caused by TX Timeout */
	96	u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
	97	u16 tx_pkt_cnt;
	98	u16 queue_start_addr;
	99	u16 dbug_cnt;
	100	u8 phy_addr;
	101	u8 device_wait_reset; /* device state */
281e00a3	102	unsigned char srom[128];
0e38c938	103	void (outblk)(volatile void data_ptr, int count);
a101361b RB	104	void (inblk)(void data_ptr, int count);
a101361b RB	105	void (rx_status)(u16 RxStatus, u16 *RxLen);
60f61e6d	106	struct eth_device netdev;
98291e2e	107	} board_info_t;
a101361b	108	static board_info_t dm9000_info;
281e00a3	109
60f61e6d	110
281e00a3	111	/* function declaration ------------------------------------- */
281e00a3 WD	112	static int dm9000_probe(void);
	113	static u16 phy_read(int);
	114	static void phy_write(int, u16);
281e00a3 WD	115	static u8 DM9000_ior(int);
	116	static void DM9000_iow(int reg, u8 value);
	117
	118	/* DM9000 network board routine ---------------------------- */
	119
a45dde22 MF	120	#define DM9000_outb(d,r) outb(d, r)
	121	#define DM9000_outw(d,r) outw(d, r)
	122	#define DM9000_outl(d,r) outl(d, r)
	123	#define DM9000_inb(r) inb(r)
	124	#define DM9000_inw(r) inw(r)
	125	#define DM9000_inl(r) inl(r)
281e00a3 WD	126
	127	#ifdef CONFIG_DM9000_DEBUG
	128	static void
	129	dump_regs(void)
	130	{
	131	DM9000_DBG("\n");
	132	DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
	133	DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
	134	DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
	135	DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
	136	DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
	137	DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
	138	DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
134e2662	139	DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
281e00a3 WD	140	DM9000_DBG("\n");
281e00a3 WD	141	}
a101361b RB	142	#endif
a101361b RB	143
0e38c938	144	static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
a101361b RB	145	{
	146	int i;
	147	for (i = 0; i < count; i++)
	148	DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
	149	}
	150
0e38c938	151	static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
a101361b RB	152	{
	153	int i;
	154	u32 tmplen = (count + 1) / 2;
	155
	156	for (i = 0; i < tmplen; i++)
	157	DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
	158	}
0e38c938	159	static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
a101361b RB	160	{
	161	int i;
	162	u32 tmplen = (count + 3) / 4;
	163
	164	for (i = 0; i < tmplen; i++)
	165	DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
	166	}
	167
	168	static void dm9000_inblk_8bit(void *data_ptr, int count)
	169	{
	170	int i;
	171	for (i = 0; i < count; i++)
	172	((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
	173	}
	174
	175	static void dm9000_inblk_16bit(void *data_ptr, int count)
	176	{
	177	int i;
	178	u32 tmplen = (count + 1) / 2;
	179
	180	for (i = 0; i < tmplen; i++)
	181	((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
	182	}
	183	static void dm9000_inblk_32bit(void *data_ptr, int count)
	184	{
	185	int i;
	186	u32 tmplen = (count + 3) / 4;
	187
	188	for (i = 0; i < tmplen; i++)
	189	((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
	190	}
	191
	192	static void dm9000_rx_status_32bit(u16 RxStatus, u16 RxLen)
	193	{
d6ee5fa4	194	u32 tmpdata;
a101361b RB	195
	196	DM9000_outb(DM9000_MRCMD, DM9000_IO);
	197
d6ee5fa4	198	tmpdata = DM9000_inl(DM9000_DATA);
943b825b TL	199	*RxStatus = __le16_to_cpu(tmpdata);
943b825b TL	200	*RxLen = __le16_to_cpu(tmpdata >> 16);
a101361b RB	201	}
	202
	203	static void dm9000_rx_status_16bit(u16 RxStatus, u16 RxLen)
	204	{
	205	DM9000_outb(DM9000_MRCMD, DM9000_IO);
	206
943b825b TL	207	*RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
943b825b TL	208	*RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
a101361b RB	209	}
	210
	211	static void dm9000_rx_status_8bit(u16 RxStatus, u16 RxLen)
	212	{
	213	DM9000_outb(DM9000_MRCMD, DM9000_IO);
	214
943b825b TL	215	*RxStatus =
	216	__le16_to_cpu(DM9000_inb(DM9000_DATA) +
	217	(DM9000_inb(DM9000_DATA) << 8));
	218	*RxLen =
	219	__le16_to_cpu(DM9000_inb(DM9000_DATA) +
	220	(DM9000_inb(DM9000_DATA) << 8));
a101361b	221	}
281e00a3 WD	222
	223	/*
	224	Search DM9000 board, allocate space and register it
	225	*/
	226	int
	227	dm9000_probe(void)
	228	{
	229	u32 id_val;
	230	id_val = DM9000_ior(DM9000_VIDL);
	231	id_val \|= DM9000_ior(DM9000_VIDH) << 8;
	232	id_val \|= DM9000_ior(DM9000_PIDL) << 16;
	233	id_val \|= DM9000_ior(DM9000_PIDH) << 24;
	234	if (id_val == DM9000_ID) {
	235	printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
	236	id_val);
	237	return 0;
	238	} else {
	239	printf("dm9000 not found at 0x%08x id: 0x%08x\n",
	240	CONFIG_DM9000_BASE, id_val);
	241	return -1;
	242	}
	243	}
	244
281e00a3 WD	245	/* General Purpose dm9000 reset routine */
	246	static void
	247	dm9000_reset(void)
	248	{
fbcb7ece RB	249	DM9000_DBG("resetting DM9000\n");
	250
	251	/* Reset DM9000,
	252	see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
	253
d26b739a AD	254	/* DEBUG: Make all GPIO0 outputs, all others inputs */
d26b739a AD	255	DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
fbcb7ece RB	256	/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
	257	DM9000_iow(DM9000_GPR, 0);
	258	/* Step 2: Software reset */
d26b739a	259	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC \| NCR_RST));
fbcb7ece RB	260
	261	do {
	262	DM9000_DBG("resetting the DM9000, 1st reset\n");
	263	udelay(25); /* Wait at least 20 us */
	264	} while (DM9000_ior(DM9000_NCR) & 1);
	265
	266	DM9000_iow(DM9000_NCR, 0);
d26b739a	267	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC \| NCR_RST)); /* Issue a second reset */
fbcb7ece RB	268
	269	do {
	270	DM9000_DBG("resetting the DM9000, 2nd reset\n");
	271	udelay(25); /* Wait at least 20 us */
	272	} while (DM9000_ior(DM9000_NCR) & 1);
	273
	274	/* Check whether the ethernet controller is present */
	275	if ((DM9000_ior(DM9000_PIDL) != 0x0) \|\|
	276	(DM9000_ior(DM9000_PIDH) != 0x90))
	277	printf("ERROR: resetting DM9000 -> not responding\n");
281e00a3 WD	278	}
281e00a3 WD	279
60f61e6d	280	/* Initialize dm9000 board
281e00a3	281	*/
60f61e6d	282	static int dm9000_init(struct eth_device dev, bd_t bd)
281e00a3 WD	283	{
281e00a3 WD	284	int i, oft, lnk;
a101361b RB	285	u8 io_mode;
	286	struct board_info *db = &dm9000_info;
	287
60f61e6d	288	DM9000_DBG("%s\n", __func__);
281e00a3 WD	289
	290	/* RESET device */
	291	dm9000_reset();
d26b739a AD	292
	293	if (dm9000_probe() < 0)
	294	return -1;
281e00a3	295
a101361b RB	296	/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
	297	io_mode = DM9000_ior(DM9000_ISR) >> 6;
	298
	299	switch (io_mode) {
	300	case 0x0: /* 16-bit mode */
	301	printf("DM9000: running in 16 bit mode\n");
	302	db->outblk = dm9000_outblk_16bit;
	303	db->inblk = dm9000_inblk_16bit;
	304	db->rx_status = dm9000_rx_status_16bit;
	305	break;
	306	case 0x01: /* 32-bit mode */
	307	printf("DM9000: running in 32 bit mode\n");
	308	db->outblk = dm9000_outblk_32bit;
	309	db->inblk = dm9000_inblk_32bit;
	310	db->rx_status = dm9000_rx_status_32bit;
	311	break;
	312	case 0x02: /* 8 bit mode */
	313	printf("DM9000: running in 8 bit mode\n");
	314	db->outblk = dm9000_outblk_8bit;
	315	db->inblk = dm9000_inblk_8bit;
	316	db->rx_status = dm9000_rx_status_8bit;
	317	break;
	318	default:
	319	/* Assume 8 bit mode, will probably not work anyway */
	320	printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
	321	db->outblk = dm9000_outblk_8bit;
	322	db->inblk = dm9000_inblk_8bit;
	323	db->rx_status = dm9000_rx_status_8bit;
	324	break;
	325	}
	326
d26b739a	327	/* Program operating register, only internal phy supported */
98291e2e RB	328	DM9000_iow(DM9000_NCR, 0x0);
	329	/* TX Polling clear */
	330	DM9000_iow(DM9000_TCR, 0);
	331	/* Less 3Kb, 200us */
d26b739a	332	DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) \| BPTR_JPT_600US);
98291e2e RB	333	/* Flow Control : High/Low Water */
	334	DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) \| FCTR_LWOT(8));
	335	/* SH FIXME: This looks strange! Flow Control */
	336	DM9000_iow(DM9000_FCR, 0x0);
	337	/* Special Mode */
	338	DM9000_iow(DM9000_SMCR, 0);
	339	/* clear TX status */
	340	DM9000_iow(DM9000_NSR, NSR_WAKEST \| NSR_TX2END \| NSR_TX1END);
	341	/* Clear interrupt status */
d26b739a	342	DM9000_iow(DM9000_ISR, ISR_ROOS \| ISR_ROS \| ISR_PTS \| ISR_PRS);
281e00a3	343
07754372	344	printf("MAC: %pM\n", dev->enetaddr);
d26b739a AD	345
	346	/* fill device MAC address registers */
	347	for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
07754372	348	DM9000_iow(oft, dev->enetaddr[i]);
281e00a3 WD	349	for (i = 0, oft = 0x16; i < 8; i++, oft++)
	350	DM9000_iow(oft, 0xff);
	351
	352	/* read back mac, just to be sure */
	353	for (i = 0, oft = 0x10; i < 6; i++, oft++)
	354	DM9000_DBG("%02x:", DM9000_ior(oft));
	355	DM9000_DBG("\n");
	356
	357	/* Activate DM9000 */
98291e2e RB	358	/* RX enable */
	359	DM9000_iow(DM9000_RCR, RCR_DIS_LONG \| RCR_DIS_CRC \| RCR_RXEN);
	360	/* Enable TX/RX interrupt mask */
	361	DM9000_iow(DM9000_IMR, IMR_PAR);
	362
281e00a3 WD	363	i = 0;
	364	while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
	365	udelay(1000);
	366	i++;
	367	if (i == 10000) {
	368	printf("could not establish link\n");
	369	return 0;
	370	}
	371	}
	372
	373	/* see what we've got */
	374	lnk = phy_read(17) >> 12;
	375	printf("operating at ");
	376	switch (lnk) {
	377	case 1:
	378	printf("10M half duplex ");
	379	break;
	380	case 2:
	381	printf("10M full duplex ");
	382	break;
	383	case 4:
	384	printf("100M half duplex ");
	385	break;
	386	case 8:
	387	printf("100M full duplex ");
	388	break;
	389	default:
	390	printf("unknown: %d ", lnk);
	391	break;
	392	}
	393	printf("mode\n");
	394	return 0;
	395	}
	396
	397	/*
	398	Hardware start transmission.
	399	Send a packet to media from the upper layer.
	400	*/
60f61e6d RB	401	static int dm9000_send(struct eth_device netdev, volatile void packet,
60f61e6d RB	402	int length)
281e00a3	403	{
281e00a3	404	int tmo;
a101361b RB	405	struct board_info *db = &dm9000_info;
a101361b RB	406
60f61e6d	407	DM9000_DMP_PACKET(__func__ , packet, length);
281e00a3	408
acba3184 RB	409	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
acba3184 RB	410
281e00a3	411	/* Move data to DM9000 TX RAM */
acba3184	412	DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
281e00a3	413
a101361b	414	/* push the data to the TX-fifo */
0e38c938	415	(db->outblk)(packet, length);
281e00a3 WD	416
	417	/* Set TX length to DM9000 */
	418	DM9000_iow(DM9000_TXPLL, length & 0xff);
	419	DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
	420
	421	/* Issue TX polling command */
acba3184	422	DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
281e00a3 WD	423
281e00a3 WD	424	/* wait for end of transmission */
6d0f6bcf	425	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
acba3184 RB	426	while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END \| NSR_TX2END)) \|\|
acba3184 RB	427	!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
281e00a3 WD	428	if (get_timer(0) >= tmo) {
	429	printf("transmission timeout\n");
	430	break;
	431	}
	432	}
acba3184 RB	433	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
acba3184 RB	434
281e00a3 WD	435	DM9000_DBG("transmit done\n\n");
	436	return 0;
	437	}
	438
	439	/*
	440	Stop the interface.
	441	The interface is stopped when it is brought.
	442	*/
60f61e6d	443	static void dm9000_halt(struct eth_device *netdev)
281e00a3	444	{
60f61e6d	445	DM9000_DBG("%s\n", __func__);
281e00a3 WD	446
	447	/* RESET devie */
	448	phy_write(0, 0x8000); /* PHY RESET */
	449	DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
	450	DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
	451	DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
	452	}
	453
	454	/*
	455	Received a packet and pass to upper layer
	456	*/
60f61e6d	457	static int dm9000_rx(struct eth_device *netdev)
281e00a3 WD	458	{
	459	u8 rxbyte, rdptr = (u8 ) NetRxPackets[0];
	460	u16 RxStatus, RxLen = 0;
a101361b	461	struct board_info *db = &dm9000_info;
281e00a3	462
850ba755 RB	463	/* Check packet ready or not, we must check
	464	the ISR status first for DM9000A */
	465	if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
281e00a3 WD	466	return 0;
281e00a3 WD	467
850ba755	468	DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
281e00a3	469
850ba755 RB	470	/* There is _at least_ 1 package in the fifo, read them all */
	471	for (;;) {
	472	DM9000_ior(DM9000_MRCMDX); /* Dummy read */
281e00a3	473
0e38c938 RB	474	/* Get most updated data,
	475	only look at bits 0:1, See application notes DM9000 */
	476	rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
281e00a3	477
850ba755 RB	478	/* Status check: this byte must be 0 or 1 */
	479	if (rxbyte > DM9000_PKT_RDY) {
	480	DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
	481	DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
	482	printf("DM9000 error: status check fail: 0x%x\n",
	483	rxbyte);
	484	return 0;
	485	}
281e00a3	486
850ba755 RB	487	if (rxbyte != DM9000_PKT_RDY)
	488	return 0; /* No packet received, ignore */
	489
	490	DM9000_DBG("receiving packet\n");
	491
	492	/* A packet ready now & Get status/length */
	493	(db->rx_status)(&RxStatus, &RxLen);
	494
	495	DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
	496
	497	/* Move data from DM9000 */
	498	/* Read received packet from RX SRAM */
	499	(db->inblk)(rdptr, RxLen);
	500
	501	if ((RxStatus & 0xbf00) \|\| (RxLen < 0x40)
	502	\|\| (RxLen > DM9000_PKT_MAX)) {
	503	if (RxStatus & 0x100) {
	504	printf("rx fifo error\n");
	505	}
	506	if (RxStatus & 0x200) {
	507	printf("rx crc error\n");
	508	}
	509	if (RxStatus & 0x8000) {
	510	printf("rx length error\n");
	511	}
	512	if (RxLen > DM9000_PKT_MAX) {
	513	printf("rx length too big\n");
	514	dm9000_reset();
	515	}
	516	} else {
60f61e6d	517	DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
281e00a3	518
850ba755 RB	519	DM9000_DBG("passing packet to upper layer\n");
850ba755 RB	520	NetReceive(NetRxPackets[0], RxLen);
281e00a3	521	}
281e00a3 WD	522	}
	523	return 0;
	524	}
	525
	526	/*
	527	Read a word data from SROM
	528	*/
e5a3bc24 RB	529	#if !defined(CONFIG_DM9000_NO_SROM)
e5a3bc24 RB	530	void dm9000_read_srom_word(int offset, u8 *to)
281e00a3 WD	531	{
	532	DM9000_iow(DM9000_EPAR, offset);
	533	DM9000_iow(DM9000_EPCR, 0x4);
5f470948	534	udelay(8000);
281e00a3	535	DM9000_iow(DM9000_EPCR, 0x0);
ad74cae9 DB	536	to[0] = DM9000_ior(DM9000_EPDRL);
ad74cae9 DB	537	to[1] = DM9000_ior(DM9000_EPDRH);
281e00a3 WD	538	}
281e00a3 WD	539
e5a3bc24	540	void dm9000_write_srom_word(int offset, u16 val)
5e5803e1 SB	541	{
	542	DM9000_iow(DM9000_EPAR, offset);
	543	DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
	544	DM9000_iow(DM9000_EPDRL, (val & 0xff));
	545	DM9000_iow(DM9000_EPCR, 0x12);
	546	udelay(8000);
	547	DM9000_iow(DM9000_EPCR, 0);
	548	}
e5a3bc24	549	#endif
5e5803e1	550
07754372 BW	551	static void dm9000_get_enetaddr(struct eth_device *dev)
	552	{
	553	#if !defined(CONFIG_DM9000_NO_SROM)
	554	int i;
	555	for (i = 0; i < 3; i++)
	556	dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
	557	#endif
	558	}
	559
281e00a3 WD	560	/*
	561	Read a byte from I/O port
	562	*/
	563	static u8
	564	DM9000_ior(int reg)
	565	{
	566	DM9000_outb(reg, DM9000_IO);
	567	return DM9000_inb(DM9000_DATA);
	568	}
	569
	570	/*
	571	Write a byte to I/O port
	572	*/
	573	static void
	574	DM9000_iow(int reg, u8 value)
	575	{
	576	DM9000_outb(reg, DM9000_IO);
	577	DM9000_outb(value, DM9000_DATA);
	578	}
	579
	580	/*
	581	Read a word from phyxcer
	582	*/
	583	static u16
	584	phy_read(int reg)
	585	{
	586	u16 val;
	587
	588	/* Fill the phyxcer register into REG_0C */
	589	DM9000_iow(DM9000_EPAR, DM9000_PHY \| reg);
	590	DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
98291e2e	591	udelay(100); /* Wait read complete */
281e00a3 WD	592	DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
	593	val = (DM9000_ior(DM9000_EPDRH) << 8) \| DM9000_ior(DM9000_EPDRL);
	594
	595	/* The read data keeps on REG_0D & REG_0E */
134e2662	596	DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
281e00a3 WD	597	return val;
	598	}
	599
	600	/*
	601	Write a word to phyxcer
	602	*/
	603	static void
	604	phy_write(int reg, u16 value)
	605	{
	606
	607	/* Fill the phyxcer register into REG_0C */
	608	DM9000_iow(DM9000_EPAR, DM9000_PHY \| reg);
	609
	610	/* Fill the written data into REG_0D & REG_0E */
	611	DM9000_iow(DM9000_EPDRL, (value & 0xff));
	612	DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
	613	DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
98291e2e	614	udelay(500); /* Wait write complete */
281e00a3	615	DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
134e2662	616	DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
281e00a3	617	}
60f61e6d RB	618
	619	int dm9000_initialize(bd_t *bis)
	620	{
	621	struct eth_device *dev = &(dm9000_info.netdev);
	622
07754372 BW	623	/* Load MAC address from EEPROM */
	624	dm9000_get_enetaddr(dev);
	625
60f61e6d RB	626	dev->init = dm9000_init;
	627	dev->halt = dm9000_halt;
	628	dev->send = dm9000_send;
	629	dev->recv = dm9000_rx;
	630	sprintf(dev->name, "dm9000");
	631
	632	eth_register(dev);
	633
	634	return 0;
	635	}