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Merge tag 'drm/tegra/for-5.7-fixes' of git://anongit.freedesktop.org/tegra/linux...
[thirdparty/linux.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
b8f126a8
SW		 13#include <linux/of_mdio.h>
14#include <linux/of_net.h>
15#include <linux/of_platform.h>
ca366d6c 16#include <linux/phylink.h>
b8f126a8
SW		 17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
eb976a55 20#include <linux/gpio/consumer.h>
b8f126a8 21#include <net/dsa.h>
b8f126a8
SW		 22
23#include "mt7530.h"
24
25/* String, offset, and register size in bytes if different from 4 bytes */
26static const struct mt7530_mib_desc mt7530_mib[] = {
27 MIB_DESC(1, 0x00, "TxDrop"),
28 MIB_DESC(1, 0x04, "TxCrcErr"),
29 MIB_DESC(1, 0x08, "TxUnicast"),
30 MIB_DESC(1, 0x0c, "TxMulticast"),
31 MIB_DESC(1, 0x10, "TxBroadcast"),
32 MIB_DESC(1, 0x14, "TxCollision"),
33 MIB_DESC(1, 0x18, "TxSingleCollision"),
34 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
35 MIB_DESC(1, 0x20, "TxDeferred"),
36 MIB_DESC(1, 0x24, "TxLateCollision"),
37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
38 MIB_DESC(1, 0x2c, "TxPause"),
39 MIB_DESC(1, 0x30, "TxPktSz64"),
40 MIB_DESC(1, 0x34, "TxPktSz65To127"),
41 MIB_DESC(1, 0x38, "TxPktSz128To255"),
42 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
43 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
44 MIB_DESC(1, 0x44, "Tx1024ToMax"),
45 MIB_DESC(2, 0x48, "TxBytes"),
46 MIB_DESC(1, 0x60, "RxDrop"),
47 MIB_DESC(1, 0x64, "RxFiltering"),
48 MIB_DESC(1, 0x6c, "RxMulticast"),
49 MIB_DESC(1, 0x70, "RxBroadcast"),
50 MIB_DESC(1, 0x74, "RxAlignErr"),
51 MIB_DESC(1, 0x78, "RxCrcErr"),
52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
53 MIB_DESC(1, 0x80, "RxFragErr"),
54 MIB_DESC(1, 0x84, "RxOverSzErr"),
55 MIB_DESC(1, 0x88, "RxJabberErr"),
56 MIB_DESC(1, 0x8c, "RxPause"),
57 MIB_DESC(1, 0x90, "RxPktSz64"),
58 MIB_DESC(1, 0x94, "RxPktSz65To127"),
59 MIB_DESC(1, 0x98, "RxPktSz128To255"),
60 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
63 MIB_DESC(2, 0xa8, "RxBytes"),
64 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
65 MIB_DESC(1, 0xb4, "RxIngressDrop"),
66 MIB_DESC(1, 0xb8, "RxArlDrop"),
67};
68
b8f126a8
SW		 69static int
70core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
71{
72 struct mii_bus *bus = priv->bus;
73 int value, ret;
74
75 /* Write the desired MMD Devad */
76 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
77 if (ret < 0)
78 goto err;
79
80 /* Write the desired MMD register address */
81 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
82 if (ret < 0)
83 goto err;
84
85 /* Select the Function : DATA with no post increment */
86 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
87 if (ret < 0)
88 goto err;
89
90 /* Read the content of the MMD's selected register */
91 value = bus->read(bus, 0, MII_MMD_DATA);
92
93 return value;
94err:
95 dev_err(&bus->dev, "failed to read mmd register\n");
96
97 return ret;
98}
99
100static int
101core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
102 int devad, u32 data)
103{
104 struct mii_bus *bus = priv->bus;
105 int ret;
106
107 /* Write the desired MMD Devad */
108 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
109 if (ret < 0)
110 goto err;
111
112 /* Write the desired MMD register address */
113 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
114 if (ret < 0)
115 goto err;
116
117 /* Select the Function : DATA with no post increment */
118 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
119 if (ret < 0)
120 goto err;
121
122 /* Write the data into MMD's selected register */
123 ret = bus->write(bus, 0, MII_MMD_DATA, data);
124err:
125 if (ret < 0)
126 dev_err(&bus->dev,
127 "failed to write mmd register\n");
128 return ret;
129}
130
131static void
132core_write(struct mt7530_priv *priv, u32 reg, u32 val)
133{
134 struct mii_bus *bus = priv->bus;
135
136 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
137
138 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
139
140 mutex_unlock(&bus->mdio_lock);
141}
142
143static void
144core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
145{
146 struct mii_bus *bus = priv->bus;
147 u32 val;
148
149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
150
151 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
152 val &= ~mask;
153 val |= set;
154 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
155
156 mutex_unlock(&bus->mdio_lock);
157}
158
159static void
160core_set(struct mt7530_priv *priv, u32 reg, u32 val)
161{
162 core_rmw(priv, reg, 0, val);
163}
164
165static void
166core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
167{
168 core_rmw(priv, reg, val, 0);
169}
170
171static int
172mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
173{
174 struct mii_bus *bus = priv->bus;
175 u16 page, r, lo, hi;
176 int ret;
177
178 page = (reg >> 6) & 0x3ff;
179 r = (reg >> 2) & 0xf;
180 lo = val & 0xffff;
181 hi = val >> 16;
182
183 /* MT7530 uses 31 as the pseudo port */
184 ret = bus->write(bus, 0x1f, 0x1f, page);
185 if (ret < 0)
186 goto err;
187
188 ret = bus->write(bus, 0x1f, r, lo);
189 if (ret < 0)
190 goto err;
191
192 ret = bus->write(bus, 0x1f, 0x10, hi);
193err:
194 if (ret < 0)
195 dev_err(&bus->dev,
196 "failed to write mt7530 register\n");
197 return ret;
198}
199
200static u32
201mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
202{
203 struct mii_bus *bus = priv->bus;
204 u16 page, r, lo, hi;
205 int ret;
206
207 page = (reg >> 6) & 0x3ff;
208 r = (reg >> 2) & 0xf;
209
210 /* MT7530 uses 31 as the pseudo port */
211 ret = bus->write(bus, 0x1f, 0x1f, page);
212 if (ret < 0) {
213 dev_err(&bus->dev,
214 "failed to read mt7530 register\n");
215 return ret;
216 }
217
218 lo = bus->read(bus, 0x1f, r);
219 hi = bus->read(bus, 0x1f, 0x10);
220
221 return (hi << 16) | (lo & 0xffff);
222}
223
224static void
225mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
226{
227 struct mii_bus *bus = priv->bus;
228
229 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
230
231 mt7530_mii_write(priv, reg, val);
232
233 mutex_unlock(&bus->mdio_lock);
234}
235
236static u32
237_mt7530_read(struct mt7530_dummy_poll *p)
238{
239 struct mii_bus *bus = p->priv->bus;
240 u32 val;
241
242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
243
244 val = mt7530_mii_read(p->priv, p->reg);
245
246 mutex_unlock(&bus->mdio_lock);
247
248 return val;
249}
250
251static u32
252mt7530_read(struct mt7530_priv *priv, u32 reg)
253{
254 struct mt7530_dummy_poll p;
255
256 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
257 return _mt7530_read(&p);
258}
259
260static void
261mt7530_rmw(struct mt7530_priv *priv, u32 reg,
262 u32 mask, u32 set)
263{
264 struct mii_bus *bus = priv->bus;
265 u32 val;
266
267 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
268
269 val = mt7530_mii_read(priv, reg);
270 val &= ~mask;
271 val |= set;
272 mt7530_mii_write(priv, reg, val);
273
274 mutex_unlock(&bus->mdio_lock);
275}
276
277static void
278mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
279{
280 mt7530_rmw(priv, reg, 0, val);
281}
282
283static void
284mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
285{
286 mt7530_rmw(priv, reg, val, 0);
287}
288
289static int
290mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
291{
292 u32 val;
293 int ret;
294 struct mt7530_dummy_poll p;
295
296 /* Set the command operating upon the MAC address entries */
297 val = ATC_BUSY | ATC_MAT(0) | cmd;
298 mt7530_write(priv, MT7530_ATC, val);
299
300 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
301 ret = readx_poll_timeout(_mt7530_read, &p, val,
302 !(val & ATC_BUSY), 20, 20000);
303 if (ret < 0) {
304 dev_err(priv->dev, "reset timeout\n");
305 return ret;
306 }
307
308 /* Additional sanity for read command if the specified
309 * entry is invalid
310 */
311 val = mt7530_read(priv, MT7530_ATC);
312 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
313 return -EINVAL;
314
315 if (rsp)
316 *rsp = val;
317
318 return 0;
319}
320
321static void
322mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
323{
324 u32 reg[3];
325 int i;
326
327 /* Read from ARL table into an array */
328 for (i = 0; i < 3; i++) {
329 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
330
331 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
332 __func__, __LINE__, i, reg[i]);
333 }
334
335 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
336 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
337 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
338 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
339 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
340 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
341 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
342 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
343 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
344 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
345}
346
347static void
348mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
349 u8 port_mask, const u8 *mac,
350 u8 aging, u8 type)
351{
352 u32 reg[3] = { 0 };
353 int i;
354
355 reg[1] |= vid & CVID_MASK;
356 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
357 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
358 /* STATIC_ENT indicate that entry is static wouldn't
359 * be aged out and STATIC_EMP specified as erasing an
360 * entry
361 */
362 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
363 reg[1] |= mac[5] << MAC_BYTE_5;
364 reg[1] |= mac[4] << MAC_BYTE_4;
365 reg[0] |= mac[3] << MAC_BYTE_3;
366 reg[0] |= mac[2] << MAC_BYTE_2;
367 reg[0] |= mac[1] << MAC_BYTE_1;
368 reg[0] |= mac[0] << MAC_BYTE_0;
369
370 /* Write array into the ARL table */
371 for (i = 0; i < 3; i++)
372 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
373}
374
375static int
376mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
377{
378 struct mt7530_priv *priv = ds->priv;
7ef6f6f8
RD		 379 u32 ncpo1, ssc_delta, trgint, i, xtal;
380
381 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
382
383 if (xtal == HWTRAP_XTAL_20MHZ) {
384 dev_err(priv->dev,
385 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
386 __func__);
387 return -EINVAL;
388 }
b8f126a8
SW		 389
390 switch (mode) {
391 case PHY_INTERFACE_MODE_RGMII:
392 trgint = 0;
7ef6f6f8 393 /* PLL frequency: 125MHz */
b8f126a8 394 ncpo1 = 0x0c80;
b8f126a8
SW		 395 break;
396 case PHY_INTERFACE_MODE_TRGMII:
397 trgint = 1;
7ef6f6f8
RD		 398 if (priv->id == ID_MT7621) {
399 /* PLL frequency: 150MHz: 1.2GBit */
400 if (xtal == HWTRAP_XTAL_40MHZ)
401 ncpo1 = 0x0780;
402 if (xtal == HWTRAP_XTAL_25MHZ)
403 ncpo1 = 0x0a00;
404 } else { /* PLL frequency: 250MHz: 2.0Gbit */
405 if (xtal == HWTRAP_XTAL_40MHZ)
406 ncpo1 = 0x0c80;
407 if (xtal == HWTRAP_XTAL_25MHZ)
408 ncpo1 = 0x1400;
409 }
b8f126a8
SW		 410 break;
411 default:
412 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
413 return -EINVAL;
414 }
415
7ef6f6f8
RD		 416 if (xtal == HWTRAP_XTAL_25MHZ)
417 ssc_delta = 0x57;
418 else
419 ssc_delta = 0x87;
420
b8f126a8
SW		 421 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
422 P6_INTF_MODE(trgint));
423
424 /* Lower Tx Driving for TRGMII path */
425 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
426 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
427 TD_DM_DRVP(8) | TD_DM_DRVN(8));
428
429 /* Setup core clock for MT7530 */
430 if (!trgint) {
431 /* Disable MT7530 core clock */
432 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
433
434 /* Disable PLL, since phy_device has not yet been created
435 * provided for phy_[read,write]_mmd_indirect is called, we
436 * provide our own core_write_mmd_indirect to complete this
437 * function.
438 */
439 core_write_mmd_indirect(priv,
440 CORE_GSWPLL_GRP1,
441 MDIO_MMD_VEND2,
442 0);
443
444 /* Set core clock into 500Mhz */
445 core_write(priv, CORE_GSWPLL_GRP2,
446 RG_GSWPLL_POSDIV_500M(1) |
447 RG_GSWPLL_FBKDIV_500M(25));
448
449 /* Enable PLL */
450 core_write(priv, CORE_GSWPLL_GRP1,
451 RG_GSWPLL_EN_PRE |
452 RG_GSWPLL_POSDIV_200M(2) |
453 RG_GSWPLL_FBKDIV_200M(32));
454
455 /* Enable MT7530 core clock */
456 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
457 }
458
459 /* Setup the MT7530 TRGMII Tx Clock */
460 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
461 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
462 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
463 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
464 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
465 core_write(priv, CORE_PLL_GROUP4,
466 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
467 RG_SYSPLL_BIAS_LPF_EN);
468 core_write(priv, CORE_PLL_GROUP2,
469 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
470 RG_SYSPLL_POSDIV(1));
471 core_write(priv, CORE_PLL_GROUP7,
472 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
473 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
474 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
475 REG_GSWCK_EN | REG_TRGMIICK_EN);
476
477 if (!trgint)
478 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
479 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
480 RD_TAP_MASK, RD_TAP(16));
b8f126a8
SW		 481 return 0;
482}
483
484static void
485mt7530_mib_reset(struct dsa_switch *ds)
486{
487 struct mt7530_priv *priv = ds->priv;
488
489 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
490 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
491}
492
b8f126a8
SW		 493static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
494{
495 struct mt7530_priv *priv = ds->priv;
496
497 return mdiobus_read_nested(priv->bus, port, regnum);
498}
499
360cc342
CIK		 500static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
501 u16 val)
b8f126a8
SW		 502{
503 struct mt7530_priv *priv = ds->priv;
504
505 return mdiobus_write_nested(priv->bus, port, regnum, val);
506}
507
508static void
89f09048
FF		 509mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
510 uint8_t *data)
b8f126a8
SW		 511{
512 int i;
513
89f09048
FF		 514 if (stringset != ETH_SS_STATS)
515 return;
516
b8f126a8
SW		 517 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
518 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
519 ETH_GSTRING_LEN);
520}
521
522static void
523mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
524 uint64_t *data)
525{
526 struct mt7530_priv *priv = ds->priv;
527 const struct mt7530_mib_desc *mib;
528 u32 reg, i;
529 u64 hi;
530
531 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
532 mib = &mt7530_mib[i];
533 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
534
535 data[i] = mt7530_read(priv, reg);
536 if (mib->size == 2) {
537 hi = mt7530_read(priv, reg + 4);
538 data[i] |= hi << 32;
539 }
540 }
541}
542
543static int
89f09048 544mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 545{
89f09048
FF		 546 if (sset != ETH_SS_STATS)
547 return 0;
548
b8f126a8
SW		 549 return ARRAY_SIZE(mt7530_mib);
550}
551
38f790a8
RD		 552static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
553{
554 struct mt7530_priv *priv = ds->priv;
555 u8 tx_delay = 0;
556 int val;
557
558 mutex_lock(&priv->reg_mutex);
559
560 val = mt7530_read(priv, MT7530_MHWTRAP);
561
562 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
563 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
564
565 switch (priv->p5_intf_sel) {
566 case P5_INTF_SEL_PHY_P0:
567 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
568 val |= MHWTRAP_PHY0_SEL;
569 /* fall through */
570 case P5_INTF_SEL_PHY_P4:
571 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
572 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
573
574 /* Setup the MAC by default for the cpu port */
575 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
576 break;
577 case P5_INTF_SEL_GMAC5:
578 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
579 val &= ~MHWTRAP_P5_DIS;
580 break;
581 case P5_DISABLED:
582 interface = PHY_INTERFACE_MODE_NA;
583 break;
584 default:
585 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
586 priv->p5_intf_sel);
587 goto unlock_exit;
588 }
589
590 /* Setup RGMII settings */
591 if (phy_interface_mode_is_rgmii(interface)) {
592 val |= MHWTRAP_P5_RGMII_MODE;
593
594 /* P5 RGMII RX Clock Control: delay setting for 1000M */
595 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
596
597 /* Don't set delay in DSA mode */
598 if (!dsa_is_dsa_port(priv->ds, 5) &&
599 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
600 interface == PHY_INTERFACE_MODE_RGMII_ID))
601 tx_delay = 4; /* n * 0.5 ns */
602
603 /* P5 RGMII TX Clock Control: delay x */
604 mt7530_write(priv, MT7530_P5RGMIITXCR,
605 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
606
607 /* reduce P5 RGMII Tx driving, 8mA */
608 mt7530_write(priv, MT7530_IO_DRV_CR,
609 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
610 }
611
612 mt7530_write(priv, MT7530_MHWTRAP, val);
613
614 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
615 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
616
617 priv->p5_interface = interface;
618
619unlock_exit:
620 mutex_unlock(&priv->reg_mutex);
621}
622
b8f126a8
SW		 623static int
624mt7530_cpu_port_enable(struct mt7530_priv *priv,
625 int port)
626{
627 /* Enable Mediatek header mode on the cpu port */
628 mt7530_write(priv, MT7530_PVC_P(port),
629 PORT_SPEC_TAG);
630
b8f126a8
SW		 631 /* Disable auto learning on the cpu port */
632 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
633
634 /* Unknown unicast frame fordwarding to the cpu port */
635 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
636
ddda1ac1
GU		 637 /* Set CPU port number */
638 if (priv->id == ID_MT7621)
639 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
640
b8f126a8
SW		 641 /* CPU port gets connected to all user ports of
642 * the switch
643 */
644 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 645 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8
SW		 646
647 return 0;
648}
649
650static int
651mt7530_port_enable(struct dsa_switch *ds, int port,
652 struct phy_device *phy)
653{
654 struct mt7530_priv *priv = ds->priv;
655
74be4bab
VD		 656 if (!dsa_is_user_port(ds, port))
657 return 0;
658
b8f126a8
SW		 659 mutex_lock(&priv->reg_mutex);
660
b8f126a8
SW		 661 /* Allow the user port gets connected to the cpu port and also
662 * restore the port matrix if the port is the member of a certain
663 * bridge.
664 */
665 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
666 priv->ports[port].enable = true;
667 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
668 priv->ports[port].pm);
1d01145f 669 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 670
671 mutex_unlock(&priv->reg_mutex);
672
673 return 0;
674}
675
676static void
75104db0 677mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 678{
679 struct mt7530_priv *priv = ds->priv;
680
74be4bab
VD		 681 if (!dsa_is_user_port(ds, port))
682 return;
683
b8f126a8
SW		 684 mutex_lock(&priv->reg_mutex);
685
686 /* Clear up all port matrix which could be restored in the next
687 * enablement for the port.
688 */
689 priv->ports[port].enable = false;
690 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
691 PCR_MATRIX_CLR);
1d01145f 692 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 693
694 mutex_unlock(&priv->reg_mutex);
695}
696
697static void
698mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
699{
700 struct mt7530_priv *priv = ds->priv;
701 u32 stp_state;
702
703 switch (state) {
704 case BR_STATE_DISABLED:
705 stp_state = MT7530_STP_DISABLED;
706 break;
707 case BR_STATE_BLOCKING:
708 stp_state = MT7530_STP_BLOCKING;
709 break;
710 case BR_STATE_LISTENING:
711 stp_state = MT7530_STP_LISTENING;
712 break;
713 case BR_STATE_LEARNING:
714 stp_state = MT7530_STP_LEARNING;
715 break;
716 case BR_STATE_FORWARDING:
717 default:
718 stp_state = MT7530_STP_FORWARDING;
719 break;
720 }
721
722 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
723}
724
725static int
726mt7530_port_bridge_join(struct dsa_switch *ds, int port,
727 struct net_device *bridge)
728{
729 struct mt7530_priv *priv = ds->priv;
730 u32 port_bitmap = BIT(MT7530_CPU_PORT);
731 int i;
732
733 mutex_lock(&priv->reg_mutex);
734
735 for (i = 0; i < MT7530_NUM_PORTS; i++) {
736 /* Add this port to the port matrix of the other ports in the
737 * same bridge. If the port is disabled, port matrix is kept
738 * and not being setup until the port becomes enabled.
739 */
4a5b85ff 740 if (dsa_is_user_port(ds, i) && i != port) {
c8652c83 741 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 742 continue;
743 if (priv->ports[i].enable)
744 mt7530_set(priv, MT7530_PCR_P(i),
745 PCR_MATRIX(BIT(port)));
746 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
747
748 port_bitmap |= BIT(i);
749 }
750 }
751
752 /* Add the all other ports to this port matrix. */
753 if (priv->ports[port].enable)
754 mt7530_rmw(priv, MT7530_PCR_P(port),
755 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
756 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
757
758 mutex_unlock(&priv->reg_mutex);
759
760 return 0;
761}
762
83163f7d
SW		 763static void
764mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
765{
766 struct mt7530_priv *priv = ds->priv;
767 bool all_user_ports_removed = true;
768 int i;
769
770 /* When a port is removed from the bridge, the port would be set up
771 * back to the default as is at initial boot which is a VLAN-unaware
772 * port.
773 */
774 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
775 MT7530_PORT_MATRIX_MODE);
e045124e
DQ		 776 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
777 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
778 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d 779
83163f7d
SW		 780 for (i = 0; i < MT7530_NUM_PORTS; i++) {
781 if (dsa_is_user_port(ds, i) &&
68bb8ea8 782 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 783 all_user_ports_removed = false;
784 break;
785 }
786 }
787
788 /* CPU port also does the same thing until all user ports belonging to
789 * the CPU port get out of VLAN filtering mode.
790 */
791 if (all_user_ports_removed) {
792 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
793 PCR_MATRIX(dsa_user_ports(priv->ds)));
e045124e
DQ		 794 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
795 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 796 }
797}
798
799static void
800mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
801{
802 struct mt7530_priv *priv = ds->priv;
803
804 /* The real fabric path would be decided on the membership in the
805 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
806 * means potential VLAN can be consisting of certain subset of all
807 * ports.
808 */
809 mt7530_rmw(priv, MT7530_PCR_P(port),
810 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
811
812 /* Trapped into security mode allows packet forwarding through VLAN
813 * table lookup.
814 */
815 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
816 MT7530_PORT_SECURITY_MODE);
817
818 /* Set the port as a user port which is to be able to recognize VID
819 * from incoming packets before fetching entry within the VLAN table.
820 */
e045124e
DQ		 821 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
822 VLAN_ATTR(MT7530_VLAN_USER) |
823 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
83163f7d
SW		 824}
825
b8f126a8
SW		 826static void
827mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
828 struct net_device *bridge)
829{
830 struct mt7530_priv *priv = ds->priv;
831 int i;
832
833 mutex_lock(&priv->reg_mutex);
834
835 for (i = 0; i < MT7530_NUM_PORTS; i++) {
836 /* Remove this port from the port matrix of the other ports
837 * in the same bridge. If the port is disabled, port matrix
838 * is kept and not being setup until the port becomes enabled.
83163f7d
SW		 839 * And the other port's port matrix cannot be broken when the
840 * other port is still a VLAN-aware port.
b8f126a8 841 */
2a130551 842 if (dsa_is_user_port(ds, i) && i != port &&
68bb8ea8 843 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
c8652c83 844 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 845 continue;
846 if (priv->ports[i].enable)
847 mt7530_clear(priv, MT7530_PCR_P(i),
848 PCR_MATRIX(BIT(port)));
849 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
850 }
851 }
852
853 /* Set the cpu port to be the only one in the port matrix of
854 * this port.
855 */
856 if (priv->ports[port].enable)
857 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
858 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
859 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
860
861 mutex_unlock(&priv->reg_mutex);
862}
863
864static int
b8f126a8 865mt7530_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 866 const unsigned char *addr, u16 vid)
b8f126a8
SW		 867{
868 struct mt7530_priv *priv = ds->priv;
1b6dd556 869 int ret;
b8f126a8
SW		 870 u8 port_mask = BIT(port);
871
872 mutex_lock(&priv->reg_mutex);
6c2c1dcb 873 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 874 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 875 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 876
877 return ret;
b8f126a8
SW		 878}
879
880static int
881mt7530_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 882 const unsigned char *addr, u16 vid)
b8f126a8
SW		 883{
884 struct mt7530_priv *priv = ds->priv;
885 int ret;
886 u8 port_mask = BIT(port);
887
888 mutex_lock(&priv->reg_mutex);
6c2c1dcb 889 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 890 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 891 mutex_unlock(&priv->reg_mutex);
892
893 return ret;
894}
895
896static int
897mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 898 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 899{
900 struct mt7530_priv *priv = ds->priv;
901 struct mt7530_fdb _fdb = { 0 };
902 int cnt = MT7530_NUM_FDB_RECORDS;
903 int ret = 0;
904 u32 rsp = 0;
905
906 mutex_lock(&priv->reg_mutex);
907
908 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
909 if (ret < 0)
910 goto err;
911
912 do {
913 if (rsp & ATC_SRCH_HIT) {
914 mt7530_fdb_read(priv, &_fdb);
915 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 916 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
917 data);
b8f126a8
SW		 918 if (ret < 0)
919 break;
920 }
921 }
922 } while (--cnt &&
923 !(rsp & ATC_SRCH_END) &&
924 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
925err:
926 mutex_unlock(&priv->reg_mutex);
927
928 return 0;
929}
930
83163f7d
SW		 931static int
932mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
933{
934 struct mt7530_dummy_poll p;
935 u32 val;
936 int ret;
937
938 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
939 mt7530_write(priv, MT7530_VTCR, val);
940
941 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
942 ret = readx_poll_timeout(_mt7530_read, &p, val,
943 !(val & VTCR_BUSY), 20, 20000);
944 if (ret < 0) {
945 dev_err(priv->dev, "poll timeout\n");
946 return ret;
947 }
948
949 val = mt7530_read(priv, MT7530_VTCR);
950 if (val & VTCR_INVALID) {
951 dev_err(priv->dev, "read VTCR invalid\n");
952 return -EINVAL;
953 }
954
955 return 0;
956}
957
958static int
959mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
960 bool vlan_filtering)
961{
83163f7d
SW		 962 if (vlan_filtering) {
963 /* The port is being kept as VLAN-unaware port when bridge is
964 * set up with vlan_filtering not being set, Otherwise, the
965 * port and the corresponding CPU port is required the setup
966 * for becoming a VLAN-aware port.
967 */
968 mt7530_port_set_vlan_aware(ds, port);
969 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
e3ee07d1
VO		 970 } else {
971 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 972 }
973
974 return 0;
975}
976
977static int
978mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
979 const struct switchdev_obj_port_vlan *vlan)
980{
981 /* nothing needed */
982
983 return 0;
984}
985
986static void
987mt7530_hw_vlan_add(struct mt7530_priv *priv,
988 struct mt7530_hw_vlan_entry *entry)
989{
990 u8 new_members;
991 u32 val;
992
993 new_members = entry->old_members | BIT(entry->port) |
994 BIT(MT7530_CPU_PORT);
995
996 /* Validate the entry with independent learning, create egress tag per
997 * VLAN and joining the port as one of the port members.
998 */
999 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1000 mt7530_write(priv, MT7530_VAWD1, val);
1001
1002 /* Decide whether adding tag or not for those outgoing packets from the
1003 * port inside the VLAN.
1004 */
1005 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1006 MT7530_VLAN_EGRESS_TAG;
1007 mt7530_rmw(priv, MT7530_VAWD2,
1008 ETAG_CTRL_P_MASK(entry->port),
1009 ETAG_CTRL_P(entry->port, val));
1010
1011 /* CPU port is always taken as a tagged port for serving more than one
1012 * VLANs across and also being applied with egress type stack mode for
1013 * that VLAN tags would be appended after hardware special tag used as
1014 * DSA tag.
1015 */
1016 mt7530_rmw(priv, MT7530_VAWD2,
1017 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1018 ETAG_CTRL_P(MT7530_CPU_PORT,
1019 MT7530_VLAN_EGRESS_STACK));
1020}
1021
1022static void
1023mt7530_hw_vlan_del(struct mt7530_priv *priv,
1024 struct mt7530_hw_vlan_entry *entry)
1025{
1026 u8 new_members;
1027 u32 val;
1028
1029 new_members = entry->old_members & ~BIT(entry->port);
1030
1031 val = mt7530_read(priv, MT7530_VAWD1);
1032 if (!(val & VLAN_VALID)) {
1033 dev_err(priv->dev,
1034 "Cannot be deleted due to invalid entry\n");
1035 return;
1036 }
1037
1038 /* If certain member apart from CPU port is still alive in the VLAN,
1039 * the entry would be kept valid. Otherwise, the entry is got to be
1040 * disabled.
1041 */
1042 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1043 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1044 VLAN_VALID;
1045 mt7530_write(priv, MT7530_VAWD1, val);
1046 } else {
1047 mt7530_write(priv, MT7530_VAWD1, 0);
1048 mt7530_write(priv, MT7530_VAWD2, 0);
1049 }
1050}
1051
1052static void
1053mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1054 struct mt7530_hw_vlan_entry *entry,
1055 mt7530_vlan_op vlan_op)
1056{
1057 u32 val;
1058
1059 /* Fetch entry */
1060 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1061
1062 val = mt7530_read(priv, MT7530_VAWD1);
1063
1064 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1065
1066 /* Manipulate entry */
1067 vlan_op(priv, entry);
1068
1069 /* Flush result to hardware */
1070 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1071}
1072
1073static void
1074mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1075 const struct switchdev_obj_port_vlan *vlan)
1076{
1077 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1078 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1079 struct mt7530_hw_vlan_entry new_entry;
1080 struct mt7530_priv *priv = ds->priv;
1081 u16 vid;
1082
1083 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1084 * being set.
1085 */
68bb8ea8 1086 if (!dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
83163f7d
SW		 1087 return;
1088
1089 mutex_lock(&priv->reg_mutex);
1090
1091 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1092 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1093 mt7530_hw_vlan_update(priv, vid, &new_entry,
1094 mt7530_hw_vlan_add);
1095 }
1096
1097 if (pvid) {
1098 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1099 G0_PORT_VID(vlan->vid_end));
1100 priv->ports[port].pvid = vlan->vid_end;
1101 }
1102
1103 mutex_unlock(&priv->reg_mutex);
1104}
1105
1106static int
1107mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1108 const struct switchdev_obj_port_vlan *vlan)
1109{
1110 struct mt7530_hw_vlan_entry target_entry;
1111 struct mt7530_priv *priv = ds->priv;
1112 u16 vid, pvid;
1113
1114 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1115 * being set.
1116 */
68bb8ea8 1117 if (!dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
83163f7d
SW		 1118 return 0;
1119
1120 mutex_lock(&priv->reg_mutex);
1121
1122 pvid = priv->ports[port].pvid;
1123 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1124 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1125 mt7530_hw_vlan_update(priv, vid, &target_entry,
1126 mt7530_hw_vlan_del);
1127
1128 /* PVID is being restored to the default whenever the PVID port
1129 * is being removed from the VLAN.
1130 */
1131 if (pvid == vid)
1132 pvid = G0_PORT_VID_DEF;
1133 }
1134
1135 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1136 priv->ports[port].pvid = pvid;
1137
1138 mutex_unlock(&priv->reg_mutex);
1139
1140 return 0;
1141}
1142
37feab60
DQ		 1143static int mt7530_port_mirror_add(struct dsa_switch *ds, int port,
1144 struct dsa_mall_mirror_tc_entry *mirror,
1145 bool ingress)
1146{
1147 struct mt7530_priv *priv = ds->priv;
1148 u32 val;
1149
1150 /* Check for existent entry */
1151 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1152 return -EEXIST;
1153
1154 val = mt7530_read(priv, MT7530_MFC);
1155
1156 /* MT7530 only supports one monitor port */
1157 if (val & MIRROR_EN && MIRROR_PORT(val) != mirror->to_local_port)
1158 return -EEXIST;
1159
1160 val |= MIRROR_EN;
1161 val &= ~MIRROR_MASK;
1162 val |= mirror->to_local_port;
1163 mt7530_write(priv, MT7530_MFC, val);
1164
1165 val = mt7530_read(priv, MT7530_PCR_P(port));
1166 if (ingress) {
1167 val |= PORT_RX_MIR;
1168 priv->mirror_rx |= BIT(port);
1169 } else {
1170 val |= PORT_TX_MIR;
1171 priv->mirror_tx |= BIT(port);
1172 }
1173 mt7530_write(priv, MT7530_PCR_P(port), val);
1174
1175 return 0;
1176}
1177
1178static void mt7530_port_mirror_del(struct dsa_switch *ds, int port,
1179 struct dsa_mall_mirror_tc_entry *mirror)
1180{
1181 struct mt7530_priv *priv = ds->priv;
1182 u32 val;
1183
1184 val = mt7530_read(priv, MT7530_PCR_P(port));
1185 if (mirror->ingress) {
1186 val &= ~PORT_RX_MIR;
1187 priv->mirror_rx &= ~BIT(port);
1188 } else {
1189 val &= ~PORT_TX_MIR;
1190 priv->mirror_tx &= ~BIT(port);
1191 }
1192 mt7530_write(priv, MT7530_PCR_P(port), val);
1193
1194 if (!priv->mirror_rx && !priv->mirror_tx) {
1195 val = mt7530_read(priv, MT7530_MFC);
1196 val &= ~MIRROR_EN;
1197 mt7530_write(priv, MT7530_MFC, val);
1198 }
1199}
1200
b8f126a8 1201static enum dsa_tag_protocol
4d776482
FF		 1202mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1203 enum dsa_tag_protocol mp)
b8f126a8
SW		 1204{
1205 struct mt7530_priv *priv = ds->priv;
1206
5ed4e3eb 1207 if (port != MT7530_CPU_PORT) {
b8f126a8
SW		 1208 dev_warn(priv->dev,
1209 "port not matched with tagging CPU port\n");
1210 return DSA_TAG_PROTO_NONE;
1211 } else {
1212 return DSA_TAG_PROTO_MTK;
1213 }
1214}
1215
1216static int
1217mt7530_setup(struct dsa_switch *ds)
1218{
1219 struct mt7530_priv *priv = ds->priv;
38f790a8
RD		 1220 struct device_node *phy_node;
1221 struct device_node *mac_np;
b8f126a8 1222 struct mt7530_dummy_poll p;
38f790a8 1223 phy_interface_t interface;
ca366d6c
RD		 1224 struct device_node *dn;
1225 u32 id, val;
1226 int ret, i;
b8f126a8 1227
0abfd494 1228 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 1229 * controller also is the container for two GMACs nodes representing
1230 * as two netdev instances.
1231 */
68bb8ea8 1232 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
b8f126a8 1233
ddda1ac1 1234 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 1235 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1236 ret = regulator_enable(priv->core_pwr);
1237 if (ret < 0) {
1238 dev_err(priv->dev,
1239 "Failed to enable core power: %d\n", ret);
1240 return ret;
1241 }
b8f126a8 1242
ddda1ac1
GU		 1243 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1244 ret = regulator_enable(priv->io_pwr);
1245 if (ret < 0) {
1246 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1247 ret);
1248 return ret;
1249 }
b8f126a8
SW		 1250 }
1251
1252 /* Reset whole chip through gpio pin or memory-mapped registers for
1253 * different type of hardware
1254 */
1255 if (priv->mcm) {
1256 reset_control_assert(priv->rstc);
1257 usleep_range(1000, 1100);
1258 reset_control_deassert(priv->rstc);
1259 } else {
1260 gpiod_set_value_cansleep(priv->reset, 0);
1261 usleep_range(1000, 1100);
1262 gpiod_set_value_cansleep(priv->reset, 1);
1263 }
1264
1265 /* Waiting for MT7530 got to stable */
1266 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1267 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1268 20, 1000000);
1269 if (ret < 0) {
1270 dev_err(priv->dev, "reset timeout\n");
1271 return ret;
1272 }
1273
1274 id = mt7530_read(priv, MT7530_CREV);
1275 id >>= CHIP_NAME_SHIFT;
1276 if (id != MT7530_ID) {
1277 dev_err(priv->dev, "chip %x can't be supported\n", id);
1278 return -ENODEV;
1279 }
1280
1281 /* Reset the switch through internal reset */
1282 mt7530_write(priv, MT7530_SYS_CTRL,
1283 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1284 SYS_CTRL_REG_RST);
1285
1286 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1287 val = mt7530_read(priv, MT7530_MHWTRAP);
1288 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1289 val |= MHWTRAP_MANUAL;
1290 mt7530_write(priv, MT7530_MHWTRAP, val);
1291
ca366d6c
RD		 1292 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1293
b8f126a8
SW		 1294 /* Enable and reset MIB counters */
1295 mt7530_mib_reset(ds);
1296
1297 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
1298
1299 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1300 /* Disable forwarding by default on all ports */
1301 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1302 PCR_MATRIX_CLR);
1303
1304 if (dsa_is_cpu_port(ds, i))
1305 mt7530_cpu_port_enable(priv, i);
1306 else
75104db0 1307 mt7530_port_disable(ds, i);
e045124e
DQ		 1308
1309 /* Enable consistent egress tag */
1310 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1311 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 1312 }
1313
38f790a8
RD		 1314 /* Setup port 5 */
1315 priv->p5_intf_sel = P5_DISABLED;
1316 interface = PHY_INTERFACE_MODE_NA;
1317
1318 if (!dsa_is_unused_port(ds, 5)) {
1319 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
0c65b2b9
AL		 1320 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
1321 if (ret && ret != -ENODEV)
1322 return ret;
38f790a8
RD		 1323 } else {
1324 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1325 for_each_child_of_node(dn, mac_np) {
1326 if (!of_device_is_compatible(mac_np,
1327 "mediatek,eth-mac"))
1328 continue;
1329
1330 ret = of_property_read_u32(mac_np, "reg", &id);
1331 if (ret < 0 || id != 1)
1332 continue;
1333
1334 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 1335 if (!phy_node)
1336 continue;
1337
38f790a8 1338 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9
AL		 1339 ret = of_get_phy_mode(mac_np, &interface);
1340 if (ret && ret != -ENODEV)
1341 return ret;
38f790a8
RD		 1342 id = of_mdio_parse_addr(ds->dev, phy_node);
1343 if (id == 0)
1344 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1345 if (id == 4)
1346 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1347 }
1348 of_node_put(phy_node);
1349 break;
1350 }
1351 }
1352
1353 mt7530_setup_port5(ds, interface);
1354
b8f126a8 1355 /* Flush the FDB table */
18bd5949 1356 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 1357 if (ret < 0)
1358 return ret;
1359
1360 return 0;
1361}
1362
ca366d6c
RD		 1363static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
1364 unsigned int mode,
1365 const struct phylink_link_state *state)
1366{
1367 struct mt7530_priv *priv = ds->priv;
1368 u32 mcr_cur, mcr_new;
1369
1370 switch (port) {
1371 case 0: /* Internal phy */
1372 case 1:
1373 case 2:
1374 case 3:
1375 case 4:
1376 if (state->interface != PHY_INTERFACE_MODE_GMII)
1377 return;
1378 break;
38f790a8
RD		 1379 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1380 if (priv->p5_interface == state->interface)
1381 break;
1382 if (!phy_interface_mode_is_rgmii(state->interface) &&
1383 state->interface != PHY_INTERFACE_MODE_MII &&
1384 state->interface != PHY_INTERFACE_MODE_GMII)
1385 return;
1386
1387 mt7530_setup_port5(ds, state->interface);
1388 break;
ca366d6c
RD		 1389 case 6: /* 1st cpu port */
1390 if (priv->p6_interface == state->interface)
1391 break;
1392
1393 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1394 state->interface != PHY_INTERFACE_MODE_TRGMII)
1395 return;
1396
1397 /* Setup TX circuit incluing relevant PAD and driving */
1398 mt7530_pad_clk_setup(ds, state->interface);
1399
ca366d6c
RD		 1400 priv->p6_interface = state->interface;
1401 break;
1402 default:
1403 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1404 return;
1405 }
1406
1407 if (phylink_autoneg_inband(mode)) {
1408 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1409 __func__);
1410 return;
1411 }
1412
1413 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
1414 mcr_new = mcr_cur;
1d01145f 1415 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 1416 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
22259471 1417 PMCR_BACKPR_EN | PMCR_FORCE_MODE;
ca366d6c 1418
38f790a8
RD		 1419 /* Are we connected to external phy */
1420 if (port == 5 && dsa_is_user_port(ds, 5))
1421 mcr_new |= PMCR_EXT_PHY;
1422
ca366d6c
RD		 1423 if (mcr_new != mcr_cur)
1424 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
1425}
1426
1427static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
1428 unsigned int mode,
1429 phy_interface_t interface)
1430{
1431 struct mt7530_priv *priv = ds->priv;
1432
1d01145f 1433 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 1434}
1435
1436static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,
1437 unsigned int mode,
1438 phy_interface_t interface,
5b502a7b
RK		 1439 struct phy_device *phydev,
1440 int speed, int duplex,
1441 bool tx_pause, bool rx_pause)
ca366d6c
RD		 1442{
1443 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 1444 u32 mcr;
1445
1446 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
1447
1448 switch (speed) {
1449 case SPEED_1000:
1450 mcr |= PMCR_FORCE_SPEED_1000;
1451 break;
1452 case SPEED_100:
1453 mcr |= PMCR_FORCE_SPEED_100;
1454 break;
1455 }
1456 if (duplex == DUPLEX_FULL) {
1457 mcr |= PMCR_FORCE_FDX;
1458 if (tx_pause)
1459 mcr |= PMCR_TX_FC_EN;
1460 if (rx_pause)
1461 mcr |= PMCR_RX_FC_EN;
1462 }
ca366d6c 1463
1d01145f 1464 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 1465}
1466
1467static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
1468 unsigned long *supported,
1469 struct phylink_link_state *state)
1470{
1471 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1472
1473 switch (port) {
1474 case 0: /* Internal phy */
1475 case 1:
1476 case 2:
1477 case 3:
1478 case 4:
1479 if (state->interface != PHY_INTERFACE_MODE_NA &&
1480 state->interface != PHY_INTERFACE_MODE_GMII)
1481 goto unsupported;
1482 break;
38f790a8
RD		 1483 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1484 if (state->interface != PHY_INTERFACE_MODE_NA &&
1485 !phy_interface_mode_is_rgmii(state->interface) &&
1486 state->interface != PHY_INTERFACE_MODE_MII &&
1487 state->interface != PHY_INTERFACE_MODE_GMII)
1488 goto unsupported;
1489 break;
ca366d6c
RD		 1490 case 6: /* 1st cpu port */
1491 if (state->interface != PHY_INTERFACE_MODE_NA &&
1492 state->interface != PHY_INTERFACE_MODE_RGMII &&
1493 state->interface != PHY_INTERFACE_MODE_TRGMII)
1494 goto unsupported;
1495 break;
1496 default:
1497 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1498unsupported:
1499 linkmode_zero(supported);
1500 return;
1501 }
1502
1503 phylink_set_port_modes(mask);
1504 phylink_set(mask, Autoneg);
1505
38f790a8
RD		 1506 if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
1507 phylink_set(mask, 1000baseT_Full);
1508 } else {
ca366d6c
RD		 1509 phylink_set(mask, 10baseT_Half);
1510 phylink_set(mask, 10baseT_Full);
1511 phylink_set(mask, 100baseT_Half);
1512 phylink_set(mask, 100baseT_Full);
ca366d6c 1513
38f790a8
RD		 1514 if (state->interface != PHY_INTERFACE_MODE_MII) {
1515 phylink_set(mask, 1000baseT_Half);
1516 phylink_set(mask, 1000baseT_Full);
1517 if (port == 5)
1518 phylink_set(mask, 1000baseX_Full);
1519 }
1520 }
ca366d6c
RD		 1521
1522 phylink_set(mask, Pause);
1523 phylink_set(mask, Asym_Pause);
1524
1525 linkmode_and(supported, supported, mask);
1526 linkmode_and(state->advertising, state->advertising, mask);
1527}
1528
1529static int
1530mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
1531 struct phylink_link_state *state)
1532{
1533 struct mt7530_priv *priv = ds->priv;
1534 u32 pmsr;
1535
1536 if (port < 0 || port >= MT7530_NUM_PORTS)
1537 return -EINVAL;
1538
1539 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
1540
1541 state->link = (pmsr & PMSR_LINK);
1542 state->an_complete = state->link;
1543 state->duplex = !!(pmsr & PMSR_DPX);
1544
1545 switch (pmsr & PMSR_SPEED_MASK) {
1546 case PMSR_SPEED_10:
1547 state->speed = SPEED_10;
1548 break;
1549 case PMSR_SPEED_100:
1550 state->speed = SPEED_100;
1551 break;
1552 case PMSR_SPEED_1000:
1553 state->speed = SPEED_1000;
1554 break;
1555 default:
1556 state->speed = SPEED_UNKNOWN;
1557 break;
1558 }
1559
1560 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
1561 if (pmsr & PMSR_RX_FC)
1562 state->pause |= MLO_PAUSE_RX;
1563 if (pmsr & PMSR_TX_FC)
1564 state->pause |= MLO_PAUSE_TX;
1565
1566 return 1;
1567}
1568
d78d6776 1569static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8
SW		 1570 .get_tag_protocol = mtk_get_tag_protocol,
1571 .setup = mt7530_setup,
1572 .get_strings = mt7530_get_strings,
1573 .phy_read = mt7530_phy_read,
1574 .phy_write = mt7530_phy_write,
1575 .get_ethtool_stats = mt7530_get_ethtool_stats,
1576 .get_sset_count = mt7530_get_sset_count,
b8f126a8
SW		 1577 .port_enable = mt7530_port_enable,
1578 .port_disable = mt7530_port_disable,
1579 .port_stp_state_set = mt7530_stp_state_set,
1580 .port_bridge_join = mt7530_port_bridge_join,
1581 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 1582 .port_fdb_add = mt7530_port_fdb_add,
1583 .port_fdb_del = mt7530_port_fdb_del,
1584 .port_fdb_dump = mt7530_port_fdb_dump,
83163f7d
SW		 1585 .port_vlan_filtering = mt7530_port_vlan_filtering,
1586 .port_vlan_prepare = mt7530_port_vlan_prepare,
1587 .port_vlan_add = mt7530_port_vlan_add,
1588 .port_vlan_del = mt7530_port_vlan_del,
37feab60
DQ		 1589 .port_mirror_add = mt7530_port_mirror_add,
1590 .port_mirror_del = mt7530_port_mirror_del,
ca366d6c
RD		 1591 .phylink_validate = mt7530_phylink_validate,
1592 .phylink_mac_link_state = mt7530_phylink_mac_link_state,
1593 .phylink_mac_config = mt7530_phylink_mac_config,
1594 .phylink_mac_link_down = mt7530_phylink_mac_link_down,
1595 .phylink_mac_link_up = mt7530_phylink_mac_link_up,
b8f126a8
SW		 1596};
1597
ddda1ac1
GU		 1598static const struct of_device_id mt7530_of_match[] = {
1599 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, },
1600 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, },
1601 { /* sentinel */ },
1602};
1603MODULE_DEVICE_TABLE(of, mt7530_of_match);
1604
b8f126a8
SW		 1605static int
1606mt7530_probe(struct mdio_device *mdiodev)
1607{
1608 struct mt7530_priv *priv;
1609 struct device_node *dn;
1610
1611 dn = mdiodev->dev.of_node;
1612
1613 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1614 if (!priv)
1615 return -ENOMEM;
1616
7e99e347 1617 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 1618 if (!priv->ds)
1619 return -ENOMEM;
1620
7e99e347
VD		 1621 priv->ds->dev = &mdiodev->dev;
1622 priv->ds->num_ports = DSA_MAX_PORTS;
1623
b8f126a8
SW		 1624 /* Use medatek,mcm property to distinguish hardware type that would
1625 * casues a little bit differences on power-on sequence.
1626 */
1627 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1628 if (priv->mcm) {
1629 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1630
1631 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1632 if (IS_ERR(priv->rstc)) {
1633 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1634 return PTR_ERR(priv->rstc);
1635 }
1636 }
1637
ddda1ac1
GU		 1638 /* Get the hardware identifier from the devicetree node.
1639 * We will need it for some of the clock and regulator setup.
1640 */
1641 priv->id = (unsigned int)(unsigned long)
1642 of_device_get_match_data(&mdiodev->dev);
b8f126a8 1643
ddda1ac1
GU		 1644 if (priv->id == ID_MT7530) {
1645 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1646 if (IS_ERR(priv->core_pwr))
1647 return PTR_ERR(priv->core_pwr);
1648
1649 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1650 if (IS_ERR(priv->io_pwr))
1651 return PTR_ERR(priv->io_pwr);
1652 }
b8f126a8
SW		 1653
1654 /* Not MCM that indicates switch works as the remote standalone
1655 * integrated circuit so the GPIO pin would be used to complete
1656 * the reset, otherwise memory-mapped register accessing used
1657 * through syscon provides in the case of MCM.
1658 */
1659 if (!priv->mcm) {
1660 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1661 GPIOD_OUT_LOW);
1662 if (IS_ERR(priv->reset)) {
1663 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1664 return PTR_ERR(priv->reset);
1665 }
1666 }
1667
1668 priv->bus = mdiodev->bus;
1669 priv->dev = &mdiodev->dev;
1670 priv->ds->priv = priv;
1671 priv->ds->ops = &mt7530_switch_ops;
1672 mutex_init(&priv->reg_mutex);
1673 dev_set_drvdata(&mdiodev->dev, priv);
1674
23c9ee49 1675 return dsa_register_switch(priv->ds);
b8f126a8
SW		 1676}
1677
1678static void
1679mt7530_remove(struct mdio_device *mdiodev)
1680{
1681 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1682 int ret = 0;
1683
1684 ret = regulator_disable(priv->core_pwr);
1685 if (ret < 0)
1686 dev_err(priv->dev,
1687 "Failed to disable core power: %d\n", ret);
1688
1689 ret = regulator_disable(priv->io_pwr);
1690 if (ret < 0)
1691 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1692 ret);
1693
1694 dsa_unregister_switch(priv->ds);
1695 mutex_destroy(&priv->reg_mutex);
1696}
1697
b8f126a8
SW		 1698static struct mdio_driver mt7530_mdio_driver = {
1699 .probe = mt7530_probe,
1700 .remove = mt7530_remove,
1701 .mdiodrv.driver = {
1702 .name = "mt7530",
1703 .of_match_table = mt7530_of_match,
1704 },
1705};
1706
1707mdio_module_driver(mt7530_mdio_driver);
1708
1709MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1710MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1711MODULE_LICENSE("GPL");
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