[thirdparty/linux.git] / drivers / net / dsa / mv88e6xxx / port.h

/*
 * Marvell 88E6xxx Switch Port Registers support
 *
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef _MV88E6XXX_PORT_H
#define _MV88E6XXX_PORT_H

#include "chip.h"

/* Offset 0x00: Port Status Register */
#define MV88E6XXX_PORT_STS			0x00
#define MV88E6XXX_PORT_STS_PAUSE_EN		0x8000
#define MV88E6XXX_PORT_STS_MY_PAUSE		0x4000
#define MV88E6XXX_PORT_STS_HD_FLOW		0x2000
#define MV88E6XXX_PORT_STS_PHY_DETECT		0x1000
#define MV88E6250_PORT_STS_LINK				0x1000
#define MV88E6250_PORT_STS_PORTMODE_MASK		0x0f00
#define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF		0x0800
#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF	0x0900
#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL		0x0a00
#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL	0x0b00
#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF		0x0c00
#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF	0x0d00
#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL		0x0e00
#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL	0x0f00
#define MV88E6XXX_PORT_STS_LINK			0x0800
#define MV88E6XXX_PORT_STS_DUPLEX		0x0400
#define MV88E6XXX_PORT_STS_SPEED_MASK		0x0300
#define MV88E6XXX_PORT_STS_SPEED_10		0x0000
#define MV88E6XXX_PORT_STS_SPEED_100		0x0100
#define MV88E6XXX_PORT_STS_SPEED_1000		0x0200
#define MV88E6XXX_PORT_STS_SPEED_10000		0x0300
#define MV88E6352_PORT_STS_EEE			0x0040
#define MV88E6165_PORT_STS_AM_DIS		0x0040
#define MV88E6185_PORT_STS_MGMII		0x0040
#define MV88E6XXX_PORT_STS_TX_PAUSED		0x0020
#define MV88E6XXX_PORT_STS_FLOW_CTL		0x0010
#define MV88E6XXX_PORT_STS_CMODE_MASK		0x000f
#define MV88E6XXX_PORT_STS_CMODE_100BASE_X	0x0008
#define MV88E6XXX_PORT_STS_CMODE_1000BASE_X	0x0009
#define MV88E6XXX_PORT_STS_CMODE_SGMII		0x000a
#define MV88E6XXX_PORT_STS_CMODE_2500BASEX	0x000b
#define MV88E6XXX_PORT_STS_CMODE_XAUI		0x000c
#define MV88E6XXX_PORT_STS_CMODE_RXAUI		0x000d
#define MV88E6185_PORT_STS_CDUPLEX		0x0008
#define MV88E6185_PORT_STS_CMODE_MASK		0x0007
#define MV88E6185_PORT_STS_CMODE_GMII_FD	0x0000
#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS	0x0001
#define MV88E6185_PORT_STS_CMODE_MII_100	0x0002
#define MV88E6185_PORT_STS_CMODE_MII_10		0x0003
#define MV88E6185_PORT_STS_CMODE_SERDES		0x0004
#define MV88E6185_PORT_STS_CMODE_1000BASE_X	0x0005
#define MV88E6185_PORT_STS_CMODE_PHY		0x0006
#define MV88E6185_PORT_STS_CMODE_DISABLED	0x0007

/* Offset 0x01: MAC (or PCS or Physical) Control Register */
#define MV88E6XXX_PORT_MAC_CTL				0x01
#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK	0x8000
#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK	0x4000
#define MV88E6185_PORT_MAC_CTL_SYNC_OK			0x4000
#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED		0x2000
#define MV88E6390_PORT_MAC_CTL_ALTSPEED			0x1000
#define MV88E6352_PORT_MAC_CTL_200BASE			0x1000
#define MV88E6185_PORT_MAC_CTL_AN_EN			0x0400
#define MV88E6185_PORT_MAC_CTL_AN_RESTART		0x0200
#define MV88E6185_PORT_MAC_CTL_AN_DONE			0x0100
#define MV88E6XXX_PORT_MAC_CTL_FC			0x0080
#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC			0x0040
#define MV88E6XXX_PORT_MAC_CTL_LINK_UP			0x0020
#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK		0x0010
#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL		0x0008
#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX		0x0004
#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK		0x0003
#define MV88E6XXX_PORT_MAC_CTL_SPEED_10			0x0000
#define MV88E6XXX_PORT_MAC_CTL_SPEED_100		0x0001
#define MV88E6065_PORT_MAC_CTL_SPEED_200		0x0002
#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000		0x0002
#define MV88E6390_PORT_MAC_CTL_SPEED_10000		0x0003
#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED		0x0003

/* Offset 0x02: Jamming Control Register */
#define MV88E6097_PORT_JAM_CTL			0x02
#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK	0xff00
#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK	0x00ff

/* Offset 0x02: Flow Control Register */
#define MV88E6390_PORT_FLOW_CTL			0x02
#define MV88E6390_PORT_FLOW_CTL_UPDATE		0x8000
#define MV88E6390_PORT_FLOW_CTL_PTR_MASK	0x7f00
#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN	0x0000
#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT	0x0100
#define MV88E6390_PORT_FLOW_CTL_DATA_MASK	0x00ff

/* Offset 0x03: Switch Identifier Register */
#define MV88E6XXX_PORT_SWITCH_ID		0x03
#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK	0xfff0
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085	0x04a0
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095	0x0950
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097	0x0990
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X	0x0a00
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X	0x0a10
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131	0x1060
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320	0x1150
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123	0x1210
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161	0x1610
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165	0x1650
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171	0x1710
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172	0x1720
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175	0x1750
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176	0x1760
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190	0x1900
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191	0x1910
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185	0x1a70
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240	0x2400
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250	0x2500
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290	0x2900
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321	0x3100
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141	0x3400
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341	0x3410
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352	0x3520
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350	0x3710
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351	0x3750
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390	0x3900
#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK	0x000f

/* Offset 0x04: Port Control Register */
#define MV88E6XXX_PORT_CTL0					0x04
#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG			0x8000
#define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK			0x4000
#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK			0x3000
#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED		0x0000
#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED		0x1000
#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED			0x2000
#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA		0x3000
#define MV88E6XXX_PORT_CTL0_HEADER				0x0800
#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP			0x0400
#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG				0x0200
#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK			0x0300
#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL			0x0000
#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA			0x0100
#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER			0x0200
#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA		0x0300
#define MV88E6XXX_PORT_CTL0_DSA_TAG				0x0100
#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL				0x0080
#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH				0x0040
#define MV88E6185_PORT_CTL0_USE_IP				0x0020
#define MV88E6185_PORT_CTL0_USE_TAG				0x0010
#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN			0x0004
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK			0x000c
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA		0x0000
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA	0x0004
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA	0x0008
#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA	0x000c
#define MV88E6XXX_PORT_CTL0_STATE_MASK				0x0003
#define MV88E6XXX_PORT_CTL0_STATE_DISABLED			0x0000
#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING			0x0001
#define MV88E6XXX_PORT_CTL0_STATE_LEARNING			0x0002
#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING			0x0003

/* Offset 0x05: Port Control 1 */
#define MV88E6XXX_PORT_CTL1			0x05
#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT	0x8000
#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK	0x00ff

/* Offset 0x06: Port Based VLAN Map */
#define MV88E6XXX_PORT_BASE_VLAN		0x06
#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK	0xf000

/* Offset 0x07: Default Port VLAN ID & Priority */
#define MV88E6XXX_PORT_DEFAULT_VLAN		0x07
#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK	0x0fff

/* Offset 0x08: Port Control 2 Register */
#define MV88E6XXX_PORT_CTL2				0x08
#define MV88E6XXX_PORT_CTL2_IGNORE_FCS			0x8000
#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE		0x4000
#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE		0x2000
#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE		0x1000
#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK		0x3000
#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522		0x0000
#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048		0x1000
#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240		0x2000
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK		0x0c00
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED		0x0000
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK		0x0400
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK		0x0800
#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE		0x0c00
#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED		0x0200
#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED		0x0100
#define MV88E6XXX_PORT_CTL2_MAP_DA			0x0080
#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD		0x0040
#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR		0x0020
#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR		0x0010
#define MV88E6095_PORT_CTL2_CPU_PORT_MASK		0x000f

/* Offset 0x09: Egress Rate Control */
#define MV88E6XXX_PORT_EGRESS_RATE_CTL1		0x09

/* Offset 0x0A: Egress Rate Control 2 */
#define MV88E6XXX_PORT_EGRESS_RATE_CTL2		0x0a

/* Offset 0x0B: Port Association Vector */
#define MV88E6XXX_PORT_ASSOC_VECTOR			0x0b
#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1		0x8000
#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT		0x4000
#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT		0x2000
#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG	0x1000
#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED	0x0800

/* Offset 0x0C: Port ATU Control */
#define MV88E6XXX_PORT_ATU_CTL		0x0c

/* Offset 0x0D: Priority Override Register */
#define MV88E6XXX_PORT_PRI_OVERRIDE	0x0d

/* Offset 0x0E: Policy Control Register */
#define MV88E6XXX_PORT_POLICY_CTL	0x0e

/* Offset 0x0F: Port Special Ether Type */
#define MV88E6XXX_PORT_ETH_TYPE		0x0f
#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT	0x9100

/* Offset 0x10: InDiscards Low Counter */
#define MV88E6XXX_PORT_IN_DISCARD_LO	0x10

/* Offset 0x11: InDiscards High Counter */
#define MV88E6XXX_PORT_IN_DISCARD_HI	0x11

/* Offset 0x12: InFiltered Counter */
#define MV88E6XXX_PORT_IN_FILTERED	0x12

/* Offset 0x13: OutFiltered Counter */
#define MV88E6XXX_PORT_OUT_FILTERED	0x13

/* Offset 0x18: IEEE Priority Mapping Table */
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE			0x18
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE		0x8000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK			0x7000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP		0x0000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP	0x1000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP	0x2000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP	0x3000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP	0x5000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP	0x6000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP	0x7000
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK		0x0e00
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK		0x01ff

/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123	0x18

/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567	0x19

/* Offset 0x1a: Magic undocumented errata register */
#define PORT_RESERVED_1A			0x1a
#define PORT_RESERVED_1A_BUSY			BIT(15)
#define PORT_RESERVED_1A_WRITE			BIT(14)
#define PORT_RESERVED_1A_READ			0
#define PORT_RESERVED_1A_PORT_SHIFT		5
#define PORT_RESERVED_1A_BLOCK			(0xf << 10)
#define PORT_RESERVED_1A_CTRL_PORT		4
#define PORT_RESERVED_1A_DATA_PORT		5

int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
			u16 *val);
int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
			 u16 val);

int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
			     int pause);
int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
				   phy_interface_t mode);
int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
				   phy_interface_t mode);

int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);

int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup);

int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
int mv88e6250_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);

phy_interface_t mv88e6341_port_max_speed_mode(int port);
phy_interface_t mv88e6390_port_max_speed_mode(int port);
phy_interface_t mv88e6390x_port_max_speed_mode(int port);

int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);

int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);

int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);

int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);

int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
				  u16 mode);
int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
				   enum mv88e6xxx_egress_mode mode);
int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
				  enum mv88e6xxx_frame_mode mode);
int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
				  enum mv88e6xxx_frame_mode mode);
int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
				     bool unicast, bool multicast);
int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
				     bool unicast, bool multicast);
int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
				  u16 etype);
int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
				    bool message_port);
int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
				  size_t size);
int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
			       u8 out);
int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
			       u8 out);
int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
			     phy_interface_t mode);
int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
			      phy_interface_t mode);
int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
			      struct phylink_link_state *state);
int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,
			      struct phylink_link_state *state);
int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
			      struct phylink_link_state *state);
int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
				     int upstream_port);

int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);

#endif /* _MV88E6XXX_PORT_H */
Commit	Line	Data
18abed21 VD	1	/*
	2	* Marvell 88E6xxx Switch Port Registers support
	3	*
	4	* Copyright (c) 2008 Marvell Semiconductor
	5	*
4333d619 VD	6	* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
4333d619 VD	7	* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
18abed21 VD	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#ifndef _MV88E6XXX_PORT_H
	16	#define _MV88E6XXX_PORT_H
	17
4d5f2ba7	18	#include "chip.h"
18abed21	19
5f83dc93 VD	20	/* Offset 0x00: Port Status Register */
	21	#define MV88E6XXX_PORT_STS 0x00
	22	#define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
	23	#define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
	24	#define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
	25	#define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
ce91c453 RV	26	#define MV88E6250_PORT_STS_LINK 0x1000
	27	#define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
	28	#define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
	29	#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
	30	#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00
	31	#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00
	32	#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF 0x0c00
	33	#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF 0x0d00
	34	#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL 0x0e00
	35	#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL 0x0f00
5f83dc93 VD	36	#define MV88E6XXX_PORT_STS_LINK 0x0800
	37	#define MV88E6XXX_PORT_STS_DUPLEX 0x0400
	38	#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300
	39	#define MV88E6XXX_PORT_STS_SPEED_10 0x0000
	40	#define MV88E6XXX_PORT_STS_SPEED_100 0x0100
	41	#define MV88E6XXX_PORT_STS_SPEED_1000 0x0200
c9a2356f	42	#define MV88E6XXX_PORT_STS_SPEED_10000 0x0300
5f83dc93 VD	43	#define MV88E6352_PORT_STS_EEE 0x0040
	44	#define MV88E6165_PORT_STS_AM_DIS 0x0040
	45	#define MV88E6185_PORT_STS_MGMII 0x0040
	46	#define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020
	47	#define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010
	48	#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f
	49	#define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008
	50	#define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009
	51	#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a
	52	#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b
	53	#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c
	54	#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d
6c422e34 RK	55	#define MV88E6185_PORT_STS_CDUPLEX 0x0008
	56	#define MV88E6185_PORT_STS_CMODE_MASK 0x0007
	57	#define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000
	58	#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001
	59	#define MV88E6185_PORT_STS_CMODE_MII_100 0x0002
	60	#define MV88E6185_PORT_STS_CMODE_MII_10 0x0003
	61	#define MV88E6185_PORT_STS_CMODE_SERDES 0x0004
	62	#define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005
	63	#define MV88E6185_PORT_STS_CMODE_PHY 0x0006
	64	#define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007
5f83dc93	65
5ee55577 VD	66	/* Offset 0x01: MAC (or PCS or Physical) Control Register */
	67	#define MV88E6XXX_PORT_MAC_CTL 0x01
	68	#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000
	69	#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000
6c422e34	70	#define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000
5ee55577 VD	71	#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000
	72	#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000
	73	#define MV88E6352_PORT_MAC_CTL_200BASE 0x1000
6c422e34 RK	74	#define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400
	75	#define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200
	76	#define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100
5ee55577 VD	77	#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080
	78	#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040
	79	#define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020
	80	#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010
	81	#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008
	82	#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004
	83	#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003
	84	#define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000
	85	#define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001
	86	#define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002
	87	#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002
	88	#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003
	89	#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003
	90
6c96bbfd VD	91	/* Offset 0x02: Jamming Control Register */
	92	#define MV88E6097_PORT_JAM_CTL 0x02
	93	#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00
	94	#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff
	95
	96	/* Offset 0x02: Flow Control Register */
	97	#define MV88E6390_PORT_FLOW_CTL 0x02
	98	#define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000
	99	#define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00
	100	#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000
	101	#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100
	102	#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff
	103
107fcc10 VD	104	/* Offset 0x03: Switch Identifier Register */
	105	#define MV88E6XXX_PORT_SWITCH_ID 0x03
	106	#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0
	107	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0
	108	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950
	109	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990
	110	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00
	111	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10
	112	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060
	113	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150
	114	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210
	115	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610
	116	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650
	117	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710
	118	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720
	119	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750
	120	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760
	121	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900
	122	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910
	123	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70
	124	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
1f71836f	125	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500
107fcc10 VD	126	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
	127	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
	128	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400
	129	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410
	130	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520
	131	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710
	132	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750
	133	#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900
	134	#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f
	135
a89b433b VD	136	/* Offset 0x04: Port Control Register */
	137	#define MV88E6XXX_PORT_CTL0 0x04
	138	#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000
	139	#define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000
	140	#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000
	141	#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000
	142	#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000
	143	#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000
	144	#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000
	145	#define MV88E6XXX_PORT_CTL0_HEADER 0x0800
	146	#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400
	147	#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200
	148	#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300
	149	#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000
	150	#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100
	151	#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200
	152	#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300
	153	#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100
	154	#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080
	155	#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040
	156	#define MV88E6185_PORT_CTL0_USE_IP 0x0020
	157	#define MV88E6185_PORT_CTL0_USE_TAG 0x0010
	158	#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004
	159	#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c
	160	#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA 0x0000
	161	#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA 0x0004
	162	#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA 0x0008
	163	#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA 0x000c
	164	#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003
	165	#define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000
	166	#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001
	167	#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002
	168	#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003
	169
cd985bbf VD	170	/* Offset 0x05: Port Control 1 */
	171	#define MV88E6XXX_PORT_CTL1 0x05
	172	#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000
	173	#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff
	174
7e5cc5f1 VD	175	/* Offset 0x06: Port Based VLAN Map */
	176	#define MV88E6XXX_PORT_BASE_VLAN 0x06
	177	#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000
	178
b7929fb3 VD	179	/* Offset 0x07: Default Port VLAN ID & Priority */
	180	#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07
	181	#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff
	182
81c6edb2 VD	183	/* Offset 0x08: Port Control 2 Register */
	184	#define MV88E6XXX_PORT_CTL2 0x08
	185	#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000
	186	#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000
	187	#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000
	188	#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000
	189	#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000
	190	#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000
	191	#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000
	192	#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000
	193	#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00
	194	#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000
	195	#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400
	196	#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800
	197	#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00
	198	#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200
	199	#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100
	200	#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080
	201	#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040
	202	#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020
	203	#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010
	204	#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f
	205
2cb8cb14 VD	206	/* Offset 0x09: Egress Rate Control */
	207	#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09
	208
	209	/* Offset 0x0A: Egress Rate Control 2 */
	210	#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a
	211
2a4614e4 VD	212	/* Offset 0x0B: Port Association Vector */
	213	#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b
	214	#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000
	215	#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000
	216	#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000
	217	#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000
	218	#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800
	219
b8109594 VD	220	/* Offset 0x0C: Port ATU Control */
	221	#define MV88E6XXX_PORT_ATU_CTL 0x0c
	222
	223	/* Offset 0x0D: Priority Override Register */
	224	#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d
	225
	226	/* Offset 0x0E: Policy Control Register */
	227	#define MV88E6XXX_PORT_POLICY_CTL 0x0e
	228
	229	/* Offset 0x0F: Port Special Ether Type */
	230	#define MV88E6XXX_PORT_ETH_TYPE 0x0f
	231	#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100
	232
	233	/* Offset 0x10: InDiscards Low Counter */
	234	#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10
	235
	236	/* Offset 0x11: InDiscards High Counter */
	237	#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11
	238
	239	/* Offset 0x12: InFiltered Counter */
	240	#define MV88E6XXX_PORT_IN_FILTERED 0x12
	241
	242	/* Offset 0x13: OutFiltered Counter */
	243	#define MV88E6XXX_PORT_OUT_FILTERED 0x13
	244
8009df9e VD	245	/* Offset 0x18: IEEE Priority Mapping Table */
	246	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18
	247	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000
ddcbabf4	248	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000
8009df9e VD	249	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000
	250	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000
	251	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000
	252	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000
	253	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000
	254	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000
	255	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000
ddcbabf4 VD	256	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00
ddcbabf4 VD	257	#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff
8009df9e VD	258
	259	/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
	260	#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18
	261
	262	/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
	263	#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19
d2a160b5	264
ea89098e AL	265	/* Offset 0x1a: Magic undocumented errata register */
	266	#define PORT_RESERVED_1A 0x1a
	267	#define PORT_RESERVED_1A_BUSY BIT(15)
	268	#define PORT_RESERVED_1A_WRITE BIT(14)
	269	#define PORT_RESERVED_1A_READ 0
	270	#define PORT_RESERVED_1A_PORT_SHIFT 5
	271	#define PORT_RESERVED_1A_BLOCK (0xf << 10)
	272	#define PORT_RESERVED_1A_CTRL_PORT 4
	273	#define PORT_RESERVED_1A_DATA_PORT 5
	274
18abed21 VD	275	int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
	276	u16 *val);
	277	int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
	278	u16 val);
	279
54186b91 AL	280	int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
54186b91 AL	281	int pause);
a0a0f622 VD	282	int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
	283	phy_interface_t mode);
	284	int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
	285	phy_interface_t mode);
	286
08ef7f10 VD	287	int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
08ef7f10 VD	288
7f1ae07b VD	289	int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup);
7f1ae07b VD	290
96a2b40c VD	291	int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
96a2b40c VD	292	int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
a528e5be	293	int mv88e6250_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
26422340	294	int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
96a2b40c VD	295	int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
	296	int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
	297	int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
	298
7cbbee05 AL	299	phy_interface_t mv88e6341_port_max_speed_mode(int port);
	300	phy_interface_t mv88e6390_port_max_speed_mode(int port);
	301	phy_interface_t mv88e6390x_port_max_speed_mode(int port);
	302
e28def33 VD	303	int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
e28def33 VD	304
5a7921f4 VD	305	int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
5a7921f4 VD	306
b4e48c50 VD	307	int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip chip, int port, u16 fid);
	308	int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
	309
77064f37 VD	310	int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip chip, int port, u16 pvid);
	311	int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
	312
385a0995 VD	313	int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
385a0995 VD	314	u16 mode);
ef0a7318 AL	315	int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
ef0a7318 AL	316	int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
56995cbc	317	int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9	318	enum mv88e6xxx_egress_mode mode);
56995cbc AL	319	int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
	320	enum mv88e6xxx_frame_mode mode);
	321	int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
	322	enum mv88e6xxx_frame_mode mode);
601aeed3 VD	323	int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
	324	bool unicast, bool multicast);
	325	int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
	326	bool unicast, bool multicast);
56995cbc AL	327	int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
56995cbc AL	328	u16 etype);
ea698f4f VD	329	int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
ea698f4f VD	330	bool message_port);
cd782656 VD	331	int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
cd782656 VD	332	size_t size);
ef70b111 AL	333	int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
ef70b111 AL	334	int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
0898432c VD	335	int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
	336	u8 out);
	337	int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
	338	u8 out);
fdc71eea AL	339	int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
fdc71eea AL	340	phy_interface_t mode);
f39908d3 AL	341	int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
f39908d3 AL	342	phy_interface_t mode);
2d2e1dd2 AL	343	int mv88e6185_port_get_cmode(struct mv88e6xxx_chip chip, int port, u8 cmode);
2d2e1dd2 AL	344	int mv88e6352_port_get_cmode(struct mv88e6xxx_chip chip, int port, u8 cmode);
6c422e34 RK	345	int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
6c422e34 RK	346	struct phylink_link_state *state);
ce91c453 RV	347	int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,
ce91c453 RV	348	struct phylink_link_state *state);
6c422e34	349	int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
c9a2356f	350	struct phylink_link_state *state);
a23b2961 AL	351	int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
	352	int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
	353	int upstream_port);
c8c94891 VD	354
c8c94891 VD	355	int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
9dbfb4e1	356	int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
c8c94891	357
18abed21	358	#endif /* _MV88E6XXX_PORT_H */