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8aa9ebcc VO |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH | |
3 | * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> | |
4 | */ | |
5 | ||
6 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
7 | ||
8 | #include <linux/delay.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/printk.h> | |
11 | #include <linux/spi/spi.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/gpio/consumer.h> | |
ad9f299a | 14 | #include <linux/phylink.h> |
8aa9ebcc VO |
15 | #include <linux/of.h> |
16 | #include <linux/of_net.h> | |
17 | #include <linux/of_mdio.h> | |
18 | #include <linux/of_device.h> | |
19 | #include <linux/netdev_features.h> | |
20 | #include <linux/netdevice.h> | |
21 | #include <linux/if_bridge.h> | |
22 | #include <linux/if_ether.h> | |
227d07a0 | 23 | #include <linux/dsa/8021q.h> |
8aa9ebcc VO |
24 | #include "sja1105.h" |
25 | ||
26 | static void sja1105_hw_reset(struct gpio_desc *gpio, unsigned int pulse_len, | |
27 | unsigned int startup_delay) | |
28 | { | |
29 | gpiod_set_value_cansleep(gpio, 1); | |
30 | /* Wait for minimum reset pulse length */ | |
31 | msleep(pulse_len); | |
32 | gpiod_set_value_cansleep(gpio, 0); | |
33 | /* Wait until chip is ready after reset */ | |
34 | msleep(startup_delay); | |
35 | } | |
36 | ||
37 | static void | |
38 | sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd, | |
39 | int from, int to, bool allow) | |
40 | { | |
41 | if (allow) { | |
42 | l2_fwd[from].bc_domain |= BIT(to); | |
43 | l2_fwd[from].reach_port |= BIT(to); | |
44 | l2_fwd[from].fl_domain |= BIT(to); | |
45 | } else { | |
46 | l2_fwd[from].bc_domain &= ~BIT(to); | |
47 | l2_fwd[from].reach_port &= ~BIT(to); | |
48 | l2_fwd[from].fl_domain &= ~BIT(to); | |
49 | } | |
50 | } | |
51 | ||
52 | /* Structure used to temporarily transport device tree | |
53 | * settings into sja1105_setup | |
54 | */ | |
55 | struct sja1105_dt_port { | |
56 | phy_interface_t phy_mode; | |
57 | sja1105_mii_role_t role; | |
58 | }; | |
59 | ||
60 | static int sja1105_init_mac_settings(struct sja1105_private *priv) | |
61 | { | |
62 | struct sja1105_mac_config_entry default_mac = { | |
63 | /* Enable all 8 priority queues on egress. | |
64 | * Every queue i holds top[i] - base[i] frames. | |
65 | * Sum of top[i] - base[i] is 511 (max hardware limit). | |
66 | */ | |
67 | .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF}, | |
68 | .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0}, | |
69 | .enabled = {true, true, true, true, true, true, true, true}, | |
70 | /* Keep standard IFG of 12 bytes on egress. */ | |
71 | .ifg = 0, | |
72 | /* Always put the MAC speed in automatic mode, where it can be | |
1fd4a173 | 73 | * adjusted at runtime by PHYLINK. |
8aa9ebcc VO |
74 | */ |
75 | .speed = SJA1105_SPEED_AUTO, | |
76 | /* No static correction for 1-step 1588 events */ | |
77 | .tp_delin = 0, | |
78 | .tp_delout = 0, | |
79 | /* Disable aging for critical TTEthernet traffic */ | |
80 | .maxage = 0xFF, | |
81 | /* Internal VLAN (pvid) to apply to untagged ingress */ | |
82 | .vlanprio = 0, | |
e3502b82 | 83 | .vlanid = 1, |
8aa9ebcc VO |
84 | .ing_mirr = false, |
85 | .egr_mirr = false, | |
86 | /* Don't drop traffic with other EtherType than ETH_P_IP */ | |
87 | .drpnona664 = false, | |
88 | /* Don't drop double-tagged traffic */ | |
89 | .drpdtag = false, | |
90 | /* Don't drop untagged traffic */ | |
91 | .drpuntag = false, | |
92 | /* Don't retag 802.1p (VID 0) traffic with the pvid */ | |
93 | .retag = false, | |
640f763f VO |
94 | /* Disable learning and I/O on user ports by default - |
95 | * STP will enable it. | |
96 | */ | |
97 | .dyn_learn = false, | |
8aa9ebcc VO |
98 | .egress = false, |
99 | .ingress = false, | |
100 | }; | |
101 | struct sja1105_mac_config_entry *mac; | |
102 | struct sja1105_table *table; | |
103 | int i; | |
104 | ||
105 | table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG]; | |
106 | ||
107 | /* Discard previous MAC Configuration Table */ | |
108 | if (table->entry_count) { | |
109 | kfree(table->entries); | |
110 | table->entry_count = 0; | |
111 | } | |
112 | ||
113 | table->entries = kcalloc(SJA1105_NUM_PORTS, | |
114 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
115 | if (!table->entries) | |
116 | return -ENOMEM; | |
117 | ||
8aa9ebcc VO |
118 | table->entry_count = SJA1105_NUM_PORTS; |
119 | ||
120 | mac = table->entries; | |
121 | ||
640f763f | 122 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { |
8aa9ebcc | 123 | mac[i] = default_mac; |
640f763f VO |
124 | if (i == dsa_upstream_port(priv->ds, i)) { |
125 | /* STP doesn't get called for CPU port, so we need to | |
126 | * set the I/O parameters statically. | |
127 | */ | |
128 | mac[i].dyn_learn = true; | |
129 | mac[i].ingress = true; | |
130 | mac[i].egress = true; | |
131 | } | |
132 | } | |
8aa9ebcc VO |
133 | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static int sja1105_init_mii_settings(struct sja1105_private *priv, | |
138 | struct sja1105_dt_port *ports) | |
139 | { | |
140 | struct device *dev = &priv->spidev->dev; | |
141 | struct sja1105_xmii_params_entry *mii; | |
142 | struct sja1105_table *table; | |
143 | int i; | |
144 | ||
145 | table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS]; | |
146 | ||
147 | /* Discard previous xMII Mode Parameters Table */ | |
148 | if (table->entry_count) { | |
149 | kfree(table->entries); | |
150 | table->entry_count = 0; | |
151 | } | |
152 | ||
153 | table->entries = kcalloc(SJA1105_MAX_XMII_PARAMS_COUNT, | |
154 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
155 | if (!table->entries) | |
156 | return -ENOMEM; | |
157 | ||
1fd4a173 | 158 | /* Override table based on PHYLINK DT bindings */ |
8aa9ebcc VO |
159 | table->entry_count = SJA1105_MAX_XMII_PARAMS_COUNT; |
160 | ||
161 | mii = table->entries; | |
162 | ||
163 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
164 | switch (ports[i].phy_mode) { | |
165 | case PHY_INTERFACE_MODE_MII: | |
166 | mii->xmii_mode[i] = XMII_MODE_MII; | |
167 | break; | |
168 | case PHY_INTERFACE_MODE_RMII: | |
169 | mii->xmii_mode[i] = XMII_MODE_RMII; | |
170 | break; | |
171 | case PHY_INTERFACE_MODE_RGMII: | |
172 | case PHY_INTERFACE_MODE_RGMII_ID: | |
173 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
174 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
175 | mii->xmii_mode[i] = XMII_MODE_RGMII; | |
176 | break; | |
177 | default: | |
178 | dev_err(dev, "Unsupported PHY mode %s!\n", | |
179 | phy_modes(ports[i].phy_mode)); | |
180 | } | |
181 | ||
182 | mii->phy_mac[i] = ports[i].role; | |
183 | } | |
184 | return 0; | |
185 | } | |
186 | ||
187 | static int sja1105_init_static_fdb(struct sja1105_private *priv) | |
188 | { | |
189 | struct sja1105_table *table; | |
190 | ||
191 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; | |
192 | ||
291d1e72 VO |
193 | /* We only populate the FDB table through dynamic |
194 | * L2 Address Lookup entries | |
195 | */ | |
8aa9ebcc VO |
196 | if (table->entry_count) { |
197 | kfree(table->entries); | |
198 | table->entry_count = 0; | |
199 | } | |
200 | return 0; | |
201 | } | |
202 | ||
203 | static int sja1105_init_l2_lookup_params(struct sja1105_private *priv) | |
204 | { | |
205 | struct sja1105_table *table; | |
6c56e167 | 206 | u64 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / SJA1105_NUM_PORTS; |
8aa9ebcc | 207 | struct sja1105_l2_lookup_params_entry default_l2_lookup_params = { |
8456721d VO |
208 | /* Learned FDB entries are forgotten after 300 seconds */ |
209 | .maxage = SJA1105_AGEING_TIME_MS(300000), | |
8aa9ebcc VO |
210 | /* All entries within a FDB bin are available for learning */ |
211 | .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE, | |
1da73821 VO |
212 | /* And the P/Q/R/S equivalent setting: */ |
213 | .start_dynspc = 0, | |
6c56e167 VO |
214 | .maxaddrp = {max_fdb_entries, max_fdb_entries, max_fdb_entries, |
215 | max_fdb_entries, max_fdb_entries, }, | |
8aa9ebcc VO |
216 | /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */ |
217 | .poly = 0x97, | |
218 | /* This selects between Independent VLAN Learning (IVL) and | |
219 | * Shared VLAN Learning (SVL) | |
220 | */ | |
221 | .shared_learn = false, | |
222 | /* Don't discard management traffic based on ENFPORT - | |
223 | * we don't perform SMAC port enforcement anyway, so | |
224 | * what we are setting here doesn't matter. | |
225 | */ | |
226 | .no_enf_hostprt = false, | |
227 | /* Don't learn SMAC for mac_fltres1 and mac_fltres0. | |
228 | * Maybe correlate with no_linklocal_learn from bridge driver? | |
229 | */ | |
230 | .no_mgmt_learn = true, | |
1da73821 VO |
231 | /* P/Q/R/S only */ |
232 | .use_static = true, | |
233 | /* Dynamically learned FDB entries can overwrite other (older) | |
234 | * dynamic FDB entries | |
235 | */ | |
236 | .owr_dyn = true, | |
237 | .drpnolearn = true, | |
8aa9ebcc VO |
238 | }; |
239 | ||
240 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; | |
241 | ||
242 | if (table->entry_count) { | |
243 | kfree(table->entries); | |
244 | table->entry_count = 0; | |
245 | } | |
246 | ||
247 | table->entries = kcalloc(SJA1105_MAX_L2_LOOKUP_PARAMS_COUNT, | |
248 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
249 | if (!table->entries) | |
250 | return -ENOMEM; | |
251 | ||
252 | table->entry_count = SJA1105_MAX_L2_LOOKUP_PARAMS_COUNT; | |
253 | ||
254 | /* This table only has a single entry */ | |
255 | ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] = | |
256 | default_l2_lookup_params; | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static int sja1105_init_static_vlan(struct sja1105_private *priv) | |
262 | { | |
263 | struct sja1105_table *table; | |
264 | struct sja1105_vlan_lookup_entry pvid = { | |
265 | .ving_mirr = 0, | |
266 | .vegr_mirr = 0, | |
267 | .vmemb_port = 0, | |
268 | .vlan_bc = 0, | |
269 | .tag_port = 0, | |
e3502b82 | 270 | .vlanid = 1, |
8aa9ebcc VO |
271 | }; |
272 | int i; | |
273 | ||
274 | table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; | |
275 | ||
e3502b82 | 276 | /* The static VLAN table will only contain the initial pvid of 1. |
6666cebc VO |
277 | * All other VLANs are to be configured through dynamic entries, |
278 | * and kept in the static configuration table as backing memory. | |
8aa9ebcc VO |
279 | */ |
280 | if (table->entry_count) { | |
281 | kfree(table->entries); | |
282 | table->entry_count = 0; | |
283 | } | |
284 | ||
285 | table->entries = kcalloc(1, table->ops->unpacked_entry_size, | |
286 | GFP_KERNEL); | |
287 | if (!table->entries) | |
288 | return -ENOMEM; | |
289 | ||
290 | table->entry_count = 1; | |
291 | ||
e3502b82 | 292 | /* VLAN 1: all DT-defined ports are members; no restrictions on |
8aa9ebcc VO |
293 | * forwarding; always transmit priority-tagged frames as untagged. |
294 | */ | |
295 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
296 | pvid.vmemb_port |= BIT(i); | |
297 | pvid.vlan_bc |= BIT(i); | |
298 | pvid.tag_port &= ~BIT(i); | |
299 | } | |
300 | ||
301 | ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid; | |
302 | return 0; | |
303 | } | |
304 | ||
305 | static int sja1105_init_l2_forwarding(struct sja1105_private *priv) | |
306 | { | |
307 | struct sja1105_l2_forwarding_entry *l2fwd; | |
308 | struct sja1105_table *table; | |
309 | int i, j; | |
310 | ||
311 | table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING]; | |
312 | ||
313 | if (table->entry_count) { | |
314 | kfree(table->entries); | |
315 | table->entry_count = 0; | |
316 | } | |
317 | ||
318 | table->entries = kcalloc(SJA1105_MAX_L2_FORWARDING_COUNT, | |
319 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
320 | if (!table->entries) | |
321 | return -ENOMEM; | |
322 | ||
323 | table->entry_count = SJA1105_MAX_L2_FORWARDING_COUNT; | |
324 | ||
325 | l2fwd = table->entries; | |
326 | ||
327 | /* First 5 entries define the forwarding rules */ | |
328 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
329 | unsigned int upstream = dsa_upstream_port(priv->ds, i); | |
330 | ||
331 | for (j = 0; j < SJA1105_NUM_TC; j++) | |
332 | l2fwd[i].vlan_pmap[j] = j; | |
333 | ||
334 | if (i == upstream) | |
335 | continue; | |
336 | ||
337 | sja1105_port_allow_traffic(l2fwd, i, upstream, true); | |
338 | sja1105_port_allow_traffic(l2fwd, upstream, i, true); | |
339 | } | |
340 | /* Next 8 entries define VLAN PCP mapping from ingress to egress. | |
341 | * Create a one-to-one mapping. | |
342 | */ | |
343 | for (i = 0; i < SJA1105_NUM_TC; i++) | |
344 | for (j = 0; j < SJA1105_NUM_PORTS; j++) | |
345 | l2fwd[SJA1105_NUM_PORTS + i].vlan_pmap[j] = i; | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv) | |
351 | { | |
352 | struct sja1105_l2_forwarding_params_entry default_l2fwd_params = { | |
353 | /* Disallow dynamic reconfiguration of vlan_pmap */ | |
354 | .max_dynp = 0, | |
355 | /* Use a single memory partition for all ingress queues */ | |
356 | .part_spc = { SJA1105_MAX_FRAME_MEMORY, 0, 0, 0, 0, 0, 0, 0 }, | |
357 | }; | |
358 | struct sja1105_table *table; | |
359 | ||
360 | table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; | |
361 | ||
362 | if (table->entry_count) { | |
363 | kfree(table->entries); | |
364 | table->entry_count = 0; | |
365 | } | |
366 | ||
367 | table->entries = kcalloc(SJA1105_MAX_L2_FORWARDING_PARAMS_COUNT, | |
368 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
369 | if (!table->entries) | |
370 | return -ENOMEM; | |
371 | ||
372 | table->entry_count = SJA1105_MAX_L2_FORWARDING_PARAMS_COUNT; | |
373 | ||
374 | /* This table only has a single entry */ | |
375 | ((struct sja1105_l2_forwarding_params_entry *)table->entries)[0] = | |
376 | default_l2fwd_params; | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static int sja1105_init_general_params(struct sja1105_private *priv) | |
382 | { | |
383 | struct sja1105_general_params_entry default_general_params = { | |
384 | /* Disallow dynamic changing of the mirror port */ | |
385 | .mirr_ptacu = 0, | |
386 | .switchid = priv->ds->index, | |
387 | /* Priority queue for link-local frames trapped to CPU */ | |
08fde09a | 388 | .hostprio = 7, |
8aa9ebcc VO |
389 | .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A, |
390 | .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK, | |
42824463 | 391 | .incl_srcpt1 = false, |
8aa9ebcc VO |
392 | .send_meta1 = false, |
393 | .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B, | |
394 | .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK, | |
42824463 | 395 | .incl_srcpt0 = false, |
8aa9ebcc VO |
396 | .send_meta0 = false, |
397 | /* The destination for traffic matching mac_fltres1 and | |
398 | * mac_fltres0 on all ports except host_port. Such traffic | |
399 | * receieved on host_port itself would be dropped, except | |
400 | * by installing a temporary 'management route' | |
401 | */ | |
402 | .host_port = dsa_upstream_port(priv->ds, 0), | |
403 | /* Same as host port */ | |
404 | .mirr_port = dsa_upstream_port(priv->ds, 0), | |
405 | /* Link-local traffic received on casc_port will be forwarded | |
406 | * to host_port without embedding the source port and device ID | |
407 | * info in the destination MAC address (presumably because it | |
408 | * is a cascaded port and a downstream SJA switch already did | |
409 | * that). Default to an invalid port (to disable the feature) | |
410 | * and overwrite this if we find any DSA (cascaded) ports. | |
411 | */ | |
412 | .casc_port = SJA1105_NUM_PORTS, | |
413 | /* No TTEthernet */ | |
414 | .vllupformat = 0, | |
415 | .vlmarker = 0, | |
416 | .vlmask = 0, | |
417 | /* Only update correctionField for 1-step PTP (L2 transport) */ | |
418 | .ignore2stf = 0, | |
6666cebc VO |
419 | /* Forcefully disable VLAN filtering by telling |
420 | * the switch that VLAN has a different EtherType. | |
421 | */ | |
422 | .tpid = ETH_P_SJA1105, | |
423 | .tpid2 = ETH_P_SJA1105, | |
8aa9ebcc VO |
424 | }; |
425 | struct sja1105_table *table; | |
227d07a0 | 426 | int i, k = 0; |
8aa9ebcc | 427 | |
227d07a0 | 428 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { |
8aa9ebcc VO |
429 | if (dsa_is_dsa_port(priv->ds, i)) |
430 | default_general_params.casc_port = i; | |
227d07a0 VO |
431 | else if (dsa_is_user_port(priv->ds, i)) |
432 | priv->ports[i].mgmt_slot = k++; | |
433 | } | |
8aa9ebcc VO |
434 | |
435 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; | |
436 | ||
437 | if (table->entry_count) { | |
438 | kfree(table->entries); | |
439 | table->entry_count = 0; | |
440 | } | |
441 | ||
442 | table->entries = kcalloc(SJA1105_MAX_GENERAL_PARAMS_COUNT, | |
443 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
444 | if (!table->entries) | |
445 | return -ENOMEM; | |
446 | ||
447 | table->entry_count = SJA1105_MAX_GENERAL_PARAMS_COUNT; | |
448 | ||
449 | /* This table only has a single entry */ | |
450 | ((struct sja1105_general_params_entry *)table->entries)[0] = | |
451 | default_general_params; | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000) | |
457 | ||
458 | static inline void | |
459 | sja1105_setup_policer(struct sja1105_l2_policing_entry *policing, | |
460 | int index) | |
461 | { | |
462 | policing[index].sharindx = index; | |
463 | policing[index].smax = 65535; /* Burst size in bytes */ | |
464 | policing[index].rate = SJA1105_RATE_MBPS(1000); | |
465 | policing[index].maxlen = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN; | |
466 | policing[index].partition = 0; | |
467 | } | |
468 | ||
469 | static int sja1105_init_l2_policing(struct sja1105_private *priv) | |
470 | { | |
471 | struct sja1105_l2_policing_entry *policing; | |
472 | struct sja1105_table *table; | |
473 | int i, j, k; | |
474 | ||
475 | table = &priv->static_config.tables[BLK_IDX_L2_POLICING]; | |
476 | ||
477 | /* Discard previous L2 Policing Table */ | |
478 | if (table->entry_count) { | |
479 | kfree(table->entries); | |
480 | table->entry_count = 0; | |
481 | } | |
482 | ||
483 | table->entries = kcalloc(SJA1105_MAX_L2_POLICING_COUNT, | |
484 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
485 | if (!table->entries) | |
486 | return -ENOMEM; | |
487 | ||
488 | table->entry_count = SJA1105_MAX_L2_POLICING_COUNT; | |
489 | ||
490 | policing = table->entries; | |
491 | ||
492 | /* k sweeps through all unicast policers (0-39). | |
493 | * bcast sweeps through policers 40-44. | |
494 | */ | |
495 | for (i = 0, k = 0; i < SJA1105_NUM_PORTS; i++) { | |
496 | int bcast = (SJA1105_NUM_PORTS * SJA1105_NUM_TC) + i; | |
497 | ||
498 | for (j = 0; j < SJA1105_NUM_TC; j++, k++) | |
499 | sja1105_setup_policer(policing, k); | |
500 | ||
501 | /* Set up this port's policer for broadcast traffic */ | |
502 | sja1105_setup_policer(policing, bcast); | |
503 | } | |
504 | return 0; | |
505 | } | |
506 | ||
24c01949 VO |
507 | static int sja1105_init_avb_params(struct sja1105_private *priv, |
508 | bool on) | |
509 | { | |
510 | struct sja1105_avb_params_entry *avb; | |
511 | struct sja1105_table *table; | |
512 | ||
513 | table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS]; | |
514 | ||
515 | /* Discard previous AVB Parameters Table */ | |
516 | if (table->entry_count) { | |
517 | kfree(table->entries); | |
518 | table->entry_count = 0; | |
519 | } | |
520 | ||
521 | /* Configure the reception of meta frames only if requested */ | |
522 | if (!on) | |
523 | return 0; | |
524 | ||
525 | table->entries = kcalloc(SJA1105_MAX_AVB_PARAMS_COUNT, | |
526 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
527 | if (!table->entries) | |
528 | return -ENOMEM; | |
529 | ||
530 | table->entry_count = SJA1105_MAX_AVB_PARAMS_COUNT; | |
531 | ||
532 | avb = table->entries; | |
533 | ||
534 | avb->destmeta = SJA1105_META_DMAC; | |
535 | avb->srcmeta = SJA1105_META_SMAC; | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
8aa9ebcc VO |
540 | static int sja1105_static_config_load(struct sja1105_private *priv, |
541 | struct sja1105_dt_port *ports) | |
542 | { | |
543 | int rc; | |
544 | ||
545 | sja1105_static_config_free(&priv->static_config); | |
546 | rc = sja1105_static_config_init(&priv->static_config, | |
547 | priv->info->static_ops, | |
548 | priv->info->device_id); | |
549 | if (rc) | |
550 | return rc; | |
551 | ||
552 | /* Build static configuration */ | |
553 | rc = sja1105_init_mac_settings(priv); | |
554 | if (rc < 0) | |
555 | return rc; | |
556 | rc = sja1105_init_mii_settings(priv, ports); | |
557 | if (rc < 0) | |
558 | return rc; | |
559 | rc = sja1105_init_static_fdb(priv); | |
560 | if (rc < 0) | |
561 | return rc; | |
562 | rc = sja1105_init_static_vlan(priv); | |
563 | if (rc < 0) | |
564 | return rc; | |
565 | rc = sja1105_init_l2_lookup_params(priv); | |
566 | if (rc < 0) | |
567 | return rc; | |
568 | rc = sja1105_init_l2_forwarding(priv); | |
569 | if (rc < 0) | |
570 | return rc; | |
571 | rc = sja1105_init_l2_forwarding_params(priv); | |
572 | if (rc < 0) | |
573 | return rc; | |
574 | rc = sja1105_init_l2_policing(priv); | |
575 | if (rc < 0) | |
576 | return rc; | |
577 | rc = sja1105_init_general_params(priv); | |
24c01949 VO |
578 | if (rc < 0) |
579 | return rc; | |
580 | rc = sja1105_init_avb_params(priv, false); | |
8aa9ebcc VO |
581 | if (rc < 0) |
582 | return rc; | |
583 | ||
584 | /* Send initial configuration to hardware via SPI */ | |
585 | return sja1105_static_config_upload(priv); | |
586 | } | |
587 | ||
f5b8631c VO |
588 | static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, |
589 | const struct sja1105_dt_port *ports) | |
590 | { | |
591 | int i; | |
592 | ||
593 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
594 | if (ports->role == XMII_MAC) | |
595 | continue; | |
596 | ||
597 | if (ports->phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || | |
598 | ports->phy_mode == PHY_INTERFACE_MODE_RGMII_ID) | |
599 | priv->rgmii_rx_delay[i] = true; | |
600 | ||
601 | if (ports->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || | |
602 | ports->phy_mode == PHY_INTERFACE_MODE_RGMII_ID) | |
603 | priv->rgmii_tx_delay[i] = true; | |
604 | ||
605 | if ((priv->rgmii_rx_delay[i] || priv->rgmii_tx_delay[i]) && | |
606 | !priv->info->setup_rgmii_delay) | |
607 | return -EINVAL; | |
608 | } | |
609 | return 0; | |
610 | } | |
611 | ||
8aa9ebcc VO |
612 | static int sja1105_parse_ports_node(struct sja1105_private *priv, |
613 | struct sja1105_dt_port *ports, | |
614 | struct device_node *ports_node) | |
615 | { | |
616 | struct device *dev = &priv->spidev->dev; | |
617 | struct device_node *child; | |
618 | ||
619 | for_each_child_of_node(ports_node, child) { | |
620 | struct device_node *phy_node; | |
621 | int phy_mode; | |
622 | u32 index; | |
623 | ||
624 | /* Get switch port number from DT */ | |
625 | if (of_property_read_u32(child, "reg", &index) < 0) { | |
626 | dev_err(dev, "Port number not defined in device tree " | |
627 | "(property \"reg\")\n"); | |
628 | return -ENODEV; | |
629 | } | |
630 | ||
631 | /* Get PHY mode from DT */ | |
632 | phy_mode = of_get_phy_mode(child); | |
633 | if (phy_mode < 0) { | |
634 | dev_err(dev, "Failed to read phy-mode or " | |
635 | "phy-interface-type property for port %d\n", | |
636 | index); | |
637 | return -ENODEV; | |
638 | } | |
639 | ports[index].phy_mode = phy_mode; | |
640 | ||
641 | phy_node = of_parse_phandle(child, "phy-handle", 0); | |
642 | if (!phy_node) { | |
643 | if (!of_phy_is_fixed_link(child)) { | |
644 | dev_err(dev, "phy-handle or fixed-link " | |
645 | "properties missing!\n"); | |
646 | return -ENODEV; | |
647 | } | |
648 | /* phy-handle is missing, but fixed-link isn't. | |
649 | * So it's a fixed link. Default to PHY role. | |
650 | */ | |
651 | ports[index].role = XMII_PHY; | |
652 | } else { | |
653 | /* phy-handle present => put port in MAC role */ | |
654 | ports[index].role = XMII_MAC; | |
655 | of_node_put(phy_node); | |
656 | } | |
657 | ||
658 | /* The MAC/PHY role can be overridden with explicit bindings */ | |
659 | if (of_property_read_bool(child, "sja1105,role-mac")) | |
660 | ports[index].role = XMII_MAC; | |
661 | else if (of_property_read_bool(child, "sja1105,role-phy")) | |
662 | ports[index].role = XMII_PHY; | |
663 | } | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
668 | static int sja1105_parse_dt(struct sja1105_private *priv, | |
669 | struct sja1105_dt_port *ports) | |
670 | { | |
671 | struct device *dev = &priv->spidev->dev; | |
672 | struct device_node *switch_node = dev->of_node; | |
673 | struct device_node *ports_node; | |
674 | int rc; | |
675 | ||
676 | ports_node = of_get_child_by_name(switch_node, "ports"); | |
677 | if (!ports_node) { | |
678 | dev_err(dev, "Incorrect bindings: absent \"ports\" node\n"); | |
679 | return -ENODEV; | |
680 | } | |
681 | ||
682 | rc = sja1105_parse_ports_node(priv, ports, ports_node); | |
683 | of_node_put(ports_node); | |
684 | ||
685 | return rc; | |
686 | } | |
687 | ||
c44d0535 | 688 | /* Convert link speed from SJA1105 to ethtool encoding */ |
8aa9ebcc | 689 | static int sja1105_speed[] = { |
c44d0535 VO |
690 | [SJA1105_SPEED_AUTO] = SPEED_UNKNOWN, |
691 | [SJA1105_SPEED_10MBPS] = SPEED_10, | |
692 | [SJA1105_SPEED_100MBPS] = SPEED_100, | |
693 | [SJA1105_SPEED_1000MBPS] = SPEED_1000, | |
8aa9ebcc VO |
694 | }; |
695 | ||
8400cff6 | 696 | /* Set link speed in the MAC configuration for a specific port. */ |
8aa9ebcc | 697 | static int sja1105_adjust_port_config(struct sja1105_private *priv, int port, |
8400cff6 | 698 | int speed_mbps) |
8aa9ebcc VO |
699 | { |
700 | struct sja1105_xmii_params_entry *mii; | |
701 | struct sja1105_mac_config_entry *mac; | |
702 | struct device *dev = priv->ds->dev; | |
703 | sja1105_phy_interface_t phy_mode; | |
704 | sja1105_speed_t speed; | |
705 | int rc; | |
706 | ||
8400cff6 VO |
707 | /* On P/Q/R/S, one can read from the device via the MAC reconfiguration |
708 | * tables. On E/T, MAC reconfig tables are not readable, only writable. | |
709 | * We have to *know* what the MAC looks like. For the sake of keeping | |
710 | * the code common, we'll use the static configuration tables as a | |
711 | * reasonable approximation for both E/T and P/Q/R/S. | |
712 | */ | |
8aa9ebcc | 713 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
8400cff6 | 714 | mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; |
8aa9ebcc | 715 | |
f4cfcfbd | 716 | switch (speed_mbps) { |
c44d0535 | 717 | case SPEED_UNKNOWN: |
f4cfcfbd VO |
718 | /* No speed update requested */ |
719 | speed = SJA1105_SPEED_AUTO; | |
720 | break; | |
c44d0535 | 721 | case SPEED_10: |
f4cfcfbd VO |
722 | speed = SJA1105_SPEED_10MBPS; |
723 | break; | |
c44d0535 | 724 | case SPEED_100: |
f4cfcfbd VO |
725 | speed = SJA1105_SPEED_100MBPS; |
726 | break; | |
c44d0535 | 727 | case SPEED_1000: |
f4cfcfbd VO |
728 | speed = SJA1105_SPEED_1000MBPS; |
729 | break; | |
730 | default: | |
8aa9ebcc VO |
731 | dev_err(dev, "Invalid speed %iMbps\n", speed_mbps); |
732 | return -EINVAL; | |
733 | } | |
734 | ||
8400cff6 VO |
735 | /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration |
736 | * table, since this will be used for the clocking setup, and we no | |
737 | * longer need to store it in the static config (already told hardware | |
738 | * we want auto during upload phase). | |
8aa9ebcc | 739 | */ |
f4cfcfbd | 740 | mac[port].speed = speed; |
8aa9ebcc | 741 | |
8aa9ebcc | 742 | /* Write to the dynamic reconfiguration tables */ |
8400cff6 VO |
743 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, |
744 | &mac[port], true); | |
8aa9ebcc VO |
745 | if (rc < 0) { |
746 | dev_err(dev, "Failed to write MAC config: %d\n", rc); | |
747 | return rc; | |
748 | } | |
749 | ||
750 | /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at | |
751 | * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and | |
752 | * RMII no change of the clock setup is required. Actually, changing | |
753 | * the clock setup does interrupt the clock signal for a certain time | |
754 | * which causes trouble for all PHYs relying on this signal. | |
755 | */ | |
8aa9ebcc VO |
756 | phy_mode = mii->xmii_mode[port]; |
757 | if (phy_mode != XMII_MODE_RGMII) | |
758 | return 0; | |
759 | ||
760 | return sja1105_clocking_setup_port(priv, port); | |
761 | } | |
762 | ||
af7cd036 VO |
763 | static void sja1105_mac_config(struct dsa_switch *ds, int port, |
764 | unsigned int link_an_mode, | |
765 | const struct phylink_link_state *state) | |
8aa9ebcc VO |
766 | { |
767 | struct sja1105_private *priv = ds->priv; | |
768 | ||
af7cd036 | 769 | if (!state->link) |
8400cff6 VO |
770 | return; |
771 | ||
772 | sja1105_adjust_port_config(priv, port, state->speed); | |
773 | } | |
774 | ||
775 | static void sja1105_mac_link_down(struct dsa_switch *ds, int port, | |
776 | unsigned int mode, | |
777 | phy_interface_t interface) | |
778 | { | |
779 | sja1105_inhibit_tx(ds->priv, BIT(port), true); | |
780 | } | |
781 | ||
782 | static void sja1105_mac_link_up(struct dsa_switch *ds, int port, | |
783 | unsigned int mode, | |
784 | phy_interface_t interface, | |
785 | struct phy_device *phydev) | |
786 | { | |
787 | sja1105_inhibit_tx(ds->priv, BIT(port), false); | |
8aa9ebcc VO |
788 | } |
789 | ||
ad9f299a VO |
790 | static void sja1105_phylink_validate(struct dsa_switch *ds, int port, |
791 | unsigned long *supported, | |
792 | struct phylink_link_state *state) | |
793 | { | |
794 | /* Construct a new mask which exhaustively contains all link features | |
795 | * supported by the MAC, and then apply that (logical AND) to what will | |
796 | * be sent to the PHY for "marketing". | |
797 | */ | |
798 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; | |
799 | struct sja1105_private *priv = ds->priv; | |
800 | struct sja1105_xmii_params_entry *mii; | |
801 | ||
802 | mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; | |
803 | ||
804 | /* The MAC does not support pause frames, and also doesn't | |
805 | * support half-duplex traffic modes. | |
806 | */ | |
807 | phylink_set(mask, Autoneg); | |
808 | phylink_set(mask, MII); | |
809 | phylink_set(mask, 10baseT_Full); | |
810 | phylink_set(mask, 100baseT_Full); | |
811 | if (mii->xmii_mode[port] == XMII_MODE_RGMII) | |
812 | phylink_set(mask, 1000baseT_Full); | |
813 | ||
814 | bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
815 | bitmap_and(state->advertising, state->advertising, mask, | |
816 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
817 | } | |
818 | ||
291d1e72 VO |
819 | /* First-generation switches have a 4-way set associative TCAM that |
820 | * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of | |
821 | * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin). | |
822 | * For the placement of a newly learnt FDB entry, the switch selects the bin | |
823 | * based on a hash function, and the way within that bin incrementally. | |
824 | */ | |
825 | static inline int sja1105et_fdb_index(int bin, int way) | |
826 | { | |
827 | return bin * SJA1105ET_FDB_BIN_SIZE + way; | |
828 | } | |
829 | ||
9dfa6911 VO |
830 | static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin, |
831 | const u8 *addr, u16 vid, | |
832 | struct sja1105_l2_lookup_entry *match, | |
833 | int *last_unused) | |
291d1e72 VO |
834 | { |
835 | int way; | |
836 | ||
837 | for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) { | |
838 | struct sja1105_l2_lookup_entry l2_lookup = {0}; | |
839 | int index = sja1105et_fdb_index(bin, way); | |
840 | ||
841 | /* Skip unused entries, optionally marking them | |
842 | * into the return value | |
843 | */ | |
844 | if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
845 | index, &l2_lookup)) { | |
846 | if (last_unused) | |
847 | *last_unused = way; | |
848 | continue; | |
849 | } | |
850 | ||
851 | if (l2_lookup.macaddr == ether_addr_to_u64(addr) && | |
852 | l2_lookup.vlanid == vid) { | |
853 | if (match) | |
854 | *match = l2_lookup; | |
855 | return way; | |
856 | } | |
857 | } | |
858 | /* Return an invalid entry index if not found */ | |
859 | return -1; | |
860 | } | |
861 | ||
9dfa6911 VO |
862 | int sja1105et_fdb_add(struct dsa_switch *ds, int port, |
863 | const unsigned char *addr, u16 vid) | |
291d1e72 VO |
864 | { |
865 | struct sja1105_l2_lookup_entry l2_lookup = {0}; | |
866 | struct sja1105_private *priv = ds->priv; | |
867 | struct device *dev = ds->dev; | |
868 | int last_unused = -1; | |
869 | int bin, way; | |
870 | ||
9dfa6911 | 871 | bin = sja1105et_fdb_hash(priv, addr, vid); |
291d1e72 | 872 | |
9dfa6911 VO |
873 | way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, |
874 | &l2_lookup, &last_unused); | |
291d1e72 VO |
875 | if (way >= 0) { |
876 | /* We have an FDB entry. Is our port in the destination | |
877 | * mask? If yes, we need to do nothing. If not, we need | |
878 | * to rewrite the entry by adding this port to it. | |
879 | */ | |
880 | if (l2_lookup.destports & BIT(port)) | |
881 | return 0; | |
882 | l2_lookup.destports |= BIT(port); | |
883 | } else { | |
884 | int index = sja1105et_fdb_index(bin, way); | |
885 | ||
886 | /* We don't have an FDB entry. We construct a new one and | |
887 | * try to find a place for it within the FDB table. | |
888 | */ | |
889 | l2_lookup.macaddr = ether_addr_to_u64(addr); | |
890 | l2_lookup.destports = BIT(port); | |
891 | l2_lookup.vlanid = vid; | |
892 | ||
893 | if (last_unused >= 0) { | |
894 | way = last_unused; | |
895 | } else { | |
896 | /* Bin is full, need to evict somebody. | |
897 | * Choose victim at random. If you get these messages | |
898 | * often, you may need to consider changing the | |
899 | * distribution function: | |
900 | * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly | |
901 | */ | |
902 | get_random_bytes(&way, sizeof(u8)); | |
903 | way %= SJA1105ET_FDB_BIN_SIZE; | |
904 | dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n", | |
905 | bin, addr, way); | |
906 | /* Evict entry */ | |
907 | sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, | |
908 | index, NULL, false); | |
909 | } | |
910 | } | |
911 | l2_lookup.index = sja1105et_fdb_index(bin, way); | |
912 | ||
913 | return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, | |
914 | l2_lookup.index, &l2_lookup, | |
915 | true); | |
916 | } | |
917 | ||
9dfa6911 VO |
918 | int sja1105et_fdb_del(struct dsa_switch *ds, int port, |
919 | const unsigned char *addr, u16 vid) | |
291d1e72 VO |
920 | { |
921 | struct sja1105_l2_lookup_entry l2_lookup = {0}; | |
922 | struct sja1105_private *priv = ds->priv; | |
923 | int index, bin, way; | |
924 | bool keep; | |
925 | ||
9dfa6911 VO |
926 | bin = sja1105et_fdb_hash(priv, addr, vid); |
927 | way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, | |
928 | &l2_lookup, NULL); | |
291d1e72 VO |
929 | if (way < 0) |
930 | return 0; | |
931 | index = sja1105et_fdb_index(bin, way); | |
932 | ||
933 | /* We have an FDB entry. Is our port in the destination mask? If yes, | |
934 | * we need to remove it. If the resulting port mask becomes empty, we | |
935 | * need to completely evict the FDB entry. | |
936 | * Otherwise we just write it back. | |
937 | */ | |
7752e937 VO |
938 | l2_lookup.destports &= ~BIT(port); |
939 | ||
291d1e72 VO |
940 | if (l2_lookup.destports) |
941 | keep = true; | |
942 | else | |
943 | keep = false; | |
944 | ||
945 | return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, | |
946 | index, &l2_lookup, keep); | |
947 | } | |
948 | ||
9dfa6911 VO |
949 | int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, |
950 | const unsigned char *addr, u16 vid) | |
951 | { | |
1da73821 VO |
952 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
953 | struct sja1105_private *priv = ds->priv; | |
954 | int rc, i; | |
955 | ||
956 | /* Search for an existing entry in the FDB table */ | |
957 | l2_lookup.macaddr = ether_addr_to_u64(addr); | |
958 | l2_lookup.vlanid = vid; | |
959 | l2_lookup.iotag = SJA1105_S_TAG; | |
960 | l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); | |
961 | l2_lookup.mask_vlanid = VLAN_VID_MASK; | |
962 | l2_lookup.mask_iotag = BIT(0); | |
963 | l2_lookup.destports = BIT(port); | |
964 | ||
965 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
966 | SJA1105_SEARCH, &l2_lookup); | |
967 | if (rc == 0) { | |
968 | /* Found and this port is already in the entry's | |
969 | * port mask => job done | |
970 | */ | |
971 | if (l2_lookup.destports & BIT(port)) | |
972 | return 0; | |
973 | /* l2_lookup.index is populated by the switch in case it | |
974 | * found something. | |
975 | */ | |
976 | l2_lookup.destports |= BIT(port); | |
977 | goto skip_finding_an_index; | |
978 | } | |
979 | ||
980 | /* Not found, so try to find an unused spot in the FDB. | |
981 | * This is slightly inefficient because the strategy is knock-knock at | |
982 | * every possible position from 0 to 1023. | |
983 | */ | |
984 | for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { | |
985 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
986 | i, NULL); | |
987 | if (rc < 0) | |
988 | break; | |
989 | } | |
990 | if (i == SJA1105_MAX_L2_LOOKUP_COUNT) { | |
991 | dev_err(ds->dev, "FDB is full, cannot add entry.\n"); | |
992 | return -EINVAL; | |
993 | } | |
994 | l2_lookup.index = i; | |
995 | ||
996 | skip_finding_an_index: | |
997 | return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, | |
998 | l2_lookup.index, &l2_lookup, | |
999 | true); | |
9dfa6911 VO |
1000 | } |
1001 | ||
1002 | int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, | |
1003 | const unsigned char *addr, u16 vid) | |
1004 | { | |
1da73821 VO |
1005 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
1006 | struct sja1105_private *priv = ds->priv; | |
1007 | bool keep; | |
1008 | int rc; | |
1009 | ||
1010 | l2_lookup.macaddr = ether_addr_to_u64(addr); | |
1011 | l2_lookup.vlanid = vid; | |
1012 | l2_lookup.iotag = SJA1105_S_TAG; | |
1013 | l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); | |
1014 | l2_lookup.mask_vlanid = VLAN_VID_MASK; | |
1015 | l2_lookup.mask_iotag = BIT(0); | |
1016 | l2_lookup.destports = BIT(port); | |
1017 | ||
1018 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
1019 | SJA1105_SEARCH, &l2_lookup); | |
1020 | if (rc < 0) | |
1021 | return 0; | |
1022 | ||
1023 | l2_lookup.destports &= ~BIT(port); | |
1024 | ||
1025 | /* Decide whether we remove just this port from the FDB entry, | |
1026 | * or if we remove it completely. | |
1027 | */ | |
1028 | if (l2_lookup.destports) | |
1029 | keep = true; | |
1030 | else | |
1031 | keep = false; | |
1032 | ||
1033 | return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, | |
1034 | l2_lookup.index, &l2_lookup, keep); | |
9dfa6911 VO |
1035 | } |
1036 | ||
1037 | static int sja1105_fdb_add(struct dsa_switch *ds, int port, | |
1038 | const unsigned char *addr, u16 vid) | |
1039 | { | |
1040 | struct sja1105_private *priv = ds->priv; | |
93647594 VO |
1041 | int rc; |
1042 | ||
1043 | /* Since we make use of VLANs even when the bridge core doesn't tell us | |
1044 | * to, translate these FDB entries into the correct dsa_8021q ones. | |
1045 | */ | |
1046 | if (!dsa_port_is_vlan_filtering(&ds->ports[port])) { | |
1047 | unsigned int upstream = dsa_upstream_port(priv->ds, port); | |
1048 | u16 tx_vid = dsa_8021q_tx_vid(ds, port); | |
1049 | u16 rx_vid = dsa_8021q_rx_vid(ds, port); | |
9dfa6911 | 1050 | |
93647594 VO |
1051 | rc = priv->info->fdb_add_cmd(ds, port, addr, tx_vid); |
1052 | if (rc < 0) | |
1053 | return rc; | |
1054 | return priv->info->fdb_add_cmd(ds, upstream, addr, rx_vid); | |
1055 | } | |
9dfa6911 VO |
1056 | return priv->info->fdb_add_cmd(ds, port, addr, vid); |
1057 | } | |
1058 | ||
1059 | static int sja1105_fdb_del(struct dsa_switch *ds, int port, | |
1060 | const unsigned char *addr, u16 vid) | |
1061 | { | |
1062 | struct sja1105_private *priv = ds->priv; | |
93647594 | 1063 | int rc; |
9dfa6911 | 1064 | |
93647594 VO |
1065 | /* Since we make use of VLANs even when the bridge core doesn't tell us |
1066 | * to, translate these FDB entries into the correct dsa_8021q ones. | |
1067 | */ | |
1068 | if (!dsa_port_is_vlan_filtering(&ds->ports[port])) { | |
1069 | unsigned int upstream = dsa_upstream_port(priv->ds, port); | |
1070 | u16 tx_vid = dsa_8021q_tx_vid(ds, port); | |
1071 | u16 rx_vid = dsa_8021q_rx_vid(ds, port); | |
1072 | ||
1073 | rc = priv->info->fdb_del_cmd(ds, port, addr, tx_vid); | |
1074 | if (rc < 0) | |
1075 | return rc; | |
1076 | return priv->info->fdb_del_cmd(ds, upstream, addr, rx_vid); | |
1077 | } | |
9dfa6911 VO |
1078 | return priv->info->fdb_del_cmd(ds, port, addr, vid); |
1079 | } | |
1080 | ||
291d1e72 VO |
1081 | static int sja1105_fdb_dump(struct dsa_switch *ds, int port, |
1082 | dsa_fdb_dump_cb_t *cb, void *data) | |
1083 | { | |
1084 | struct sja1105_private *priv = ds->priv; | |
1085 | struct device *dev = ds->dev; | |
1086 | int i; | |
1087 | ||
1088 | for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { | |
1089 | struct sja1105_l2_lookup_entry l2_lookup = {0}; | |
1090 | u8 macaddr[ETH_ALEN]; | |
1091 | int rc; | |
1092 | ||
1093 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
1094 | i, &l2_lookup); | |
1095 | /* No fdb entry at i, not an issue */ | |
def84604 | 1096 | if (rc == -ENOENT) |
291d1e72 VO |
1097 | continue; |
1098 | if (rc) { | |
1099 | dev_err(dev, "Failed to dump FDB: %d\n", rc); | |
1100 | return rc; | |
1101 | } | |
1102 | ||
1103 | /* FDB dump callback is per port. This means we have to | |
1104 | * disregard a valid entry if it's not for this port, even if | |
1105 | * only to revisit it later. This is inefficient because the | |
1106 | * 1024-sized FDB table needs to be traversed 4 times through | |
1107 | * SPI during a 'bridge fdb show' command. | |
1108 | */ | |
1109 | if (!(l2_lookup.destports & BIT(port))) | |
1110 | continue; | |
1111 | u64_to_ether_addr(l2_lookup.macaddr, macaddr); | |
93647594 VO |
1112 | |
1113 | /* We need to hide the dsa_8021q VLAN from the user. | |
1114 | * Convert the TX VID into the pvid that is active in | |
1115 | * standalone and non-vlan_filtering modes, aka 1. | |
1116 | * The RX VID is applied on the CPU port, which is not seen by | |
1117 | * the bridge core anyway, so there's nothing to hide. | |
1118 | */ | |
1119 | if (!dsa_port_is_vlan_filtering(&ds->ports[port])) | |
1120 | l2_lookup.vlanid = 1; | |
291d1e72 VO |
1121 | cb(macaddr, l2_lookup.vlanid, false, data); |
1122 | } | |
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | /* This callback needs to be present */ | |
1127 | static int sja1105_mdb_prepare(struct dsa_switch *ds, int port, | |
1128 | const struct switchdev_obj_port_mdb *mdb) | |
1129 | { | |
1130 | return 0; | |
1131 | } | |
1132 | ||
1133 | static void sja1105_mdb_add(struct dsa_switch *ds, int port, | |
1134 | const struct switchdev_obj_port_mdb *mdb) | |
1135 | { | |
1136 | sja1105_fdb_add(ds, port, mdb->addr, mdb->vid); | |
1137 | } | |
1138 | ||
1139 | static int sja1105_mdb_del(struct dsa_switch *ds, int port, | |
1140 | const struct switchdev_obj_port_mdb *mdb) | |
1141 | { | |
1142 | return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid); | |
1143 | } | |
1144 | ||
8aa9ebcc VO |
1145 | static int sja1105_bridge_member(struct dsa_switch *ds, int port, |
1146 | struct net_device *br, bool member) | |
1147 | { | |
1148 | struct sja1105_l2_forwarding_entry *l2_fwd; | |
1149 | struct sja1105_private *priv = ds->priv; | |
1150 | int i, rc; | |
1151 | ||
1152 | l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; | |
1153 | ||
1154 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
1155 | /* Add this port to the forwarding matrix of the | |
1156 | * other ports in the same bridge, and viceversa. | |
1157 | */ | |
1158 | if (!dsa_is_user_port(ds, i)) | |
1159 | continue; | |
1160 | /* For the ports already under the bridge, only one thing needs | |
1161 | * to be done, and that is to add this port to their | |
1162 | * reachability domain. So we can perform the SPI write for | |
1163 | * them immediately. However, for this port itself (the one | |
1164 | * that is new to the bridge), we need to add all other ports | |
1165 | * to its reachability domain. So we do that incrementally in | |
1166 | * this loop, and perform the SPI write only at the end, once | |
1167 | * the domain contains all other bridge ports. | |
1168 | */ | |
1169 | if (i == port) | |
1170 | continue; | |
1171 | if (dsa_to_port(ds, i)->bridge_dev != br) | |
1172 | continue; | |
1173 | sja1105_port_allow_traffic(l2_fwd, i, port, member); | |
1174 | sja1105_port_allow_traffic(l2_fwd, port, i, member); | |
1175 | ||
1176 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, | |
1177 | i, &l2_fwd[i], true); | |
1178 | if (rc < 0) | |
1179 | return rc; | |
1180 | } | |
1181 | ||
1182 | return sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, | |
1183 | port, &l2_fwd[port], true); | |
1184 | } | |
1185 | ||
640f763f VO |
1186 | static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port, |
1187 | u8 state) | |
1188 | { | |
1189 | struct sja1105_private *priv = ds->priv; | |
1190 | struct sja1105_mac_config_entry *mac; | |
1191 | ||
1192 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; | |
1193 | ||
1194 | switch (state) { | |
1195 | case BR_STATE_DISABLED: | |
1196 | case BR_STATE_BLOCKING: | |
1197 | /* From UM10944 description of DRPDTAG (why put this there?): | |
1198 | * "Management traffic flows to the port regardless of the state | |
1199 | * of the INGRESS flag". So BPDUs are still be allowed to pass. | |
1200 | * At the moment no difference between DISABLED and BLOCKING. | |
1201 | */ | |
1202 | mac[port].ingress = false; | |
1203 | mac[port].egress = false; | |
1204 | mac[port].dyn_learn = false; | |
1205 | break; | |
1206 | case BR_STATE_LISTENING: | |
1207 | mac[port].ingress = true; | |
1208 | mac[port].egress = false; | |
1209 | mac[port].dyn_learn = false; | |
1210 | break; | |
1211 | case BR_STATE_LEARNING: | |
1212 | mac[port].ingress = true; | |
1213 | mac[port].egress = false; | |
1214 | mac[port].dyn_learn = true; | |
1215 | break; | |
1216 | case BR_STATE_FORWARDING: | |
1217 | mac[port].ingress = true; | |
1218 | mac[port].egress = true; | |
1219 | mac[port].dyn_learn = true; | |
1220 | break; | |
1221 | default: | |
1222 | dev_err(ds->dev, "invalid STP state: %d\n", state); | |
1223 | return; | |
1224 | } | |
1225 | ||
1226 | sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, | |
1227 | &mac[port], true); | |
1228 | } | |
1229 | ||
8aa9ebcc VO |
1230 | static int sja1105_bridge_join(struct dsa_switch *ds, int port, |
1231 | struct net_device *br) | |
1232 | { | |
1233 | return sja1105_bridge_member(ds, port, br, true); | |
1234 | } | |
1235 | ||
1236 | static void sja1105_bridge_leave(struct dsa_switch *ds, int port, | |
1237 | struct net_device *br) | |
1238 | { | |
1239 | sja1105_bridge_member(ds, port, br, false); | |
1240 | } | |
1241 | ||
6666cebc VO |
1242 | /* For situations where we need to change a setting at runtime that is only |
1243 | * available through the static configuration, resetting the switch in order | |
1244 | * to upload the new static config is unavoidable. Back up the settings we | |
1245 | * modify at runtime (currently only MAC) and restore them after uploading, | |
1246 | * such that this operation is relatively seamless. | |
1247 | */ | |
1248 | static int sja1105_static_config_reload(struct sja1105_private *priv) | |
1249 | { | |
1250 | struct sja1105_mac_config_entry *mac; | |
1251 | int speed_mbps[SJA1105_NUM_PORTS]; | |
1252 | int rc, i; | |
1253 | ||
1254 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; | |
1255 | ||
8400cff6 VO |
1256 | /* Back up the dynamic link speed changed by sja1105_adjust_port_config |
1257 | * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the | |
1258 | * switch wants to see in the static config in order to allow us to | |
1259 | * change it through the dynamic interface later. | |
6666cebc VO |
1260 | */ |
1261 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
1262 | speed_mbps[i] = sja1105_speed[mac[i].speed]; | |
1263 | mac[i].speed = SJA1105_SPEED_AUTO; | |
1264 | } | |
1265 | ||
1266 | /* Reset switch and send updated static configuration */ | |
1267 | rc = sja1105_static_config_upload(priv); | |
1268 | if (rc < 0) | |
1269 | goto out; | |
1270 | ||
1271 | /* Configure the CGU (PLLs) for MII and RMII PHYs. | |
1272 | * For these interfaces there is no dynamic configuration | |
1273 | * needed, since PLLs have same settings at all speeds. | |
1274 | */ | |
1275 | rc = sja1105_clocking_setup(priv); | |
1276 | if (rc < 0) | |
1277 | goto out; | |
1278 | ||
1279 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
8400cff6 | 1280 | rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]); |
6666cebc VO |
1281 | if (rc < 0) |
1282 | goto out; | |
1283 | } | |
1284 | out: | |
1285 | return rc; | |
1286 | } | |
1287 | ||
6666cebc VO |
1288 | static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid) |
1289 | { | |
1290 | struct sja1105_mac_config_entry *mac; | |
1291 | ||
1292 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; | |
1293 | ||
1294 | mac[port].vlanid = pvid; | |
1295 | ||
1296 | return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, | |
1297 | &mac[port], true); | |
1298 | } | |
1299 | ||
1300 | static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid) | |
1301 | { | |
1302 | struct sja1105_vlan_lookup_entry *vlan; | |
1303 | int count, i; | |
1304 | ||
1305 | vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; | |
1306 | count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; | |
1307 | ||
1308 | for (i = 0; i < count; i++) | |
1309 | if (vlan[i].vlanid == vid) | |
1310 | return i; | |
1311 | ||
1312 | /* Return an invalid entry index if not found */ | |
1313 | return -1; | |
1314 | } | |
1315 | ||
1316 | static int sja1105_vlan_apply(struct sja1105_private *priv, int port, u16 vid, | |
1317 | bool enabled, bool untagged) | |
1318 | { | |
1319 | struct sja1105_vlan_lookup_entry *vlan; | |
1320 | struct sja1105_table *table; | |
1321 | bool keep = true; | |
1322 | int match, rc; | |
1323 | ||
1324 | table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; | |
1325 | ||
1326 | match = sja1105_is_vlan_configured(priv, vid); | |
1327 | if (match < 0) { | |
1328 | /* Can't delete a missing entry. */ | |
1329 | if (!enabled) | |
1330 | return 0; | |
1331 | rc = sja1105_table_resize(table, table->entry_count + 1); | |
1332 | if (rc) | |
1333 | return rc; | |
1334 | match = table->entry_count - 1; | |
1335 | } | |
1336 | /* Assign pointer after the resize (it's new memory) */ | |
1337 | vlan = table->entries; | |
1338 | vlan[match].vlanid = vid; | |
1339 | if (enabled) { | |
1340 | vlan[match].vlan_bc |= BIT(port); | |
1341 | vlan[match].vmemb_port |= BIT(port); | |
1342 | } else { | |
1343 | vlan[match].vlan_bc &= ~BIT(port); | |
1344 | vlan[match].vmemb_port &= ~BIT(port); | |
1345 | } | |
1346 | /* Also unset tag_port if removing this VLAN was requested, | |
1347 | * just so we don't have a confusing bitmap (no practical purpose). | |
1348 | */ | |
1349 | if (untagged || !enabled) | |
1350 | vlan[match].tag_port &= ~BIT(port); | |
1351 | else | |
1352 | vlan[match].tag_port |= BIT(port); | |
1353 | /* If there's no port left as member of this VLAN, | |
1354 | * it's time for it to go. | |
1355 | */ | |
1356 | if (!vlan[match].vmemb_port) | |
1357 | keep = false; | |
1358 | ||
1359 | dev_dbg(priv->ds->dev, | |
1360 | "%s: port %d, vid %llu, broadcast domain 0x%llx, " | |
1361 | "port members 0x%llx, tagged ports 0x%llx, keep %d\n", | |
1362 | __func__, port, vlan[match].vlanid, vlan[match].vlan_bc, | |
1363 | vlan[match].vmemb_port, vlan[match].tag_port, keep); | |
1364 | ||
1365 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid, | |
1366 | &vlan[match], keep); | |
1367 | if (rc < 0) | |
1368 | return rc; | |
1369 | ||
1370 | if (!keep) | |
1371 | return sja1105_table_delete_entry(table, match); | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
227d07a0 VO |
1376 | static int sja1105_setup_8021q_tagging(struct dsa_switch *ds, bool enabled) |
1377 | { | |
1378 | int rc, i; | |
1379 | ||
1380 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
1381 | rc = dsa_port_setup_8021q_tagging(ds, i, enabled); | |
1382 | if (rc < 0) { | |
1383 | dev_err(ds->dev, "Failed to setup VLAN tagging for port %d: %d\n", | |
1384 | i, rc); | |
1385 | return rc; | |
1386 | } | |
1387 | } | |
1388 | dev_info(ds->dev, "%s switch tagging\n", | |
1389 | enabled ? "Enabled" : "Disabled"); | |
1390 | return 0; | |
1391 | } | |
1392 | ||
8aa9ebcc VO |
1393 | static enum dsa_tag_protocol |
1394 | sja1105_get_tag_protocol(struct dsa_switch *ds, int port) | |
1395 | { | |
227d07a0 | 1396 | return DSA_TAG_PROTO_SJA1105; |
8aa9ebcc VO |
1397 | } |
1398 | ||
6666cebc VO |
1399 | /* This callback needs to be present */ |
1400 | static int sja1105_vlan_prepare(struct dsa_switch *ds, int port, | |
1401 | const struct switchdev_obj_port_vlan *vlan) | |
1402 | { | |
1403 | return 0; | |
1404 | } | |
1405 | ||
070ca3bb VO |
1406 | /* The TPID setting belongs to the General Parameters table, |
1407 | * which can only be partially reconfigured at runtime (and not the TPID). | |
1408 | * So a switch reset is required. | |
1409 | */ | |
6666cebc VO |
1410 | static int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled) |
1411 | { | |
070ca3bb | 1412 | struct sja1105_general_params_entry *general_params; |
6666cebc | 1413 | struct sja1105_private *priv = ds->priv; |
070ca3bb VO |
1414 | struct sja1105_table *table; |
1415 | u16 tpid, tpid2; | |
6666cebc VO |
1416 | int rc; |
1417 | ||
070ca3bb | 1418 | if (enabled) { |
6666cebc | 1419 | /* Enable VLAN filtering. */ |
f9a1a764 VO |
1420 | tpid = ETH_P_8021AD; |
1421 | tpid2 = ETH_P_8021Q; | |
070ca3bb | 1422 | } else { |
6666cebc | 1423 | /* Disable VLAN filtering. */ |
070ca3bb VO |
1424 | tpid = ETH_P_SJA1105; |
1425 | tpid2 = ETH_P_SJA1105; | |
1426 | } | |
1427 | ||
1428 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; | |
1429 | general_params = table->entries; | |
f9a1a764 | 1430 | /* EtherType used to identify outer tagged (S-tag) VLAN traffic */ |
070ca3bb | 1431 | general_params->tpid = tpid; |
f9a1a764 | 1432 | /* EtherType used to identify inner tagged (C-tag) VLAN traffic */ |
070ca3bb | 1433 | general_params->tpid2 = tpid2; |
42824463 VO |
1434 | /* When VLAN filtering is on, we need to at least be able to |
1435 | * decode management traffic through the "backup plan". | |
1436 | */ | |
1437 | general_params->incl_srcpt1 = enabled; | |
1438 | general_params->incl_srcpt0 = enabled; | |
070ca3bb VO |
1439 | |
1440 | rc = sja1105_static_config_reload(priv); | |
6666cebc VO |
1441 | if (rc) |
1442 | dev_err(ds->dev, "Failed to change VLAN Ethertype\n"); | |
1443 | ||
227d07a0 VO |
1444 | /* Switch port identification based on 802.1Q is only passable |
1445 | * if we are not under a vlan_filtering bridge. So make sure | |
1446 | * the two configurations are mutually exclusive. | |
1447 | */ | |
1448 | return sja1105_setup_8021q_tagging(ds, !enabled); | |
6666cebc VO |
1449 | } |
1450 | ||
1451 | static void sja1105_vlan_add(struct dsa_switch *ds, int port, | |
1452 | const struct switchdev_obj_port_vlan *vlan) | |
1453 | { | |
1454 | struct sja1105_private *priv = ds->priv; | |
1455 | u16 vid; | |
1456 | int rc; | |
1457 | ||
1458 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { | |
1459 | rc = sja1105_vlan_apply(priv, port, vid, true, vlan->flags & | |
1460 | BRIDGE_VLAN_INFO_UNTAGGED); | |
1461 | if (rc < 0) { | |
1462 | dev_err(ds->dev, "Failed to add VLAN %d to port %d: %d\n", | |
1463 | vid, port, rc); | |
1464 | return; | |
1465 | } | |
1466 | if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { | |
1467 | rc = sja1105_pvid_apply(ds->priv, port, vid); | |
1468 | if (rc < 0) { | |
1469 | dev_err(ds->dev, "Failed to set pvid %d on port %d: %d\n", | |
1470 | vid, port, rc); | |
1471 | return; | |
1472 | } | |
1473 | } | |
1474 | } | |
1475 | } | |
1476 | ||
1477 | static int sja1105_vlan_del(struct dsa_switch *ds, int port, | |
1478 | const struct switchdev_obj_port_vlan *vlan) | |
1479 | { | |
1480 | struct sja1105_private *priv = ds->priv; | |
1481 | u16 vid; | |
1482 | int rc; | |
1483 | ||
1484 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { | |
1485 | rc = sja1105_vlan_apply(priv, port, vid, false, vlan->flags & | |
1486 | BRIDGE_VLAN_INFO_UNTAGGED); | |
1487 | if (rc < 0) { | |
1488 | dev_err(ds->dev, "Failed to remove VLAN %d from port %d: %d\n", | |
1489 | vid, port, rc); | |
1490 | return rc; | |
1491 | } | |
1492 | } | |
1493 | return 0; | |
1494 | } | |
1495 | ||
8aa9ebcc VO |
1496 | /* The programming model for the SJA1105 switch is "all-at-once" via static |
1497 | * configuration tables. Some of these can be dynamically modified at runtime, | |
1498 | * but not the xMII mode parameters table. | |
1499 | * Furthermode, some PHYs may not have crystals for generating their clocks | |
1500 | * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's | |
1501 | * ref_clk pin. So port clocking needs to be initialized early, before | |
1502 | * connecting to PHYs is attempted, otherwise they won't respond through MDIO. | |
1503 | * Setting correct PHY link speed does not matter now. | |
1504 | * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY | |
1505 | * bindings are not yet parsed by DSA core. We need to parse early so that we | |
1506 | * can populate the xMII mode parameters table. | |
1507 | */ | |
1508 | static int sja1105_setup(struct dsa_switch *ds) | |
1509 | { | |
1510 | struct sja1105_dt_port ports[SJA1105_NUM_PORTS]; | |
1511 | struct sja1105_private *priv = ds->priv; | |
1512 | int rc; | |
1513 | ||
1514 | rc = sja1105_parse_dt(priv, ports); | |
1515 | if (rc < 0) { | |
1516 | dev_err(ds->dev, "Failed to parse DT: %d\n", rc); | |
1517 | return rc; | |
1518 | } | |
f5b8631c VO |
1519 | |
1520 | /* Error out early if internal delays are required through DT | |
1521 | * and we can't apply them. | |
1522 | */ | |
1523 | rc = sja1105_parse_rgmii_delays(priv, ports); | |
1524 | if (rc < 0) { | |
1525 | dev_err(ds->dev, "RGMII delay not supported\n"); | |
1526 | return rc; | |
1527 | } | |
1528 | ||
bb77f36a VO |
1529 | rc = sja1105_ptp_clock_register(priv); |
1530 | if (rc < 0) { | |
1531 | dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc); | |
1532 | return rc; | |
1533 | } | |
8aa9ebcc VO |
1534 | /* Create and send configuration down to device */ |
1535 | rc = sja1105_static_config_load(priv, ports); | |
1536 | if (rc < 0) { | |
1537 | dev_err(ds->dev, "Failed to load static config: %d\n", rc); | |
1538 | return rc; | |
1539 | } | |
1540 | /* Configure the CGU (PHY link modes and speeds) */ | |
1541 | rc = sja1105_clocking_setup(priv); | |
1542 | if (rc < 0) { | |
1543 | dev_err(ds->dev, "Failed to configure MII clocking: %d\n", rc); | |
1544 | return rc; | |
1545 | } | |
6666cebc VO |
1546 | /* On SJA1105, VLAN filtering per se is always enabled in hardware. |
1547 | * The only thing we can do to disable it is lie about what the 802.1Q | |
1548 | * EtherType is. | |
1549 | * So it will still try to apply VLAN filtering, but all ingress | |
1550 | * traffic (except frames received with EtherType of ETH_P_SJA1105) | |
1551 | * will be internally tagged with a distorted VLAN header where the | |
1552 | * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid. | |
1553 | */ | |
1554 | ds->vlan_filtering_is_global = true; | |
8aa9ebcc | 1555 | |
227d07a0 VO |
1556 | /* The DSA/switchdev model brings up switch ports in standalone mode by |
1557 | * default, and that means vlan_filtering is 0 since they're not under | |
1558 | * a bridge, so it's safe to set up switch tagging at this time. | |
1559 | */ | |
1560 | return sja1105_setup_8021q_tagging(ds, true); | |
1561 | } | |
1562 | ||
f3097be2 VO |
1563 | static void sja1105_teardown(struct dsa_switch *ds) |
1564 | { | |
1565 | struct sja1105_private *priv = ds->priv; | |
1566 | ||
1567 | cancel_work_sync(&priv->tagger_data.rxtstamp_work); | |
1568 | skb_queue_purge(&priv->tagger_data.skb_rxtstamp_queue); | |
1569 | } | |
1570 | ||
227d07a0 | 1571 | static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot, |
47ed985e | 1572 | struct sk_buff *skb, bool takets) |
227d07a0 VO |
1573 | { |
1574 | struct sja1105_mgmt_entry mgmt_route = {0}; | |
1575 | struct sja1105_private *priv = ds->priv; | |
1576 | struct ethhdr *hdr; | |
1577 | int timeout = 10; | |
1578 | int rc; | |
1579 | ||
1580 | hdr = eth_hdr(skb); | |
1581 | ||
1582 | mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest); | |
1583 | mgmt_route.destports = BIT(port); | |
1584 | mgmt_route.enfport = 1; | |
47ed985e VO |
1585 | mgmt_route.tsreg = 0; |
1586 | mgmt_route.takets = takets; | |
227d07a0 VO |
1587 | |
1588 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE, | |
1589 | slot, &mgmt_route, true); | |
1590 | if (rc < 0) { | |
1591 | kfree_skb(skb); | |
1592 | return rc; | |
1593 | } | |
1594 | ||
1595 | /* Transfer skb to the host port. */ | |
1596 | dsa_enqueue_skb(skb, ds->ports[port].slave); | |
1597 | ||
1598 | /* Wait until the switch has processed the frame */ | |
1599 | do { | |
1600 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE, | |
1601 | slot, &mgmt_route); | |
1602 | if (rc < 0) { | |
1603 | dev_err_ratelimited(priv->ds->dev, | |
1604 | "failed to poll for mgmt route\n"); | |
1605 | continue; | |
1606 | } | |
1607 | ||
1608 | /* UM10944: The ENFPORT flag of the respective entry is | |
1609 | * cleared when a match is found. The host can use this | |
1610 | * flag as an acknowledgment. | |
1611 | */ | |
1612 | cpu_relax(); | |
1613 | } while (mgmt_route.enfport && --timeout); | |
1614 | ||
1615 | if (!timeout) { | |
1616 | /* Clean up the management route so that a follow-up | |
1617 | * frame may not match on it by mistake. | |
2a7e7409 VO |
1618 | * This is only hardware supported on P/Q/R/S - on E/T it is |
1619 | * a no-op and we are silently discarding the -EOPNOTSUPP. | |
227d07a0 VO |
1620 | */ |
1621 | sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE, | |
1622 | slot, &mgmt_route, false); | |
1623 | dev_err_ratelimited(priv->ds->dev, "xmit timed out\n"); | |
1624 | } | |
1625 | ||
1626 | return NETDEV_TX_OK; | |
1627 | } | |
1628 | ||
1629 | /* Deferred work is unfortunately necessary because setting up the management | |
1630 | * route cannot be done from atomit context (SPI transfer takes a sleepable | |
1631 | * lock on the bus) | |
1632 | */ | |
1633 | static netdev_tx_t sja1105_port_deferred_xmit(struct dsa_switch *ds, int port, | |
1634 | struct sk_buff *skb) | |
1635 | { | |
1636 | struct sja1105_private *priv = ds->priv; | |
1637 | struct sja1105_port *sp = &priv->ports[port]; | |
47ed985e | 1638 | struct skb_shared_hwtstamps shwt = {0}; |
227d07a0 | 1639 | int slot = sp->mgmt_slot; |
47ed985e VO |
1640 | struct sk_buff *clone; |
1641 | u64 now, ts; | |
1642 | int rc; | |
227d07a0 VO |
1643 | |
1644 | /* The tragic fact about the switch having 4x2 slots for installing | |
1645 | * management routes is that all of them except one are actually | |
1646 | * useless. | |
1647 | * If 2 slots are simultaneously configured for two BPDUs sent to the | |
1648 | * same (multicast) DMAC but on different egress ports, the switch | |
1649 | * would confuse them and redirect first frame it receives on the CPU | |
1650 | * port towards the port configured on the numerically first slot | |
1651 | * (therefore wrong port), then second received frame on second slot | |
1652 | * (also wrong port). | |
1653 | * So for all practical purposes, there needs to be a lock that | |
1654 | * prevents that from happening. The slot used here is utterly useless | |
1655 | * (could have simply been 0 just as fine), but we are doing it | |
1656 | * nonetheless, in case a smarter idea ever comes up in the future. | |
1657 | */ | |
1658 | mutex_lock(&priv->mgmt_lock); | |
1659 | ||
47ed985e VO |
1660 | /* The clone, if there, was made by dsa_skb_tx_timestamp */ |
1661 | clone = DSA_SKB_CB(skb)->clone; | |
1662 | ||
1663 | sja1105_mgmt_xmit(ds, port, slot, skb, !!clone); | |
1664 | ||
1665 | if (!clone) | |
1666 | goto out; | |
1667 | ||
1668 | skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; | |
1669 | ||
1670 | mutex_lock(&priv->ptp_lock); | |
1671 | ||
1672 | now = priv->tstamp_cc.read(&priv->tstamp_cc); | |
1673 | ||
1674 | rc = sja1105_ptpegr_ts_poll(priv, slot, &ts); | |
1675 | if (rc < 0) { | |
1676 | dev_err(ds->dev, "xmit: timed out polling for tstamp\n"); | |
1677 | kfree_skb(clone); | |
1678 | goto out_unlock_ptp; | |
1679 | } | |
1680 | ||
1681 | ts = sja1105_tstamp_reconstruct(priv, now, ts); | |
1682 | ts = timecounter_cyc2time(&priv->tstamp_tc, ts); | |
227d07a0 | 1683 | |
47ed985e VO |
1684 | shwt.hwtstamp = ns_to_ktime(ts); |
1685 | skb_complete_tx_timestamp(clone, &shwt); | |
1686 | ||
1687 | out_unlock_ptp: | |
1688 | mutex_unlock(&priv->ptp_lock); | |
1689 | out: | |
227d07a0 VO |
1690 | mutex_unlock(&priv->mgmt_lock); |
1691 | return NETDEV_TX_OK; | |
8aa9ebcc VO |
1692 | } |
1693 | ||
8456721d VO |
1694 | /* The MAXAGE setting belongs to the L2 Forwarding Parameters table, |
1695 | * which cannot be reconfigured at runtime. So a switch reset is required. | |
1696 | */ | |
1697 | static int sja1105_set_ageing_time(struct dsa_switch *ds, | |
1698 | unsigned int ageing_time) | |
1699 | { | |
1700 | struct sja1105_l2_lookup_params_entry *l2_lookup_params; | |
1701 | struct sja1105_private *priv = ds->priv; | |
1702 | struct sja1105_table *table; | |
1703 | unsigned int maxage; | |
1704 | ||
1705 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; | |
1706 | l2_lookup_params = table->entries; | |
1707 | ||
1708 | maxage = SJA1105_AGEING_TIME_MS(ageing_time); | |
1709 | ||
1710 | if (l2_lookup_params->maxage == maxage) | |
1711 | return 0; | |
1712 | ||
1713 | l2_lookup_params->maxage = maxage; | |
1714 | ||
1715 | return sja1105_static_config_reload(priv); | |
1716 | } | |
1717 | ||
a602afd2 VO |
1718 | /* Caller must hold priv->tagger_data.meta_lock */ |
1719 | static int sja1105_change_rxtstamping(struct sja1105_private *priv, | |
1720 | bool on) | |
1721 | { | |
1722 | struct sja1105_general_params_entry *general_params; | |
1723 | struct sja1105_table *table; | |
1724 | int rc; | |
1725 | ||
1726 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; | |
1727 | general_params = table->entries; | |
1728 | general_params->send_meta1 = on; | |
1729 | general_params->send_meta0 = on; | |
1730 | ||
1731 | rc = sja1105_init_avb_params(priv, on); | |
1732 | if (rc < 0) | |
1733 | return rc; | |
1734 | ||
1735 | /* Initialize the meta state machine to a known state */ | |
1736 | if (priv->tagger_data.stampable_skb) { | |
1737 | kfree_skb(priv->tagger_data.stampable_skb); | |
1738 | priv->tagger_data.stampable_skb = NULL; | |
1739 | } | |
1740 | ||
1741 | return sja1105_static_config_reload(priv); | |
1742 | } | |
1743 | ||
1744 | static int sja1105_hwtstamp_set(struct dsa_switch *ds, int port, | |
1745 | struct ifreq *ifr) | |
1746 | { | |
1747 | struct sja1105_private *priv = ds->priv; | |
1748 | struct hwtstamp_config config; | |
1749 | bool rx_on; | |
1750 | int rc; | |
1751 | ||
1752 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
1753 | return -EFAULT; | |
1754 | ||
1755 | switch (config.tx_type) { | |
1756 | case HWTSTAMP_TX_OFF: | |
1757 | priv->ports[port].hwts_tx_en = false; | |
1758 | break; | |
1759 | case HWTSTAMP_TX_ON: | |
1760 | priv->ports[port].hwts_tx_en = true; | |
1761 | break; | |
1762 | default: | |
1763 | return -ERANGE; | |
1764 | } | |
1765 | ||
1766 | switch (config.rx_filter) { | |
1767 | case HWTSTAMP_FILTER_NONE: | |
1768 | rx_on = false; | |
1769 | break; | |
1770 | default: | |
1771 | rx_on = true; | |
1772 | break; | |
1773 | } | |
1774 | ||
1775 | if (rx_on != priv->tagger_data.hwts_rx_en) { | |
1776 | spin_lock(&priv->tagger_data.meta_lock); | |
1777 | rc = sja1105_change_rxtstamping(priv, rx_on); | |
1778 | spin_unlock(&priv->tagger_data.meta_lock); | |
1779 | if (rc < 0) { | |
1780 | dev_err(ds->dev, | |
1781 | "Failed to change RX timestamping: %d\n", rc); | |
1782 | return -EFAULT; | |
1783 | } | |
1784 | priv->tagger_data.hwts_rx_en = rx_on; | |
1785 | } | |
1786 | ||
1787 | if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) | |
1788 | return -EFAULT; | |
1789 | return 0; | |
1790 | } | |
1791 | ||
1792 | static int sja1105_hwtstamp_get(struct dsa_switch *ds, int port, | |
1793 | struct ifreq *ifr) | |
1794 | { | |
1795 | struct sja1105_private *priv = ds->priv; | |
1796 | struct hwtstamp_config config; | |
1797 | ||
1798 | config.flags = 0; | |
1799 | if (priv->ports[port].hwts_tx_en) | |
1800 | config.tx_type = HWTSTAMP_TX_ON; | |
1801 | else | |
1802 | config.tx_type = HWTSTAMP_TX_OFF; | |
1803 | if (priv->tagger_data.hwts_rx_en) | |
1804 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
1805 | else | |
1806 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
1807 | ||
1808 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
1809 | -EFAULT : 0; | |
1810 | } | |
1811 | ||
f3097be2 VO |
1812 | #define to_tagger(d) \ |
1813 | container_of((d), struct sja1105_tagger_data, rxtstamp_work) | |
1814 | #define to_sja1105(d) \ | |
1815 | container_of((d), struct sja1105_private, tagger_data) | |
1816 | ||
1817 | static void sja1105_rxtstamp_work(struct work_struct *work) | |
1818 | { | |
1819 | struct sja1105_tagger_data *data = to_tagger(work); | |
1820 | struct sja1105_private *priv = to_sja1105(data); | |
1821 | struct sk_buff *skb; | |
1822 | u64 now; | |
1823 | ||
1824 | mutex_lock(&priv->ptp_lock); | |
1825 | ||
1826 | now = priv->tstamp_cc.read(&priv->tstamp_cc); | |
1827 | ||
1828 | while ((skb = skb_dequeue(&data->skb_rxtstamp_queue)) != NULL) { | |
1829 | struct skb_shared_hwtstamps *shwt = skb_hwtstamps(skb); | |
1830 | u64 ts; | |
1831 | ||
1832 | *shwt = (struct skb_shared_hwtstamps) {0}; | |
1833 | ||
1834 | ts = SJA1105_SKB_CB(skb)->meta_tstamp; | |
1835 | ts = sja1105_tstamp_reconstruct(priv, now, ts); | |
1836 | ts = timecounter_cyc2time(&priv->tstamp_tc, ts); | |
1837 | ||
1838 | shwt->hwtstamp = ns_to_ktime(ts); | |
1839 | netif_rx_ni(skb); | |
1840 | } | |
1841 | ||
1842 | mutex_unlock(&priv->ptp_lock); | |
1843 | } | |
1844 | ||
1845 | /* Called from dsa_skb_defer_rx_timestamp */ | |
1dbb9869 Y |
1846 | static bool sja1105_port_rxtstamp(struct dsa_switch *ds, int port, |
1847 | struct sk_buff *skb, unsigned int type) | |
f3097be2 VO |
1848 | { |
1849 | struct sja1105_private *priv = ds->priv; | |
1850 | struct sja1105_tagger_data *data = &priv->tagger_data; | |
1851 | ||
1852 | if (!data->hwts_rx_en) | |
1853 | return false; | |
1854 | ||
1855 | /* We need to read the full PTP clock to reconstruct the Rx | |
1856 | * timestamp. For that we need a sleepable context. | |
1857 | */ | |
1858 | skb_queue_tail(&data->skb_rxtstamp_queue, skb); | |
1859 | schedule_work(&data->rxtstamp_work); | |
1860 | return true; | |
1861 | } | |
1862 | ||
47ed985e VO |
1863 | /* Called from dsa_skb_tx_timestamp. This callback is just to make DSA clone |
1864 | * the skb and have it available in DSA_SKB_CB in the .port_deferred_xmit | |
1865 | * callback, where we will timestamp it synchronously. | |
1866 | */ | |
1dbb9869 Y |
1867 | static bool sja1105_port_txtstamp(struct dsa_switch *ds, int port, |
1868 | struct sk_buff *skb, unsigned int type) | |
47ed985e VO |
1869 | { |
1870 | struct sja1105_private *priv = ds->priv; | |
1871 | struct sja1105_port *sp = &priv->ports[port]; | |
1872 | ||
1873 | if (!sp->hwts_tx_en) | |
1874 | return false; | |
1875 | ||
1876 | return true; | |
1877 | } | |
1878 | ||
8aa9ebcc VO |
1879 | static const struct dsa_switch_ops sja1105_switch_ops = { |
1880 | .get_tag_protocol = sja1105_get_tag_protocol, | |
1881 | .setup = sja1105_setup, | |
f3097be2 | 1882 | .teardown = sja1105_teardown, |
8456721d | 1883 | .set_ageing_time = sja1105_set_ageing_time, |
ad9f299a | 1884 | .phylink_validate = sja1105_phylink_validate, |
af7cd036 | 1885 | .phylink_mac_config = sja1105_mac_config, |
8400cff6 VO |
1886 | .phylink_mac_link_up = sja1105_mac_link_up, |
1887 | .phylink_mac_link_down = sja1105_mac_link_down, | |
52c34e6e VO |
1888 | .get_strings = sja1105_get_strings, |
1889 | .get_ethtool_stats = sja1105_get_ethtool_stats, | |
1890 | .get_sset_count = sja1105_get_sset_count, | |
bb77f36a | 1891 | .get_ts_info = sja1105_get_ts_info, |
291d1e72 VO |
1892 | .port_fdb_dump = sja1105_fdb_dump, |
1893 | .port_fdb_add = sja1105_fdb_add, | |
1894 | .port_fdb_del = sja1105_fdb_del, | |
8aa9ebcc VO |
1895 | .port_bridge_join = sja1105_bridge_join, |
1896 | .port_bridge_leave = sja1105_bridge_leave, | |
640f763f | 1897 | .port_stp_state_set = sja1105_bridge_stp_state_set, |
6666cebc VO |
1898 | .port_vlan_prepare = sja1105_vlan_prepare, |
1899 | .port_vlan_filtering = sja1105_vlan_filtering, | |
1900 | .port_vlan_add = sja1105_vlan_add, | |
1901 | .port_vlan_del = sja1105_vlan_del, | |
291d1e72 VO |
1902 | .port_mdb_prepare = sja1105_mdb_prepare, |
1903 | .port_mdb_add = sja1105_mdb_add, | |
1904 | .port_mdb_del = sja1105_mdb_del, | |
227d07a0 | 1905 | .port_deferred_xmit = sja1105_port_deferred_xmit, |
a602afd2 VO |
1906 | .port_hwtstamp_get = sja1105_hwtstamp_get, |
1907 | .port_hwtstamp_set = sja1105_hwtstamp_set, | |
f3097be2 | 1908 | .port_rxtstamp = sja1105_port_rxtstamp, |
47ed985e | 1909 | .port_txtstamp = sja1105_port_txtstamp, |
8aa9ebcc VO |
1910 | }; |
1911 | ||
1912 | static int sja1105_check_device_id(struct sja1105_private *priv) | |
1913 | { | |
1914 | const struct sja1105_regs *regs = priv->info->regs; | |
1915 | u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0}; | |
1916 | struct device *dev = &priv->spidev->dev; | |
1917 | u64 device_id; | |
1918 | u64 part_no; | |
1919 | int rc; | |
1920 | ||
1921 | rc = sja1105_spi_send_int(priv, SPI_READ, regs->device_id, | |
1922 | &device_id, SJA1105_SIZE_DEVICE_ID); | |
1923 | if (rc < 0) | |
1924 | return rc; | |
1925 | ||
1926 | if (device_id != priv->info->device_id) { | |
1927 | dev_err(dev, "Expected device ID 0x%llx but read 0x%llx\n", | |
1928 | priv->info->device_id, device_id); | |
1929 | return -ENODEV; | |
1930 | } | |
1931 | ||
1932 | rc = sja1105_spi_send_packed_buf(priv, SPI_READ, regs->prod_id, | |
1933 | prod_id, SJA1105_SIZE_DEVICE_ID); | |
1934 | if (rc < 0) | |
1935 | return rc; | |
1936 | ||
1937 | sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID); | |
1938 | ||
1939 | if (part_no != priv->info->part_no) { | |
1940 | dev_err(dev, "Expected part number 0x%llx but read 0x%llx\n", | |
1941 | priv->info->part_no, part_no); | |
1942 | return -ENODEV; | |
1943 | } | |
1944 | ||
1945 | return 0; | |
1946 | } | |
1947 | ||
1948 | static int sja1105_probe(struct spi_device *spi) | |
1949 | { | |
844d7edc | 1950 | struct sja1105_tagger_data *tagger_data; |
8aa9ebcc VO |
1951 | struct device *dev = &spi->dev; |
1952 | struct sja1105_private *priv; | |
1953 | struct dsa_switch *ds; | |
227d07a0 | 1954 | int rc, i; |
8aa9ebcc VO |
1955 | |
1956 | if (!dev->of_node) { | |
1957 | dev_err(dev, "No DTS bindings for SJA1105 driver\n"); | |
1958 | return -EINVAL; | |
1959 | } | |
1960 | ||
1961 | priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL); | |
1962 | if (!priv) | |
1963 | return -ENOMEM; | |
1964 | ||
1965 | /* Configure the optional reset pin and bring up switch */ | |
1966 | priv->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); | |
1967 | if (IS_ERR(priv->reset_gpio)) | |
1968 | dev_dbg(dev, "reset-gpios not defined, ignoring\n"); | |
1969 | else | |
1970 | sja1105_hw_reset(priv->reset_gpio, 1, 1); | |
1971 | ||
1972 | /* Populate our driver private structure (priv) based on | |
1973 | * the device tree node that was probed (spi) | |
1974 | */ | |
1975 | priv->spidev = spi; | |
1976 | spi_set_drvdata(spi, priv); | |
1977 | ||
1978 | /* Configure the SPI bus */ | |
1979 | spi->bits_per_word = 8; | |
1980 | rc = spi_setup(spi); | |
1981 | if (rc < 0) { | |
1982 | dev_err(dev, "Could not init SPI\n"); | |
1983 | return rc; | |
1984 | } | |
1985 | ||
1986 | priv->info = of_device_get_match_data(dev); | |
1987 | ||
1988 | /* Detect hardware device */ | |
1989 | rc = sja1105_check_device_id(priv); | |
1990 | if (rc < 0) { | |
1991 | dev_err(dev, "Device ID check failed: %d\n", rc); | |
1992 | return rc; | |
1993 | } | |
1994 | ||
1995 | dev_info(dev, "Probed switch chip: %s\n", priv->info->name); | |
1996 | ||
1997 | ds = dsa_switch_alloc(dev, SJA1105_NUM_PORTS); | |
1998 | if (!ds) | |
1999 | return -ENOMEM; | |
2000 | ||
2001 | ds->ops = &sja1105_switch_ops; | |
2002 | ds->priv = priv; | |
2003 | priv->ds = ds; | |
2004 | ||
844d7edc VO |
2005 | tagger_data = &priv->tagger_data; |
2006 | skb_queue_head_init(&tagger_data->skb_rxtstamp_queue); | |
f3097be2 | 2007 | INIT_WORK(&tagger_data->rxtstamp_work, sja1105_rxtstamp_work); |
844d7edc | 2008 | |
227d07a0 VO |
2009 | /* Connections between dsa_port and sja1105_port */ |
2010 | for (i = 0; i < SJA1105_NUM_PORTS; i++) { | |
2011 | struct sja1105_port *sp = &priv->ports[i]; | |
2012 | ||
2013 | ds->ports[i].priv = sp; | |
2014 | sp->dp = &ds->ports[i]; | |
844d7edc | 2015 | sp->data = tagger_data; |
227d07a0 VO |
2016 | } |
2017 | mutex_init(&priv->mgmt_lock); | |
2018 | ||
8aa9ebcc VO |
2019 | return dsa_register_switch(priv->ds); |
2020 | } | |
2021 | ||
2022 | static int sja1105_remove(struct spi_device *spi) | |
2023 | { | |
2024 | struct sja1105_private *priv = spi_get_drvdata(spi); | |
2025 | ||
bb77f36a | 2026 | sja1105_ptp_clock_unregister(priv); |
8aa9ebcc VO |
2027 | dsa_unregister_switch(priv->ds); |
2028 | sja1105_static_config_free(&priv->static_config); | |
2029 | return 0; | |
2030 | } | |
2031 | ||
2032 | static const struct of_device_id sja1105_dt_ids[] = { | |
2033 | { .compatible = "nxp,sja1105e", .data = &sja1105e_info }, | |
2034 | { .compatible = "nxp,sja1105t", .data = &sja1105t_info }, | |
2035 | { .compatible = "nxp,sja1105p", .data = &sja1105p_info }, | |
2036 | { .compatible = "nxp,sja1105q", .data = &sja1105q_info }, | |
2037 | { .compatible = "nxp,sja1105r", .data = &sja1105r_info }, | |
2038 | { .compatible = "nxp,sja1105s", .data = &sja1105s_info }, | |
2039 | { /* sentinel */ }, | |
2040 | }; | |
2041 | MODULE_DEVICE_TABLE(of, sja1105_dt_ids); | |
2042 | ||
2043 | static struct spi_driver sja1105_driver = { | |
2044 | .driver = { | |
2045 | .name = "sja1105", | |
2046 | .owner = THIS_MODULE, | |
2047 | .of_match_table = of_match_ptr(sja1105_dt_ids), | |
2048 | }, | |
2049 | .probe = sja1105_probe, | |
2050 | .remove = sja1105_remove, | |
2051 | }; | |
2052 | ||
2053 | module_spi_driver(sja1105_driver); | |
2054 | ||
2055 | MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>"); | |
2056 | MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>"); | |
2057 | MODULE_DESCRIPTION("SJA1105 Driver"); | |
2058 | MODULE_LICENSE("GPL v2"); |