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Commit | Line | Data |
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682011ff | 1 | /************************************************************************** |
ac3315c2 | 2 | Intel Pro 1000 for ppcboot/das-u-boot |
682011ff WD |
3 | Drivers are port from Intel's Linux driver e1000-4.3.15 |
4 | and from Etherboot pro 1000 driver by mrakes at vivato dot net | |
5 | tested on both gig copper and gig fiber boards | |
6 | ***************************************************************************/ | |
7 | /******************************************************************************* | |
8 | ||
8bde7f77 | 9 | |
682011ff | 10 | Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. |
8bde7f77 | 11 | |
1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
8bde7f77 | 13 | |
682011ff WD |
14 | Contact Information: |
15 | Linux NICS <linux.nics@intel.com> | |
16 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
17 | ||
18 | *******************************************************************************/ | |
19 | /* | |
20 | * Copyright (C) Archway Digital Solutions. | |
21 | * | |
22 | * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> | |
23 | * 2/9/2002 | |
24 | * | |
25 | * Copyright (C) Linux Networx. | |
26 | * Massive upgrade to work with the new intel gigabit NICs. | |
27 | * <ebiederman at lnxi dot com> | |
2c2668f9 RZ |
28 | * |
29 | * Copyright 2011 Freescale Semiconductor, Inc. | |
682011ff WD |
30 | */ |
31 | ||
c752cd2a | 32 | #include <common.h> |
c6d80a15 | 33 | #include <dm.h> |
5c5e707a | 34 | #include <errno.h> |
cf92e05c | 35 | #include <memalign.h> |
5c5e707a | 36 | #include <pci.h> |
682011ff WD |
37 | #include "e1000.h" |
38 | ||
682011ff WD |
39 | #define TOUT_LOOP 100000 |
40 | ||
81dab9af BM |
41 | #ifdef CONFIG_DM_ETH |
42 | #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v)) | |
43 | #define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a) | |
44 | #else | |
f81ecb5d | 45 | #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) |
682011ff | 46 | #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) |
81dab9af | 47 | #endif |
682011ff | 48 | |
9ea005fb RZ |
49 | #define E1000_DEFAULT_PCI_PBA 0x00000030 |
50 | #define E1000_DEFAULT_PCIE_PBA 0x000a0026 | |
682011ff WD |
51 | |
52 | /* NIC specific static variables go here */ | |
53 | ||
873e8e01 MV |
54 | /* Intel i210 needs the DMA descriptor rings aligned to 128b */ |
55 | #define E1000_BUFFER_ALIGN 128 | |
682011ff | 56 | |
c6d80a15 SG |
57 | /* |
58 | * TODO(sjg@chromium.org): Even with driver model we share these buffers. | |
59 | * Concurrent receiving on multiple active Ethernet devices will not work. | |
60 | * Normally U-Boot does not support this anyway. To fix it in this driver, | |
61 | * move these buffers and the tx/rx pointers to struct e1000_hw. | |
62 | */ | |
873e8e01 MV |
63 | DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); |
64 | DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); | |
65 | DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); | |
682011ff WD |
66 | |
67 | static int tx_tail; | |
68 | static int rx_tail, rx_last; | |
c6d80a15 SG |
69 | #ifdef CONFIG_DM_ETH |
70 | static int num_cards; /* Number of E1000 devices seen so far */ | |
71 | #endif | |
682011ff | 72 | |
d60626f8 | 73 | static struct pci_device_id e1000_supported[] = { |
5c5e707a SG |
74 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, |
75 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, | |
76 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, | |
77 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, | |
78 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, | |
79 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, | |
80 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, | |
81 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, | |
82 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, | |
83 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, | |
84 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, | |
85 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, | |
86 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, | |
87 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, | |
88 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, | |
89 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, | |
90 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, | |
aa070789 | 91 | /* E1000 PCIe card */ |
5c5e707a SG |
92 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, |
93 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, | |
94 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, | |
95 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, | |
96 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, | |
97 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, | |
98 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, | |
99 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, | |
100 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, | |
101 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, | |
102 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, | |
103 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, | |
104 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, | |
105 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, | |
106 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, | |
118 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, | |
119 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, | |
120 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, | |
95186063 | 122 | |
1bc43437 | 123 | {} |
682011ff WD |
124 | }; |
125 | ||
126 | /* Function forward declarations */ | |
5c5e707a SG |
127 | static int e1000_setup_link(struct e1000_hw *hw); |
128 | static int e1000_setup_fiber_link(struct e1000_hw *hw); | |
129 | static int e1000_setup_copper_link(struct e1000_hw *hw); | |
682011ff WD |
130 | static int e1000_phy_setup_autoneg(struct e1000_hw *hw); |
131 | static void e1000_config_collision_dist(struct e1000_hw *hw); | |
132 | static int e1000_config_mac_to_phy(struct e1000_hw *hw); | |
133 | static int e1000_config_fc_after_link_up(struct e1000_hw *hw); | |
5c5e707a | 134 | static int e1000_check_for_link(struct e1000_hw *hw); |
682011ff | 135 | static int e1000_wait_autoneg(struct e1000_hw *hw); |
aa070789 | 136 | static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, |
682011ff WD |
137 | uint16_t * duplex); |
138 | static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, | |
139 | uint16_t * phy_data); | |
140 | static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, | |
141 | uint16_t phy_data); | |
aa070789 | 142 | static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); |
682011ff WD |
143 | static int e1000_phy_reset(struct e1000_hw *hw); |
144 | static int e1000_detect_gig_phy(struct e1000_hw *hw); | |
aa070789 RZ |
145 | static void e1000_set_media_type(struct e1000_hw *hw); |
146 | ||
147 | static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); | |
7e2d991d | 148 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); |
aa070789 | 149 | static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); |
682011ff | 150 | |
8712adfd RI |
151 | #ifndef CONFIG_E1000_NO_NVM |
152 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); | |
ecbd2078 RZ |
153 | static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, |
154 | uint16_t words, | |
155 | uint16_t *data); | |
682011ff WD |
156 | /****************************************************************************** |
157 | * Raises the EEPROM's clock input. | |
158 | * | |
159 | * hw - Struct containing variables accessed by shared code | |
160 | * eecd - EECD's current value | |
161 | *****************************************************************************/ | |
2326a94d | 162 | void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) |
682011ff WD |
163 | { |
164 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then | |
165 | * wait 50 microseconds. | |
166 | */ | |
167 | *eecd = *eecd | E1000_EECD_SK; | |
168 | E1000_WRITE_REG(hw, EECD, *eecd); | |
169 | E1000_WRITE_FLUSH(hw); | |
170 | udelay(50); | |
171 | } | |
172 | ||
173 | /****************************************************************************** | |
174 | * Lowers the EEPROM's clock input. | |
175 | * | |
8bde7f77 | 176 | * hw - Struct containing variables accessed by shared code |
682011ff WD |
177 | * eecd - EECD's current value |
178 | *****************************************************************************/ | |
2326a94d | 179 | void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) |
682011ff | 180 | { |
8bde7f77 WD |
181 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
182 | * wait 50 microseconds. | |
682011ff WD |
183 | */ |
184 | *eecd = *eecd & ~E1000_EECD_SK; | |
185 | E1000_WRITE_REG(hw, EECD, *eecd); | |
186 | E1000_WRITE_FLUSH(hw); | |
187 | udelay(50); | |
188 | } | |
189 | ||
190 | /****************************************************************************** | |
191 | * Shift data bits out to the EEPROM. | |
192 | * | |
193 | * hw - Struct containing variables accessed by shared code | |
194 | * data - data to send to the EEPROM | |
195 | * count - number of bits to shift out | |
196 | *****************************************************************************/ | |
197 | static void | |
198 | e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) | |
199 | { | |
200 | uint32_t eecd; | |
201 | uint32_t mask; | |
202 | ||
203 | /* We need to shift "count" bits out to the EEPROM. So, value in the | |
204 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
8bde7f77 | 205 | * In order to do this, "data" must be broken down into bits. |
682011ff WD |
206 | */ |
207 | mask = 0x01 << (count - 1); | |
208 | eecd = E1000_READ_REG(hw, EECD); | |
209 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
210 | do { | |
211 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", | |
212 | * and then raising and then lowering the clock (the SK bit controls | |
213 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM | |
214 | * by setting "DI" to "0" and then raising and then lowering the clock. | |
215 | */ | |
216 | eecd &= ~E1000_EECD_DI; | |
217 | ||
218 | if (data & mask) | |
219 | eecd |= E1000_EECD_DI; | |
220 | ||
221 | E1000_WRITE_REG(hw, EECD, eecd); | |
222 | E1000_WRITE_FLUSH(hw); | |
223 | ||
224 | udelay(50); | |
225 | ||
226 | e1000_raise_ee_clk(hw, &eecd); | |
227 | e1000_lower_ee_clk(hw, &eecd); | |
228 | ||
229 | mask = mask >> 1; | |
230 | ||
231 | } while (mask); | |
232 | ||
233 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
234 | eecd &= ~E1000_EECD_DI; | |
235 | E1000_WRITE_REG(hw, EECD, eecd); | |
236 | } | |
237 | ||
238 | /****************************************************************************** | |
239 | * Shift data bits in from the EEPROM | |
240 | * | |
241 | * hw - Struct containing variables accessed by shared code | |
242 | *****************************************************************************/ | |
243 | static uint16_t | |
aa070789 | 244 | e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) |
682011ff WD |
245 | { |
246 | uint32_t eecd; | |
247 | uint32_t i; | |
248 | uint16_t data; | |
249 | ||
aa070789 RZ |
250 | /* In order to read a register from the EEPROM, we need to shift 'count' |
251 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock | |
252 | * input to the EEPROM (setting the SK bit), and then reading the | |
253 | * value of the "DO" bit. During this "shifting in" process the | |
254 | * "DI" bit should always be clear. | |
682011ff WD |
255 | */ |
256 | ||
257 | eecd = E1000_READ_REG(hw, EECD); | |
258 | ||
259 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
260 | data = 0; | |
261 | ||
aa070789 | 262 | for (i = 0; i < count; i++) { |
682011ff WD |
263 | data = data << 1; |
264 | e1000_raise_ee_clk(hw, &eecd); | |
265 | ||
266 | eecd = E1000_READ_REG(hw, EECD); | |
267 | ||
268 | eecd &= ~(E1000_EECD_DI); | |
269 | if (eecd & E1000_EECD_DO) | |
270 | data |= 1; | |
271 | ||
272 | e1000_lower_ee_clk(hw, &eecd); | |
273 | } | |
274 | ||
275 | return data; | |
276 | } | |
277 | ||
278 | /****************************************************************************** | |
aa070789 | 279 | * Returns EEPROM to a "standby" state |
682011ff WD |
280 | * |
281 | * hw - Struct containing variables accessed by shared code | |
682011ff | 282 | *****************************************************************************/ |
2326a94d | 283 | void e1000_standby_eeprom(struct e1000_hw *hw) |
682011ff | 284 | { |
aa070789 | 285 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
682011ff WD |
286 | uint32_t eecd; |
287 | ||
288 | eecd = E1000_READ_REG(hw, EECD); | |
289 | ||
aa070789 RZ |
290 | if (eeprom->type == e1000_eeprom_microwire) { |
291 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
292 | E1000_WRITE_REG(hw, EECD, eecd); | |
293 | E1000_WRITE_FLUSH(hw); | |
294 | udelay(eeprom->delay_usec); | |
682011ff | 295 | |
aa070789 RZ |
296 | /* Clock high */ |
297 | eecd |= E1000_EECD_SK; | |
298 | E1000_WRITE_REG(hw, EECD, eecd); | |
299 | E1000_WRITE_FLUSH(hw); | |
300 | udelay(eeprom->delay_usec); | |
301 | ||
302 | /* Select EEPROM */ | |
303 | eecd |= E1000_EECD_CS; | |
304 | E1000_WRITE_REG(hw, EECD, eecd); | |
305 | E1000_WRITE_FLUSH(hw); | |
306 | udelay(eeprom->delay_usec); | |
307 | ||
308 | /* Clock low */ | |
309 | eecd &= ~E1000_EECD_SK; | |
310 | E1000_WRITE_REG(hw, EECD, eecd); | |
311 | E1000_WRITE_FLUSH(hw); | |
312 | udelay(eeprom->delay_usec); | |
313 | } else if (eeprom->type == e1000_eeprom_spi) { | |
314 | /* Toggle CS to flush commands */ | |
315 | eecd |= E1000_EECD_CS; | |
316 | E1000_WRITE_REG(hw, EECD, eecd); | |
317 | E1000_WRITE_FLUSH(hw); | |
318 | udelay(eeprom->delay_usec); | |
319 | eecd &= ~E1000_EECD_CS; | |
320 | E1000_WRITE_REG(hw, EECD, eecd); | |
321 | E1000_WRITE_FLUSH(hw); | |
322 | udelay(eeprom->delay_usec); | |
323 | } | |
324 | } | |
325 | ||
326 | /*************************************************************************** | |
327 | * Description: Determines if the onboard NVM is FLASH or EEPROM. | |
328 | * | |
329 | * hw - Struct containing variables accessed by shared code | |
330 | ****************************************************************************/ | |
472d5460 | 331 | static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
aa070789 RZ |
332 | { |
333 | uint32_t eecd = 0; | |
334 | ||
335 | DEBUGFUNC(); | |
336 | ||
337 | if (hw->mac_type == e1000_ich8lan) | |
472d5460 | 338 | return false; |
aa070789 | 339 | |
2c2668f9 | 340 | if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { |
aa070789 RZ |
341 | eecd = E1000_READ_REG(hw, EECD); |
342 | ||
343 | /* Isolate bits 15 & 16 */ | |
344 | eecd = ((eecd >> 15) & 0x03); | |
345 | ||
346 | /* If both bits are set, device is Flash type */ | |
347 | if (eecd == 0x03) | |
472d5460 | 348 | return false; |
aa070789 | 349 | } |
472d5460 | 350 | return true; |
682011ff WD |
351 | } |
352 | ||
353 | /****************************************************************************** | |
aa070789 | 354 | * Prepares EEPROM for access |
8bde7f77 | 355 | * |
682011ff | 356 | * hw - Struct containing variables accessed by shared code |
aa070789 RZ |
357 | * |
358 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This | |
359 | * function should be called before issuing a command to the EEPROM. | |
682011ff | 360 | *****************************************************************************/ |
2326a94d | 361 | int32_t e1000_acquire_eeprom(struct e1000_hw *hw) |
682011ff | 362 | { |
aa070789 RZ |
363 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
364 | uint32_t eecd, i = 0; | |
682011ff | 365 | |
f81ecb5d | 366 | DEBUGFUNC(); |
aa070789 RZ |
367 | |
368 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) | |
369 | return -E1000_ERR_SWFW_SYNC; | |
682011ff WD |
370 | eecd = E1000_READ_REG(hw, EECD); |
371 | ||
95186063 | 372 | if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { |
aa070789 RZ |
373 | /* Request EEPROM Access */ |
374 | if (hw->mac_type > e1000_82544) { | |
375 | eecd |= E1000_EECD_REQ; | |
376 | E1000_WRITE_REG(hw, EECD, eecd); | |
377 | eecd = E1000_READ_REG(hw, EECD); | |
378 | while ((!(eecd & E1000_EECD_GNT)) && | |
379 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { | |
380 | i++; | |
381 | udelay(5); | |
382 | eecd = E1000_READ_REG(hw, EECD); | |
383 | } | |
384 | if (!(eecd & E1000_EECD_GNT)) { | |
385 | eecd &= ~E1000_EECD_REQ; | |
386 | E1000_WRITE_REG(hw, EECD, eecd); | |
387 | DEBUGOUT("Could not acquire EEPROM grant\n"); | |
388 | return -E1000_ERR_EEPROM; | |
389 | } | |
390 | } | |
391 | } | |
682011ff | 392 | |
aa070789 | 393 | /* Setup EEPROM for Read/Write */ |
682011ff | 394 | |
aa070789 RZ |
395 | if (eeprom->type == e1000_eeprom_microwire) { |
396 | /* Clear SK and DI */ | |
397 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | |
398 | E1000_WRITE_REG(hw, EECD, eecd); | |
682011ff | 399 | |
aa070789 RZ |
400 | /* Set CS */ |
401 | eecd |= E1000_EECD_CS; | |
402 | E1000_WRITE_REG(hw, EECD, eecd); | |
403 | } else if (eeprom->type == e1000_eeprom_spi) { | |
404 | /* Clear SK and CS */ | |
405 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
406 | E1000_WRITE_REG(hw, EECD, eecd); | |
407 | udelay(1); | |
408 | } | |
409 | ||
410 | return E1000_SUCCESS; | |
682011ff WD |
411 | } |
412 | ||
413 | /****************************************************************************** | |
aa070789 RZ |
414 | * Sets up eeprom variables in the hw struct. Must be called after mac_type |
415 | * is configured. Additionally, if this is ICH8, the flash controller GbE | |
416 | * registers must be mapped, or this will crash. | |
682011ff WD |
417 | * |
418 | * hw - Struct containing variables accessed by shared code | |
682011ff | 419 | *****************************************************************************/ |
aa070789 | 420 | static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) |
682011ff | 421 | { |
aa070789 | 422 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
95186063 | 423 | uint32_t eecd; |
aa070789 RZ |
424 | int32_t ret_val = E1000_SUCCESS; |
425 | uint16_t eeprom_size; | |
682011ff | 426 | |
95186063 MV |
427 | if (hw->mac_type == e1000_igb) |
428 | eecd = E1000_READ_REG(hw, I210_EECD); | |
429 | else | |
430 | eecd = E1000_READ_REG(hw, EECD); | |
431 | ||
f81ecb5d | 432 | DEBUGFUNC(); |
aa070789 RZ |
433 | |
434 | switch (hw->mac_type) { | |
435 | case e1000_82542_rev2_0: | |
436 | case e1000_82542_rev2_1: | |
437 | case e1000_82543: | |
438 | case e1000_82544: | |
439 | eeprom->type = e1000_eeprom_microwire; | |
440 | eeprom->word_size = 64; | |
441 | eeprom->opcode_bits = 3; | |
442 | eeprom->address_bits = 6; | |
443 | eeprom->delay_usec = 50; | |
472d5460 YS |
444 | eeprom->use_eerd = false; |
445 | eeprom->use_eewr = false; | |
aa070789 RZ |
446 | break; |
447 | case e1000_82540: | |
448 | case e1000_82545: | |
449 | case e1000_82545_rev_3: | |
450 | case e1000_82546: | |
451 | case e1000_82546_rev_3: | |
452 | eeprom->type = e1000_eeprom_microwire; | |
453 | eeprom->opcode_bits = 3; | |
454 | eeprom->delay_usec = 50; | |
455 | if (eecd & E1000_EECD_SIZE) { | |
456 | eeprom->word_size = 256; | |
457 | eeprom->address_bits = 8; | |
458 | } else { | |
459 | eeprom->word_size = 64; | |
460 | eeprom->address_bits = 6; | |
461 | } | |
472d5460 YS |
462 | eeprom->use_eerd = false; |
463 | eeprom->use_eewr = false; | |
aa070789 RZ |
464 | break; |
465 | case e1000_82541: | |
466 | case e1000_82541_rev_2: | |
467 | case e1000_82547: | |
468 | case e1000_82547_rev_2: | |
469 | if (eecd & E1000_EECD_TYPE) { | |
470 | eeprom->type = e1000_eeprom_spi; | |
471 | eeprom->opcode_bits = 8; | |
472 | eeprom->delay_usec = 1; | |
473 | if (eecd & E1000_EECD_ADDR_BITS) { | |
474 | eeprom->page_size = 32; | |
475 | eeprom->address_bits = 16; | |
476 | } else { | |
477 | eeprom->page_size = 8; | |
478 | eeprom->address_bits = 8; | |
479 | } | |
480 | } else { | |
481 | eeprom->type = e1000_eeprom_microwire; | |
482 | eeprom->opcode_bits = 3; | |
483 | eeprom->delay_usec = 50; | |
484 | if (eecd & E1000_EECD_ADDR_BITS) { | |
485 | eeprom->word_size = 256; | |
486 | eeprom->address_bits = 8; | |
487 | } else { | |
488 | eeprom->word_size = 64; | |
489 | eeprom->address_bits = 6; | |
490 | } | |
491 | } | |
472d5460 YS |
492 | eeprom->use_eerd = false; |
493 | eeprom->use_eewr = false; | |
aa070789 RZ |
494 | break; |
495 | case e1000_82571: | |
496 | case e1000_82572: | |
497 | eeprom->type = e1000_eeprom_spi; | |
498 | eeprom->opcode_bits = 8; | |
499 | eeprom->delay_usec = 1; | |
500 | if (eecd & E1000_EECD_ADDR_BITS) { | |
501 | eeprom->page_size = 32; | |
502 | eeprom->address_bits = 16; | |
503 | } else { | |
504 | eeprom->page_size = 8; | |
505 | eeprom->address_bits = 8; | |
506 | } | |
472d5460 YS |
507 | eeprom->use_eerd = false; |
508 | eeprom->use_eewr = false; | |
aa070789 RZ |
509 | break; |
510 | case e1000_82573: | |
2c2668f9 | 511 | case e1000_82574: |
aa070789 RZ |
512 | eeprom->type = e1000_eeprom_spi; |
513 | eeprom->opcode_bits = 8; | |
514 | eeprom->delay_usec = 1; | |
515 | if (eecd & E1000_EECD_ADDR_BITS) { | |
516 | eeprom->page_size = 32; | |
517 | eeprom->address_bits = 16; | |
518 | } else { | |
519 | eeprom->page_size = 8; | |
520 | eeprom->address_bits = 8; | |
682011ff | 521 | } |
472d5460 | 522 | if (e1000_is_onboard_nvm_eeprom(hw) == false) { |
95186063 MV |
523 | eeprom->use_eerd = true; |
524 | eeprom->use_eewr = true; | |
525 | ||
aa070789 RZ |
526 | eeprom->type = e1000_eeprom_flash; |
527 | eeprom->word_size = 2048; | |
528 | ||
529 | /* Ensure that the Autonomous FLASH update bit is cleared due to | |
530 | * Flash update issue on parts which use a FLASH for NVM. */ | |
531 | eecd &= ~E1000_EECD_AUPDEN; | |
682011ff | 532 | E1000_WRITE_REG(hw, EECD, eecd); |
682011ff | 533 | } |
aa070789 RZ |
534 | break; |
535 | case e1000_80003es2lan: | |
536 | eeprom->type = e1000_eeprom_spi; | |
537 | eeprom->opcode_bits = 8; | |
538 | eeprom->delay_usec = 1; | |
539 | if (eecd & E1000_EECD_ADDR_BITS) { | |
540 | eeprom->page_size = 32; | |
541 | eeprom->address_bits = 16; | |
542 | } else { | |
543 | eeprom->page_size = 8; | |
544 | eeprom->address_bits = 8; | |
545 | } | |
472d5460 YS |
546 | eeprom->use_eerd = true; |
547 | eeprom->use_eewr = false; | |
aa070789 | 548 | break; |
95186063 MV |
549 | case e1000_igb: |
550 | /* i210 has 4k of iNVM mapped as EEPROM */ | |
551 | eeprom->type = e1000_eeprom_invm; | |
552 | eeprom->opcode_bits = 8; | |
553 | eeprom->delay_usec = 1; | |
554 | eeprom->page_size = 32; | |
555 | eeprom->address_bits = 16; | |
556 | eeprom->use_eerd = true; | |
557 | eeprom->use_eewr = false; | |
558 | break; | |
aa070789 RZ |
559 | default: |
560 | break; | |
682011ff WD |
561 | } |
562 | ||
95186063 MV |
563 | if (eeprom->type == e1000_eeprom_spi || |
564 | eeprom->type == e1000_eeprom_invm) { | |
aa070789 RZ |
565 | /* eeprom_size will be an enum [0..8] that maps |
566 | * to eeprom sizes 128B to | |
567 | * 32KB (incremented by powers of 2). | |
568 | */ | |
569 | if (hw->mac_type <= e1000_82547_rev_2) { | |
570 | /* Set to default value for initial eeprom read. */ | |
571 | eeprom->word_size = 64; | |
572 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, | |
573 | &eeprom_size); | |
574 | if (ret_val) | |
575 | return ret_val; | |
576 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) | |
577 | >> EEPROM_SIZE_SHIFT; | |
578 | /* 256B eeprom size was not supported in earlier | |
579 | * hardware, so we bump eeprom_size up one to | |
580 | * ensure that "1" (which maps to 256B) is never | |
581 | * the result used in the shifting logic below. */ | |
582 | if (eeprom_size) | |
583 | eeprom_size++; | |
584 | } else { | |
585 | eeprom_size = (uint16_t)((eecd & | |
586 | E1000_EECD_SIZE_EX_MASK) >> | |
587 | E1000_EECD_SIZE_EX_SHIFT); | |
588 | } | |
589 | ||
590 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); | |
591 | } | |
592 | return ret_val; | |
682011ff WD |
593 | } |
594 | ||
aa070789 RZ |
595 | /****************************************************************************** |
596 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
597 | * | |
598 | * hw - Struct containing variables accessed by shared code | |
599 | *****************************************************************************/ | |
600 | static int32_t | |
601 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) | |
682011ff | 602 | { |
aa070789 RZ |
603 | uint32_t attempts = 100000; |
604 | uint32_t i, reg = 0; | |
605 | int32_t done = E1000_ERR_EEPROM; | |
682011ff | 606 | |
aa070789 | 607 | for (i = 0; i < attempts; i++) { |
95186063 MV |
608 | if (eerd == E1000_EEPROM_POLL_READ) { |
609 | if (hw->mac_type == e1000_igb) | |
610 | reg = E1000_READ_REG(hw, I210_EERD); | |
611 | else | |
612 | reg = E1000_READ_REG(hw, EERD); | |
613 | } else { | |
614 | if (hw->mac_type == e1000_igb) | |
615 | reg = E1000_READ_REG(hw, I210_EEWR); | |
616 | else | |
617 | reg = E1000_READ_REG(hw, EEWR); | |
618 | } | |
aa070789 RZ |
619 | |
620 | if (reg & E1000_EEPROM_RW_REG_DONE) { | |
621 | done = E1000_SUCCESS; | |
622 | break; | |
623 | } | |
624 | udelay(5); | |
625 | } | |
626 | ||
627 | return done; | |
682011ff WD |
628 | } |
629 | ||
aa070789 RZ |
630 | /****************************************************************************** |
631 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
632 | * | |
633 | * hw - Struct containing variables accessed by shared code | |
634 | * offset - offset of word in the EEPROM to read | |
635 | * data - word read from the EEPROM | |
636 | * words - number of words to read | |
637 | *****************************************************************************/ | |
638 | static int32_t | |
639 | e1000_read_eeprom_eerd(struct e1000_hw *hw, | |
640 | uint16_t offset, | |
641 | uint16_t words, | |
642 | uint16_t *data) | |
682011ff | 643 | { |
aa070789 RZ |
644 | uint32_t i, eerd = 0; |
645 | int32_t error = 0; | |
646 | ||
647 | for (i = 0; i < words; i++) { | |
648 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + | |
649 | E1000_EEPROM_RW_REG_START; | |
650 | ||
95186063 MV |
651 | if (hw->mac_type == e1000_igb) |
652 | E1000_WRITE_REG(hw, I210_EERD, eerd); | |
653 | else | |
654 | E1000_WRITE_REG(hw, EERD, eerd); | |
655 | ||
aa070789 RZ |
656 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
657 | ||
658 | if (error) | |
659 | break; | |
95186063 MV |
660 | |
661 | if (hw->mac_type == e1000_igb) { | |
662 | data[i] = (E1000_READ_REG(hw, I210_EERD) >> | |
663 | E1000_EEPROM_RW_REG_DATA); | |
664 | } else { | |
665 | data[i] = (E1000_READ_REG(hw, EERD) >> | |
aa070789 | 666 | E1000_EEPROM_RW_REG_DATA); |
95186063 | 667 | } |
682011ff | 668 | |
682011ff | 669 | } |
aa070789 RZ |
670 | |
671 | return error; | |
682011ff WD |
672 | } |
673 | ||
2326a94d | 674 | void e1000_release_eeprom(struct e1000_hw *hw) |
682011ff WD |
675 | { |
676 | uint32_t eecd; | |
682011ff | 677 | |
aa070789 RZ |
678 | DEBUGFUNC(); |
679 | ||
680 | eecd = E1000_READ_REG(hw, EECD); | |
681 | ||
682 | if (hw->eeprom.type == e1000_eeprom_spi) { | |
683 | eecd |= E1000_EECD_CS; /* Pull CS high */ | |
684 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ | |
685 | ||
682011ff | 686 | E1000_WRITE_REG(hw, EECD, eecd); |
aa070789 RZ |
687 | |
688 | udelay(hw->eeprom.delay_usec); | |
689 | } else if (hw->eeprom.type == e1000_eeprom_microwire) { | |
690 | /* cleanup eeprom */ | |
691 | ||
692 | /* CS on Microwire is active-high */ | |
693 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | |
694 | ||
695 | E1000_WRITE_REG(hw, EECD, eecd); | |
696 | ||
697 | /* Rising edge of clock */ | |
698 | eecd |= E1000_EECD_SK; | |
699 | E1000_WRITE_REG(hw, EECD, eecd); | |
700 | E1000_WRITE_FLUSH(hw); | |
701 | udelay(hw->eeprom.delay_usec); | |
702 | ||
703 | /* Falling edge of clock */ | |
704 | eecd &= ~E1000_EECD_SK; | |
705 | E1000_WRITE_REG(hw, EECD, eecd); | |
706 | E1000_WRITE_FLUSH(hw); | |
707 | udelay(hw->eeprom.delay_usec); | |
682011ff | 708 | } |
682011ff WD |
709 | |
710 | /* Stop requesting EEPROM access */ | |
711 | if (hw->mac_type > e1000_82544) { | |
682011ff WD |
712 | eecd &= ~E1000_EECD_REQ; |
713 | E1000_WRITE_REG(hw, EECD, eecd); | |
714 | } | |
7e2d991d TH |
715 | |
716 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); | |
682011ff | 717 | } |
7e2d991d | 718 | |
682011ff | 719 | /****************************************************************************** |
aa070789 | 720 | * Reads a 16 bit word from the EEPROM. |
8bde7f77 | 721 | * |
682011ff | 722 | * hw - Struct containing variables accessed by shared code |
682011ff | 723 | *****************************************************************************/ |
aa070789 RZ |
724 | static int32_t |
725 | e1000_spi_eeprom_ready(struct e1000_hw *hw) | |
682011ff | 726 | { |
aa070789 RZ |
727 | uint16_t retry_count = 0; |
728 | uint8_t spi_stat_reg; | |
682011ff WD |
729 | |
730 | DEBUGFUNC(); | |
731 | ||
aa070789 RZ |
732 | /* Read "Status Register" repeatedly until the LSB is cleared. The |
733 | * EEPROM will signal that the command has been completed by clearing | |
734 | * bit 0 of the internal status register. If it's not cleared within | |
735 | * 5 milliseconds, then error out. | |
736 | */ | |
737 | retry_count = 0; | |
738 | do { | |
739 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, | |
740 | hw->eeprom.opcode_bits); | |
741 | spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); | |
742 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) | |
743 | break; | |
8bde7f77 | 744 | |
aa070789 RZ |
745 | udelay(5); |
746 | retry_count += 5; | |
747 | ||
748 | e1000_standby_eeprom(hw); | |
749 | } while (retry_count < EEPROM_MAX_RETRY_SPI); | |
750 | ||
751 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and | |
752 | * only 0-5mSec on 5V devices) | |
753 | */ | |
754 | if (retry_count >= EEPROM_MAX_RETRY_SPI) { | |
755 | DEBUGOUT("SPI EEPROM Status error\n"); | |
682011ff WD |
756 | return -E1000_ERR_EEPROM; |
757 | } | |
aa070789 RZ |
758 | |
759 | return E1000_SUCCESS; | |
682011ff WD |
760 | } |
761 | ||
762 | /****************************************************************************** | |
aa070789 | 763 | * Reads a 16 bit word from the EEPROM. |
682011ff | 764 | * |
aa070789 RZ |
765 | * hw - Struct containing variables accessed by shared code |
766 | * offset - offset of word in the EEPROM to read | |
767 | * data - word read from the EEPROM | |
682011ff | 768 | *****************************************************************************/ |
aa070789 RZ |
769 | static int32_t |
770 | e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, | |
771 | uint16_t words, uint16_t *data) | |
682011ff | 772 | { |
aa070789 RZ |
773 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
774 | uint32_t i = 0; | |
682011ff WD |
775 | |
776 | DEBUGFUNC(); | |
777 | ||
aa070789 RZ |
778 | /* If eeprom is not yet detected, do so now */ |
779 | if (eeprom->word_size == 0) | |
780 | e1000_init_eeprom_params(hw); | |
781 | ||
782 | /* A check for invalid values: offset too large, too many words, | |
783 | * and not enough words. | |
784 | */ | |
785 | if ((offset >= eeprom->word_size) || | |
786 | (words > eeprom->word_size - offset) || | |
787 | (words == 0)) { | |
788 | DEBUGOUT("\"words\" parameter out of bounds." | |
789 | "Words = %d, size = %d\n", offset, eeprom->word_size); | |
790 | return -E1000_ERR_EEPROM; | |
791 | } | |
792 | ||
793 | /* EEPROM's that don't use EERD to read require us to bit-bang the SPI | |
794 | * directly. In this case, we need to acquire the EEPROM so that | |
795 | * FW or other port software does not interrupt. | |
796 | */ | |
472d5460 YS |
797 | if (e1000_is_onboard_nvm_eeprom(hw) == true && |
798 | hw->eeprom.use_eerd == false) { | |
aa070789 RZ |
799 | |
800 | /* Prepare the EEPROM for bit-bang reading */ | |
801 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
802 | return -E1000_ERR_EEPROM; | |
803 | } | |
804 | ||
805 | /* Eerd register EEPROM access requires no eeprom aquire/release */ | |
472d5460 | 806 | if (eeprom->use_eerd == true) |
aa070789 RZ |
807 | return e1000_read_eeprom_eerd(hw, offset, words, data); |
808 | ||
aa070789 RZ |
809 | /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
810 | * acquired the EEPROM at this point, so any returns should relase it */ | |
811 | if (eeprom->type == e1000_eeprom_spi) { | |
812 | uint16_t word_in; | |
813 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; | |
814 | ||
815 | if (e1000_spi_eeprom_ready(hw)) { | |
816 | e1000_release_eeprom(hw); | |
817 | return -E1000_ERR_EEPROM; | |
818 | } | |
819 | ||
820 | e1000_standby_eeprom(hw); | |
821 | ||
822 | /* Some SPI eeproms use the 8th address bit embedded in | |
823 | * the opcode */ | |
824 | if ((eeprom->address_bits == 8) && (offset >= 128)) | |
825 | read_opcode |= EEPROM_A8_OPCODE_SPI; | |
826 | ||
827 | /* Send the READ command (opcode + addr) */ | |
828 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); | |
829 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), | |
830 | eeprom->address_bits); | |
831 | ||
832 | /* Read the data. The address of the eeprom internally | |
833 | * increments with each byte (spi) being read, saving on the | |
834 | * overhead of eeprom setup and tear-down. The address | |
835 | * counter will roll over if reading beyond the size of | |
836 | * the eeprom, thus allowing the entire memory to be read | |
837 | * starting from any offset. */ | |
838 | for (i = 0; i < words; i++) { | |
839 | word_in = e1000_shift_in_ee_bits(hw, 16); | |
840 | data[i] = (word_in >> 8) | (word_in << 8); | |
841 | } | |
842 | } else if (eeprom->type == e1000_eeprom_microwire) { | |
843 | for (i = 0; i < words; i++) { | |
844 | /* Send the READ command (opcode + addr) */ | |
845 | e1000_shift_out_ee_bits(hw, | |
846 | EEPROM_READ_OPCODE_MICROWIRE, | |
847 | eeprom->opcode_bits); | |
848 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), | |
849 | eeprom->address_bits); | |
850 | ||
851 | /* Read the data. For microwire, each word requires | |
852 | * the overhead of eeprom setup and tear-down. */ | |
853 | data[i] = e1000_shift_in_ee_bits(hw, 16); | |
854 | e1000_standby_eeprom(hw); | |
855 | } | |
856 | } | |
857 | ||
858 | /* End this read operation */ | |
859 | e1000_release_eeprom(hw); | |
860 | ||
861 | return E1000_SUCCESS; | |
862 | } | |
863 | ||
864 | /****************************************************************************** | |
865 | * Verifies that the EEPROM has a valid checksum | |
866 | * | |
867 | * hw - Struct containing variables accessed by shared code | |
868 | * | |
869 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. | |
870 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is | |
871 | * valid. | |
872 | *****************************************************************************/ | |
114d7fc0 | 873 | static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
aa070789 | 874 | { |
114d7fc0 | 875 | uint16_t i, checksum, checksum_reg, *buf; |
aa070789 RZ |
876 | |
877 | DEBUGFUNC(); | |
878 | ||
114d7fc0 KM |
879 | /* Allocate a temporary buffer */ |
880 | buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); | |
881 | if (!buf) { | |
5c5e707a | 882 | E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); |
114d7fc0 | 883 | return -E1000_ERR_EEPROM; |
aa070789 RZ |
884 | } |
885 | ||
114d7fc0 KM |
886 | /* Read the EEPROM */ |
887 | if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { | |
5c5e707a | 888 | E1000_ERR(hw, "Unable to read EEPROM!\n"); |
aa070789 RZ |
889 | return -E1000_ERR_EEPROM; |
890 | } | |
114d7fc0 KM |
891 | |
892 | /* Compute the checksum */ | |
7a341066 | 893 | checksum = 0; |
114d7fc0 KM |
894 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) |
895 | checksum += buf[i]; | |
896 | checksum = ((uint16_t)EEPROM_SUM) - checksum; | |
897 | checksum_reg = buf[i]; | |
898 | ||
899 | /* Verify it! */ | |
900 | if (checksum == checksum_reg) | |
901 | return 0; | |
902 | ||
903 | /* Hrm, verification failed, print an error */ | |
5c5e707a SG |
904 | E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); |
905 | E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", | |
906 | checksum_reg, checksum); | |
114d7fc0 KM |
907 | |
908 | return -E1000_ERR_EEPROM; | |
aa070789 | 909 | } |
8712adfd | 910 | #endif /* CONFIG_E1000_NO_NVM */ |
ecbd2078 RZ |
911 | |
912 | /***************************************************************************** | |
913 | * Set PHY to class A mode | |
914 | * Assumes the following operations will follow to enable the new class mode. | |
915 | * 1. Do a PHY soft reset | |
916 | * 2. Restart auto-negotiation or force link. | |
917 | * | |
918 | * hw - Struct containing variables accessed by shared code | |
919 | ****************************************************************************/ | |
920 | static int32_t | |
921 | e1000_set_phy_mode(struct e1000_hw *hw) | |
922 | { | |
8712adfd | 923 | #ifndef CONFIG_E1000_NO_NVM |
ecbd2078 RZ |
924 | int32_t ret_val; |
925 | uint16_t eeprom_data; | |
926 | ||
927 | DEBUGFUNC(); | |
928 | ||
929 | if ((hw->mac_type == e1000_82545_rev_3) && | |
930 | (hw->media_type == e1000_media_type_copper)) { | |
931 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, | |
932 | 1, &eeprom_data); | |
933 | if (ret_val) | |
934 | return ret_val; | |
935 | ||
936 | if ((eeprom_data != EEPROM_RESERVED_WORD) && | |
937 | (eeprom_data & EEPROM_PHY_CLASS_A)) { | |
938 | ret_val = e1000_write_phy_reg(hw, | |
939 | M88E1000_PHY_PAGE_SELECT, 0x000B); | |
940 | if (ret_val) | |
941 | return ret_val; | |
942 | ret_val = e1000_write_phy_reg(hw, | |
943 | M88E1000_PHY_GEN_CONTROL, 0x8104); | |
944 | if (ret_val) | |
945 | return ret_val; | |
946 | ||
472d5460 | 947 | hw->phy_reset_disable = false; |
ecbd2078 RZ |
948 | } |
949 | } | |
8712adfd | 950 | #endif |
ecbd2078 RZ |
951 | return E1000_SUCCESS; |
952 | } | |
aa070789 | 953 | |
8712adfd | 954 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
955 | /*************************************************************************** |
956 | * | |
957 | * Obtaining software semaphore bit (SMBI) before resetting PHY. | |
958 | * | |
959 | * hw: Struct containing variables accessed by shared code | |
960 | * | |
961 | * returns: - E1000_ERR_RESET if fail to obtain semaphore. | |
962 | * E1000_SUCCESS at any other case. | |
963 | * | |
964 | ***************************************************************************/ | |
965 | static int32_t | |
966 | e1000_get_software_semaphore(struct e1000_hw *hw) | |
967 | { | |
968 | int32_t timeout = hw->eeprom.word_size + 1; | |
969 | uint32_t swsm; | |
970 | ||
971 | DEBUGFUNC(); | |
972 | ||
973 | if (hw->mac_type != e1000_80003es2lan) | |
974 | return E1000_SUCCESS; | |
975 | ||
976 | while (timeout) { | |
977 | swsm = E1000_READ_REG(hw, SWSM); | |
978 | /* If SMBI bit cleared, it is now set and we hold | |
979 | * the semaphore */ | |
980 | if (!(swsm & E1000_SWSM_SMBI)) | |
981 | break; | |
982 | mdelay(1); | |
983 | timeout--; | |
984 | } | |
985 | ||
986 | if (!timeout) { | |
987 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); | |
988 | return -E1000_ERR_RESET; | |
989 | } | |
990 | ||
991 | return E1000_SUCCESS; | |
992 | } | |
8712adfd | 993 | #endif |
aa070789 RZ |
994 | |
995 | /*************************************************************************** | |
996 | * This function clears HW semaphore bits. | |
997 | * | |
998 | * hw: Struct containing variables accessed by shared code | |
999 | * | |
1000 | * returns: - None. | |
1001 | * | |
1002 | ***************************************************************************/ | |
1003 | static void | |
1004 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) | |
1005 | { | |
8712adfd | 1006 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
1007 | uint32_t swsm; |
1008 | ||
1009 | DEBUGFUNC(); | |
1010 | ||
1011 | if (!hw->eeprom_semaphore_present) | |
1012 | return; | |
1013 | ||
1014 | swsm = E1000_READ_REG(hw, SWSM); | |
1015 | if (hw->mac_type == e1000_80003es2lan) { | |
1016 | /* Release both semaphores. */ | |
1017 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | |
1018 | } else | |
1019 | swsm &= ~(E1000_SWSM_SWESMBI); | |
1020 | E1000_WRITE_REG(hw, SWSM, swsm); | |
8712adfd | 1021 | #endif |
aa070789 RZ |
1022 | } |
1023 | ||
1024 | /*************************************************************************** | |
1025 | * | |
1026 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting | |
1027 | * adapter or Eeprom access. | |
1028 | * | |
1029 | * hw: Struct containing variables accessed by shared code | |
1030 | * | |
1031 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. | |
1032 | * E1000_SUCCESS at any other case. | |
1033 | * | |
1034 | ***************************************************************************/ | |
1035 | static int32_t | |
1036 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) | |
1037 | { | |
8712adfd | 1038 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
1039 | int32_t timeout; |
1040 | uint32_t swsm; | |
1041 | ||
1042 | DEBUGFUNC(); | |
1043 | ||
1044 | if (!hw->eeprom_semaphore_present) | |
1045 | return E1000_SUCCESS; | |
1046 | ||
1047 | if (hw->mac_type == e1000_80003es2lan) { | |
1048 | /* Get the SW semaphore. */ | |
1049 | if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) | |
1050 | return -E1000_ERR_EEPROM; | |
1051 | } | |
1052 | ||
1053 | /* Get the FW semaphore. */ | |
1054 | timeout = hw->eeprom.word_size + 1; | |
1055 | while (timeout) { | |
1056 | swsm = E1000_READ_REG(hw, SWSM); | |
1057 | swsm |= E1000_SWSM_SWESMBI; | |
1058 | E1000_WRITE_REG(hw, SWSM, swsm); | |
1059 | /* if we managed to set the bit we got the semaphore. */ | |
1060 | swsm = E1000_READ_REG(hw, SWSM); | |
1061 | if (swsm & E1000_SWSM_SWESMBI) | |
1062 | break; | |
1063 | ||
1064 | udelay(50); | |
1065 | timeout--; | |
1066 | } | |
1067 | ||
1068 | if (!timeout) { | |
1069 | /* Release semaphores */ | |
1070 | e1000_put_hw_eeprom_semaphore(hw); | |
1071 | DEBUGOUT("Driver can't access the Eeprom - " | |
1072 | "SWESMBI bit is set.\n"); | |
1073 | return -E1000_ERR_EEPROM; | |
1074 | } | |
8712adfd | 1075 | #endif |
aa070789 RZ |
1076 | return E1000_SUCCESS; |
1077 | } | |
1078 | ||
7e2d991d | 1079 | /* Take ownership of the PHY */ |
aa070789 RZ |
1080 | static int32_t |
1081 | e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) | |
1082 | { | |
1083 | uint32_t swfw_sync = 0; | |
1084 | uint32_t swmask = mask; | |
1085 | uint32_t fwmask = mask << 16; | |
1086 | int32_t timeout = 200; | |
1087 | ||
1088 | DEBUGFUNC(); | |
1089 | while (timeout) { | |
1090 | if (e1000_get_hw_eeprom_semaphore(hw)) | |
1091 | return -E1000_ERR_SWFW_SYNC; | |
1092 | ||
3c63dd53 | 1093 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
76f8cdb2 | 1094 | if (!(swfw_sync & (fwmask | swmask))) |
aa070789 RZ |
1095 | break; |
1096 | ||
1097 | /* firmware currently using resource (fwmask) */ | |
1098 | /* or other software thread currently using resource (swmask) */ | |
1099 | e1000_put_hw_eeprom_semaphore(hw); | |
1100 | mdelay(5); | |
1101 | timeout--; | |
1102 | } | |
1103 | ||
1104 | if (!timeout) { | |
1105 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); | |
1106 | return -E1000_ERR_SWFW_SYNC; | |
1107 | } | |
1108 | ||
1109 | swfw_sync |= swmask; | |
1110 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); | |
1111 | ||
1112 | e1000_put_hw_eeprom_semaphore(hw); | |
1113 | return E1000_SUCCESS; | |
1114 | } | |
1115 | ||
7e2d991d TH |
1116 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) |
1117 | { | |
1118 | uint32_t swfw_sync = 0; | |
1119 | ||
1120 | DEBUGFUNC(); | |
1121 | while (e1000_get_hw_eeprom_semaphore(hw)) | |
1122 | ; /* Empty */ | |
1123 | ||
1124 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); | |
1125 | swfw_sync &= ~mask; | |
1126 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); | |
1127 | ||
1128 | e1000_put_hw_eeprom_semaphore(hw); | |
1129 | } | |
1130 | ||
472d5460 | 1131 | static bool e1000_is_second_port(struct e1000_hw *hw) |
987b43a1 KM |
1132 | { |
1133 | switch (hw->mac_type) { | |
1134 | case e1000_80003es2lan: | |
1135 | case e1000_82546: | |
1136 | case e1000_82571: | |
1137 | if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) | |
472d5460 | 1138 | return true; |
987b43a1 KM |
1139 | /* Fallthrough */ |
1140 | default: | |
472d5460 | 1141 | return false; |
987b43a1 KM |
1142 | } |
1143 | } | |
1144 | ||
8712adfd | 1145 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
1146 | /****************************************************************************** |
1147 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the | |
1148 | * second function of dual function devices | |
1149 | * | |
1150 | * nic - Struct containing variables accessed by shared code | |
1151 | *****************************************************************************/ | |
1152 | static int | |
5c5e707a | 1153 | e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) |
aa070789 | 1154 | { |
aa070789 RZ |
1155 | uint16_t offset; |
1156 | uint16_t eeprom_data; | |
95186063 | 1157 | uint32_t reg_data = 0; |
aa070789 RZ |
1158 | int i; |
1159 | ||
1160 | DEBUGFUNC(); | |
1161 | ||
1162 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { | |
1163 | offset = i >> 1; | |
95186063 MV |
1164 | if (hw->mac_type == e1000_igb) { |
1165 | /* i210 preloads MAC address into RAL/RAH registers */ | |
1166 | if (offset == 0) | |
1167 | reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); | |
1168 | else if (offset == 1) | |
1169 | reg_data >>= 16; | |
1170 | else if (offset == 2) | |
1171 | reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); | |
1172 | eeprom_data = reg_data & 0xffff; | |
1173 | } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { | |
682011ff WD |
1174 | DEBUGOUT("EEPROM Read Error\n"); |
1175 | return -E1000_ERR_EEPROM; | |
1176 | } | |
5c5e707a SG |
1177 | enetaddr[i] = eeprom_data & 0xff; |
1178 | enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; | |
682011ff | 1179 | } |
987b43a1 KM |
1180 | |
1181 | /* Invert the last bit if this is the second device */ | |
1182 | if (e1000_is_second_port(hw)) | |
5c5e707a | 1183 | enetaddr[5] ^= 1; |
987b43a1 | 1184 | |
682011ff WD |
1185 | return 0; |
1186 | } | |
8712adfd | 1187 | #endif |
682011ff WD |
1188 | |
1189 | /****************************************************************************** | |
1190 | * Initializes receive address filters. | |
1191 | * | |
8bde7f77 | 1192 | * hw - Struct containing variables accessed by shared code |
682011ff WD |
1193 | * |
1194 | * Places the MAC address in receive address register 0 and clears the rest | |
1195 | * of the receive addresss registers. Clears the multicast table. Assumes | |
1196 | * the receiver is in reset when the routine is called. | |
1197 | *****************************************************************************/ | |
1198 | static void | |
5c5e707a | 1199 | e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) |
682011ff | 1200 | { |
682011ff WD |
1201 | uint32_t i; |
1202 | uint32_t addr_low; | |
1203 | uint32_t addr_high; | |
1204 | ||
1205 | DEBUGFUNC(); | |
1206 | ||
1207 | /* Setup the receive address. */ | |
1208 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); | |
5c5e707a SG |
1209 | addr_low = (enetaddr[0] | |
1210 | (enetaddr[1] << 8) | | |
1211 | (enetaddr[2] << 16) | (enetaddr[3] << 24)); | |
682011ff | 1212 | |
5c5e707a | 1213 | addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); |
682011ff WD |
1214 | |
1215 | E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); | |
1216 | E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); | |
1217 | ||
1218 | /* Zero out the other 15 receive addresses. */ | |
1219 | DEBUGOUT("Clearing RAR[1-15]\n"); | |
1220 | for (i = 1; i < E1000_RAR_ENTRIES; i++) { | |
1221 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); | |
1222 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | /****************************************************************************** | |
1227 | * Clears the VLAN filer table | |
1228 | * | |
1229 | * hw - Struct containing variables accessed by shared code | |
1230 | *****************************************************************************/ | |
1231 | static void | |
1232 | e1000_clear_vfta(struct e1000_hw *hw) | |
1233 | { | |
1234 | uint32_t offset; | |
1235 | ||
1236 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) | |
1237 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); | |
1238 | } | |
1239 | ||
1240 | /****************************************************************************** | |
1241 | * Set the mac type member in the hw struct. | |
8bde7f77 | 1242 | * |
682011ff WD |
1243 | * hw - Struct containing variables accessed by shared code |
1244 | *****************************************************************************/ | |
aa070789 | 1245 | int32_t |
682011ff WD |
1246 | e1000_set_mac_type(struct e1000_hw *hw) |
1247 | { | |
1248 | DEBUGFUNC(); | |
1249 | ||
1250 | switch (hw->device_id) { | |
1251 | case E1000_DEV_ID_82542: | |
1252 | switch (hw->revision_id) { | |
1253 | case E1000_82542_2_0_REV_ID: | |
1254 | hw->mac_type = e1000_82542_rev2_0; | |
1255 | break; | |
1256 | case E1000_82542_2_1_REV_ID: | |
1257 | hw->mac_type = e1000_82542_rev2_1; | |
1258 | break; | |
1259 | default: | |
1260 | /* Invalid 82542 revision ID */ | |
1261 | return -E1000_ERR_MAC_TYPE; | |
1262 | } | |
1263 | break; | |
1264 | case E1000_DEV_ID_82543GC_FIBER: | |
1265 | case E1000_DEV_ID_82543GC_COPPER: | |
1266 | hw->mac_type = e1000_82543; | |
1267 | break; | |
1268 | case E1000_DEV_ID_82544EI_COPPER: | |
1269 | case E1000_DEV_ID_82544EI_FIBER: | |
1270 | case E1000_DEV_ID_82544GC_COPPER: | |
1271 | case E1000_DEV_ID_82544GC_LOM: | |
1272 | hw->mac_type = e1000_82544; | |
1273 | break; | |
1274 | case E1000_DEV_ID_82540EM: | |
1275 | case E1000_DEV_ID_82540EM_LOM: | |
aa070789 RZ |
1276 | case E1000_DEV_ID_82540EP: |
1277 | case E1000_DEV_ID_82540EP_LOM: | |
1278 | case E1000_DEV_ID_82540EP_LP: | |
682011ff WD |
1279 | hw->mac_type = e1000_82540; |
1280 | break; | |
1281 | case E1000_DEV_ID_82545EM_COPPER: | |
1282 | case E1000_DEV_ID_82545EM_FIBER: | |
1283 | hw->mac_type = e1000_82545; | |
1284 | break; | |
aa070789 RZ |
1285 | case E1000_DEV_ID_82545GM_COPPER: |
1286 | case E1000_DEV_ID_82545GM_FIBER: | |
1287 | case E1000_DEV_ID_82545GM_SERDES: | |
1288 | hw->mac_type = e1000_82545_rev_3; | |
1289 | break; | |
682011ff WD |
1290 | case E1000_DEV_ID_82546EB_COPPER: |
1291 | case E1000_DEV_ID_82546EB_FIBER: | |
aa070789 | 1292 | case E1000_DEV_ID_82546EB_QUAD_COPPER: |
682011ff WD |
1293 | hw->mac_type = e1000_82546; |
1294 | break; | |
aa070789 RZ |
1295 | case E1000_DEV_ID_82546GB_COPPER: |
1296 | case E1000_DEV_ID_82546GB_FIBER: | |
1297 | case E1000_DEV_ID_82546GB_SERDES: | |
1298 | case E1000_DEV_ID_82546GB_PCIE: | |
1299 | case E1000_DEV_ID_82546GB_QUAD_COPPER: | |
1300 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: | |
1301 | hw->mac_type = e1000_82546_rev_3; | |
1302 | break; | |
1303 | case E1000_DEV_ID_82541EI: | |
1304 | case E1000_DEV_ID_82541EI_MOBILE: | |
1305 | case E1000_DEV_ID_82541ER_LOM: | |
1306 | hw->mac_type = e1000_82541; | |
1307 | break; | |
ac3315c2 | 1308 | case E1000_DEV_ID_82541ER: |
aa070789 | 1309 | case E1000_DEV_ID_82541GI: |
aa3b8bf9 | 1310 | case E1000_DEV_ID_82541GI_LF: |
aa070789 | 1311 | case E1000_DEV_ID_82541GI_MOBILE: |
1aeed8d7 WD |
1312 | hw->mac_type = e1000_82541_rev_2; |
1313 | break; | |
aa070789 RZ |
1314 | case E1000_DEV_ID_82547EI: |
1315 | case E1000_DEV_ID_82547EI_MOBILE: | |
1316 | hw->mac_type = e1000_82547; | |
1317 | break; | |
1318 | case E1000_DEV_ID_82547GI: | |
1319 | hw->mac_type = e1000_82547_rev_2; | |
1320 | break; | |
1321 | case E1000_DEV_ID_82571EB_COPPER: | |
1322 | case E1000_DEV_ID_82571EB_FIBER: | |
1323 | case E1000_DEV_ID_82571EB_SERDES: | |
1324 | case E1000_DEV_ID_82571EB_SERDES_DUAL: | |
1325 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
1326 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
1327 | case E1000_DEV_ID_82571PT_QUAD_COPPER: | |
1328 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
1329 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: | |
1330 | hw->mac_type = e1000_82571; | |
1331 | break; | |
1332 | case E1000_DEV_ID_82572EI_COPPER: | |
1333 | case E1000_DEV_ID_82572EI_FIBER: | |
1334 | case E1000_DEV_ID_82572EI_SERDES: | |
1335 | case E1000_DEV_ID_82572EI: | |
1336 | hw->mac_type = e1000_82572; | |
1337 | break; | |
1338 | case E1000_DEV_ID_82573E: | |
1339 | case E1000_DEV_ID_82573E_IAMT: | |
1340 | case E1000_DEV_ID_82573L: | |
1341 | hw->mac_type = e1000_82573; | |
1342 | break; | |
2c2668f9 RZ |
1343 | case E1000_DEV_ID_82574L: |
1344 | hw->mac_type = e1000_82574; | |
1345 | break; | |
aa070789 RZ |
1346 | case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: |
1347 | case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: | |
1348 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: | |
1349 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
1350 | hw->mac_type = e1000_80003es2lan; | |
1351 | break; | |
1352 | case E1000_DEV_ID_ICH8_IGP_M_AMT: | |
1353 | case E1000_DEV_ID_ICH8_IGP_AMT: | |
1354 | case E1000_DEV_ID_ICH8_IGP_C: | |
1355 | case E1000_DEV_ID_ICH8_IFE: | |
1356 | case E1000_DEV_ID_ICH8_IFE_GT: | |
1357 | case E1000_DEV_ID_ICH8_IFE_G: | |
1358 | case E1000_DEV_ID_ICH8_IGP_M: | |
1359 | hw->mac_type = e1000_ich8lan; | |
1360 | break; | |
6c499abe MZ |
1361 | case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: |
1362 | case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: | |
95186063 | 1363 | case PCI_DEVICE_ID_INTEL_I210_COPPER: |
6c499abe | 1364 | case PCI_DEVICE_ID_INTEL_I211_COPPER: |
95186063 MV |
1365 | case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: |
1366 | case PCI_DEVICE_ID_INTEL_I210_SERDES: | |
1367 | case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: | |
1368 | case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: | |
1369 | hw->mac_type = e1000_igb; | |
1370 | break; | |
682011ff WD |
1371 | default: |
1372 | /* Should never have loaded on this device */ | |
1373 | return -E1000_ERR_MAC_TYPE; | |
1374 | } | |
1375 | return E1000_SUCCESS; | |
1376 | } | |
1377 | ||
1378 | /****************************************************************************** | |
1379 | * Reset the transmit and receive units; mask and clear all interrupts. | |
1380 | * | |
1381 | * hw - Struct containing variables accessed by shared code | |
1382 | *****************************************************************************/ | |
1383 | void | |
1384 | e1000_reset_hw(struct e1000_hw *hw) | |
1385 | { | |
1386 | uint32_t ctrl; | |
1387 | uint32_t ctrl_ext; | |
682011ff | 1388 | uint32_t manc; |
9ea005fb | 1389 | uint32_t pba = 0; |
95186063 | 1390 | uint32_t reg; |
682011ff WD |
1391 | |
1392 | DEBUGFUNC(); | |
1393 | ||
9ea005fb RZ |
1394 | /* get the correct pba value for both PCI and PCIe*/ |
1395 | if (hw->mac_type < e1000_82571) | |
1396 | pba = E1000_DEFAULT_PCI_PBA; | |
1397 | else | |
1398 | pba = E1000_DEFAULT_PCIE_PBA; | |
1399 | ||
682011ff WD |
1400 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
1401 | if (hw->mac_type == e1000_82542_rev2_0) { | |
1402 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | |
81dab9af BM |
1403 | #ifdef CONFIG_DM_ETH |
1404 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, | |
1405 | hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); | |
1406 | #else | |
682011ff | 1407 | pci_write_config_word(hw->pdev, PCI_COMMAND, |
aa070789 | 1408 | hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); |
81dab9af | 1409 | #endif |
682011ff WD |
1410 | } |
1411 | ||
1412 | /* Clear interrupt mask to stop board from generating interrupts */ | |
1413 | DEBUGOUT("Masking off all interrupts\n"); | |
95186063 MV |
1414 | if (hw->mac_type == e1000_igb) |
1415 | E1000_WRITE_REG(hw, I210_IAM, 0); | |
682011ff WD |
1416 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
1417 | ||
1418 | /* Disable the Transmit and Receive units. Then delay to allow | |
1419 | * any pending transactions to complete before we hit the MAC with | |
1420 | * the global reset. | |
1421 | */ | |
1422 | E1000_WRITE_REG(hw, RCTL, 0); | |
1423 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); | |
1424 | E1000_WRITE_FLUSH(hw); | |
1425 | ||
1426 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ | |
472d5460 | 1427 | hw->tbi_compatibility_on = false; |
682011ff WD |
1428 | |
1429 | /* Delay to allow any outstanding PCI transactions to complete before | |
1430 | * resetting the device | |
1431 | */ | |
1432 | mdelay(10); | |
1433 | ||
1434 | /* Issue a global reset to the MAC. This will reset the chip's | |
1435 | * transmit, receive, DMA, and link units. It will not effect | |
1436 | * the current PCI configuration. The global reset bit is self- | |
1437 | * clearing, and should clear within a microsecond. | |
1438 | */ | |
1439 | DEBUGOUT("Issuing a global reset to MAC\n"); | |
1440 | ctrl = E1000_READ_REG(hw, CTRL); | |
1441 | ||
aa070789 | 1442 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
682011ff WD |
1443 | |
1444 | /* Force a reload from the EEPROM if necessary */ | |
95186063 MV |
1445 | if (hw->mac_type == e1000_igb) { |
1446 | mdelay(20); | |
1447 | reg = E1000_READ_REG(hw, STATUS); | |
1448 | if (reg & E1000_STATUS_PF_RST_DONE) | |
1449 | DEBUGOUT("PF OK\n"); | |
1450 | reg = E1000_READ_REG(hw, I210_EECD); | |
1451 | if (reg & E1000_EECD_AUTO_RD) | |
1452 | DEBUGOUT("EEC OK\n"); | |
1453 | } else if (hw->mac_type < e1000_82540) { | |
682011ff WD |
1454 | /* Wait for reset to complete */ |
1455 | udelay(10); | |
1456 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
1457 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
1458 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
1459 | E1000_WRITE_FLUSH(hw); | |
1460 | /* Wait for EEPROM reload */ | |
1461 | mdelay(2); | |
1462 | } else { | |
1463 | /* Wait for EEPROM reload (it happens automatically) */ | |
1464 | mdelay(4); | |
1465 | /* Dissable HW ARPs on ASF enabled adapters */ | |
1466 | manc = E1000_READ_REG(hw, MANC); | |
1467 | manc &= ~(E1000_MANC_ARP_EN); | |
1468 | E1000_WRITE_REG(hw, MANC, manc); | |
1469 | } | |
1470 | ||
1471 | /* Clear interrupt mask to stop board from generating interrupts */ | |
1472 | DEBUGOUT("Masking off all interrupts\n"); | |
95186063 MV |
1473 | if (hw->mac_type == e1000_igb) |
1474 | E1000_WRITE_REG(hw, I210_IAM, 0); | |
682011ff WD |
1475 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
1476 | ||
1477 | /* Clear any pending interrupt events. */ | |
56b13b1e | 1478 | E1000_READ_REG(hw, ICR); |
682011ff WD |
1479 | |
1480 | /* If MWI was previously enabled, reenable it. */ | |
1481 | if (hw->mac_type == e1000_82542_rev2_0) { | |
81dab9af BM |
1482 | #ifdef CONFIG_DM_ETH |
1483 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); | |
1484 | #else | |
682011ff | 1485 | pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); |
81dab9af | 1486 | #endif |
682011ff | 1487 | } |
95186063 MV |
1488 | if (hw->mac_type != e1000_igb) |
1489 | E1000_WRITE_REG(hw, PBA, pba); | |
aa070789 RZ |
1490 | } |
1491 | ||
1492 | /****************************************************************************** | |
1493 | * | |
1494 | * Initialize a number of hardware-dependent bits | |
1495 | * | |
1496 | * hw: Struct containing variables accessed by shared code | |
1497 | * | |
1498 | * This function contains hardware limitation workarounds for PCI-E adapters | |
1499 | * | |
1500 | *****************************************************************************/ | |
1501 | static void | |
1502 | e1000_initialize_hardware_bits(struct e1000_hw *hw) | |
1503 | { | |
1504 | if ((hw->mac_type >= e1000_82571) && | |
1505 | (!hw->initialize_hw_bits_disable)) { | |
1506 | /* Settings common to all PCI-express silicon */ | |
1507 | uint32_t reg_ctrl, reg_ctrl_ext; | |
1508 | uint32_t reg_tarc0, reg_tarc1; | |
1509 | uint32_t reg_tctl; | |
1510 | uint32_t reg_txdctl, reg_txdctl1; | |
1511 | ||
1512 | /* link autonegotiation/sync workarounds */ | |
1513 | reg_tarc0 = E1000_READ_REG(hw, TARC0); | |
1514 | reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); | |
1515 | ||
1516 | /* Enable not-done TX descriptor counting */ | |
1517 | reg_txdctl = E1000_READ_REG(hw, TXDCTL); | |
1518 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC; | |
1519 | E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); | |
1520 | ||
1521 | reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); | |
1522 | reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; | |
1523 | E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); | |
1524 | ||
95186063 | 1525 | |
aa070789 | 1526 | switch (hw->mac_type) { |
063bb708 AP |
1527 | case e1000_igb: /* IGB is cool */ |
1528 | return; | |
aa070789 RZ |
1529 | case e1000_82571: |
1530 | case e1000_82572: | |
1531 | /* Clear PHY TX compatible mode bits */ | |
1532 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
1533 | reg_tarc1 &= ~((1 << 30)|(1 << 29)); | |
1534 | ||
1535 | /* link autonegotiation/sync workarounds */ | |
1536 | reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); | |
1537 | ||
1538 | /* TX ring control fixes */ | |
1539 | reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); | |
1540 | ||
1541 | /* Multiple read bit is reversed polarity */ | |
1542 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
1543 | if (reg_tctl & E1000_TCTL_MULR) | |
1544 | reg_tarc1 &= ~(1 << 28); | |
1545 | else | |
1546 | reg_tarc1 |= (1 << 28); | |
1547 | ||
1548 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
1549 | break; | |
1550 | case e1000_82573: | |
2c2668f9 | 1551 | case e1000_82574: |
aa070789 RZ |
1552 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
1553 | reg_ctrl_ext &= ~(1 << 23); | |
1554 | reg_ctrl_ext |= (1 << 22); | |
1555 | ||
1556 | /* TX byte count fix */ | |
1557 | reg_ctrl = E1000_READ_REG(hw, CTRL); | |
1558 | reg_ctrl &= ~(1 << 29); | |
1559 | ||
1560 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); | |
1561 | E1000_WRITE_REG(hw, CTRL, reg_ctrl); | |
1562 | break; | |
1563 | case e1000_80003es2lan: | |
1564 | /* improve small packet performace for fiber/serdes */ | |
1565 | if ((hw->media_type == e1000_media_type_fiber) | |
1566 | || (hw->media_type == | |
1567 | e1000_media_type_internal_serdes)) { | |
1568 | reg_tarc0 &= ~(1 << 20); | |
1569 | } | |
1570 | ||
1571 | /* Multiple read bit is reversed polarity */ | |
1572 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
1573 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
1574 | if (reg_tctl & E1000_TCTL_MULR) | |
1575 | reg_tarc1 &= ~(1 << 28); | |
1576 | else | |
1577 | reg_tarc1 |= (1 << 28); | |
1578 | ||
1579 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
1580 | break; | |
1581 | case e1000_ich8lan: | |
1582 | /* Reduce concurrent DMA requests to 3 from 4 */ | |
1583 | if ((hw->revision_id < 3) || | |
1584 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | |
1585 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) | |
1586 | reg_tarc0 |= ((1 << 29)|(1 << 28)); | |
1587 | ||
1588 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
1589 | reg_ctrl_ext |= (1 << 22); | |
1590 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); | |
1591 | ||
1592 | /* workaround TX hang with TSO=on */ | |
1593 | reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); | |
1594 | ||
1595 | /* Multiple read bit is reversed polarity */ | |
1596 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
1597 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
1598 | if (reg_tctl & E1000_TCTL_MULR) | |
1599 | reg_tarc1 &= ~(1 << 28); | |
1600 | else | |
1601 | reg_tarc1 |= (1 << 28); | |
1602 | ||
1603 | /* workaround TX hang with TSO=on */ | |
1604 | reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); | |
1605 | ||
1606 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
1607 | break; | |
1608 | default: | |
1609 | break; | |
1610 | } | |
1611 | ||
1612 | E1000_WRITE_REG(hw, TARC0, reg_tarc0); | |
1613 | } | |
682011ff WD |
1614 | } |
1615 | ||
1616 | /****************************************************************************** | |
1617 | * Performs basic configuration of the adapter. | |
1618 | * | |
1619 | * hw - Struct containing variables accessed by shared code | |
8bde7f77 WD |
1620 | * |
1621 | * Assumes that the controller has previously been reset and is in a | |
682011ff WD |
1622 | * post-reset uninitialized state. Initializes the receive address registers, |
1623 | * multicast table, and VLAN filter table. Calls routines to setup link | |
1624 | * configuration and flow control settings. Clears all on-chip counters. Leaves | |
1625 | * the transmit and receive units disabled and uninitialized. | |
1626 | *****************************************************************************/ | |
1627 | static int | |
5c5e707a | 1628 | e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) |
682011ff | 1629 | { |
aa070789 | 1630 | uint32_t ctrl; |
682011ff WD |
1631 | uint32_t i; |
1632 | int32_t ret_val; | |
1633 | uint16_t pcix_cmd_word; | |
1634 | uint16_t pcix_stat_hi_word; | |
1635 | uint16_t cmd_mmrbc; | |
1636 | uint16_t stat_mmrbc; | |
aa070789 RZ |
1637 | uint32_t mta_size; |
1638 | uint32_t reg_data; | |
1639 | uint32_t ctrl_ext; | |
682011ff | 1640 | DEBUGFUNC(); |
aa070789 RZ |
1641 | /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ |
1642 | if ((hw->mac_type == e1000_ich8lan) && | |
1643 | ((hw->revision_id < 3) || | |
1644 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | |
1645 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { | |
1646 | reg_data = E1000_READ_REG(hw, STATUS); | |
1647 | reg_data &= ~0x80000000; | |
1648 | E1000_WRITE_REG(hw, STATUS, reg_data); | |
682011ff | 1649 | } |
aa070789 | 1650 | /* Do not need initialize Identification LED */ |
682011ff | 1651 | |
aa070789 RZ |
1652 | /* Set the media type and TBI compatibility */ |
1653 | e1000_set_media_type(hw); | |
1654 | ||
1655 | /* Must be called after e1000_set_media_type | |
1656 | * because media_type is used */ | |
1657 | e1000_initialize_hardware_bits(hw); | |
682011ff WD |
1658 | |
1659 | /* Disabling VLAN filtering. */ | |
1660 | DEBUGOUT("Initializing the IEEE VLAN\n"); | |
aa070789 RZ |
1661 | /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ |
1662 | if (hw->mac_type != e1000_ich8lan) { | |
1663 | if (hw->mac_type < e1000_82545_rev_3) | |
1664 | E1000_WRITE_REG(hw, VET, 0); | |
1665 | e1000_clear_vfta(hw); | |
1666 | } | |
682011ff WD |
1667 | |
1668 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ | |
1669 | if (hw->mac_type == e1000_82542_rev2_0) { | |
1670 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | |
81dab9af BM |
1671 | #ifdef CONFIG_DM_ETH |
1672 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, | |
1673 | hw-> | |
1674 | pci_cmd_word & ~PCI_COMMAND_INVALIDATE); | |
1675 | #else | |
682011ff WD |
1676 | pci_write_config_word(hw->pdev, PCI_COMMAND, |
1677 | hw-> | |
1678 | pci_cmd_word & ~PCI_COMMAND_INVALIDATE); | |
81dab9af | 1679 | #endif |
682011ff WD |
1680 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
1681 | E1000_WRITE_FLUSH(hw); | |
1682 | mdelay(5); | |
1683 | } | |
1684 | ||
1685 | /* Setup the receive address. This involves initializing all of the Receive | |
1686 | * Address Registers (RARs 0 - 15). | |
1687 | */ | |
5c5e707a | 1688 | e1000_init_rx_addrs(hw, enetaddr); |
682011ff WD |
1689 | |
1690 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ | |
1691 | if (hw->mac_type == e1000_82542_rev2_0) { | |
1692 | E1000_WRITE_REG(hw, RCTL, 0); | |
1693 | E1000_WRITE_FLUSH(hw); | |
1694 | mdelay(1); | |
81dab9af BM |
1695 | #ifdef CONFIG_DM_ETH |
1696 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); | |
1697 | #else | |
682011ff | 1698 | pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); |
81dab9af | 1699 | #endif |
682011ff WD |
1700 | } |
1701 | ||
1702 | /* Zero out the Multicast HASH table */ | |
1703 | DEBUGOUT("Zeroing the MTA\n"); | |
aa070789 RZ |
1704 | mta_size = E1000_MC_TBL_SIZE; |
1705 | if (hw->mac_type == e1000_ich8lan) | |
1706 | mta_size = E1000_MC_TBL_SIZE_ICH8LAN; | |
1707 | for (i = 0; i < mta_size; i++) { | |
682011ff | 1708 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
aa070789 RZ |
1709 | /* use write flush to prevent Memory Write Block (MWB) from |
1710 | * occuring when accessing our register space */ | |
1711 | E1000_WRITE_FLUSH(hw); | |
1712 | } | |
e97f7fbb | 1713 | |
aa070789 RZ |
1714 | switch (hw->mac_type) { |
1715 | case e1000_82545_rev_3: | |
1716 | case e1000_82546_rev_3: | |
95186063 | 1717 | case e1000_igb: |
aa070789 RZ |
1718 | break; |
1719 | default: | |
682011ff | 1720 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
aa070789 | 1721 | if (hw->bus_type == e1000_bus_type_pcix) { |
81dab9af BM |
1722 | #ifdef CONFIG_DM_ETH |
1723 | dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, | |
1724 | &pcix_cmd_word); | |
1725 | dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, | |
1726 | &pcix_stat_hi_word); | |
1727 | #else | |
682011ff WD |
1728 | pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, |
1729 | &pcix_cmd_word); | |
1730 | pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, | |
1731 | &pcix_stat_hi_word); | |
81dab9af | 1732 | #endif |
682011ff WD |
1733 | cmd_mmrbc = |
1734 | (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> | |
1735 | PCIX_COMMAND_MMRBC_SHIFT; | |
1736 | stat_mmrbc = | |
1737 | (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> | |
1738 | PCIX_STATUS_HI_MMRBC_SHIFT; | |
1739 | if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) | |
1740 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; | |
1741 | if (cmd_mmrbc > stat_mmrbc) { | |
1742 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; | |
1743 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; | |
81dab9af BM |
1744 | #ifdef CONFIG_DM_ETH |
1745 | dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, | |
1746 | pcix_cmd_word); | |
1747 | #else | |
682011ff WD |
1748 | pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, |
1749 | pcix_cmd_word); | |
81dab9af | 1750 | #endif |
682011ff WD |
1751 | } |
1752 | } | |
aa070789 RZ |
1753 | break; |
1754 | } | |
1755 | ||
1756 | /* More time needed for PHY to initialize */ | |
1757 | if (hw->mac_type == e1000_ich8lan) | |
1758 | mdelay(15); | |
95186063 MV |
1759 | if (hw->mac_type == e1000_igb) |
1760 | mdelay(15); | |
682011ff WD |
1761 | |
1762 | /* Call a subroutine to configure the link and setup flow control. */ | |
5c5e707a | 1763 | ret_val = e1000_setup_link(hw); |
682011ff WD |
1764 | |
1765 | /* Set the transmit descriptor write-back policy */ | |
1766 | if (hw->mac_type > e1000_82544) { | |
1767 | ctrl = E1000_READ_REG(hw, TXDCTL); | |
1768 | ctrl = | |
1769 | (ctrl & ~E1000_TXDCTL_WTHRESH) | | |
1770 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
1771 | E1000_WRITE_REG(hw, TXDCTL, ctrl); | |
1772 | } | |
aa070789 | 1773 | |
776e66e8 | 1774 | /* Set the receive descriptor write back policy */ |
776e66e8 RG |
1775 | if (hw->mac_type >= e1000_82571) { |
1776 | ctrl = E1000_READ_REG(hw, RXDCTL); | |
1777 | ctrl = | |
1778 | (ctrl & ~E1000_RXDCTL_WTHRESH) | | |
1779 | E1000_RXDCTL_FULL_RX_DESC_WB; | |
1780 | E1000_WRITE_REG(hw, RXDCTL, ctrl); | |
1781 | } | |
1782 | ||
aa070789 RZ |
1783 | switch (hw->mac_type) { |
1784 | default: | |
1785 | break; | |
1786 | case e1000_80003es2lan: | |
1787 | /* Enable retransmit on late collisions */ | |
1788 | reg_data = E1000_READ_REG(hw, TCTL); | |
1789 | reg_data |= E1000_TCTL_RTLC; | |
1790 | E1000_WRITE_REG(hw, TCTL, reg_data); | |
1791 | ||
1792 | /* Configure Gigabit Carry Extend Padding */ | |
1793 | reg_data = E1000_READ_REG(hw, TCTL_EXT); | |
1794 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
1795 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; | |
1796 | E1000_WRITE_REG(hw, TCTL_EXT, reg_data); | |
1797 | ||
1798 | /* Configure Transmit Inter-Packet Gap */ | |
1799 | reg_data = E1000_READ_REG(hw, TIPG); | |
1800 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
1801 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
1802 | E1000_WRITE_REG(hw, TIPG, reg_data); | |
1803 | ||
1804 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); | |
1805 | reg_data &= ~0x00100000; | |
1806 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); | |
1807 | /* Fall through */ | |
1808 | case e1000_82571: | |
1809 | case e1000_82572: | |
1810 | case e1000_ich8lan: | |
1811 | ctrl = E1000_READ_REG(hw, TXDCTL1); | |
1812 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | |
1813 | | E1000_TXDCTL_FULL_TX_DESC_WB; | |
1814 | E1000_WRITE_REG(hw, TXDCTL1, ctrl); | |
1815 | break; | |
2c2668f9 RZ |
1816 | case e1000_82573: |
1817 | case e1000_82574: | |
1818 | reg_data = E1000_READ_REG(hw, GCR); | |
1819 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
1820 | E1000_WRITE_REG(hw, GCR, reg_data); | |
95186063 MV |
1821 | case e1000_igb: |
1822 | break; | |
aa070789 RZ |
1823 | } |
1824 | ||
aa070789 RZ |
1825 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
1826 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { | |
1827 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
1828 | /* Relaxed ordering must be disabled to avoid a parity | |
1829 | * error crash in a PCI slot. */ | |
1830 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
1831 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
1832 | } | |
1833 | ||
682011ff WD |
1834 | return ret_val; |
1835 | } | |
1836 | ||
1837 | /****************************************************************************** | |
1838 | * Configures flow control and link settings. | |
8bde7f77 | 1839 | * |
682011ff | 1840 | * hw - Struct containing variables accessed by shared code |
8bde7f77 | 1841 | * |
682011ff WD |
1842 | * Determines which flow control settings to use. Calls the apropriate media- |
1843 | * specific link configuration function. Configures the flow control settings. | |
1844 | * Assuming the adapter has a valid link partner, a valid link should be | |
8bde7f77 | 1845 | * established. Assumes the hardware has previously been reset and the |
682011ff WD |
1846 | * transmitter and receiver are not enabled. |
1847 | *****************************************************************************/ | |
1848 | static int | |
5c5e707a | 1849 | e1000_setup_link(struct e1000_hw *hw) |
682011ff | 1850 | { |
682011ff | 1851 | int32_t ret_val; |
8712adfd RI |
1852 | #ifndef CONFIG_E1000_NO_NVM |
1853 | uint32_t ctrl_ext; | |
682011ff | 1854 | uint16_t eeprom_data; |
8712adfd | 1855 | #endif |
682011ff WD |
1856 | |
1857 | DEBUGFUNC(); | |
1858 | ||
aa070789 RZ |
1859 | /* In the case of the phy reset being blocked, we already have a link. |
1860 | * We do not have to set it up again. */ | |
1861 | if (e1000_check_phy_reset_block(hw)) | |
1862 | return E1000_SUCCESS; | |
1863 | ||
8712adfd | 1864 | #ifndef CONFIG_E1000_NO_NVM |
682011ff WD |
1865 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
1866 | * that determine the hardware's default PAUSE (flow control) mode, | |
1867 | * a bit that determines whether the HW defaults to enabling or | |
1868 | * disabling auto-negotiation, and the direction of the | |
1869 | * SW defined pins. If there is no SW over-ride of the flow | |
1870 | * control setting, then the variable hw->fc will | |
1871 | * be initialized based on a value in the EEPROM. | |
1872 | */ | |
aa070789 RZ |
1873 | if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, |
1874 | &eeprom_data) < 0) { | |
682011ff WD |
1875 | DEBUGOUT("EEPROM Read Error\n"); |
1876 | return -E1000_ERR_EEPROM; | |
1877 | } | |
8712adfd | 1878 | #endif |
682011ff | 1879 | if (hw->fc == e1000_fc_default) { |
aa070789 RZ |
1880 | switch (hw->mac_type) { |
1881 | case e1000_ich8lan: | |
1882 | case e1000_82573: | |
2c2668f9 | 1883 | case e1000_82574: |
95186063 | 1884 | case e1000_igb: |
682011ff | 1885 | hw->fc = e1000_fc_full; |
aa070789 RZ |
1886 | break; |
1887 | default: | |
8712adfd | 1888 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
1889 | ret_val = e1000_read_eeprom(hw, |
1890 | EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); | |
1891 | if (ret_val) { | |
1892 | DEBUGOUT("EEPROM Read Error\n"); | |
1893 | return -E1000_ERR_EEPROM; | |
1894 | } | |
aa070789 RZ |
1895 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
1896 | hw->fc = e1000_fc_none; | |
1897 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == | |
1898 | EEPROM_WORD0F_ASM_DIR) | |
1899 | hw->fc = e1000_fc_tx_pause; | |
1900 | else | |
8712adfd | 1901 | #endif |
aa070789 RZ |
1902 | hw->fc = e1000_fc_full; |
1903 | break; | |
1904 | } | |
682011ff WD |
1905 | } |
1906 | ||
1907 | /* We want to save off the original Flow Control configuration just | |
1908 | * in case we get disconnected and then reconnected into a different | |
1909 | * hub or switch with different Flow Control capabilities. | |
1910 | */ | |
1911 | if (hw->mac_type == e1000_82542_rev2_0) | |
1912 | hw->fc &= (~e1000_fc_tx_pause); | |
1913 | ||
1914 | if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) | |
1915 | hw->fc &= (~e1000_fc_rx_pause); | |
1916 | ||
1917 | hw->original_fc = hw->fc; | |
1918 | ||
1919 | DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); | |
1920 | ||
8712adfd | 1921 | #ifndef CONFIG_E1000_NO_NVM |
682011ff WD |
1922 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
1923 | * polarity value for the SW controlled pins, and setup the | |
1924 | * Extended Device Control reg with that info. | |
1925 | * This is needed because one of the SW controlled pins is used for | |
1926 | * signal detection. So this should be done before e1000_setup_pcs_link() | |
1927 | * or e1000_phy_setup() is called. | |
1928 | */ | |
1929 | if (hw->mac_type == e1000_82543) { | |
1930 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << | |
1931 | SWDPIO__EXT_SHIFT); | |
1932 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
1933 | } | |
8712adfd | 1934 | #endif |
682011ff WD |
1935 | |
1936 | /* Call the necessary subroutine to configure the link. */ | |
1937 | ret_val = (hw->media_type == e1000_media_type_fiber) ? | |
5c5e707a | 1938 | e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); |
682011ff WD |
1939 | if (ret_val < 0) { |
1940 | return ret_val; | |
1941 | } | |
1942 | ||
1943 | /* Initialize the flow control address, type, and PAUSE timer | |
1944 | * registers to their default values. This is done even if flow | |
1945 | * control is disabled, because it does not hurt anything to | |
1946 | * initialize these registers. | |
1947 | */ | |
aa070789 RZ |
1948 | DEBUGOUT("Initializing the Flow Control address, type" |
1949 | "and timer regs\n"); | |
1950 | ||
1951 | /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ | |
1952 | if (hw->mac_type != e1000_ich8lan) { | |
1953 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); | |
1954 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); | |
1955 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); | |
1956 | } | |
682011ff | 1957 | |
682011ff WD |
1958 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
1959 | ||
1960 | /* Set the flow control receive threshold registers. Normally, | |
1961 | * these registers will be set to a default threshold that may be | |
1962 | * adjusted later by the driver's runtime code. However, if the | |
1963 | * ability to transmit pause frames in not enabled, then these | |
8bde7f77 | 1964 | * registers will be set to 0. |
682011ff WD |
1965 | */ |
1966 | if (!(hw->fc & e1000_fc_tx_pause)) { | |
1967 | E1000_WRITE_REG(hw, FCRTL, 0); | |
1968 | E1000_WRITE_REG(hw, FCRTH, 0); | |
1969 | } else { | |
1970 | /* We need to set up the Receive Threshold high and low water marks | |
1971 | * as well as (optionally) enabling the transmission of XON frames. | |
1972 | */ | |
1973 | if (hw->fc_send_xon) { | |
1974 | E1000_WRITE_REG(hw, FCRTL, | |
1975 | (hw->fc_low_water | E1000_FCRTL_XONE)); | |
1976 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
1977 | } else { | |
1978 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); | |
1979 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
1980 | } | |
1981 | } | |
1982 | return ret_val; | |
1983 | } | |
1984 | ||
1985 | /****************************************************************************** | |
1986 | * Sets up link for a fiber based adapter | |
1987 | * | |
1988 | * hw - Struct containing variables accessed by shared code | |
1989 | * | |
1990 | * Manipulates Physical Coding Sublayer functions in order to configure | |
1991 | * link. Assumes the hardware has been previously reset and the transmitter | |
1992 | * and receiver are not enabled. | |
1993 | *****************************************************************************/ | |
1994 | static int | |
5c5e707a | 1995 | e1000_setup_fiber_link(struct e1000_hw *hw) |
682011ff | 1996 | { |
682011ff WD |
1997 | uint32_t ctrl; |
1998 | uint32_t status; | |
1999 | uint32_t txcw = 0; | |
2000 | uint32_t i; | |
2001 | uint32_t signal; | |
2002 | int32_t ret_val; | |
2003 | ||
2004 | DEBUGFUNC(); | |
8bde7f77 WD |
2005 | /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be |
2006 | * set when the optics detect a signal. On older adapters, it will be | |
682011ff WD |
2007 | * cleared when there is a signal |
2008 | */ | |
2009 | ctrl = E1000_READ_REG(hw, CTRL); | |
2010 | if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) | |
2011 | signal = E1000_CTRL_SWDPIN1; | |
2012 | else | |
2013 | signal = 0; | |
2014 | ||
5c5e707a | 2015 | printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, |
682011ff WD |
2016 | ctrl); |
2017 | /* Take the link out of reset */ | |
2018 | ctrl &= ~(E1000_CTRL_LRST); | |
2019 | ||
2020 | e1000_config_collision_dist(hw); | |
2021 | ||
2022 | /* Check for a software override of the flow control settings, and setup | |
2023 | * the device accordingly. If auto-negotiation is enabled, then software | |
2024 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit | |
2025 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if | |
8bde7f77 | 2026 | * auto-negotiation is disabled, then software will have to manually |
682011ff WD |
2027 | * configure the two flow control enable bits in the CTRL register. |
2028 | * | |
2029 | * The possible values of the "fc" parameter are: | |
1aeed8d7 WD |
2030 | * 0: Flow control is completely disabled |
2031 | * 1: Rx flow control is enabled (we can receive pause frames, but | |
2032 | * not send pause frames). | |
2033 | * 2: Tx flow control is enabled (we can send pause frames but we do | |
2034 | * not support receiving pause frames). | |
2035 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
682011ff WD |
2036 | */ |
2037 | switch (hw->fc) { | |
2038 | case e1000_fc_none: | |
2039 | /* Flow control is completely disabled by a software over-ride. */ | |
2040 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); | |
2041 | break; | |
2042 | case e1000_fc_rx_pause: | |
8bde7f77 WD |
2043 | /* RX Flow control is enabled and TX Flow control is disabled by a |
2044 | * software over-ride. Since there really isn't a way to advertise | |
682011ff WD |
2045 | * that we are capable of RX Pause ONLY, we will advertise that we |
2046 | * support both symmetric and asymmetric RX PAUSE. Later, we will | |
2047 | * disable the adapter's ability to send PAUSE frames. | |
2048 | */ | |
2049 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
2050 | break; | |
2051 | case e1000_fc_tx_pause: | |
8bde7f77 | 2052 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
682011ff WD |
2053 | * software over-ride. |
2054 | */ | |
2055 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); | |
2056 | break; | |
2057 | case e1000_fc_full: | |
2058 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ | |
2059 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
2060 | break; | |
2061 | default: | |
2062 | DEBUGOUT("Flow control param set incorrectly\n"); | |
2063 | return -E1000_ERR_CONFIG; | |
2064 | break; | |
2065 | } | |
2066 | ||
2067 | /* Since auto-negotiation is enabled, take the link out of reset (the link | |
2068 | * will be in reset, because we previously reset the chip). This will | |
2069 | * restart auto-negotiation. If auto-neogtiation is successful then the | |
2070 | * link-up status bit will be set and the flow control enable bits (RFCE | |
2071 | * and TFCE) will be set according to their negotiated value. | |
2072 | */ | |
2073 | DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); | |
2074 | ||
2075 | E1000_WRITE_REG(hw, TXCW, txcw); | |
2076 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2077 | E1000_WRITE_FLUSH(hw); | |
2078 | ||
2079 | hw->txcw = txcw; | |
2080 | mdelay(1); | |
2081 | ||
2082 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | |
8bde7f77 WD |
2083 | * indication in the Device Status Register. Time-out if a link isn't |
2084 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in | |
682011ff WD |
2085 | * less than 500 milliseconds even if the other end is doing it in SW). |
2086 | */ | |
2087 | if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { | |
2088 | DEBUGOUT("Looking for Link\n"); | |
2089 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { | |
2090 | mdelay(10); | |
2091 | status = E1000_READ_REG(hw, STATUS); | |
2092 | if (status & E1000_STATUS_LU) | |
2093 | break; | |
2094 | } | |
2095 | if (i == (LINK_UP_TIMEOUT / 10)) { | |
8bde7f77 | 2096 | /* AutoNeg failed to achieve a link, so we'll call |
682011ff WD |
2097 | * e1000_check_for_link. This routine will force the link up if we |
2098 | * detect a signal. This will allow us to communicate with | |
2099 | * non-autonegotiating link partners. | |
2100 | */ | |
2101 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); | |
2102 | hw->autoneg_failed = 1; | |
5c5e707a | 2103 | ret_val = e1000_check_for_link(hw); |
682011ff WD |
2104 | if (ret_val < 0) { |
2105 | DEBUGOUT("Error while checking for link\n"); | |
2106 | return ret_val; | |
2107 | } | |
2108 | hw->autoneg_failed = 0; | |
2109 | } else { | |
2110 | hw->autoneg_failed = 0; | |
2111 | DEBUGOUT("Valid Link Found\n"); | |
2112 | } | |
aa070789 RZ |
2113 | } else { |
2114 | DEBUGOUT("No Signal Detected\n"); | |
2115 | return -E1000_ERR_NOLINK; | |
2116 | } | |
2117 | return 0; | |
2118 | } | |
2119 | ||
aa070789 RZ |
2120 | /****************************************************************************** |
2121 | * Make sure we have a valid PHY and change PHY mode before link setup. | |
2122 | * | |
2123 | * hw - Struct containing variables accessed by shared code | |
2124 | ******************************************************************************/ | |
2125 | static int32_t | |
2126 | e1000_copper_link_preconfig(struct e1000_hw *hw) | |
2127 | { | |
2128 | uint32_t ctrl; | |
2129 | int32_t ret_val; | |
2130 | uint16_t phy_data; | |
2131 | ||
2132 | DEBUGFUNC(); | |
2133 | ||
2134 | ctrl = E1000_READ_REG(hw, CTRL); | |
2135 | /* With 82543, we need to force speed and duplex on the MAC equal to what | |
2136 | * the PHY speed and duplex configuration is. In addition, we need to | |
2137 | * perform a hardware reset on the PHY to take it out of reset. | |
2138 | */ | |
2139 | if (hw->mac_type > e1000_82543) { | |
2140 | ctrl |= E1000_CTRL_SLU; | |
2141 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2142 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2143 | } else { | |
2144 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | |
2145 | | E1000_CTRL_SLU); | |
2146 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2147 | ret_val = e1000_phy_hw_reset(hw); | |
2148 | if (ret_val) | |
2149 | return ret_val; | |
2150 | } | |
2151 | ||
2152 | /* Make sure we have a valid PHY */ | |
2153 | ret_val = e1000_detect_gig_phy(hw); | |
2154 | if (ret_val) { | |
2155 | DEBUGOUT("Error, did not detect valid phy.\n"); | |
2156 | return ret_val; | |
2157 | } | |
5abf13e4 | 2158 | DEBUGOUT("Phy ID = %x\n", hw->phy_id); |
aa070789 | 2159 | |
aa070789 RZ |
2160 | /* Set PHY to class A mode (if necessary) */ |
2161 | ret_val = e1000_set_phy_mode(hw); | |
2162 | if (ret_val) | |
2163 | return ret_val; | |
aa070789 RZ |
2164 | if ((hw->mac_type == e1000_82545_rev_3) || |
2165 | (hw->mac_type == e1000_82546_rev_3)) { | |
2166 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, | |
2167 | &phy_data); | |
2168 | phy_data |= 0x00000008; | |
2169 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, | |
2170 | phy_data); | |
2171 | } | |
2172 | ||
2173 | if (hw->mac_type <= e1000_82543 || | |
2174 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || | |
2175 | hw->mac_type == e1000_82541_rev_2 | |
2176 | || hw->mac_type == e1000_82547_rev_2) | |
472d5460 | 2177 | hw->phy_reset_disable = false; |
aa070789 RZ |
2178 | |
2179 | return E1000_SUCCESS; | |
2180 | } | |
2181 | ||
2182 | /***************************************************************************** | |
2183 | * | |
2184 | * This function sets the lplu state according to the active flag. When | |
2185 | * activating lplu this function also disables smart speed and vise versa. | |
2186 | * lplu will not be activated unless the device autonegotiation advertisment | |
2187 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
2188 | * hw: Struct containing variables accessed by shared code | |
2189 | * active - true to enable lplu false to disable lplu. | |
2190 | * | |
2191 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
2192 | * E1000_SUCCESS at any other case. | |
2193 | * | |
2194 | ****************************************************************************/ | |
2195 | ||
2196 | static int32_t | |
472d5460 | 2197 | e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
aa070789 RZ |
2198 | { |
2199 | uint32_t phy_ctrl = 0; | |
2200 | int32_t ret_val; | |
2201 | uint16_t phy_data; | |
2202 | DEBUGFUNC(); | |
2203 | ||
2204 | if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 | |
2205 | && hw->phy_type != e1000_phy_igp_3) | |
2206 | return E1000_SUCCESS; | |
2207 | ||
2208 | /* During driver activity LPLU should not be used or it will attain link | |
2209 | * from the lowest speeds starting from 10Mbps. The capability is used | |
2210 | * for Dx transitions and states */ | |
2211 | if (hw->mac_type == e1000_82541_rev_2 | |
2212 | || hw->mac_type == e1000_82547_rev_2) { | |
2213 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
2214 | &phy_data); | |
2215 | if (ret_val) | |
2216 | return ret_val; | |
2217 | } else if (hw->mac_type == e1000_ich8lan) { | |
2218 | /* MAC writes into PHY register based on the state transition | |
2219 | * and start auto-negotiation. SW driver can overwrite the | |
2220 | * settings in CSR PHY power control E1000_PHY_CTRL register. */ | |
2221 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); | |
2222 | } else { | |
2223 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
2224 | &phy_data); | |
2225 | if (ret_val) | |
2226 | return ret_val; | |
2227 | } | |
2228 | ||
2229 | if (!active) { | |
2230 | if (hw->mac_type == e1000_82541_rev_2 || | |
2231 | hw->mac_type == e1000_82547_rev_2) { | |
2232 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; | |
2233 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
2234 | phy_data); | |
2235 | if (ret_val) | |
2236 | return ret_val; | |
2237 | } else { | |
2238 | if (hw->mac_type == e1000_ich8lan) { | |
2239 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
2240 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
2241 | } else { | |
2242 | phy_data &= ~IGP02E1000_PM_D3_LPLU; | |
2243 | ret_val = e1000_write_phy_reg(hw, | |
2244 | IGP02E1000_PHY_POWER_MGMT, phy_data); | |
2245 | if (ret_val) | |
2246 | return ret_val; | |
2247 | } | |
2248 | } | |
2249 | ||
2250 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
2251 | * Dx states where the power conservation is most important. During | |
2252 | * driver activity we should enable SmartSpeed, so performance is | |
2253 | * maintained. */ | |
2254 | if (hw->smart_speed == e1000_smart_speed_on) { | |
2255 | ret_val = e1000_read_phy_reg(hw, | |
2256 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2257 | if (ret_val) | |
2258 | return ret_val; | |
2259 | ||
2260 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
2261 | ret_val = e1000_write_phy_reg(hw, | |
2262 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2263 | if (ret_val) | |
2264 | return ret_val; | |
2265 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
2266 | ret_val = e1000_read_phy_reg(hw, | |
2267 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2268 | if (ret_val) | |
2269 | return ret_val; | |
2270 | ||
2271 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2272 | ret_val = e1000_write_phy_reg(hw, | |
2273 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2274 | if (ret_val) | |
2275 | return ret_val; | |
2276 | } | |
2277 | ||
2278 | } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) | |
2279 | || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || | |
2280 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { | |
2281 | ||
2282 | if (hw->mac_type == e1000_82541_rev_2 || | |
2283 | hw->mac_type == e1000_82547_rev_2) { | |
2284 | phy_data |= IGP01E1000_GMII_FLEX_SPD; | |
2285 | ret_val = e1000_write_phy_reg(hw, | |
2286 | IGP01E1000_GMII_FIFO, phy_data); | |
2287 | if (ret_val) | |
2288 | return ret_val; | |
2289 | } else { | |
2290 | if (hw->mac_type == e1000_ich8lan) { | |
2291 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
2292 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
2293 | } else { | |
2294 | phy_data |= IGP02E1000_PM_D3_LPLU; | |
2295 | ret_val = e1000_write_phy_reg(hw, | |
2296 | IGP02E1000_PHY_POWER_MGMT, phy_data); | |
2297 | if (ret_val) | |
2298 | return ret_val; | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | /* When LPLU is enabled we should disable SmartSpeed */ | |
2303 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2304 | &phy_data); | |
2305 | if (ret_val) | |
2306 | return ret_val; | |
2307 | ||
2308 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2309 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2310 | phy_data); | |
2311 | if (ret_val) | |
2312 | return ret_val; | |
2313 | } | |
2314 | return E1000_SUCCESS; | |
2315 | } | |
2316 | ||
2317 | /***************************************************************************** | |
2318 | * | |
2319 | * This function sets the lplu d0 state according to the active flag. When | |
2320 | * activating lplu this function also disables smart speed and vise versa. | |
2321 | * lplu will not be activated unless the device autonegotiation advertisment | |
2322 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
2323 | * hw: Struct containing variables accessed by shared code | |
2324 | * active - true to enable lplu false to disable lplu. | |
2325 | * | |
2326 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
2327 | * E1000_SUCCESS at any other case. | |
2328 | * | |
2329 | ****************************************************************************/ | |
2330 | ||
2331 | static int32_t | |
472d5460 | 2332 | e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
aa070789 RZ |
2333 | { |
2334 | uint32_t phy_ctrl = 0; | |
2335 | int32_t ret_val; | |
2336 | uint16_t phy_data; | |
2337 | DEBUGFUNC(); | |
2338 | ||
2339 | if (hw->mac_type <= e1000_82547_rev_2) | |
2340 | return E1000_SUCCESS; | |
2341 | ||
2342 | if (hw->mac_type == e1000_ich8lan) { | |
2343 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); | |
95186063 MV |
2344 | } else if (hw->mac_type == e1000_igb) { |
2345 | phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); | |
aa070789 RZ |
2346 | } else { |
2347 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
2348 | &phy_data); | |
2349 | if (ret_val) | |
2350 | return ret_val; | |
2351 | } | |
2352 | ||
2353 | if (!active) { | |
2354 | if (hw->mac_type == e1000_ich8lan) { | |
2355 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
2356 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
95186063 MV |
2357 | } else if (hw->mac_type == e1000_igb) { |
2358 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
2359 | E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); | |
aa070789 RZ |
2360 | } else { |
2361 | phy_data &= ~IGP02E1000_PM_D0_LPLU; | |
2362 | ret_val = e1000_write_phy_reg(hw, | |
2363 | IGP02E1000_PHY_POWER_MGMT, phy_data); | |
2364 | if (ret_val) | |
2365 | return ret_val; | |
2366 | } | |
2367 | ||
95186063 MV |
2368 | if (hw->mac_type == e1000_igb) |
2369 | return E1000_SUCCESS; | |
2370 | ||
aa070789 RZ |
2371 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
2372 | * Dx states where the power conservation is most important. During | |
2373 | * driver activity we should enable SmartSpeed, so performance is | |
2374 | * maintained. */ | |
2375 | if (hw->smart_speed == e1000_smart_speed_on) { | |
2376 | ret_val = e1000_read_phy_reg(hw, | |
2377 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2378 | if (ret_val) | |
2379 | return ret_val; | |
2380 | ||
2381 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
2382 | ret_val = e1000_write_phy_reg(hw, | |
2383 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2384 | if (ret_val) | |
2385 | return ret_val; | |
2386 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
2387 | ret_val = e1000_read_phy_reg(hw, | |
2388 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2389 | if (ret_val) | |
2390 | return ret_val; | |
2391 | ||
2392 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2393 | ret_val = e1000_write_phy_reg(hw, | |
2394 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2395 | if (ret_val) | |
2396 | return ret_val; | |
2397 | } | |
2398 | ||
2399 | ||
2400 | } else { | |
2401 | ||
2402 | if (hw->mac_type == e1000_ich8lan) { | |
2403 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
2404 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
95186063 MV |
2405 | } else if (hw->mac_type == e1000_igb) { |
2406 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
2407 | E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); | |
aa070789 RZ |
2408 | } else { |
2409 | phy_data |= IGP02E1000_PM_D0_LPLU; | |
2410 | ret_val = e1000_write_phy_reg(hw, | |
2411 | IGP02E1000_PHY_POWER_MGMT, phy_data); | |
2412 | if (ret_val) | |
2413 | return ret_val; | |
2414 | } | |
2415 | ||
95186063 MV |
2416 | if (hw->mac_type == e1000_igb) |
2417 | return E1000_SUCCESS; | |
2418 | ||
aa070789 RZ |
2419 | /* When LPLU is enabled we should disable SmartSpeed */ |
2420 | ret_val = e1000_read_phy_reg(hw, | |
2421 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2422 | if (ret_val) | |
2423 | return ret_val; | |
2424 | ||
2425 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2426 | ret_val = e1000_write_phy_reg(hw, | |
2427 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2428 | if (ret_val) | |
2429 | return ret_val; | |
2430 | ||
2431 | } | |
2432 | return E1000_SUCCESS; | |
2433 | } | |
2434 | ||
2435 | /******************************************************************** | |
2436 | * Copper link setup for e1000_phy_igp series. | |
2437 | * | |
2438 | * hw - Struct containing variables accessed by shared code | |
2439 | *********************************************************************/ | |
2440 | static int32_t | |
2441 | e1000_copper_link_igp_setup(struct e1000_hw *hw) | |
2442 | { | |
2443 | uint32_t led_ctrl; | |
2444 | int32_t ret_val; | |
2445 | uint16_t phy_data; | |
2446 | ||
f81ecb5d | 2447 | DEBUGFUNC(); |
aa070789 RZ |
2448 | |
2449 | if (hw->phy_reset_disable) | |
2450 | return E1000_SUCCESS; | |
2451 | ||
2452 | ret_val = e1000_phy_reset(hw); | |
2453 | if (ret_val) { | |
2454 | DEBUGOUT("Error Resetting the PHY\n"); | |
2455 | return ret_val; | |
2456 | } | |
2457 | ||
2458 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ | |
2459 | mdelay(15); | |
2460 | if (hw->mac_type != e1000_ich8lan) { | |
2461 | /* Configure activity LED after PHY reset */ | |
2462 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
2463 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
2464 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
2465 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
2466 | } | |
2467 | ||
2468 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ | |
2469 | if (hw->phy_type == e1000_phy_igp) { | |
2470 | /* disable lplu d3 during driver init */ | |
472d5460 | 2471 | ret_val = e1000_set_d3_lplu_state(hw, false); |
aa070789 RZ |
2472 | if (ret_val) { |
2473 | DEBUGOUT("Error Disabling LPLU D3\n"); | |
2474 | return ret_val; | |
2475 | } | |
2476 | } | |
2477 | ||
2478 | /* disable lplu d0 during driver init */ | |
472d5460 | 2479 | ret_val = e1000_set_d0_lplu_state(hw, false); |
aa070789 RZ |
2480 | if (ret_val) { |
2481 | DEBUGOUT("Error Disabling LPLU D0\n"); | |
2482 | return ret_val; | |
2483 | } | |
2484 | /* Configure mdi-mdix settings */ | |
2485 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
2486 | if (ret_val) | |
2487 | return ret_val; | |
2488 | ||
2489 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
2490 | hw->dsp_config_state = e1000_dsp_config_disabled; | |
2491 | /* Force MDI for earlier revs of the IGP PHY */ | |
2492 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | |
2493 | | IGP01E1000_PSCR_FORCE_MDI_MDIX); | |
2494 | hw->mdix = 1; | |
2495 | ||
2496 | } else { | |
2497 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
2498 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
2499 | ||
2500 | switch (hw->mdix) { | |
2501 | case 1: | |
2502 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
2503 | break; | |
2504 | case 2: | |
2505 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
2506 | break; | |
2507 | case 0: | |
2508 | default: | |
2509 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | |
2510 | break; | |
2511 | } | |
2512 | } | |
2513 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
2514 | if (ret_val) | |
2515 | return ret_val; | |
2516 | ||
2517 | /* set auto-master slave resolution settings */ | |
2518 | if (hw->autoneg) { | |
2519 | e1000_ms_type phy_ms_setting = hw->master_slave; | |
2520 | ||
2521 | if (hw->ffe_config_state == e1000_ffe_config_active) | |
2522 | hw->ffe_config_state = e1000_ffe_config_enabled; | |
2523 | ||
2524 | if (hw->dsp_config_state == e1000_dsp_config_activated) | |
2525 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
2526 | ||
2527 | /* when autonegotiation advertisment is only 1000Mbps then we | |
2528 | * should disable SmartSpeed and enable Auto MasterSlave | |
2529 | * resolution as hardware default. */ | |
2530 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { | |
2531 | /* Disable SmartSpeed */ | |
2532 | ret_val = e1000_read_phy_reg(hw, | |
2533 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2534 | if (ret_val) | |
2535 | return ret_val; | |
2536 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2537 | ret_val = e1000_write_phy_reg(hw, | |
2538 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2539 | if (ret_val) | |
2540 | return ret_val; | |
2541 | /* Set auto Master/Slave resolution process */ | |
2542 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, | |
2543 | &phy_data); | |
2544 | if (ret_val) | |
2545 | return ret_val; | |
2546 | phy_data &= ~CR_1000T_MS_ENABLE; | |
2547 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, | |
2548 | phy_data); | |
2549 | if (ret_val) | |
2550 | return ret_val; | |
2551 | } | |
2552 | ||
2553 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | |
2554 | if (ret_val) | |
2555 | return ret_val; | |
2556 | ||
2557 | /* load defaults for future use */ | |
2558 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? | |
2559 | ((phy_data & CR_1000T_MS_VALUE) ? | |
2560 | e1000_ms_force_master : | |
2561 | e1000_ms_force_slave) : | |
2562 | e1000_ms_auto; | |
2563 | ||
2564 | switch (phy_ms_setting) { | |
2565 | case e1000_ms_force_master: | |
2566 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
2567 | break; | |
2568 | case e1000_ms_force_slave: | |
2569 | phy_data |= CR_1000T_MS_ENABLE; | |
2570 | phy_data &= ~(CR_1000T_MS_VALUE); | |
2571 | break; | |
2572 | case e1000_ms_auto: | |
2573 | phy_data &= ~CR_1000T_MS_ENABLE; | |
2574 | default: | |
2575 | break; | |
2576 | } | |
2577 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
2578 | if (ret_val) | |
2579 | return ret_val; | |
2580 | } | |
2581 | ||
2582 | return E1000_SUCCESS; | |
2583 | } | |
2584 | ||
2585 | /***************************************************************************** | |
2586 | * This function checks the mode of the firmware. | |
2587 | * | |
472d5460 | 2588 | * returns - true when the mode is IAMT or false. |
aa070789 | 2589 | ****************************************************************************/ |
472d5460 | 2590 | bool |
aa070789 RZ |
2591 | e1000_check_mng_mode(struct e1000_hw *hw) |
2592 | { | |
2593 | uint32_t fwsm; | |
2594 | DEBUGFUNC(); | |
2595 | ||
2596 | fwsm = E1000_READ_REG(hw, FWSM); | |
2597 | ||
2598 | if (hw->mac_type == e1000_ich8lan) { | |
2599 | if ((fwsm & E1000_FWSM_MODE_MASK) == | |
2600 | (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
472d5460 | 2601 | return true; |
aa070789 RZ |
2602 | } else if ((fwsm & E1000_FWSM_MODE_MASK) == |
2603 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
472d5460 | 2604 | return true; |
aa070789 | 2605 | |
472d5460 | 2606 | return false; |
aa070789 RZ |
2607 | } |
2608 | ||
2609 | static int32_t | |
2610 | e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) | |
2611 | { | |
987b43a1 | 2612 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
aa070789 | 2613 | uint32_t reg_val; |
aa070789 RZ |
2614 | DEBUGFUNC(); |
2615 | ||
987b43a1 | 2616 | if (e1000_is_second_port(hw)) |
aa070789 | 2617 | swfw = E1000_SWFW_PHY1_SM; |
987b43a1 | 2618 | |
aa070789 RZ |
2619 | if (e1000_swfw_sync_acquire(hw, swfw)) |
2620 | return -E1000_ERR_SWFW_SYNC; | |
2621 | ||
2622 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) | |
2623 | & E1000_KUMCTRLSTA_OFFSET) | data; | |
2624 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); | |
2625 | udelay(2); | |
2626 | ||
2627 | return E1000_SUCCESS; | |
2628 | } | |
2629 | ||
2630 | static int32_t | |
2631 | e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) | |
2632 | { | |
987b43a1 | 2633 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
aa070789 | 2634 | uint32_t reg_val; |
aa070789 RZ |
2635 | DEBUGFUNC(); |
2636 | ||
987b43a1 | 2637 | if (e1000_is_second_port(hw)) |
aa070789 | 2638 | swfw = E1000_SWFW_PHY1_SM; |
987b43a1 | 2639 | |
95186063 MV |
2640 | if (e1000_swfw_sync_acquire(hw, swfw)) { |
2641 | debug("%s[%i]\n", __func__, __LINE__); | |
aa070789 | 2642 | return -E1000_ERR_SWFW_SYNC; |
95186063 | 2643 | } |
aa070789 RZ |
2644 | |
2645 | /* Write register address */ | |
2646 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | |
2647 | E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; | |
2648 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); | |
2649 | udelay(2); | |
2650 | ||
2651 | /* Read the data returned */ | |
2652 | reg_val = E1000_READ_REG(hw, KUMCTRLSTA); | |
2653 | *data = (uint16_t)reg_val; | |
2654 | ||
2655 | return E1000_SUCCESS; | |
2656 | } | |
2657 | ||
2658 | /******************************************************************** | |
2659 | * Copper link setup for e1000_phy_gg82563 series. | |
2660 | * | |
2661 | * hw - Struct containing variables accessed by shared code | |
2662 | *********************************************************************/ | |
2663 | static int32_t | |
2664 | e1000_copper_link_ggp_setup(struct e1000_hw *hw) | |
2665 | { | |
2666 | int32_t ret_val; | |
2667 | uint16_t phy_data; | |
2668 | uint32_t reg_data; | |
2669 | ||
2670 | DEBUGFUNC(); | |
2671 | ||
2672 | if (!hw->phy_reset_disable) { | |
2673 | /* Enable CRS on TX for half-duplex operation. */ | |
2674 | ret_val = e1000_read_phy_reg(hw, | |
2675 | GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
2676 | if (ret_val) | |
2677 | return ret_val; | |
2678 | ||
2679 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
2680 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ | |
2681 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; | |
2682 | ||
2683 | ret_val = e1000_write_phy_reg(hw, | |
2684 | GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
2685 | if (ret_val) | |
2686 | return ret_val; | |
2687 | ||
2688 | /* Options: | |
2689 | * MDI/MDI-X = 0 (default) | |
2690 | * 0 - Auto for all speeds | |
2691 | * 1 - MDI mode | |
2692 | * 2 - MDI-X mode | |
2693 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
2694 | */ | |
2695 | ret_val = e1000_read_phy_reg(hw, | |
2696 | GG82563_PHY_SPEC_CTRL, &phy_data); | |
2697 | if (ret_val) | |
2698 | return ret_val; | |
2699 | ||
2700 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
2701 | ||
2702 | switch (hw->mdix) { | |
2703 | case 1: | |
2704 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
2705 | break; | |
2706 | case 2: | |
2707 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
2708 | break; | |
2709 | case 0: | |
2710 | default: | |
2711 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
2712 | break; | |
2713 | } | |
2714 | ||
2715 | /* Options: | |
2716 | * disable_polarity_correction = 0 (default) | |
2717 | * Automatic Correction for Reversed Cable Polarity | |
2718 | * 0 - Disabled | |
2719 | * 1 - Enabled | |
2720 | */ | |
2721 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
2722 | ret_val = e1000_write_phy_reg(hw, | |
2723 | GG82563_PHY_SPEC_CTRL, phy_data); | |
2724 | ||
2725 | if (ret_val) | |
2726 | return ret_val; | |
2727 | ||
2728 | /* SW Reset the PHY so all changes take effect */ | |
2729 | ret_val = e1000_phy_reset(hw); | |
2730 | if (ret_val) { | |
2731 | DEBUGOUT("Error Resetting the PHY\n"); | |
2732 | return ret_val; | |
2733 | } | |
2734 | } /* phy_reset_disable */ | |
2735 | ||
2736 | if (hw->mac_type == e1000_80003es2lan) { | |
2737 | /* Bypass RX and TX FIFO's */ | |
2738 | ret_val = e1000_write_kmrn_reg(hw, | |
2739 | E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, | |
2740 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | |
2741 | | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); | |
2742 | if (ret_val) | |
2743 | return ret_val; | |
2744 | ||
2745 | ret_val = e1000_read_phy_reg(hw, | |
2746 | GG82563_PHY_SPEC_CTRL_2, &phy_data); | |
2747 | if (ret_val) | |
2748 | return ret_val; | |
2749 | ||
2750 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
2751 | ret_val = e1000_write_phy_reg(hw, | |
2752 | GG82563_PHY_SPEC_CTRL_2, phy_data); | |
2753 | ||
2754 | if (ret_val) | |
2755 | return ret_val; | |
2756 | ||
2757 | reg_data = E1000_READ_REG(hw, CTRL_EXT); | |
2758 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
2759 | E1000_WRITE_REG(hw, CTRL_EXT, reg_data); | |
2760 | ||
2761 | ret_val = e1000_read_phy_reg(hw, | |
2762 | GG82563_PHY_PWR_MGMT_CTRL, &phy_data); | |
2763 | if (ret_val) | |
2764 | return ret_val; | |
2765 | ||
2766 | /* Do not init these registers when the HW is in IAMT mode, since the | |
2767 | * firmware will have already initialized them. We only initialize | |
2768 | * them if the HW is not in IAMT mode. | |
2769 | */ | |
472d5460 | 2770 | if (e1000_check_mng_mode(hw) == false) { |
aa070789 RZ |
2771 | /* Enable Electrical Idle on the PHY */ |
2772 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
2773 | ret_val = e1000_write_phy_reg(hw, | |
2774 | GG82563_PHY_PWR_MGMT_CTRL, phy_data); | |
2775 | if (ret_val) | |
2776 | return ret_val; | |
2777 | ||
2778 | ret_val = e1000_read_phy_reg(hw, | |
2779 | GG82563_PHY_KMRN_MODE_CTRL, &phy_data); | |
2780 | if (ret_val) | |
2781 | return ret_val; | |
2782 | ||
2783 | phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
2784 | ret_val = e1000_write_phy_reg(hw, | |
2785 | GG82563_PHY_KMRN_MODE_CTRL, phy_data); | |
2786 | ||
2787 | if (ret_val) | |
2788 | return ret_val; | |
2789 | } | |
2790 | ||
2791 | /* Workaround: Disable padding in Kumeran interface in the MAC | |
2792 | * and in the PHY to avoid CRC errors. | |
2793 | */ | |
2794 | ret_val = e1000_read_phy_reg(hw, | |
2795 | GG82563_PHY_INBAND_CTRL, &phy_data); | |
2796 | if (ret_val) | |
2797 | return ret_val; | |
2798 | phy_data |= GG82563_ICR_DIS_PADDING; | |
2799 | ret_val = e1000_write_phy_reg(hw, | |
2800 | GG82563_PHY_INBAND_CTRL, phy_data); | |
2801 | if (ret_val) | |
2802 | return ret_val; | |
682011ff | 2803 | } |
aa070789 | 2804 | return E1000_SUCCESS; |
682011ff WD |
2805 | } |
2806 | ||
aa070789 RZ |
2807 | /******************************************************************** |
2808 | * Copper link setup for e1000_phy_m88 series. | |
682011ff WD |
2809 | * |
2810 | * hw - Struct containing variables accessed by shared code | |
aa070789 RZ |
2811 | *********************************************************************/ |
2812 | static int32_t | |
2813 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) | |
682011ff | 2814 | { |
682011ff | 2815 | int32_t ret_val; |
682011ff WD |
2816 | uint16_t phy_data; |
2817 | ||
2818 | DEBUGFUNC(); | |
2819 | ||
aa070789 RZ |
2820 | if (hw->phy_reset_disable) |
2821 | return E1000_SUCCESS; | |
682011ff | 2822 | |
aa070789 RZ |
2823 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
2824 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
2825 | if (ret_val) | |
682011ff | 2826 | return ret_val; |
682011ff | 2827 | |
682011ff WD |
2828 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
2829 | ||
682011ff WD |
2830 | /* Options: |
2831 | * MDI/MDI-X = 0 (default) | |
2832 | * 0 - Auto for all speeds | |
2833 | * 1 - MDI mode | |
2834 | * 2 - MDI-X mode | |
2835 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
2836 | */ | |
2837 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
aa070789 | 2838 | |
682011ff WD |
2839 | switch (hw->mdix) { |
2840 | case 1: | |
2841 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
2842 | break; | |
2843 | case 2: | |
2844 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
2845 | break; | |
2846 | case 3: | |
2847 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
2848 | break; | |
2849 | case 0: | |
2850 | default: | |
2851 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
2852 | break; | |
2853 | } | |
682011ff | 2854 | |
682011ff WD |
2855 | /* Options: |
2856 | * disable_polarity_correction = 0 (default) | |
aa070789 | 2857 | * Automatic Correction for Reversed Cable Polarity |
682011ff WD |
2858 | * 0 - Disabled |
2859 | * 1 - Enabled | |
2860 | */ | |
2861 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
aa070789 RZ |
2862 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
2863 | if (ret_val) | |
2864 | return ret_val; | |
682011ff | 2865 | |
aa070789 RZ |
2866 | if (hw->phy_revision < M88E1011_I_REV_4) { |
2867 | /* Force TX_CLK in the Extended PHY Specific Control Register | |
2868 | * to 25MHz clock. | |
2869 | */ | |
2870 | ret_val = e1000_read_phy_reg(hw, | |
2871 | M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
2872 | if (ret_val) | |
2873 | return ret_val; | |
2874 | ||
2875 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
2876 | ||
2877 | if ((hw->phy_revision == E1000_REVISION_2) && | |
2878 | (hw->phy_id == M88E1111_I_PHY_ID)) { | |
2879 | /* Vidalia Phy, set the downshift counter to 5x */ | |
2880 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); | |
2881 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
2882 | ret_val = e1000_write_phy_reg(hw, | |
2883 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
2884 | if (ret_val) | |
2885 | return ret_val; | |
2886 | } else { | |
2887 | /* Configure Master and Slave downshift values */ | |
2888 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
2889 | | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
2890 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
2891 | | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
2892 | ret_val = e1000_write_phy_reg(hw, | |
2893 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
2894 | if (ret_val) | |
2895 | return ret_val; | |
2896 | } | |
682011ff WD |
2897 | } |
2898 | ||
2899 | /* SW Reset the PHY so all changes take effect */ | |
2900 | ret_val = e1000_phy_reset(hw); | |
aa070789 | 2901 | if (ret_val) { |
682011ff WD |
2902 | DEBUGOUT("Error Resetting the PHY\n"); |
2903 | return ret_val; | |
2904 | } | |
2905 | ||
aa070789 RZ |
2906 | return E1000_SUCCESS; |
2907 | } | |
2908 | ||
2909 | /******************************************************************** | |
2910 | * Setup auto-negotiation and flow control advertisements, | |
2911 | * and then perform auto-negotiation. | |
2912 | * | |
2913 | * hw - Struct containing variables accessed by shared code | |
2914 | *********************************************************************/ | |
2915 | static int32_t | |
2916 | e1000_copper_link_autoneg(struct e1000_hw *hw) | |
2917 | { | |
2918 | int32_t ret_val; | |
2919 | uint16_t phy_data; | |
2920 | ||
2921 | DEBUGFUNC(); | |
682011ff | 2922 | |
682011ff WD |
2923 | /* Perform some bounds checking on the hw->autoneg_advertised |
2924 | * parameter. If this variable is zero, then set it to the default. | |
2925 | */ | |
2926 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
2927 | ||
2928 | /* If autoneg_advertised is zero, we assume it was not defaulted | |
2929 | * by the calling code so we set to advertise full capability. | |
2930 | */ | |
2931 | if (hw->autoneg_advertised == 0) | |
2932 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
2933 | ||
aa070789 RZ |
2934 | /* IFE phy only supports 10/100 */ |
2935 | if (hw->phy_type == e1000_phy_ife) | |
2936 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; | |
2937 | ||
682011ff WD |
2938 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
2939 | ret_val = e1000_phy_setup_autoneg(hw); | |
aa070789 | 2940 | if (ret_val) { |
682011ff WD |
2941 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
2942 | return ret_val; | |
2943 | } | |
2944 | DEBUGOUT("Restarting Auto-Neg\n"); | |
2945 | ||
2946 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | |
2947 | * the Auto Neg Restart bit in the PHY control register. | |
2948 | */ | |
aa070789 RZ |
2949 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
2950 | if (ret_val) | |
2951 | return ret_val; | |
2952 | ||
682011ff | 2953 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
aa070789 RZ |
2954 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
2955 | if (ret_val) | |
2956 | return ret_val; | |
2957 | ||
682011ff WD |
2958 | /* Does the user want to wait for Auto-Neg to complete here, or |
2959 | * check at a later time (for example, callback routine). | |
2960 | */ | |
aa070789 RZ |
2961 | /* If we do not wait for autonegtation to complete I |
2962 | * do not see a valid link status. | |
2963 | * wait_autoneg_complete = 1 . | |
2964 | */ | |
682011ff WD |
2965 | if (hw->wait_autoneg_complete) { |
2966 | ret_val = e1000_wait_autoneg(hw); | |
aa070789 RZ |
2967 | if (ret_val) { |
2968 | DEBUGOUT("Error while waiting for autoneg" | |
2969 | "to complete\n"); | |
682011ff WD |
2970 | return ret_val; |
2971 | } | |
2972 | } | |
aa070789 | 2973 | |
472d5460 | 2974 | hw->get_link_status = true; |
aa070789 RZ |
2975 | |
2976 | return E1000_SUCCESS; | |
2977 | } | |
2978 | ||
2979 | /****************************************************************************** | |
2980 | * Config the MAC and the PHY after link is up. | |
2981 | * 1) Set up the MAC to the current PHY speed/duplex | |
2982 | * if we are on 82543. If we | |
2983 | * are on newer silicon, we only need to configure | |
2984 | * collision distance in the Transmit Control Register. | |
2985 | * 2) Set up flow control on the MAC to that established with | |
2986 | * the link partner. | |
2987 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. | |
2988 | * | |
2989 | * hw - Struct containing variables accessed by shared code | |
2990 | ******************************************************************************/ | |
2991 | static int32_t | |
2992 | e1000_copper_link_postconfig(struct e1000_hw *hw) | |
2993 | { | |
2994 | int32_t ret_val; | |
2995 | DEBUGFUNC(); | |
2996 | ||
2997 | if (hw->mac_type >= e1000_82544) { | |
2998 | e1000_config_collision_dist(hw); | |
2999 | } else { | |
3000 | ret_val = e1000_config_mac_to_phy(hw); | |
3001 | if (ret_val) { | |
3002 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | |
3003 | return ret_val; | |
3004 | } | |
3005 | } | |
3006 | ret_val = e1000_config_fc_after_link_up(hw); | |
3007 | if (ret_val) { | |
3008 | DEBUGOUT("Error Configuring Flow Control\n"); | |
682011ff WD |
3009 | return ret_val; |
3010 | } | |
aa070789 RZ |
3011 | return E1000_SUCCESS; |
3012 | } | |
3013 | ||
3014 | /****************************************************************************** | |
3015 | * Detects which PHY is present and setup the speed and duplex | |
3016 | * | |
3017 | * hw - Struct containing variables accessed by shared code | |
3018 | ******************************************************************************/ | |
3019 | static int | |
5c5e707a | 3020 | e1000_setup_copper_link(struct e1000_hw *hw) |
aa070789 | 3021 | { |
aa070789 RZ |
3022 | int32_t ret_val; |
3023 | uint16_t i; | |
3024 | uint16_t phy_data; | |
3025 | uint16_t reg_data; | |
3026 | ||
3027 | DEBUGFUNC(); | |
3028 | ||
3029 | switch (hw->mac_type) { | |
3030 | case e1000_80003es2lan: | |
3031 | case e1000_ich8lan: | |
3032 | /* Set the mac to wait the maximum time between each | |
3033 | * iteration and increase the max iterations when | |
3034 | * polling the phy; this fixes erroneous timeouts at 10Mbps. */ | |
3035 | ret_val = e1000_write_kmrn_reg(hw, | |
3036 | GG82563_REG(0x34, 4), 0xFFFF); | |
3037 | if (ret_val) | |
3038 | return ret_val; | |
3039 | ret_val = e1000_read_kmrn_reg(hw, | |
3040 | GG82563_REG(0x34, 9), ®_data); | |
3041 | if (ret_val) | |
3042 | return ret_val; | |
3043 | reg_data |= 0x3F; | |
3044 | ret_val = e1000_write_kmrn_reg(hw, | |
3045 | GG82563_REG(0x34, 9), reg_data); | |
3046 | if (ret_val) | |
3047 | return ret_val; | |
3048 | default: | |
3049 | break; | |
3050 | } | |
3051 | ||
3052 | /* Check if it is a valid PHY and set PHY mode if necessary. */ | |
3053 | ret_val = e1000_copper_link_preconfig(hw); | |
3054 | if (ret_val) | |
3055 | return ret_val; | |
3056 | switch (hw->mac_type) { | |
3057 | case e1000_80003es2lan: | |
3058 | /* Kumeran registers are written-only */ | |
3059 | reg_data = | |
3060 | E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; | |
3061 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; | |
3062 | ret_val = e1000_write_kmrn_reg(hw, | |
3063 | E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); | |
3064 | if (ret_val) | |
3065 | return ret_val; | |
3066 | break; | |
3067 | default: | |
3068 | break; | |
3069 | } | |
3070 | ||
3071 | if (hw->phy_type == e1000_phy_igp || | |
3072 | hw->phy_type == e1000_phy_igp_3 || | |
3073 | hw->phy_type == e1000_phy_igp_2) { | |
3074 | ret_val = e1000_copper_link_igp_setup(hw); | |
3075 | if (ret_val) | |
3076 | return ret_val; | |
95186063 MV |
3077 | } else if (hw->phy_type == e1000_phy_m88 || |
3078 | hw->phy_type == e1000_phy_igb) { | |
aa070789 RZ |
3079 | ret_val = e1000_copper_link_mgp_setup(hw); |
3080 | if (ret_val) | |
3081 | return ret_val; | |
3082 | } else if (hw->phy_type == e1000_phy_gg82563) { | |
3083 | ret_val = e1000_copper_link_ggp_setup(hw); | |
3084 | if (ret_val) | |
3085 | return ret_val; | |
3086 | } | |
3087 | ||
3088 | /* always auto */ | |
3089 | /* Setup autoneg and flow control advertisement | |
3090 | * and perform autonegotiation */ | |
3091 | ret_val = e1000_copper_link_autoneg(hw); | |
3092 | if (ret_val) | |
3093 | return ret_val; | |
682011ff WD |
3094 | |
3095 | /* Check link status. Wait up to 100 microseconds for link to become | |
3096 | * valid. | |
3097 | */ | |
3098 | for (i = 0; i < 10; i++) { | |
aa070789 RZ |
3099 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
3100 | if (ret_val) | |
3101 | return ret_val; | |
3102 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
3103 | if (ret_val) | |
3104 | return ret_val; | |
3105 | ||
682011ff | 3106 | if (phy_data & MII_SR_LINK_STATUS) { |
aa070789 RZ |
3107 | /* Config the MAC and PHY after link is up */ |
3108 | ret_val = e1000_copper_link_postconfig(hw); | |
3109 | if (ret_val) | |
682011ff | 3110 | return ret_val; |
aa070789 | 3111 | |
682011ff | 3112 | DEBUGOUT("Valid link established!!!\n"); |
aa070789 | 3113 | return E1000_SUCCESS; |
682011ff WD |
3114 | } |
3115 | udelay(10); | |
3116 | } | |
3117 | ||
3118 | DEBUGOUT("Unable to establish link!!!\n"); | |
aa070789 | 3119 | return E1000_SUCCESS; |
682011ff WD |
3120 | } |
3121 | ||
3122 | /****************************************************************************** | |
3123 | * Configures PHY autoneg and flow control advertisement settings | |
3124 | * | |
3125 | * hw - Struct containing variables accessed by shared code | |
3126 | ******************************************************************************/ | |
aa070789 | 3127 | int32_t |
682011ff WD |
3128 | e1000_phy_setup_autoneg(struct e1000_hw *hw) |
3129 | { | |
aa070789 | 3130 | int32_t ret_val; |
682011ff WD |
3131 | uint16_t mii_autoneg_adv_reg; |
3132 | uint16_t mii_1000t_ctrl_reg; | |
3133 | ||
3134 | DEBUGFUNC(); | |
3135 | ||
3136 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
aa070789 RZ |
3137 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
3138 | if (ret_val) | |
3139 | return ret_val; | |
682011ff | 3140 | |
aa070789 RZ |
3141 | if (hw->phy_type != e1000_phy_ife) { |
3142 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
3143 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, | |
3144 | &mii_1000t_ctrl_reg); | |
3145 | if (ret_val) | |
3146 | return ret_val; | |
3147 | } else | |
3148 | mii_1000t_ctrl_reg = 0; | |
682011ff WD |
3149 | |
3150 | /* Need to parse both autoneg_advertised and fc and set up | |
3151 | * the appropriate PHY registers. First we will parse for | |
3152 | * autoneg_advertised software override. Since we can advertise | |
3153 | * a plethora of combinations, we need to check each bit | |
3154 | * individually. | |
3155 | */ | |
3156 | ||
3157 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg | |
3158 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
aa070789 | 3159 | * the 1000Base-T Control Register (Address 9). |
682011ff WD |
3160 | */ |
3161 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; | |
3162 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; | |
3163 | ||
3164 | DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); | |
3165 | ||
3166 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
3167 | if (hw->autoneg_advertised & ADVERTISE_10_HALF) { | |
3168 | DEBUGOUT("Advertise 10mb Half duplex\n"); | |
3169 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; | |
3170 | } | |
3171 | ||
3172 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
3173 | if (hw->autoneg_advertised & ADVERTISE_10_FULL) { | |
3174 | DEBUGOUT("Advertise 10mb Full duplex\n"); | |
3175 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; | |
3176 | } | |
3177 | ||
3178 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
3179 | if (hw->autoneg_advertised & ADVERTISE_100_HALF) { | |
3180 | DEBUGOUT("Advertise 100mb Half duplex\n"); | |
3181 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; | |
3182 | } | |
3183 | ||
3184 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
3185 | if (hw->autoneg_advertised & ADVERTISE_100_FULL) { | |
3186 | DEBUGOUT("Advertise 100mb Full duplex\n"); | |
3187 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; | |
3188 | } | |
3189 | ||
3190 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
3191 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { | |
3192 | DEBUGOUT | |
3193 | ("Advertise 1000mb Half duplex requested, request denied!\n"); | |
3194 | } | |
3195 | ||
3196 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
3197 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { | |
3198 | DEBUGOUT("Advertise 1000mb Full duplex\n"); | |
3199 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; | |
3200 | } | |
3201 | ||
3202 | /* Check for a software override of the flow control settings, and | |
3203 | * setup the PHY advertisement registers accordingly. If | |
3204 | * auto-negotiation is enabled, then software will have to set the | |
3205 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
3206 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. | |
3207 | * | |
3208 | * The possible values of the "fc" parameter are: | |
1aeed8d7 WD |
3209 | * 0: Flow control is completely disabled |
3210 | * 1: Rx flow control is enabled (we can receive pause frames | |
3211 | * but not send pause frames). | |
3212 | * 2: Tx flow control is enabled (we can send pause frames | |
3213 | * but we do not support receiving pause frames). | |
3214 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
682011ff | 3215 | * other: No software override. The flow control configuration |
1aeed8d7 | 3216 | * in the EEPROM is used. |
682011ff WD |
3217 | */ |
3218 | switch (hw->fc) { | |
3219 | case e1000_fc_none: /* 0 */ | |
3220 | /* Flow control (RX & TX) is completely disabled by a | |
3221 | * software over-ride. | |
3222 | */ | |
3223 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
3224 | break; | |
3225 | case e1000_fc_rx_pause: /* 1 */ | |
3226 | /* RX Flow control is enabled, and TX Flow control is | |
3227 | * disabled, by a software over-ride. | |
3228 | */ | |
3229 | /* Since there really isn't a way to advertise that we are | |
3230 | * capable of RX Pause ONLY, we will advertise that we | |
3231 | * support both symmetric and asymmetric RX PAUSE. Later | |
3232 | * (in e1000_config_fc_after_link_up) we will disable the | |
3233 | *hw's ability to send PAUSE frames. | |
3234 | */ | |
3235 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
3236 | break; | |
3237 | case e1000_fc_tx_pause: /* 2 */ | |
3238 | /* TX Flow control is enabled, and RX Flow control is | |
3239 | * disabled, by a software over-ride. | |
3240 | */ | |
3241 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
3242 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
3243 | break; | |
3244 | case e1000_fc_full: /* 3 */ | |
3245 | /* Flow control (both RX and TX) is enabled by a software | |
3246 | * over-ride. | |
3247 | */ | |
3248 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
3249 | break; | |
3250 | default: | |
3251 | DEBUGOUT("Flow control param set incorrectly\n"); | |
3252 | return -E1000_ERR_CONFIG; | |
3253 | } | |
3254 | ||
aa070789 RZ |
3255 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
3256 | if (ret_val) | |
3257 | return ret_val; | |
682011ff WD |
3258 | |
3259 | DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); | |
3260 | ||
aa070789 RZ |
3261 | if (hw->phy_type != e1000_phy_ife) { |
3262 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, | |
3263 | mii_1000t_ctrl_reg); | |
3264 | if (ret_val) | |
3265 | return ret_val; | |
682011ff | 3266 | } |
aa070789 RZ |
3267 | |
3268 | return E1000_SUCCESS; | |
682011ff WD |
3269 | } |
3270 | ||
3271 | /****************************************************************************** | |
3272 | * Sets the collision distance in the Transmit Control register | |
3273 | * | |
3274 | * hw - Struct containing variables accessed by shared code | |
3275 | * | |
3276 | * Link should have been established previously. Reads the speed and duplex | |
3277 | * information from the Device Status register. | |
3278 | ******************************************************************************/ | |
3279 | static void | |
3280 | e1000_config_collision_dist(struct e1000_hw *hw) | |
3281 | { | |
aa070789 RZ |
3282 | uint32_t tctl, coll_dist; |
3283 | ||
3284 | DEBUGFUNC(); | |
3285 | ||
3286 | if (hw->mac_type < e1000_82543) | |
3287 | coll_dist = E1000_COLLISION_DISTANCE_82542; | |
3288 | else | |
3289 | coll_dist = E1000_COLLISION_DISTANCE; | |
682011ff WD |
3290 | |
3291 | tctl = E1000_READ_REG(hw, TCTL); | |
3292 | ||
3293 | tctl &= ~E1000_TCTL_COLD; | |
aa070789 | 3294 | tctl |= coll_dist << E1000_COLD_SHIFT; |
682011ff WD |
3295 | |
3296 | E1000_WRITE_REG(hw, TCTL, tctl); | |
3297 | E1000_WRITE_FLUSH(hw); | |
3298 | } | |
3299 | ||
3300 | /****************************************************************************** | |
3301 | * Sets MAC speed and duplex settings to reflect the those in the PHY | |
3302 | * | |
3303 | * hw - Struct containing variables accessed by shared code | |
3304 | * mii_reg - data to write to the MII control register | |
3305 | * | |
3306 | * The contents of the PHY register containing the needed information need to | |
3307 | * be passed in. | |
3308 | ******************************************************************************/ | |
3309 | static int | |
3310 | e1000_config_mac_to_phy(struct e1000_hw *hw) | |
3311 | { | |
3312 | uint32_t ctrl; | |
3313 | uint16_t phy_data; | |
3314 | ||
3315 | DEBUGFUNC(); | |
3316 | ||
3317 | /* Read the Device Control Register and set the bits to Force Speed | |
3318 | * and Duplex. | |
3319 | */ | |
3320 | ctrl = E1000_READ_REG(hw, CTRL); | |
3321 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
95186063 MV |
3322 | ctrl &= ~(E1000_CTRL_ILOS); |
3323 | ctrl |= (E1000_CTRL_SPD_SEL); | |
682011ff WD |
3324 | |
3325 | /* Set up duplex in the Device Control and Transmit Control | |
3326 | * registers depending on negotiated values. | |
3327 | */ | |
3328 | if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { | |
3329 | DEBUGOUT("PHY Read Error\n"); | |
3330 | return -E1000_ERR_PHY; | |
3331 | } | |
3332 | if (phy_data & M88E1000_PSSR_DPLX) | |
3333 | ctrl |= E1000_CTRL_FD; | |
3334 | else | |
3335 | ctrl &= ~E1000_CTRL_FD; | |
3336 | ||
3337 | e1000_config_collision_dist(hw); | |
3338 | ||
3339 | /* Set up speed in the Device Control register depending on | |
3340 | * negotiated values. | |
3341 | */ | |
3342 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) | |
3343 | ctrl |= E1000_CTRL_SPD_1000; | |
3344 | else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) | |
3345 | ctrl |= E1000_CTRL_SPD_100; | |
3346 | /* Write the configured values back to the Device Control Reg. */ | |
3347 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3348 | return 0; | |
3349 | } | |
3350 | ||
3351 | /****************************************************************************** | |
3352 | * Forces the MAC's flow control settings. | |
8bde7f77 | 3353 | * |
682011ff WD |
3354 | * hw - Struct containing variables accessed by shared code |
3355 | * | |
3356 | * Sets the TFCE and RFCE bits in the device control register to reflect | |
3357 | * the adapter settings. TFCE and RFCE need to be explicitly set by | |
3358 | * software when a Copper PHY is used because autonegotiation is managed | |
3359 | * by the PHY rather than the MAC. Software must also configure these | |
3360 | * bits when link is forced on a fiber connection. | |
3361 | *****************************************************************************/ | |
3362 | static int | |
3363 | e1000_force_mac_fc(struct e1000_hw *hw) | |
3364 | { | |
3365 | uint32_t ctrl; | |
3366 | ||
3367 | DEBUGFUNC(); | |
3368 | ||
3369 | /* Get the current configuration of the Device Control Register */ | |
3370 | ctrl = E1000_READ_REG(hw, CTRL); | |
3371 | ||
3372 | /* Because we didn't get link via the internal auto-negotiation | |
3373 | * mechanism (we either forced link or we got link via PHY | |
3374 | * auto-neg), we have to manually enable/disable transmit an | |
3375 | * receive flow control. | |
3376 | * | |
3377 | * The "Case" statement below enables/disable flow control | |
3378 | * according to the "hw->fc" parameter. | |
3379 | * | |
3380 | * The possible values of the "fc" parameter are: | |
1aeed8d7 WD |
3381 | * 0: Flow control is completely disabled |
3382 | * 1: Rx flow control is enabled (we can receive pause | |
3383 | * frames but not send pause frames). | |
3384 | * 2: Tx flow control is enabled (we can send pause frames | |
3385 | * frames but we do not receive pause frames). | |
3386 | * 3: Both Rx and TX flow control (symmetric) is enabled. | |
682011ff WD |
3387 | * other: No other values should be possible at this point. |
3388 | */ | |
3389 | ||
3390 | switch (hw->fc) { | |
3391 | case e1000_fc_none: | |
3392 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); | |
3393 | break; | |
3394 | case e1000_fc_rx_pause: | |
3395 | ctrl &= (~E1000_CTRL_TFCE); | |
3396 | ctrl |= E1000_CTRL_RFCE; | |
3397 | break; | |
3398 | case e1000_fc_tx_pause: | |
3399 | ctrl &= (~E1000_CTRL_RFCE); | |
3400 | ctrl |= E1000_CTRL_TFCE; | |
3401 | break; | |
3402 | case e1000_fc_full: | |
3403 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); | |
3404 | break; | |
3405 | default: | |
3406 | DEBUGOUT("Flow control param set incorrectly\n"); | |
3407 | return -E1000_ERR_CONFIG; | |
3408 | } | |
3409 | ||
3410 | /* Disable TX Flow Control for 82542 (rev 2.0) */ | |
3411 | if (hw->mac_type == e1000_82542_rev2_0) | |
3412 | ctrl &= (~E1000_CTRL_TFCE); | |
3413 | ||
3414 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3415 | return 0; | |
3416 | } | |
3417 | ||
3418 | /****************************************************************************** | |
3419 | * Configures flow control settings after link is established | |
8bde7f77 | 3420 | * |
682011ff WD |
3421 | * hw - Struct containing variables accessed by shared code |
3422 | * | |
3423 | * Should be called immediately after a valid link has been established. | |
3424 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode | |
3425 | * and autonegotiation is enabled, the MAC flow control settings will be set | |
3426 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE | |
3427 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. | |
3428 | *****************************************************************************/ | |
aa070789 | 3429 | static int32_t |
682011ff WD |
3430 | e1000_config_fc_after_link_up(struct e1000_hw *hw) |
3431 | { | |
3432 | int32_t ret_val; | |
3433 | uint16_t mii_status_reg; | |
3434 | uint16_t mii_nway_adv_reg; | |
3435 | uint16_t mii_nway_lp_ability_reg; | |
3436 | uint16_t speed; | |
3437 | uint16_t duplex; | |
3438 | ||
3439 | DEBUGFUNC(); | |
3440 | ||
3441 | /* Check for the case where we have fiber media and auto-neg failed | |
3442 | * so we had to force link. In this case, we need to force the | |
3443 | * configuration of the MAC to match the "fc" parameter. | |
3444 | */ | |
aa070789 RZ |
3445 | if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) |
3446 | || ((hw->media_type == e1000_media_type_internal_serdes) | |
3447 | && (hw->autoneg_failed)) | |
3448 | || ((hw->media_type == e1000_media_type_copper) | |
3449 | && (!hw->autoneg))) { | |
682011ff WD |
3450 | ret_val = e1000_force_mac_fc(hw); |
3451 | if (ret_val < 0) { | |
3452 | DEBUGOUT("Error forcing flow control settings\n"); | |
3453 | return ret_val; | |
3454 | } | |
3455 | } | |
3456 | ||
3457 | /* Check for the case where we have copper media and auto-neg is | |
3458 | * enabled. In this case, we need to check and see if Auto-Neg | |
3459 | * has completed, and if so, how the PHY and link partner has | |
3460 | * flow control configured. | |
3461 | */ | |
3462 | if (hw->media_type == e1000_media_type_copper) { | |
3463 | /* Read the MII Status Register and check to see if AutoNeg | |
3464 | * has completed. We read this twice because this reg has | |
3465 | * some "sticky" (latched) bits. | |
3466 | */ | |
3467 | if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { | |
5abf13e4 | 3468 | DEBUGOUT("PHY Read Error\n"); |
682011ff WD |
3469 | return -E1000_ERR_PHY; |
3470 | } | |
3471 | if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { | |
5abf13e4 | 3472 | DEBUGOUT("PHY Read Error\n"); |
682011ff WD |
3473 | return -E1000_ERR_PHY; |
3474 | } | |
3475 | ||
3476 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { | |
3477 | /* The AutoNeg process has completed, so we now need to | |
3478 | * read both the Auto Negotiation Advertisement Register | |
3479 | * (Address 4) and the Auto_Negotiation Base Page Ability | |
3480 | * Register (Address 5) to determine how flow control was | |
3481 | * negotiated. | |
3482 | */ | |
3483 | if (e1000_read_phy_reg | |
3484 | (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { | |
3485 | DEBUGOUT("PHY Read Error\n"); | |
3486 | return -E1000_ERR_PHY; | |
3487 | } | |
3488 | if (e1000_read_phy_reg | |
3489 | (hw, PHY_LP_ABILITY, | |
3490 | &mii_nway_lp_ability_reg) < 0) { | |
3491 | DEBUGOUT("PHY Read Error\n"); | |
3492 | return -E1000_ERR_PHY; | |
3493 | } | |
3494 | ||
3495 | /* Two bits in the Auto Negotiation Advertisement Register | |
3496 | * (Address 4) and two bits in the Auto Negotiation Base | |
3497 | * Page Ability Register (Address 5) determine flow control | |
3498 | * for both the PHY and the link partner. The following | |
3499 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
3500 | * 1999, describes these PAUSE resolution bits and how flow | |
3501 | * control is determined based upon these settings. | |
3502 | * NOTE: DC = Don't Care | |
3503 | * | |
3504 | * LOCAL DEVICE | LINK PARTNER | |
3505 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
3506 | *-------|---------|-------|---------|-------------------- | |
1aeed8d7 WD |
3507 | * 0 | 0 | DC | DC | e1000_fc_none |
3508 | * 0 | 1 | 0 | DC | e1000_fc_none | |
3509 | * 0 | 1 | 1 | 0 | e1000_fc_none | |
3510 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
3511 | * 1 | 0 | 0 | DC | e1000_fc_none | |
3512 | * 1 | DC | 1 | DC | e1000_fc_full | |
3513 | * 1 | 1 | 0 | 0 | e1000_fc_none | |
3514 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
682011ff WD |
3515 | * |
3516 | */ | |
3517 | /* Are both PAUSE bits set to 1? If so, this implies | |
3518 | * Symmetric Flow Control is enabled at both ends. The | |
3519 | * ASM_DIR bits are irrelevant per the spec. | |
3520 | * | |
3521 | * For Symmetric Flow Control: | |
3522 | * | |
3523 | * LOCAL DEVICE | LINK PARTNER | |
3524 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
3525 | *-------|---------|-------|---------|-------------------- | |
1aeed8d7 | 3526 | * 1 | DC | 1 | DC | e1000_fc_full |
682011ff WD |
3527 | * |
3528 | */ | |
3529 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
3530 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | |
3531 | /* Now we need to check if the user selected RX ONLY | |
3532 | * of pause frames. In this case, we had to advertise | |
3533 | * FULL flow control because we could not advertise RX | |
3534 | * ONLY. Hence, we must now check to see if we need to | |
3535 | * turn OFF the TRANSMISSION of PAUSE frames. | |
3536 | */ | |
3537 | if (hw->original_fc == e1000_fc_full) { | |
3538 | hw->fc = e1000_fc_full; | |
3539 | DEBUGOUT("Flow Control = FULL.\r\n"); | |
3540 | } else { | |
3541 | hw->fc = e1000_fc_rx_pause; | |
3542 | DEBUGOUT | |
3543 | ("Flow Control = RX PAUSE frames only.\r\n"); | |
3544 | } | |
3545 | } | |
3546 | /* For receiving PAUSE frames ONLY. | |
3547 | * | |
3548 | * LOCAL DEVICE | LINK PARTNER | |
3549 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
3550 | *-------|---------|-------|---------|-------------------- | |
1aeed8d7 | 3551 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
682011ff WD |
3552 | * |
3553 | */ | |
3554 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
3555 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
3556 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
3557 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) | |
3558 | { | |
3559 | hw->fc = e1000_fc_tx_pause; | |
3560 | DEBUGOUT | |
3561 | ("Flow Control = TX PAUSE frames only.\r\n"); | |
3562 | } | |
3563 | /* For transmitting PAUSE frames ONLY. | |
3564 | * | |
3565 | * LOCAL DEVICE | LINK PARTNER | |
3566 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
3567 | *-------|---------|-------|---------|-------------------- | |
1aeed8d7 | 3568 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
682011ff WD |
3569 | * |
3570 | */ | |
3571 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
3572 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
3573 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
3574 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) | |
3575 | { | |
3576 | hw->fc = e1000_fc_rx_pause; | |
3577 | DEBUGOUT | |
3578 | ("Flow Control = RX PAUSE frames only.\r\n"); | |
3579 | } | |
3580 | /* Per the IEEE spec, at this point flow control should be | |
3581 | * disabled. However, we want to consider that we could | |
3582 | * be connected to a legacy switch that doesn't advertise | |
3583 | * desired flow control, but can be forced on the link | |
3584 | * partner. So if we advertised no flow control, that is | |
3585 | * what we will resolve to. If we advertised some kind of | |
3586 | * receive capability (Rx Pause Only or Full Flow Control) | |
3587 | * and the link partner advertised none, we will configure | |
3588 | * ourselves to enable Rx Flow Control only. We can do | |
3589 | * this safely for two reasons: If the link partner really | |
3590 | * didn't want flow control enabled, and we enable Rx, no | |
3591 | * harm done since we won't be receiving any PAUSE frames | |
3592 | * anyway. If the intent on the link partner was to have | |
3593 | * flow control enabled, then by us enabling RX only, we | |
3594 | * can at least receive pause frames and process them. | |
3595 | * This is a good idea because in most cases, since we are | |
3596 | * predominantly a server NIC, more times than not we will | |
3597 | * be asked to delay transmission of packets than asking | |
3598 | * our link partner to pause transmission of frames. | |
3599 | */ | |
3600 | else if (hw->original_fc == e1000_fc_none || | |
3601 | hw->original_fc == e1000_fc_tx_pause) { | |
3602 | hw->fc = e1000_fc_none; | |
3603 | DEBUGOUT("Flow Control = NONE.\r\n"); | |
3604 | } else { | |
3605 | hw->fc = e1000_fc_rx_pause; | |
3606 | DEBUGOUT | |
3607 | ("Flow Control = RX PAUSE frames only.\r\n"); | |
3608 | } | |
3609 | ||
1aeed8d7 | 3610 | /* Now we need to do one last check... If we auto- |
682011ff WD |
3611 | * negotiated to HALF DUPLEX, flow control should not be |
3612 | * enabled per IEEE 802.3 spec. | |
3613 | */ | |
3614 | e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
3615 | ||
3616 | if (duplex == HALF_DUPLEX) | |
3617 | hw->fc = e1000_fc_none; | |
3618 | ||
3619 | /* Now we call a subroutine to actually force the MAC | |
3620 | * controller to use the correct flow control settings. | |
3621 | */ | |
3622 | ret_val = e1000_force_mac_fc(hw); | |
3623 | if (ret_val < 0) { | |
3624 | DEBUGOUT | |
3625 | ("Error forcing flow control settings\n"); | |
3626 | return ret_val; | |
3627 | } | |
3628 | } else { | |
3629 | DEBUGOUT | |
3630 | ("Copper PHY and Auto Neg has not completed.\r\n"); | |
3631 | } | |
3632 | } | |
aa070789 | 3633 | return E1000_SUCCESS; |
682011ff WD |
3634 | } |
3635 | ||
3636 | /****************************************************************************** | |
3637 | * Checks to see if the link status of the hardware has changed. | |
3638 | * | |
3639 | * hw - Struct containing variables accessed by shared code | |
3640 | * | |
3641 | * Called by any function that needs to check the link status of the adapter. | |
3642 | *****************************************************************************/ | |
3643 | static int | |
5c5e707a | 3644 | e1000_check_for_link(struct e1000_hw *hw) |
682011ff | 3645 | { |
682011ff WD |
3646 | uint32_t rxcw; |
3647 | uint32_t ctrl; | |
3648 | uint32_t status; | |
3649 | uint32_t rctl; | |
3650 | uint32_t signal; | |
3651 | int32_t ret_val; | |
3652 | uint16_t phy_data; | |
3653 | uint16_t lp_capability; | |
3654 | ||
3655 | DEBUGFUNC(); | |
3656 | ||
8bde7f77 WD |
3657 | /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be |
3658 | * set when the optics detect a signal. On older adapters, it will be | |
682011ff WD |
3659 | * cleared when there is a signal |
3660 | */ | |
3661 | ctrl = E1000_READ_REG(hw, CTRL); | |
3662 | if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) | |
3663 | signal = E1000_CTRL_SWDPIN1; | |
3664 | else | |
3665 | signal = 0; | |
3666 | ||
3667 | status = E1000_READ_REG(hw, STATUS); | |
3668 | rxcw = E1000_READ_REG(hw, RXCW); | |
3669 | DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); | |
3670 | ||
3671 | /* If we have a copper PHY then we only want to go out to the PHY | |
3672 | * registers to see if Auto-Neg has completed and/or if our link | |
1aeed8d7 | 3673 | * status has changed. The get_link_status flag will be set if we |
682011ff WD |
3674 | * receive a Link Status Change interrupt or we have Rx Sequence |
3675 | * Errors. | |
3676 | */ | |
3677 | if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { | |
3678 | /* First we want to see if the MII Status Register reports | |
3679 | * link. If so, then we want to get the current speed/duplex | |
3680 | * of the PHY. | |
3681 | * Read the register twice since the link bit is sticky. | |
3682 | */ | |
3683 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { | |
3684 | DEBUGOUT("PHY Read Error\n"); | |
3685 | return -E1000_ERR_PHY; | |
3686 | } | |
3687 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { | |
3688 | DEBUGOUT("PHY Read Error\n"); | |
3689 | return -E1000_ERR_PHY; | |
3690 | } | |
3691 | ||
3692 | if (phy_data & MII_SR_LINK_STATUS) { | |
472d5460 | 3693 | hw->get_link_status = false; |
682011ff WD |
3694 | } else { |
3695 | /* No link detected */ | |
3696 | return -E1000_ERR_NOLINK; | |
3697 | } | |
3698 | ||
3699 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we | |
3700 | * have Si on board that is 82544 or newer, Auto | |
3701 | * Speed Detection takes care of MAC speed/duplex | |
3702 | * configuration. So we only need to configure Collision | |
3703 | * Distance in the MAC. Otherwise, we need to force | |
3704 | * speed/duplex on the MAC to the current PHY speed/duplex | |
3705 | * settings. | |
3706 | */ | |
3707 | if (hw->mac_type >= e1000_82544) | |
3708 | e1000_config_collision_dist(hw); | |
3709 | else { | |
3710 | ret_val = e1000_config_mac_to_phy(hw); | |
3711 | if (ret_val < 0) { | |
3712 | DEBUGOUT | |
3713 | ("Error configuring MAC to PHY settings\n"); | |
3714 | return ret_val; | |
3715 | } | |
3716 | } | |
3717 | ||
8bde7f77 | 3718 | /* Configure Flow Control now that Auto-Neg has completed. First, we |
682011ff WD |
3719 | * need to restore the desired flow control settings because we may |
3720 | * have had to re-autoneg with a different link partner. | |
3721 | */ | |
3722 | ret_val = e1000_config_fc_after_link_up(hw); | |
3723 | if (ret_val < 0) { | |
3724 | DEBUGOUT("Error configuring flow control\n"); | |
3725 | return ret_val; | |
3726 | } | |
3727 | ||
3728 | /* At this point we know that we are on copper and we have | |
3729 | * auto-negotiated link. These are conditions for checking the link | |
1aeed8d7 | 3730 | * parter capability register. We use the link partner capability to |
682011ff WD |
3731 | * determine if TBI Compatibility needs to be turned on or off. If |
3732 | * the link partner advertises any speed in addition to Gigabit, then | |
3733 | * we assume that they are GMII-based, and TBI compatibility is not | |
3734 | * needed. If no other speeds are advertised, we assume the link | |
3735 | * partner is TBI-based, and we turn on TBI Compatibility. | |
3736 | */ | |
3737 | if (hw->tbi_compatibility_en) { | |
3738 | if (e1000_read_phy_reg | |
3739 | (hw, PHY_LP_ABILITY, &lp_capability) < 0) { | |
3740 | DEBUGOUT("PHY Read Error\n"); | |
3741 | return -E1000_ERR_PHY; | |
3742 | } | |
3743 | if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | | |
3744 | NWAY_LPAR_10T_FD_CAPS | | |
3745 | NWAY_LPAR_100TX_HD_CAPS | | |
3746 | NWAY_LPAR_100TX_FD_CAPS | | |
3747 | NWAY_LPAR_100T4_CAPS)) { | |
8bde7f77 | 3748 | /* If our link partner advertises anything in addition to |
682011ff WD |
3749 | * gigabit, we do not need to enable TBI compatibility. |
3750 | */ | |
3751 | if (hw->tbi_compatibility_on) { | |
3752 | /* If we previously were in the mode, turn it off. */ | |
3753 | rctl = E1000_READ_REG(hw, RCTL); | |
3754 | rctl &= ~E1000_RCTL_SBP; | |
3755 | E1000_WRITE_REG(hw, RCTL, rctl); | |
472d5460 | 3756 | hw->tbi_compatibility_on = false; |
682011ff WD |
3757 | } |
3758 | } else { | |
3759 | /* If TBI compatibility is was previously off, turn it on. For | |
3760 | * compatibility with a TBI link partner, we will store bad | |
3761 | * packets. Some frames have an additional byte on the end and | |
3762 | * will look like CRC errors to to the hardware. | |
3763 | */ | |
3764 | if (!hw->tbi_compatibility_on) { | |
472d5460 | 3765 | hw->tbi_compatibility_on = true; |
682011ff WD |
3766 | rctl = E1000_READ_REG(hw, RCTL); |
3767 | rctl |= E1000_RCTL_SBP; | |
3768 | E1000_WRITE_REG(hw, RCTL, rctl); | |
3769 | } | |
3770 | } | |
3771 | } | |
3772 | } | |
3773 | /* If we don't have link (auto-negotiation failed or link partner cannot | |
3774 | * auto-negotiate), the cable is plugged in (we have signal), and our | |
3775 | * link partner is not trying to auto-negotiate with us (we are receiving | |
3776 | * idles or data), we need to force link up. We also need to give | |
3777 | * auto-negotiation time to complete, in case the cable was just plugged | |
3778 | * in. The autoneg_failed flag does this. | |
3779 | */ | |
3780 | else if ((hw->media_type == e1000_media_type_fiber) && | |
3781 | (!(status & E1000_STATUS_LU)) && | |
3782 | ((ctrl & E1000_CTRL_SWDPIN1) == signal) && | |
3783 | (!(rxcw & E1000_RXCW_C))) { | |
3784 | if (hw->autoneg_failed == 0) { | |
3785 | hw->autoneg_failed = 1; | |
3786 | return 0; | |
3787 | } | |
3788 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); | |
3789 | ||
3790 | /* Disable auto-negotiation in the TXCW register */ | |
3791 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); | |
3792 | ||
3793 | /* Force link-up and also force full-duplex. */ | |
3794 | ctrl = E1000_READ_REG(hw, CTRL); | |
3795 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
3796 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3797 | ||
3798 | /* Configure Flow Control after forcing link up. */ | |
3799 | ret_val = e1000_config_fc_after_link_up(hw); | |
3800 | if (ret_val < 0) { | |
3801 | DEBUGOUT("Error configuring flow control\n"); | |
3802 | return ret_val; | |
3803 | } | |
3804 | } | |
3805 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable | |
3806 | * auto-negotiation in the TXCW register and disable forced link in the | |
3807 | * Device Control register in an attempt to auto-negotiate with our link | |
3808 | * partner. | |
3809 | */ | |
3810 | else if ((hw->media_type == e1000_media_type_fiber) && | |
3811 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | |
3812 | DEBUGOUT | |
3813 | ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); | |
3814 | E1000_WRITE_REG(hw, TXCW, hw->txcw); | |
3815 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); | |
3816 | } | |
3817 | return 0; | |
3818 | } | |
3819 | ||
aa070789 RZ |
3820 | /****************************************************************************** |
3821 | * Configure the MAC-to-PHY interface for 10/100Mbps | |
3822 | * | |
3823 | * hw - Struct containing variables accessed by shared code | |
3824 | ******************************************************************************/ | |
3825 | static int32_t | |
3826 | e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) | |
3827 | { | |
3828 | int32_t ret_val = E1000_SUCCESS; | |
3829 | uint32_t tipg; | |
3830 | uint16_t reg_data; | |
3831 | ||
3832 | DEBUGFUNC(); | |
3833 | ||
3834 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
3835 | ret_val = e1000_write_kmrn_reg(hw, | |
3836 | E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); | |
3837 | if (ret_val) | |
3838 | return ret_val; | |
3839 | ||
3840 | /* Configure Transmit Inter-Packet Gap */ | |
3841 | tipg = E1000_READ_REG(hw, TIPG); | |
3842 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
3843 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; | |
3844 | E1000_WRITE_REG(hw, TIPG, tipg); | |
3845 | ||
3846 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
3847 | ||
3848 | if (ret_val) | |
3849 | return ret_val; | |
3850 | ||
3851 | if (duplex == HALF_DUPLEX) | |
3852 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
3853 | else | |
3854 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
3855 | ||
3856 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
3857 | ||
3858 | return ret_val; | |
3859 | } | |
3860 | ||
3861 | static int32_t | |
3862 | e1000_configure_kmrn_for_1000(struct e1000_hw *hw) | |
3863 | { | |
3864 | int32_t ret_val = E1000_SUCCESS; | |
3865 | uint16_t reg_data; | |
3866 | uint32_t tipg; | |
3867 | ||
3868 | DEBUGFUNC(); | |
3869 | ||
3870 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; | |
3871 | ret_val = e1000_write_kmrn_reg(hw, | |
3872 | E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); | |
3873 | if (ret_val) | |
3874 | return ret_val; | |
3875 | ||
3876 | /* Configure Transmit Inter-Packet Gap */ | |
3877 | tipg = E1000_READ_REG(hw, TIPG); | |
3878 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
3879 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
3880 | E1000_WRITE_REG(hw, TIPG, tipg); | |
3881 | ||
3882 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
3883 | ||
3884 | if (ret_val) | |
3885 | return ret_val; | |
3886 | ||
3887 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
3888 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
3889 | ||
3890 | return ret_val; | |
3891 | } | |
3892 | ||
682011ff WD |
3893 | /****************************************************************************** |
3894 | * Detects the current speed and duplex settings of the hardware. | |
3895 | * | |
3896 | * hw - Struct containing variables accessed by shared code | |
3897 | * speed - Speed of the connection | |
3898 | * duplex - Duplex setting of the connection | |
3899 | *****************************************************************************/ | |
aa070789 RZ |
3900 | static int |
3901 | e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, | |
3902 | uint16_t *duplex) | |
682011ff WD |
3903 | { |
3904 | uint32_t status; | |
aa070789 RZ |
3905 | int32_t ret_val; |
3906 | uint16_t phy_data; | |
682011ff WD |
3907 | |
3908 | DEBUGFUNC(); | |
3909 | ||
3910 | if (hw->mac_type >= e1000_82543) { | |
3911 | status = E1000_READ_REG(hw, STATUS); | |
3912 | if (status & E1000_STATUS_SPEED_1000) { | |
3913 | *speed = SPEED_1000; | |
3914 | DEBUGOUT("1000 Mbs, "); | |
3915 | } else if (status & E1000_STATUS_SPEED_100) { | |
3916 | *speed = SPEED_100; | |
3917 | DEBUGOUT("100 Mbs, "); | |
3918 | } else { | |
3919 | *speed = SPEED_10; | |
3920 | DEBUGOUT("10 Mbs, "); | |
3921 | } | |
3922 | ||
3923 | if (status & E1000_STATUS_FD) { | |
3924 | *duplex = FULL_DUPLEX; | |
3925 | DEBUGOUT("Full Duplex\r\n"); | |
3926 | } else { | |
3927 | *duplex = HALF_DUPLEX; | |
3928 | DEBUGOUT(" Half Duplex\r\n"); | |
3929 | } | |
3930 | } else { | |
3931 | DEBUGOUT("1000 Mbs, Full Duplex\r\n"); | |
3932 | *speed = SPEED_1000; | |
3933 | *duplex = FULL_DUPLEX; | |
3934 | } | |
aa070789 RZ |
3935 | |
3936 | /* IGP01 PHY may advertise full duplex operation after speed downgrade | |
3937 | * even if it is operating at half duplex. Here we set the duplex | |
3938 | * settings to match the duplex in the link partner's capabilities. | |
3939 | */ | |
3940 | if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { | |
3941 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); | |
3942 | if (ret_val) | |
3943 | return ret_val; | |
3944 | ||
3945 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) | |
3946 | *duplex = HALF_DUPLEX; | |
3947 | else { | |
3948 | ret_val = e1000_read_phy_reg(hw, | |
3949 | PHY_LP_ABILITY, &phy_data); | |
3950 | if (ret_val) | |
3951 | return ret_val; | |
3952 | if ((*speed == SPEED_100 && | |
3953 | !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) | |
3954 | || (*speed == SPEED_10 | |
3955 | && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) | |
3956 | *duplex = HALF_DUPLEX; | |
3957 | } | |
3958 | } | |
3959 | ||
3960 | if ((hw->mac_type == e1000_80003es2lan) && | |
3961 | (hw->media_type == e1000_media_type_copper)) { | |
3962 | if (*speed == SPEED_1000) | |
3963 | ret_val = e1000_configure_kmrn_for_1000(hw); | |
3964 | else | |
3965 | ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); | |
3966 | if (ret_val) | |
3967 | return ret_val; | |
3968 | } | |
3969 | return E1000_SUCCESS; | |
682011ff WD |
3970 | } |
3971 | ||
3972 | /****************************************************************************** | |
3973 | * Blocks until autoneg completes or times out (~4.5 seconds) | |
3974 | * | |
3975 | * hw - Struct containing variables accessed by shared code | |
3976 | ******************************************************************************/ | |
3977 | static int | |
3978 | e1000_wait_autoneg(struct e1000_hw *hw) | |
3979 | { | |
3980 | uint16_t i; | |
3981 | uint16_t phy_data; | |
3982 | ||
3983 | DEBUGFUNC(); | |
3984 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); | |
3985 | ||
faa765d4 | 3986 | /* We will wait for autoneg to complete or timeout to expire. */ |
682011ff WD |
3987 | for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
3988 | /* Read the MII Status Register and wait for Auto-Neg | |
3989 | * Complete bit to be set. | |
3990 | */ | |
3991 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { | |
3992 | DEBUGOUT("PHY Read Error\n"); | |
3993 | return -E1000_ERR_PHY; | |
3994 | } | |
3995 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { | |
3996 | DEBUGOUT("PHY Read Error\n"); | |
3997 | return -E1000_ERR_PHY; | |
3998 | } | |
3999 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { | |
4000 | DEBUGOUT("Auto-Neg complete.\n"); | |
4001 | return 0; | |
4002 | } | |
4003 | mdelay(100); | |
4004 | } | |
4005 | DEBUGOUT("Auto-Neg timedout.\n"); | |
4006 | return -E1000_ERR_TIMEOUT; | |
4007 | } | |
4008 | ||
4009 | /****************************************************************************** | |
4010 | * Raises the Management Data Clock | |
4011 | * | |
4012 | * hw - Struct containing variables accessed by shared code | |
4013 | * ctrl - Device control register's current value | |
4014 | ******************************************************************************/ | |
4015 | static void | |
4016 | e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) | |
4017 | { | |
4018 | /* Raise the clock input to the Management Data Clock (by setting the MDC | |
4019 | * bit), and then delay 2 microseconds. | |
4020 | */ | |
4021 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); | |
4022 | E1000_WRITE_FLUSH(hw); | |
4023 | udelay(2); | |
4024 | } | |
4025 | ||
4026 | /****************************************************************************** | |
4027 | * Lowers the Management Data Clock | |
4028 | * | |
4029 | * hw - Struct containing variables accessed by shared code | |
4030 | * ctrl - Device control register's current value | |
4031 | ******************************************************************************/ | |
4032 | static void | |
4033 | e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) | |
4034 | { | |
4035 | /* Lower the clock input to the Management Data Clock (by clearing the MDC | |
4036 | * bit), and then delay 2 microseconds. | |
4037 | */ | |
4038 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); | |
4039 | E1000_WRITE_FLUSH(hw); | |
4040 | udelay(2); | |
4041 | } | |
4042 | ||
4043 | /****************************************************************************** | |
4044 | * Shifts data bits out to the PHY | |
4045 | * | |
4046 | * hw - Struct containing variables accessed by shared code | |
4047 | * data - Data to send out to the PHY | |
4048 | * count - Number of bits to shift out | |
4049 | * | |
4050 | * Bits are shifted out in MSB to LSB order. | |
4051 | ******************************************************************************/ | |
4052 | static void | |
4053 | e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) | |
4054 | { | |
4055 | uint32_t ctrl; | |
4056 | uint32_t mask; | |
4057 | ||
4058 | /* We need to shift "count" number of bits out to the PHY. So, the value | |
8bde7f77 | 4059 | * in the "data" parameter will be shifted out to the PHY one bit at a |
682011ff WD |
4060 | * time. In order to do this, "data" must be broken down into bits. |
4061 | */ | |
4062 | mask = 0x01; | |
4063 | mask <<= (count - 1); | |
4064 | ||
4065 | ctrl = E1000_READ_REG(hw, CTRL); | |
4066 | ||
4067 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ | |
4068 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); | |
4069 | ||
4070 | while (mask) { | |
4071 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and | |
4072 | * then raising and lowering the Management Data Clock. A "0" is | |
4073 | * shifted out to the PHY by setting the MDIO bit to "0" and then | |
4074 | * raising and lowering the clock. | |
4075 | */ | |
4076 | if (data & mask) | |
4077 | ctrl |= E1000_CTRL_MDIO; | |
4078 | else | |
4079 | ctrl &= ~E1000_CTRL_MDIO; | |
4080 | ||
4081 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
4082 | E1000_WRITE_FLUSH(hw); | |
4083 | ||
4084 | udelay(2); | |
4085 | ||
4086 | e1000_raise_mdi_clk(hw, &ctrl); | |
4087 | e1000_lower_mdi_clk(hw, &ctrl); | |
4088 | ||
4089 | mask = mask >> 1; | |
4090 | } | |
4091 | } | |
4092 | ||
4093 | /****************************************************************************** | |
4094 | * Shifts data bits in from the PHY | |
4095 | * | |
4096 | * hw - Struct containing variables accessed by shared code | |
4097 | * | |
8bde7f77 | 4098 | * Bits are shifted in in MSB to LSB order. |
682011ff WD |
4099 | ******************************************************************************/ |
4100 | static uint16_t | |
4101 | e1000_shift_in_mdi_bits(struct e1000_hw *hw) | |
4102 | { | |
4103 | uint32_t ctrl; | |
4104 | uint16_t data = 0; | |
4105 | uint8_t i; | |
4106 | ||
4107 | /* In order to read a register from the PHY, we need to shift in a total | |
4108 | * of 18 bits from the PHY. The first two bit (turnaround) times are used | |
4109 | * to avoid contention on the MDIO pin when a read operation is performed. | |
4110 | * These two bits are ignored by us and thrown away. Bits are "shifted in" | |
4111 | * by raising the input to the Management Data Clock (setting the MDC bit), | |
4112 | * and then reading the value of the MDIO bit. | |
4113 | */ | |
4114 | ctrl = E1000_READ_REG(hw, CTRL); | |
4115 | ||
4116 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ | |
4117 | ctrl &= ~E1000_CTRL_MDIO_DIR; | |
4118 | ctrl &= ~E1000_CTRL_MDIO; | |
4119 | ||
4120 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
4121 | E1000_WRITE_FLUSH(hw); | |
4122 | ||
4123 | /* Raise and Lower the clock before reading in the data. This accounts for | |
4124 | * the turnaround bits. The first clock occurred when we clocked out the | |
4125 | * last bit of the Register Address. | |
4126 | */ | |
4127 | e1000_raise_mdi_clk(hw, &ctrl); | |
4128 | e1000_lower_mdi_clk(hw, &ctrl); | |
4129 | ||
4130 | for (data = 0, i = 0; i < 16; i++) { | |
4131 | data = data << 1; | |
4132 | e1000_raise_mdi_clk(hw, &ctrl); | |
4133 | ctrl = E1000_READ_REG(hw, CTRL); | |
4134 | /* Check to see if we shifted in a "1". */ | |
4135 | if (ctrl & E1000_CTRL_MDIO) | |
4136 | data |= 1; | |
4137 | e1000_lower_mdi_clk(hw, &ctrl); | |
4138 | } | |
4139 | ||
4140 | e1000_raise_mdi_clk(hw, &ctrl); | |
4141 | e1000_lower_mdi_clk(hw, &ctrl); | |
4142 | ||
4143 | return data; | |
4144 | } | |
4145 | ||
4146 | /***************************************************************************** | |
4147 | * Reads the value from a PHY register | |
4148 | * | |
4149 | * hw - Struct containing variables accessed by shared code | |
4150 | * reg_addr - address of the PHY register to read | |
4151 | ******************************************************************************/ | |
4152 | static int | |
4153 | e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) | |
4154 | { | |
4155 | uint32_t i; | |
4156 | uint32_t mdic = 0; | |
4157 | const uint32_t phy_addr = 1; | |
4158 | ||
4159 | if (reg_addr > MAX_PHY_REG_ADDRESS) { | |
4160 | DEBUGOUT("PHY Address %d is out of range\n", reg_addr); | |
4161 | return -E1000_ERR_PARAM; | |
4162 | } | |
4163 | ||
4164 | if (hw->mac_type > e1000_82543) { | |
4165 | /* Set up Op-code, Phy Address, and register address in the MDI | |
4166 | * Control register. The MAC will take care of interfacing with the | |
4167 | * PHY to retrieve the desired data. | |
4168 | */ | |
4169 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | | |
4170 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
4171 | (E1000_MDIC_OP_READ)); | |
4172 | ||
4173 | E1000_WRITE_REG(hw, MDIC, mdic); | |
4174 | ||
4175 | /* Poll the ready bit to see if the MDI read completed */ | |
4176 | for (i = 0; i < 64; i++) { | |
4177 | udelay(10); | |
4178 | mdic = E1000_READ_REG(hw, MDIC); | |
4179 | if (mdic & E1000_MDIC_READY) | |
4180 | break; | |
4181 | } | |
4182 | if (!(mdic & E1000_MDIC_READY)) { | |
4183 | DEBUGOUT("MDI Read did not complete\n"); | |
4184 | return -E1000_ERR_PHY; | |
4185 | } | |
4186 | if (mdic & E1000_MDIC_ERROR) { | |
4187 | DEBUGOUT("MDI Error\n"); | |
4188 | return -E1000_ERR_PHY; | |
4189 | } | |
4190 | *phy_data = (uint16_t) mdic; | |
4191 | } else { | |
4192 | /* We must first send a preamble through the MDIO pin to signal the | |
4193 | * beginning of an MII instruction. This is done by sending 32 | |
4194 | * consecutive "1" bits. | |
4195 | */ | |
4196 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
4197 | ||
4198 | /* Now combine the next few fields that are required for a read | |
4199 | * operation. We use this method instead of calling the | |
4200 | * e1000_shift_out_mdi_bits routine five different times. The format of | |
4201 | * a MII read instruction consists of a shift out of 14 bits and is | |
4202 | * defined as follows: | |
4203 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> | |
4204 | * followed by a shift in of 18 bits. This first two bits shifted in | |
4205 | * are TurnAround bits used to avoid contention on the MDIO pin when a | |
4206 | * READ operation is performed. These two bits are thrown away | |
4207 | * followed by a shift in of 16 bits which contains the desired data. | |
4208 | */ | |
4209 | mdic = ((reg_addr) | (phy_addr << 5) | | |
4210 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); | |
4211 | ||
4212 | e1000_shift_out_mdi_bits(hw, mdic, 14); | |
4213 | ||
4214 | /* Now that we've shifted out the read command to the MII, we need to | |
4215 | * "shift in" the 16-bit value (18 total bits) of the requested PHY | |
4216 | * register address. | |
4217 | */ | |
4218 | *phy_data = e1000_shift_in_mdi_bits(hw); | |
4219 | } | |
4220 | return 0; | |
4221 | } | |
4222 | ||
4223 | /****************************************************************************** | |
4224 | * Writes a value to a PHY register | |
4225 | * | |
4226 | * hw - Struct containing variables accessed by shared code | |
4227 | * reg_addr - address of the PHY register to write | |
4228 | * data - data to write to the PHY | |
4229 | ******************************************************************************/ | |
4230 | static int | |
4231 | e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) | |
4232 | { | |
4233 | uint32_t i; | |
4234 | uint32_t mdic = 0; | |
4235 | const uint32_t phy_addr = 1; | |
4236 | ||
4237 | if (reg_addr > MAX_PHY_REG_ADDRESS) { | |
4238 | DEBUGOUT("PHY Address %d is out of range\n", reg_addr); | |
4239 | return -E1000_ERR_PARAM; | |
4240 | } | |
4241 | ||
4242 | if (hw->mac_type > e1000_82543) { | |
4243 | /* Set up Op-code, Phy Address, register address, and data intended | |
4244 | * for the PHY register in the MDI Control register. The MAC will take | |
4245 | * care of interfacing with the PHY to send the desired data. | |
4246 | */ | |
4247 | mdic = (((uint32_t) phy_data) | | |
4248 | (reg_addr << E1000_MDIC_REG_SHIFT) | | |
4249 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
4250 | (E1000_MDIC_OP_WRITE)); | |
4251 | ||
4252 | E1000_WRITE_REG(hw, MDIC, mdic); | |
4253 | ||
4254 | /* Poll the ready bit to see if the MDI read completed */ | |
4255 | for (i = 0; i < 64; i++) { | |
4256 | udelay(10); | |
4257 | mdic = E1000_READ_REG(hw, MDIC); | |
4258 | if (mdic & E1000_MDIC_READY) | |
4259 | break; | |
4260 | } | |
4261 | if (!(mdic & E1000_MDIC_READY)) { | |
4262 | DEBUGOUT("MDI Write did not complete\n"); | |
4263 | return -E1000_ERR_PHY; | |
4264 | } | |
4265 | } else { | |
4266 | /* We'll need to use the SW defined pins to shift the write command | |
4267 | * out to the PHY. We first send a preamble to the PHY to signal the | |
8bde7f77 | 4268 | * beginning of the MII instruction. This is done by sending 32 |
682011ff WD |
4269 | * consecutive "1" bits. |
4270 | */ | |
4271 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
4272 | ||
8bde7f77 | 4273 | /* Now combine the remaining required fields that will indicate a |
682011ff WD |
4274 | * write operation. We use this method instead of calling the |
4275 | * e1000_shift_out_mdi_bits routine for each field in the command. The | |
4276 | * format of a MII write instruction is as follows: | |
4277 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. | |
4278 | */ | |
4279 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | | |
4280 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); | |
4281 | mdic <<= 16; | |
4282 | mdic |= (uint32_t) phy_data; | |
4283 | ||
4284 | e1000_shift_out_mdi_bits(hw, mdic, 32); | |
4285 | } | |
4286 | return 0; | |
4287 | } | |
4288 | ||
aa070789 RZ |
4289 | /****************************************************************************** |
4290 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. | |
4291 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to | |
4292 | * the caller to figure out how to deal with it. | |
4293 | * | |
4294 | * hw - Struct containing variables accessed by shared code | |
4295 | * | |
4296 | * returns: - E1000_BLK_PHY_RESET | |
4297 | * E1000_SUCCESS | |
4298 | * | |
4299 | *****************************************************************************/ | |
4300 | int32_t | |
4301 | e1000_check_phy_reset_block(struct e1000_hw *hw) | |
4302 | { | |
4303 | uint32_t manc = 0; | |
4304 | uint32_t fwsm = 0; | |
4305 | ||
4306 | if (hw->mac_type == e1000_ich8lan) { | |
4307 | fwsm = E1000_READ_REG(hw, FWSM); | |
4308 | return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS | |
4309 | : E1000_BLK_PHY_RESET; | |
4310 | } | |
4311 | ||
4312 | if (hw->mac_type > e1000_82547_rev_2) | |
4313 | manc = E1000_READ_REG(hw, MANC); | |
4314 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
4315 | E1000_BLK_PHY_RESET : E1000_SUCCESS; | |
4316 | } | |
4317 | ||
4318 | /*************************************************************************** | |
4319 | * Checks if the PHY configuration is done | |
4320 | * | |
4321 | * hw: Struct containing variables accessed by shared code | |
4322 | * | |
4323 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
4324 | * E1000_SUCCESS at any other case. | |
4325 | * | |
4326 | ***************************************************************************/ | |
4327 | static int32_t | |
4328 | e1000_get_phy_cfg_done(struct e1000_hw *hw) | |
4329 | { | |
4330 | int32_t timeout = PHY_CFG_TIMEOUT; | |
4331 | uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; | |
4332 | ||
4333 | DEBUGFUNC(); | |
4334 | ||
4335 | switch (hw->mac_type) { | |
4336 | default: | |
4337 | mdelay(10); | |
4338 | break; | |
987b43a1 | 4339 | |
aa070789 RZ |
4340 | case e1000_80003es2lan: |
4341 | /* Separate *_CFG_DONE_* bit for each port */ | |
987b43a1 | 4342 | if (e1000_is_second_port(hw)) |
aa070789 | 4343 | cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; |
987b43a1 KM |
4344 | /* Fall Through */ |
4345 | ||
aa070789 RZ |
4346 | case e1000_82571: |
4347 | case e1000_82572: | |
95186063 | 4348 | case e1000_igb: |
aa070789 | 4349 | while (timeout) { |
95186063 MV |
4350 | if (hw->mac_type == e1000_igb) { |
4351 | if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) | |
4352 | break; | |
4353 | } else { | |
4354 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) | |
4355 | break; | |
4356 | } | |
4357 | mdelay(1); | |
aa070789 RZ |
4358 | timeout--; |
4359 | } | |
4360 | if (!timeout) { | |
4361 | DEBUGOUT("MNG configuration cycle has not " | |
4362 | "completed.\n"); | |
4363 | return -E1000_ERR_RESET; | |
4364 | } | |
4365 | break; | |
4366 | } | |
4367 | ||
4368 | return E1000_SUCCESS; | |
4369 | } | |
4370 | ||
682011ff WD |
4371 | /****************************************************************************** |
4372 | * Returns the PHY to the power-on reset state | |
4373 | * | |
4374 | * hw - Struct containing variables accessed by shared code | |
4375 | ******************************************************************************/ | |
aa070789 | 4376 | int32_t |
682011ff WD |
4377 | e1000_phy_hw_reset(struct e1000_hw *hw) |
4378 | { | |
987b43a1 | 4379 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
aa070789 RZ |
4380 | uint32_t ctrl, ctrl_ext; |
4381 | uint32_t led_ctrl; | |
4382 | int32_t ret_val; | |
682011ff WD |
4383 | |
4384 | DEBUGFUNC(); | |
4385 | ||
aa070789 RZ |
4386 | /* In the case of the phy reset being blocked, it's not an error, we |
4387 | * simply return success without performing the reset. */ | |
4388 | ret_val = e1000_check_phy_reset_block(hw); | |
4389 | if (ret_val) | |
4390 | return E1000_SUCCESS; | |
4391 | ||
682011ff WD |
4392 | DEBUGOUT("Resetting Phy...\n"); |
4393 | ||
4394 | if (hw->mac_type > e1000_82543) { | |
987b43a1 | 4395 | if (e1000_is_second_port(hw)) |
aa070789 | 4396 | swfw = E1000_SWFW_PHY1_SM; |
987b43a1 | 4397 | |
aa070789 RZ |
4398 | if (e1000_swfw_sync_acquire(hw, swfw)) { |
4399 | DEBUGOUT("Unable to acquire swfw sync\n"); | |
4400 | return -E1000_ERR_SWFW_SYNC; | |
4401 | } | |
987b43a1 | 4402 | |
682011ff WD |
4403 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
4404 | * bit. Then, take it out of reset. | |
4405 | */ | |
4406 | ctrl = E1000_READ_REG(hw, CTRL); | |
4407 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); | |
4408 | E1000_WRITE_FLUSH(hw); | |
aa070789 RZ |
4409 | |
4410 | if (hw->mac_type < e1000_82571) | |
4411 | udelay(10); | |
4412 | else | |
4413 | udelay(100); | |
4414 | ||
682011ff WD |
4415 | E1000_WRITE_REG(hw, CTRL, ctrl); |
4416 | E1000_WRITE_FLUSH(hw); | |
aa070789 RZ |
4417 | |
4418 | if (hw->mac_type >= e1000_82571) | |
4419 | mdelay(10); | |
3c63dd53 | 4420 | |
682011ff WD |
4421 | } else { |
4422 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | |
4423 | * bit to put the PHY into reset. Then, take it out of reset. | |
4424 | */ | |
4425 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
4426 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; | |
4427 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; | |
4428 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
4429 | E1000_WRITE_FLUSH(hw); | |
4430 | mdelay(10); | |
4431 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; | |
4432 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
4433 | E1000_WRITE_FLUSH(hw); | |
4434 | } | |
4435 | udelay(150); | |
aa070789 RZ |
4436 | |
4437 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
4438 | /* Configure activity LED after PHY reset */ | |
4439 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
4440 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
4441 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
4442 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
4443 | } | |
4444 | ||
7e2d991d TH |
4445 | e1000_swfw_sync_release(hw, swfw); |
4446 | ||
aa070789 RZ |
4447 | /* Wait for FW to finish PHY configuration. */ |
4448 | ret_val = e1000_get_phy_cfg_done(hw); | |
4449 | if (ret_val != E1000_SUCCESS) | |
4450 | return ret_val; | |
4451 | ||
4452 | return ret_val; | |
4453 | } | |
4454 | ||
4455 | /****************************************************************************** | |
4456 | * IGP phy init script - initializes the GbE PHY | |
4457 | * | |
4458 | * hw - Struct containing variables accessed by shared code | |
4459 | *****************************************************************************/ | |
4460 | static void | |
4461 | e1000_phy_init_script(struct e1000_hw *hw) | |
4462 | { | |
4463 | uint32_t ret_val; | |
4464 | uint16_t phy_saved_data; | |
4465 | DEBUGFUNC(); | |
4466 | ||
4467 | if (hw->phy_init_script) { | |
4468 | mdelay(20); | |
4469 | ||
4470 | /* Save off the current value of register 0x2F5B to be | |
4471 | * restored at the end of this routine. */ | |
4472 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
4473 | ||
4474 | /* Disabled the PHY transmitter */ | |
4475 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
4476 | ||
4477 | mdelay(20); | |
4478 | ||
4479 | e1000_write_phy_reg(hw, 0x0000, 0x0140); | |
4480 | ||
4481 | mdelay(5); | |
4482 | ||
4483 | switch (hw->mac_type) { | |
4484 | case e1000_82541: | |
4485 | case e1000_82547: | |
4486 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); | |
4487 | ||
4488 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); | |
4489 | ||
4490 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); | |
4491 | ||
4492 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); | |
4493 | ||
4494 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); | |
4495 | ||
4496 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); | |
4497 | ||
4498 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); | |
4499 | ||
4500 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); | |
4501 | ||
4502 | e1000_write_phy_reg(hw, 0x2010, 0x0008); | |
4503 | break; | |
4504 | ||
4505 | case e1000_82541_rev_2: | |
4506 | case e1000_82547_rev_2: | |
4507 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); | |
4508 | break; | |
4509 | default: | |
4510 | break; | |
4511 | } | |
4512 | ||
4513 | e1000_write_phy_reg(hw, 0x0000, 0x3300); | |
4514 | ||
4515 | mdelay(20); | |
4516 | ||
4517 | /* Now enable the transmitter */ | |
56b13b1e ZRR |
4518 | if (!ret_val) |
4519 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
aa070789 RZ |
4520 | |
4521 | if (hw->mac_type == e1000_82547) { | |
4522 | uint16_t fused, fine, coarse; | |
4523 | ||
4524 | /* Move to analog registers page */ | |
4525 | e1000_read_phy_reg(hw, | |
4526 | IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); | |
4527 | ||
4528 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { | |
4529 | e1000_read_phy_reg(hw, | |
4530 | IGP01E1000_ANALOG_FUSE_STATUS, &fused); | |
4531 | ||
4532 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; | |
4533 | coarse = fused | |
4534 | & IGP01E1000_ANALOG_FUSE_COARSE_MASK; | |
4535 | ||
4536 | if (coarse > | |
4537 | IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { | |
4538 | coarse -= | |
4539 | IGP01E1000_ANALOG_FUSE_COARSE_10; | |
4540 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; | |
4541 | } else if (coarse | |
4542 | == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) | |
4543 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; | |
4544 | ||
4545 | fused = (fused | |
4546 | & IGP01E1000_ANALOG_FUSE_POLY_MASK) | | |
4547 | (fine | |
4548 | & IGP01E1000_ANALOG_FUSE_FINE_MASK) | | |
4549 | (coarse | |
4550 | & IGP01E1000_ANALOG_FUSE_COARSE_MASK); | |
4551 | ||
4552 | e1000_write_phy_reg(hw, | |
4553 | IGP01E1000_ANALOG_FUSE_CONTROL, fused); | |
4554 | e1000_write_phy_reg(hw, | |
4555 | IGP01E1000_ANALOG_FUSE_BYPASS, | |
4556 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); | |
4557 | } | |
4558 | } | |
4559 | } | |
682011ff WD |
4560 | } |
4561 | ||
4562 | /****************************************************************************** | |
4563 | * Resets the PHY | |
4564 | * | |
4565 | * hw - Struct containing variables accessed by shared code | |
4566 | * | |
aa070789 | 4567 | * Sets bit 15 of the MII Control register |
682011ff | 4568 | ******************************************************************************/ |
aa070789 | 4569 | int32_t |
682011ff WD |
4570 | e1000_phy_reset(struct e1000_hw *hw) |
4571 | { | |
aa070789 | 4572 | int32_t ret_val; |
682011ff WD |
4573 | uint16_t phy_data; |
4574 | ||
4575 | DEBUGFUNC(); | |
4576 | ||
aa070789 RZ |
4577 | /* In the case of the phy reset being blocked, it's not an error, we |
4578 | * simply return success without performing the reset. */ | |
4579 | ret_val = e1000_check_phy_reset_block(hw); | |
4580 | if (ret_val) | |
4581 | return E1000_SUCCESS; | |
4582 | ||
4583 | switch (hw->phy_type) { | |
4584 | case e1000_phy_igp: | |
4585 | case e1000_phy_igp_2: | |
4586 | case e1000_phy_igp_3: | |
4587 | case e1000_phy_ife: | |
95186063 | 4588 | case e1000_phy_igb: |
aa070789 RZ |
4589 | ret_val = e1000_phy_hw_reset(hw); |
4590 | if (ret_val) | |
4591 | return ret_val; | |
4592 | break; | |
4593 | default: | |
4594 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | |
4595 | if (ret_val) | |
4596 | return ret_val; | |
4597 | ||
4598 | phy_data |= MII_CR_RESET; | |
4599 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
4600 | if (ret_val) | |
4601 | return ret_val; | |
4602 | ||
4603 | udelay(1); | |
4604 | break; | |
682011ff | 4605 | } |
aa070789 RZ |
4606 | |
4607 | if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) | |
4608 | e1000_phy_init_script(hw); | |
4609 | ||
4610 | return E1000_SUCCESS; | |
682011ff WD |
4611 | } |
4612 | ||
1aeed8d7 | 4613 | static int e1000_set_phy_type (struct e1000_hw *hw) |
ac3315c2 | 4614 | { |
1aeed8d7 WD |
4615 | DEBUGFUNC (); |
4616 | ||
4617 | if (hw->mac_type == e1000_undefined) | |
4618 | return -E1000_ERR_PHY_TYPE; | |
4619 | ||
4620 | switch (hw->phy_id) { | |
4621 | case M88E1000_E_PHY_ID: | |
4622 | case M88E1000_I_PHY_ID: | |
4623 | case M88E1011_I_PHY_ID: | |
aa070789 | 4624 | case M88E1111_I_PHY_ID: |
1aeed8d7 WD |
4625 | hw->phy_type = e1000_phy_m88; |
4626 | break; | |
4627 | case IGP01E1000_I_PHY_ID: | |
4628 | if (hw->mac_type == e1000_82541 || | |
aa070789 RZ |
4629 | hw->mac_type == e1000_82541_rev_2 || |
4630 | hw->mac_type == e1000_82547 || | |
4631 | hw->mac_type == e1000_82547_rev_2) { | |
1aeed8d7 | 4632 | hw->phy_type = e1000_phy_igp; |
aa070789 RZ |
4633 | break; |
4634 | } | |
4635 | case IGP03E1000_E_PHY_ID: | |
4636 | hw->phy_type = e1000_phy_igp_3; | |
4637 | break; | |
4638 | case IFE_E_PHY_ID: | |
4639 | case IFE_PLUS_E_PHY_ID: | |
4640 | case IFE_C_E_PHY_ID: | |
4641 | hw->phy_type = e1000_phy_ife; | |
4642 | break; | |
4643 | case GG82563_E_PHY_ID: | |
4644 | if (hw->mac_type == e1000_80003es2lan) { | |
4645 | hw->phy_type = e1000_phy_gg82563; | |
1aeed8d7 WD |
4646 | break; |
4647 | } | |
2c2668f9 RZ |
4648 | case BME1000_E_PHY_ID: |
4649 | hw->phy_type = e1000_phy_bm; | |
4650 | break; | |
95186063 MV |
4651 | case I210_I_PHY_ID: |
4652 | hw->phy_type = e1000_phy_igb; | |
4653 | break; | |
1aeed8d7 WD |
4654 | /* Fall Through */ |
4655 | default: | |
4656 | /* Should never have loaded on this device */ | |
4657 | hw->phy_type = e1000_phy_undefined; | |
4658 | return -E1000_ERR_PHY_TYPE; | |
4659 | } | |
4660 | ||
4661 | return E1000_SUCCESS; | |
ac3315c2 AS |
4662 | } |
4663 | ||
682011ff WD |
4664 | /****************************************************************************** |
4665 | * Probes the expected PHY address for known PHY IDs | |
4666 | * | |
4667 | * hw - Struct containing variables accessed by shared code | |
4668 | ******************************************************************************/ | |
aa070789 | 4669 | static int32_t |
682011ff WD |
4670 | e1000_detect_gig_phy(struct e1000_hw *hw) |
4671 | { | |
aa070789 | 4672 | int32_t phy_init_status, ret_val; |
682011ff | 4673 | uint16_t phy_id_high, phy_id_low; |
472d5460 | 4674 | bool match = false; |
682011ff WD |
4675 | |
4676 | DEBUGFUNC(); | |
4677 | ||
aa070789 RZ |
4678 | /* The 82571 firmware may still be configuring the PHY. In this |
4679 | * case, we cannot access the PHY until the configuration is done. So | |
4680 | * we explicitly set the PHY values. */ | |
4681 | if (hw->mac_type == e1000_82571 || | |
4682 | hw->mac_type == e1000_82572) { | |
4683 | hw->phy_id = IGP01E1000_I_PHY_ID; | |
4684 | hw->phy_type = e1000_phy_igp_2; | |
4685 | return E1000_SUCCESS; | |
682011ff | 4686 | } |
aa070789 RZ |
4687 | |
4688 | /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a | |
4689 | * work- around that forces PHY page 0 to be set or the reads fail. | |
4690 | * The rest of the code in this routine uses e1000_read_phy_reg to | |
4691 | * read the PHY ID. So for ESB-2 we need to have this set so our | |
4692 | * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, | |
4693 | * the routines below will figure this out as well. */ | |
4694 | if (hw->mac_type == e1000_80003es2lan) | |
4695 | hw->phy_type = e1000_phy_gg82563; | |
4696 | ||
4697 | /* Read the PHY ID Registers to identify which PHY is onboard. */ | |
4698 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); | |
4699 | if (ret_val) | |
4700 | return ret_val; | |
4701 | ||
682011ff | 4702 | hw->phy_id = (uint32_t) (phy_id_high << 16); |
aa070789 RZ |
4703 | udelay(20); |
4704 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); | |
4705 | if (ret_val) | |
4706 | return ret_val; | |
4707 | ||
682011ff | 4708 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); |
aa070789 | 4709 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; |
682011ff WD |
4710 | |
4711 | switch (hw->mac_type) { | |
4712 | case e1000_82543: | |
4713 | if (hw->phy_id == M88E1000_E_PHY_ID) | |
472d5460 | 4714 | match = true; |
682011ff WD |
4715 | break; |
4716 | case e1000_82544: | |
4717 | if (hw->phy_id == M88E1000_I_PHY_ID) | |
472d5460 | 4718 | match = true; |
682011ff WD |
4719 | break; |
4720 | case e1000_82540: | |
4721 | case e1000_82545: | |
aa070789 | 4722 | case e1000_82545_rev_3: |
682011ff | 4723 | case e1000_82546: |
aa070789 | 4724 | case e1000_82546_rev_3: |
682011ff | 4725 | if (hw->phy_id == M88E1011_I_PHY_ID) |
472d5460 | 4726 | match = true; |
682011ff | 4727 | break; |
aa070789 | 4728 | case e1000_82541: |
ac3315c2 | 4729 | case e1000_82541_rev_2: |
aa070789 RZ |
4730 | case e1000_82547: |
4731 | case e1000_82547_rev_2: | |
ac3315c2 | 4732 | if(hw->phy_id == IGP01E1000_I_PHY_ID) |
472d5460 | 4733 | match = true; |
ac3315c2 AS |
4734 | |
4735 | break; | |
aa070789 RZ |
4736 | case e1000_82573: |
4737 | if (hw->phy_id == M88E1111_I_PHY_ID) | |
472d5460 | 4738 | match = true; |
aa070789 | 4739 | break; |
2c2668f9 RZ |
4740 | case e1000_82574: |
4741 | if (hw->phy_id == BME1000_E_PHY_ID) | |
472d5460 | 4742 | match = true; |
2c2668f9 | 4743 | break; |
aa070789 RZ |
4744 | case e1000_80003es2lan: |
4745 | if (hw->phy_id == GG82563_E_PHY_ID) | |
472d5460 | 4746 | match = true; |
aa070789 RZ |
4747 | break; |
4748 | case e1000_ich8lan: | |
4749 | if (hw->phy_id == IGP03E1000_E_PHY_ID) | |
472d5460 | 4750 | match = true; |
aa070789 | 4751 | if (hw->phy_id == IFE_E_PHY_ID) |
472d5460 | 4752 | match = true; |
aa070789 | 4753 | if (hw->phy_id == IFE_PLUS_E_PHY_ID) |
472d5460 | 4754 | match = true; |
aa070789 | 4755 | if (hw->phy_id == IFE_C_E_PHY_ID) |
472d5460 | 4756 | match = true; |
aa070789 | 4757 | break; |
95186063 MV |
4758 | case e1000_igb: |
4759 | if (hw->phy_id == I210_I_PHY_ID) | |
4760 | match = true; | |
4761 | break; | |
682011ff WD |
4762 | default: |
4763 | DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); | |
4764 | return -E1000_ERR_CONFIG; | |
4765 | } | |
ac3315c2 AS |
4766 | |
4767 | phy_init_status = e1000_set_phy_type(hw); | |
4768 | ||
4769 | if ((match) && (phy_init_status == E1000_SUCCESS)) { | |
682011ff WD |
4770 | DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); |
4771 | return 0; | |
4772 | } | |
4773 | DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); | |
4774 | return -E1000_ERR_PHY; | |
4775 | } | |
4776 | ||
aa070789 RZ |
4777 | /***************************************************************************** |
4778 | * Set media type and TBI compatibility. | |
4779 | * | |
4780 | * hw - Struct containing variables accessed by shared code | |
4781 | * **************************************************************************/ | |
4782 | void | |
4783 | e1000_set_media_type(struct e1000_hw *hw) | |
4784 | { | |
4785 | uint32_t status; | |
4786 | ||
4787 | DEBUGFUNC(); | |
4788 | ||
4789 | if (hw->mac_type != e1000_82543) { | |
4790 | /* tbi_compatibility is only valid on 82543 */ | |
472d5460 | 4791 | hw->tbi_compatibility_en = false; |
aa070789 RZ |
4792 | } |
4793 | ||
4794 | switch (hw->device_id) { | |
4795 | case E1000_DEV_ID_82545GM_SERDES: | |
4796 | case E1000_DEV_ID_82546GB_SERDES: | |
4797 | case E1000_DEV_ID_82571EB_SERDES: | |
4798 | case E1000_DEV_ID_82571EB_SERDES_DUAL: | |
4799 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
4800 | case E1000_DEV_ID_82572EI_SERDES: | |
4801 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
4802 | hw->media_type = e1000_media_type_internal_serdes; | |
4803 | break; | |
4804 | default: | |
4805 | switch (hw->mac_type) { | |
4806 | case e1000_82542_rev2_0: | |
4807 | case e1000_82542_rev2_1: | |
4808 | hw->media_type = e1000_media_type_fiber; | |
4809 | break; | |
4810 | case e1000_ich8lan: | |
4811 | case e1000_82573: | |
2c2668f9 | 4812 | case e1000_82574: |
95186063 | 4813 | case e1000_igb: |
aa070789 RZ |
4814 | /* The STATUS_TBIMODE bit is reserved or reused |
4815 | * for the this device. | |
4816 | */ | |
4817 | hw->media_type = e1000_media_type_copper; | |
4818 | break; | |
4819 | default: | |
4820 | status = E1000_READ_REG(hw, STATUS); | |
4821 | if (status & E1000_STATUS_TBIMODE) { | |
4822 | hw->media_type = e1000_media_type_fiber; | |
4823 | /* tbi_compatibility not valid on fiber */ | |
472d5460 | 4824 | hw->tbi_compatibility_en = false; |
aa070789 RZ |
4825 | } else { |
4826 | hw->media_type = e1000_media_type_copper; | |
4827 | } | |
4828 | break; | |
4829 | } | |
4830 | } | |
4831 | } | |
4832 | ||
682011ff WD |
4833 | /** |
4834 | * e1000_sw_init - Initialize general software structures (struct e1000_adapter) | |
4835 | * | |
4836 | * e1000_sw_init initializes the Adapter private data structure. | |
4837 | * Fields are initialized based on PCI device information and | |
4838 | * OS network device settings (MTU size). | |
4839 | **/ | |
4840 | ||
4841 | static int | |
5c5e707a | 4842 | e1000_sw_init(struct e1000_hw *hw) |
682011ff | 4843 | { |
682011ff WD |
4844 | int result; |
4845 | ||
4846 | /* PCI config space info */ | |
81dab9af BM |
4847 | #ifdef CONFIG_DM_ETH |
4848 | dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); | |
4849 | dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); | |
4850 | dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, | |
4851 | &hw->subsystem_vendor_id); | |
4852 | dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); | |
4853 | ||
4854 | dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); | |
4855 | dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); | |
4856 | #else | |
682011ff WD |
4857 | pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); |
4858 | pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); | |
4859 | pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, | |
4860 | &hw->subsystem_vendor_id); | |
4861 | pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); | |
4862 | ||
4863 | pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); | |
4864 | pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); | |
81dab9af | 4865 | #endif |
682011ff WD |
4866 | |
4867 | /* identify the MAC */ | |
4868 | result = e1000_set_mac_type(hw); | |
4869 | if (result) { | |
5c5e707a | 4870 | E1000_ERR(hw, "Unknown MAC Type\n"); |
682011ff WD |
4871 | return result; |
4872 | } | |
4873 | ||
aa070789 RZ |
4874 | switch (hw->mac_type) { |
4875 | default: | |
4876 | break; | |
4877 | case e1000_82541: | |
4878 | case e1000_82547: | |
4879 | case e1000_82541_rev_2: | |
4880 | case e1000_82547_rev_2: | |
4881 | hw->phy_init_script = 1; | |
4882 | break; | |
4883 | } | |
4884 | ||
682011ff WD |
4885 | /* flow control settings */ |
4886 | hw->fc_high_water = E1000_FC_HIGH_THRESH; | |
4887 | hw->fc_low_water = E1000_FC_LOW_THRESH; | |
4888 | hw->fc_pause_time = E1000_FC_PAUSE_TIME; | |
4889 | hw->fc_send_xon = 1; | |
4890 | ||
4891 | /* Media type - copper or fiber */ | |
95186063 | 4892 | hw->tbi_compatibility_en = true; |
aa070789 | 4893 | e1000_set_media_type(hw); |
682011ff WD |
4894 | |
4895 | if (hw->mac_type >= e1000_82543) { | |
4896 | uint32_t status = E1000_READ_REG(hw, STATUS); | |
4897 | ||
4898 | if (status & E1000_STATUS_TBIMODE) { | |
4899 | DEBUGOUT("fiber interface\n"); | |
4900 | hw->media_type = e1000_media_type_fiber; | |
4901 | } else { | |
4902 | DEBUGOUT("copper interface\n"); | |
4903 | hw->media_type = e1000_media_type_copper; | |
4904 | } | |
4905 | } else { | |
4906 | hw->media_type = e1000_media_type_fiber; | |
4907 | } | |
4908 | ||
472d5460 | 4909 | hw->wait_autoneg_complete = true; |
682011ff WD |
4910 | if (hw->mac_type < e1000_82543) |
4911 | hw->report_tx_early = 0; | |
4912 | else | |
4913 | hw->report_tx_early = 1; | |
4914 | ||
682011ff WD |
4915 | return E1000_SUCCESS; |
4916 | } | |
4917 | ||
4918 | void | |
4919 | fill_rx(struct e1000_hw *hw) | |
4920 | { | |
4921 | struct e1000_rx_desc *rd; | |
06e07f65 | 4922 | unsigned long flush_start, flush_end; |
682011ff WD |
4923 | |
4924 | rx_last = rx_tail; | |
4925 | rd = rx_base + rx_tail; | |
4926 | rx_tail = (rx_tail + 1) % 8; | |
4927 | memset(rd, 0, 16); | |
06e07f65 | 4928 | rd->buffer_addr = cpu_to_le64((unsigned long)packet); |
873e8e01 MV |
4929 | |
4930 | /* | |
4931 | * Make sure there are no stale data in WB over this area, which | |
4932 | * might get written into the memory while the e1000 also writes | |
4933 | * into the same memory area. | |
4934 | */ | |
06e07f65 ML |
4935 | invalidate_dcache_range((unsigned long)packet, |
4936 | (unsigned long)packet + 4096); | |
873e8e01 | 4937 | /* Dump the DMA descriptor into RAM. */ |
06e07f65 | 4938 | flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); |
873e8e01 MV |
4939 | flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); |
4940 | flush_dcache_range(flush_start, flush_end); | |
4941 | ||
682011ff WD |
4942 | E1000_WRITE_REG(hw, RDT, rx_tail); |
4943 | } | |
4944 | ||
4945 | /** | |
4946 | * e1000_configure_tx - Configure 8254x Transmit Unit after Reset | |
4947 | * @adapter: board private structure | |
4948 | * | |
4949 | * Configure the Tx unit of the MAC after a reset. | |
4950 | **/ | |
4951 | ||
4952 | static void | |
4953 | e1000_configure_tx(struct e1000_hw *hw) | |
4954 | { | |
682011ff | 4955 | unsigned long tctl; |
aa070789 RZ |
4956 | unsigned long tipg, tarc; |
4957 | uint32_t ipgr1, ipgr2; | |
682011ff | 4958 | |
1d8a078b BM |
4959 | E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base)); |
4960 | E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base)); | |
682011ff WD |
4961 | |
4962 | E1000_WRITE_REG(hw, TDLEN, 128); | |
4963 | ||
4964 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
4965 | E1000_WRITE_REG(hw, TDH, 0); | |
4966 | E1000_WRITE_REG(hw, TDT, 0); | |
4967 | tx_tail = 0; | |
4968 | ||
aa070789 RZ |
4969 | /* Set the default values for the Tx Inter Packet Gap timer */ |
4970 | if (hw->mac_type <= e1000_82547_rev_2 && | |
4971 | (hw->media_type == e1000_media_type_fiber || | |
4972 | hw->media_type == e1000_media_type_internal_serdes)) | |
4973 | tipg = DEFAULT_82543_TIPG_IPGT_FIBER; | |
4974 | else | |
4975 | tipg = DEFAULT_82543_TIPG_IPGT_COPPER; | |
4976 | ||
682011ff WD |
4977 | /* Set the default values for the Tx Inter Packet Gap timer */ |
4978 | switch (hw->mac_type) { | |
4979 | case e1000_82542_rev2_0: | |
4980 | case e1000_82542_rev2_1: | |
4981 | tipg = DEFAULT_82542_TIPG_IPGT; | |
aa070789 RZ |
4982 | ipgr1 = DEFAULT_82542_TIPG_IPGR1; |
4983 | ipgr2 = DEFAULT_82542_TIPG_IPGR2; | |
4984 | break; | |
4985 | case e1000_80003es2lan: | |
4986 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; | |
4987 | ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; | |
682011ff WD |
4988 | break; |
4989 | default: | |
aa070789 RZ |
4990 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; |
4991 | ipgr2 = DEFAULT_82543_TIPG_IPGR2; | |
4992 | break; | |
682011ff | 4993 | } |
aa070789 RZ |
4994 | tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; |
4995 | tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; | |
682011ff | 4996 | E1000_WRITE_REG(hw, TIPG, tipg); |
682011ff WD |
4997 | /* Program the Transmit Control Register */ |
4998 | tctl = E1000_READ_REG(hw, TCTL); | |
4999 | tctl &= ~E1000_TCTL_CT; | |
5000 | tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | | |
5001 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
aa070789 RZ |
5002 | |
5003 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { | |
5004 | tarc = E1000_READ_REG(hw, TARC0); | |
5005 | /* set the speed mode bit, we'll clear it if we're not at | |
5006 | * gigabit link later */ | |
5007 | /* git bit can be set to 1*/ | |
5008 | } else if (hw->mac_type == e1000_80003es2lan) { | |
5009 | tarc = E1000_READ_REG(hw, TARC0); | |
5010 | tarc |= 1; | |
5011 | E1000_WRITE_REG(hw, TARC0, tarc); | |
5012 | tarc = E1000_READ_REG(hw, TARC1); | |
5013 | tarc |= 1; | |
5014 | E1000_WRITE_REG(hw, TARC1, tarc); | |
5015 | } | |
5016 | ||
682011ff WD |
5017 | |
5018 | e1000_config_collision_dist(hw); | |
aa070789 RZ |
5019 | /* Setup Transmit Descriptor Settings for eop descriptor */ |
5020 | hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; | |
682011ff | 5021 | |
aa070789 RZ |
5022 | /* Need to set up RS bit */ |
5023 | if (hw->mac_type < e1000_82543) | |
5024 | hw->txd_cmd |= E1000_TXD_CMD_RPS; | |
682011ff | 5025 | else |
aa070789 | 5026 | hw->txd_cmd |= E1000_TXD_CMD_RS; |
95186063 MV |
5027 | |
5028 | ||
5029 | if (hw->mac_type == e1000_igb) { | |
5030 | E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); | |
5031 | ||
5032 | uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); | |
5033 | reg_txdctl |= 1 << 25; | |
5034 | E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); | |
5035 | mdelay(20); | |
5036 | } | |
5037 | ||
5038 | ||
5039 | ||
aa070789 | 5040 | E1000_WRITE_REG(hw, TCTL, tctl); |
95186063 MV |
5041 | |
5042 | ||
682011ff WD |
5043 | } |
5044 | ||
5045 | /** | |
5046 | * e1000_setup_rctl - configure the receive control register | |
5047 | * @adapter: Board private structure | |
5048 | **/ | |
5049 | static void | |
5050 | e1000_setup_rctl(struct e1000_hw *hw) | |
5051 | { | |
5052 | uint32_t rctl; | |
5053 | ||
5054 | rctl = E1000_READ_REG(hw, RCTL); | |
5055 | ||
5056 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
5057 | ||
aa070789 RZ |
5058 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
5059 | | E1000_RCTL_RDMTS_HALF; /* | | |
5060 | (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ | |
682011ff WD |
5061 | |
5062 | if (hw->tbi_compatibility_on == 1) | |
5063 | rctl |= E1000_RCTL_SBP; | |
5064 | else | |
5065 | rctl &= ~E1000_RCTL_SBP; | |
5066 | ||
5067 | rctl &= ~(E1000_RCTL_SZ_4096); | |
682011ff WD |
5068 | rctl |= E1000_RCTL_SZ_2048; |
5069 | rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); | |
682011ff WD |
5070 | E1000_WRITE_REG(hw, RCTL, rctl); |
5071 | } | |
5072 | ||
5073 | /** | |
5074 | * e1000_configure_rx - Configure 8254x Receive Unit after Reset | |
5075 | * @adapter: board private structure | |
5076 | * | |
5077 | * Configure the Rx unit of the MAC after a reset. | |
5078 | **/ | |
5079 | static void | |
5080 | e1000_configure_rx(struct e1000_hw *hw) | |
5081 | { | |
aa070789 | 5082 | unsigned long rctl, ctrl_ext; |
682011ff | 5083 | rx_tail = 0; |
1d8a078b | 5084 | |
682011ff WD |
5085 | /* make sure receives are disabled while setting up the descriptors */ |
5086 | rctl = E1000_READ_REG(hw, RCTL); | |
5087 | E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); | |
682011ff | 5088 | if (hw->mac_type >= e1000_82540) { |
682011ff WD |
5089 | /* Set the interrupt throttling rate. Value is calculated |
5090 | * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ | |
1aeed8d7 WD |
5091 | #define MAX_INTS_PER_SEC 8000 |
5092 | #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) | |
682011ff WD |
5093 | E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); |
5094 | } | |
5095 | ||
aa070789 RZ |
5096 | if (hw->mac_type >= e1000_82571) { |
5097 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
5098 | /* Reset delay timers after every interrupt */ | |
5099 | ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; | |
5100 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
5101 | E1000_WRITE_FLUSH(hw); | |
5102 | } | |
682011ff | 5103 | /* Setup the Base and Length of the Rx Descriptor Ring */ |
1d8a078b BM |
5104 | E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base)); |
5105 | E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base)); | |
682011ff WD |
5106 | |
5107 | E1000_WRITE_REG(hw, RDLEN, 128); | |
5108 | ||
5109 | /* Setup the HW Rx Head and Tail Descriptor Pointers */ | |
5110 | E1000_WRITE_REG(hw, RDH, 0); | |
5111 | E1000_WRITE_REG(hw, RDT, 0); | |
682011ff WD |
5112 | /* Enable Receives */ |
5113 | ||
95186063 MV |
5114 | if (hw->mac_type == e1000_igb) { |
5115 | ||
5116 | uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); | |
5117 | reg_rxdctl |= 1 << 25; | |
5118 | E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); | |
5119 | mdelay(20); | |
5120 | } | |
5121 | ||
682011ff | 5122 | E1000_WRITE_REG(hw, RCTL, rctl); |
95186063 | 5123 | |
682011ff WD |
5124 | fill_rx(hw); |
5125 | } | |
5126 | ||
5127 | /************************************************************************** | |
5128 | POLL - Wait for a frame | |
5129 | ***************************************************************************/ | |
5130 | static int | |
5c5e707a | 5131 | _e1000_poll(struct e1000_hw *hw) |
682011ff | 5132 | { |
682011ff | 5133 | struct e1000_rx_desc *rd; |
06e07f65 | 5134 | unsigned long inval_start, inval_end; |
873e8e01 MV |
5135 | uint32_t len; |
5136 | ||
682011ff WD |
5137 | /* return true if there's an ethernet packet ready to read */ |
5138 | rd = rx_base + rx_last; | |
873e8e01 MV |
5139 | |
5140 | /* Re-load the descriptor from RAM. */ | |
06e07f65 | 5141 | inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); |
873e8e01 MV |
5142 | inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); |
5143 | invalidate_dcache_range(inval_start, inval_end); | |
5144 | ||
a40b2dff | 5145 | if (!(rd->status & E1000_RXD_STAT_DD)) |
682011ff | 5146 | return 0; |
5abf13e4 | 5147 | /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ |
873e8e01 | 5148 | /* Packet received, make sure the data are re-loaded from RAM. */ |
a40b2dff | 5149 | len = le16_to_cpu(rd->length); |
06e07f65 ML |
5150 | invalidate_dcache_range((unsigned long)packet, |
5151 | (unsigned long)packet + | |
5152 | roundup(len, ARCH_DMA_MINALIGN)); | |
5c5e707a | 5153 | return len; |
682011ff WD |
5154 | } |
5155 | ||
5c5e707a | 5156 | static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) |
682011ff | 5157 | { |
873e8e01 | 5158 | void *nv_packet = (void *)txpacket; |
682011ff WD |
5159 | struct e1000_tx_desc *txp; |
5160 | int i = 0; | |
06e07f65 | 5161 | unsigned long flush_start, flush_end; |
682011ff WD |
5162 | |
5163 | txp = tx_base + tx_tail; | |
5164 | tx_tail = (tx_tail + 1) % 8; | |
5165 | ||
8aa858cb | 5166 | txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); |
aa070789 | 5167 | txp->lower.data = cpu_to_le32(hw->txd_cmd | length); |
682011ff | 5168 | txp->upper.data = 0; |
873e8e01 MV |
5169 | |
5170 | /* Dump the packet into RAM so e1000 can pick them. */ | |
06e07f65 ML |
5171 | flush_dcache_range((unsigned long)nv_packet, |
5172 | (unsigned long)nv_packet + | |
5173 | roundup(length, ARCH_DMA_MINALIGN)); | |
873e8e01 | 5174 | /* Dump the descriptor into RAM as well. */ |
06e07f65 | 5175 | flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); |
873e8e01 MV |
5176 | flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); |
5177 | flush_dcache_range(flush_start, flush_end); | |
5178 | ||
682011ff WD |
5179 | E1000_WRITE_REG(hw, TDT, tx_tail); |
5180 | ||
aa070789 | 5181 | E1000_WRITE_FLUSH(hw); |
873e8e01 MV |
5182 | while (1) { |
5183 | invalidate_dcache_range(flush_start, flush_end); | |
5184 | if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) | |
5185 | break; | |
682011ff WD |
5186 | if (i++ > TOUT_LOOP) { |
5187 | DEBUGOUT("e1000: tx timeout\n"); | |
5188 | return 0; | |
5189 | } | |
5190 | udelay(10); /* give the nic a chance to write to the register */ | |
5191 | } | |
5192 | return 1; | |
5193 | } | |
5194 | ||
682011ff | 5195 | static void |
5c5e707a | 5196 | _e1000_disable(struct e1000_hw *hw) |
682011ff | 5197 | { |
682011ff WD |
5198 | /* Turn off the ethernet interface */ |
5199 | E1000_WRITE_REG(hw, RCTL, 0); | |
5200 | E1000_WRITE_REG(hw, TCTL, 0); | |
5201 | ||
5202 | /* Clear the transmit ring */ | |
5203 | E1000_WRITE_REG(hw, TDH, 0); | |
5204 | E1000_WRITE_REG(hw, TDT, 0); | |
5205 | ||
5206 | /* Clear the receive ring */ | |
5207 | E1000_WRITE_REG(hw, RDH, 0); | |
5208 | E1000_WRITE_REG(hw, RDT, 0); | |
5209 | ||
682011ff | 5210 | mdelay(10); |
5c5e707a | 5211 | } |
682011ff | 5212 | |
5c5e707a SG |
5213 | /*reset function*/ |
5214 | static inline int | |
5215 | e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) | |
5216 | { | |
5217 | e1000_reset_hw(hw); | |
5218 | if (hw->mac_type >= e1000_82544) | |
5219 | E1000_WRITE_REG(hw, WUC, 0); | |
5220 | ||
5221 | return e1000_init_hw(hw, enetaddr); | |
682011ff WD |
5222 | } |
5223 | ||
682011ff | 5224 | static int |
5c5e707a | 5225 | _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) |
682011ff | 5226 | { |
682011ff WD |
5227 | int ret_val = 0; |
5228 | ||
5c5e707a | 5229 | ret_val = e1000_reset(hw, enetaddr); |
682011ff WD |
5230 | if (ret_val < 0) { |
5231 | if ((ret_val == -E1000_ERR_NOLINK) || | |
5232 | (ret_val == -E1000_ERR_TIMEOUT)) { | |
5c5e707a | 5233 | E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); |
682011ff | 5234 | } else { |
5c5e707a | 5235 | E1000_ERR(hw, "Hardware Initialization Failed\n"); |
682011ff | 5236 | } |
5c5e707a | 5237 | return ret_val; |
682011ff WD |
5238 | } |
5239 | e1000_configure_tx(hw); | |
5240 | e1000_setup_rctl(hw); | |
5241 | e1000_configure_rx(hw); | |
5c5e707a | 5242 | return 0; |
682011ff WD |
5243 | } |
5244 | ||
aa070789 RZ |
5245 | /****************************************************************************** |
5246 | * Gets the current PCI bus type of hardware | |
5247 | * | |
5248 | * hw - Struct containing variables accessed by shared code | |
5249 | *****************************************************************************/ | |
5250 | void e1000_get_bus_type(struct e1000_hw *hw) | |
5251 | { | |
5252 | uint32_t status; | |
5253 | ||
5254 | switch (hw->mac_type) { | |
5255 | case e1000_82542_rev2_0: | |
5256 | case e1000_82542_rev2_1: | |
5257 | hw->bus_type = e1000_bus_type_pci; | |
5258 | break; | |
5259 | case e1000_82571: | |
5260 | case e1000_82572: | |
5261 | case e1000_82573: | |
2c2668f9 | 5262 | case e1000_82574: |
aa070789 | 5263 | case e1000_80003es2lan: |
aa070789 | 5264 | case e1000_ich8lan: |
95186063 | 5265 | case e1000_igb: |
aa070789 RZ |
5266 | hw->bus_type = e1000_bus_type_pci_express; |
5267 | break; | |
5268 | default: | |
5269 | status = E1000_READ_REG(hw, STATUS); | |
5270 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? | |
5271 | e1000_bus_type_pcix : e1000_bus_type_pci; | |
5272 | break; | |
5273 | } | |
5274 | } | |
5275 | ||
c6d80a15 | 5276 | #ifndef CONFIG_DM_ETH |
ce5207e1 KM |
5277 | /* A list of all registered e1000 devices */ |
5278 | static LIST_HEAD(e1000_hw_list); | |
c6d80a15 | 5279 | #endif |
ce5207e1 | 5280 | |
81dab9af BM |
5281 | #ifdef CONFIG_DM_ETH |
5282 | static int e1000_init_one(struct e1000_hw *hw, int cardnum, | |
5283 | struct udevice *devno, unsigned char enetaddr[6]) | |
5284 | #else | |
5c5e707a SG |
5285 | static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, |
5286 | unsigned char enetaddr[6]) | |
81dab9af | 5287 | #endif |
5c5e707a SG |
5288 | { |
5289 | u32 val; | |
5290 | ||
5291 | /* Assign the passed-in values */ | |
81dab9af | 5292 | #ifdef CONFIG_DM_ETH |
5c5e707a | 5293 | hw->pdev = devno; |
81dab9af BM |
5294 | #else |
5295 | hw->pdev = devno; | |
5296 | #endif | |
5c5e707a SG |
5297 | hw->cardnum = cardnum; |
5298 | ||
5299 | /* Print a debug message with the IO base address */ | |
81dab9af BM |
5300 | #ifdef CONFIG_DM_ETH |
5301 | dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val); | |
5302 | #else | |
5c5e707a | 5303 | pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); |
81dab9af | 5304 | #endif |
5c5e707a SG |
5305 | E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); |
5306 | ||
5307 | /* Try to enable I/O accesses and bus-mastering */ | |
5308 | val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
81dab9af BM |
5309 | #ifdef CONFIG_DM_ETH |
5310 | dm_pci_write_config32(devno, PCI_COMMAND, val); | |
5311 | #else | |
5c5e707a | 5312 | pci_write_config_dword(devno, PCI_COMMAND, val); |
81dab9af | 5313 | #endif |
5c5e707a SG |
5314 | |
5315 | /* Make sure it worked */ | |
81dab9af BM |
5316 | #ifdef CONFIG_DM_ETH |
5317 | dm_pci_read_config32(devno, PCI_COMMAND, &val); | |
5318 | #else | |
5c5e707a | 5319 | pci_read_config_dword(devno, PCI_COMMAND, &val); |
81dab9af | 5320 | #endif |
5c5e707a SG |
5321 | if (!(val & PCI_COMMAND_MEMORY)) { |
5322 | E1000_ERR(hw, "Can't enable I/O memory\n"); | |
5323 | return -ENOSPC; | |
5324 | } | |
5325 | if (!(val & PCI_COMMAND_MASTER)) { | |
5326 | E1000_ERR(hw, "Can't enable bus-mastering\n"); | |
5327 | return -EPERM; | |
5328 | } | |
5329 | ||
5330 | /* Are these variables needed? */ | |
5331 | hw->fc = e1000_fc_default; | |
5332 | hw->original_fc = e1000_fc_default; | |
5333 | hw->autoneg_failed = 0; | |
5334 | hw->autoneg = 1; | |
5335 | hw->get_link_status = true; | |
5336 | #ifndef CONFIG_E1000_NO_NVM | |
5337 | hw->eeprom_semaphore_present = true; | |
5338 | #endif | |
81dab9af BM |
5339 | #ifdef CONFIG_DM_ETH |
5340 | hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, | |
5341 | PCI_REGION_MEM); | |
5342 | #else | |
5c5e707a SG |
5343 | hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, |
5344 | PCI_REGION_MEM); | |
81dab9af | 5345 | #endif |
5c5e707a SG |
5346 | hw->mac_type = e1000_undefined; |
5347 | ||
5348 | /* MAC and Phy settings */ | |
5349 | if (e1000_sw_init(hw) < 0) { | |
5350 | E1000_ERR(hw, "Software init failed\n"); | |
5351 | return -EIO; | |
5352 | } | |
5353 | if (e1000_check_phy_reset_block(hw)) | |
5354 | E1000_ERR(hw, "PHY Reset is blocked!\n"); | |
5355 | ||
5356 | /* Basic init was OK, reset the hardware and allow SPI access */ | |
5357 | e1000_reset_hw(hw); | |
5358 | ||
5359 | #ifndef CONFIG_E1000_NO_NVM | |
5360 | /* Validate the EEPROM and get chipset information */ | |
5c5e707a SG |
5361 | if (e1000_init_eeprom_params(hw)) { |
5362 | E1000_ERR(hw, "EEPROM is invalid!\n"); | |
5363 | return -EINVAL; | |
5364 | } | |
5365 | if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && | |
5366 | e1000_validate_eeprom_checksum(hw)) | |
5367 | return -ENXIO; | |
5c5e707a SG |
5368 | e1000_read_mac_addr(hw, enetaddr); |
5369 | #endif | |
5370 | e1000_get_bus_type(hw); | |
5371 | ||
5372 | #ifndef CONFIG_E1000_NO_NVM | |
5373 | printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", | |
5374 | enetaddr[0], enetaddr[1], enetaddr[2], | |
5375 | enetaddr[3], enetaddr[4], enetaddr[5]); | |
5376 | #else | |
5377 | memset(enetaddr, 0, 6); | |
5378 | printf("e1000: no NVM\n"); | |
5379 | #endif | |
5380 | ||
5381 | return 0; | |
5382 | } | |
5383 | ||
5384 | /* Put the name of a device in a string */ | |
5385 | static void e1000_name(char *str, int cardnum) | |
5386 | { | |
5387 | sprintf(str, "e1000#%u", cardnum); | |
5388 | } | |
5389 | ||
c6d80a15 | 5390 | #ifndef CONFIG_DM_ETH |
5c5e707a SG |
5391 | /************************************************************************** |
5392 | TRANSMIT - Transmit a frame | |
5393 | ***************************************************************************/ | |
5394 | static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) | |
5395 | { | |
5396 | struct e1000_hw *hw = nic->priv; | |
5397 | ||
5398 | return _e1000_transmit(hw, txpacket, length); | |
5399 | } | |
5400 | ||
5401 | /************************************************************************** | |
5402 | DISABLE - Turn off ethernet interface | |
5403 | ***************************************************************************/ | |
5404 | static void | |
5405 | e1000_disable(struct eth_device *nic) | |
5406 | { | |
5407 | struct e1000_hw *hw = nic->priv; | |
5408 | ||
5409 | _e1000_disable(hw); | |
5410 | } | |
5411 | ||
5412 | /************************************************************************** | |
5413 | INIT - set up ethernet interface(s) | |
5414 | ***************************************************************************/ | |
5415 | static int | |
5416 | e1000_init(struct eth_device *nic, bd_t *bis) | |
5417 | { | |
5418 | struct e1000_hw *hw = nic->priv; | |
5419 | ||
5420 | return _e1000_init(hw, nic->enetaddr); | |
5421 | } | |
5422 | ||
5423 | static int | |
5424 | e1000_poll(struct eth_device *nic) | |
5425 | { | |
5426 | struct e1000_hw *hw = nic->priv; | |
5427 | int len; | |
5428 | ||
5429 | len = _e1000_poll(hw); | |
5430 | if (len) { | |
5431 | net_process_received_packet((uchar *)packet, len); | |
5432 | fill_rx(hw); | |
5433 | } | |
5434 | ||
5435 | return len ? 1 : 0; | |
5436 | } | |
5437 | ||
682011ff WD |
5438 | /************************************************************************** |
5439 | PROBE - Look for an adapter, this routine's visible to the outside | |
5440 | You should omit the last argument struct pci_device * for a non-PCI NIC | |
5441 | ***************************************************************************/ | |
5442 | int | |
5443 | e1000_initialize(bd_t * bis) | |
5444 | { | |
d60626f8 | 5445 | unsigned int i; |
682011ff | 5446 | pci_dev_t devno; |
5c5e707a | 5447 | int ret; |
682011ff | 5448 | |
f81ecb5d TT |
5449 | DEBUGFUNC(); |
5450 | ||
d60626f8 KM |
5451 | /* Find and probe all the matching PCI devices */ |
5452 | for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { | |
d60626f8 KM |
5453 | /* |
5454 | * These will never get freed due to errors, this allows us to | |
a187559e | 5455 | * perform SPI EEPROM programming from U-Boot, for example. |
d60626f8 KM |
5456 | */ |
5457 | struct eth_device *nic = malloc(sizeof(*nic)); | |
5458 | struct e1000_hw *hw = malloc(sizeof(*hw)); | |
5459 | if (!nic || !hw) { | |
5460 | printf("e1000#%u: Out of Memory!\n", i); | |
4b29bdb0 | 5461 | free(nic); |
d60626f8 KM |
5462 | free(hw); |
5463 | continue; | |
4b29bdb0 KG |
5464 | } |
5465 | ||
d60626f8 | 5466 | /* Make sure all of the fields are initially zeroed */ |
f7ac99fd | 5467 | memset(nic, 0, sizeof(*nic)); |
4b29bdb0 | 5468 | memset(hw, 0, sizeof(*hw)); |
682011ff | 5469 | nic->priv = hw; |
682011ff | 5470 | |
d60626f8 | 5471 | /* Generate a card name */ |
5c5e707a SG |
5472 | e1000_name(nic->name, i); |
5473 | hw->name = nic->name; | |
682011ff | 5474 | |
5c5e707a SG |
5475 | ret = e1000_init_one(hw, i, devno, nic->enetaddr); |
5476 | if (ret) | |
d60626f8 | 5477 | continue; |
ce5207e1 | 5478 | list_add_tail(&hw->list_node, &e1000_hw_list); |
d60626f8 | 5479 | |
5c5e707a | 5480 | hw->nic = nic; |
682011ff | 5481 | |
d60626f8 | 5482 | /* Set up the function pointers and register the device */ |
682011ff WD |
5483 | nic->init = e1000_init; |
5484 | nic->recv = e1000_poll; | |
5485 | nic->send = e1000_transmit; | |
5486 | nic->halt = e1000_disable; | |
682011ff | 5487 | eth_register(nic); |
682011ff | 5488 | } |
d60626f8 KM |
5489 | |
5490 | return i; | |
682011ff | 5491 | } |
ce5207e1 KM |
5492 | |
5493 | struct e1000_hw *e1000_find_card(unsigned int cardnum) | |
5494 | { | |
5495 | struct e1000_hw *hw; | |
5496 | ||
5497 | list_for_each_entry(hw, &e1000_hw_list, list_node) | |
5498 | if (hw->cardnum == cardnum) | |
5499 | return hw; | |
5500 | ||
5501 | return NULL; | |
5502 | } | |
c6d80a15 | 5503 | #endif /* !CONFIG_DM_ETH */ |
ce5207e1 KM |
5504 | |
5505 | #ifdef CONFIG_CMD_E1000 | |
5506 | static int do_e1000(cmd_tbl_t *cmdtp, int flag, | |
5507 | int argc, char * const argv[]) | |
5508 | { | |
5c5e707a | 5509 | unsigned char *mac = NULL; |
c6d80a15 SG |
5510 | #ifdef CONFIG_DM_ETH |
5511 | struct eth_pdata *plat; | |
5512 | struct udevice *dev; | |
5513 | char name[30]; | |
5514 | int ret; | |
eb4e8ceb AB |
5515 | #endif |
5516 | #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI) | |
ce5207e1 | 5517 | struct e1000_hw *hw; |
c6d80a15 SG |
5518 | #endif |
5519 | int cardnum; | |
ce5207e1 KM |
5520 | |
5521 | if (argc < 3) { | |
5522 | cmd_usage(cmdtp); | |
5523 | return 1; | |
5524 | } | |
5525 | ||
5526 | /* Make sure we can find the requested e1000 card */ | |
5c5e707a | 5527 | cardnum = simple_strtoul(argv[1], NULL, 10); |
c6d80a15 SG |
5528 | #ifdef CONFIG_DM_ETH |
5529 | e1000_name(name, cardnum); | |
5530 | ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); | |
5531 | if (!ret) { | |
5532 | plat = dev_get_platdata(dev); | |
5533 | mac = plat->enetaddr; | |
5534 | } | |
5535 | #else | |
5c5e707a SG |
5536 | hw = e1000_find_card(cardnum); |
5537 | if (hw) | |
5538 | mac = hw->nic->enetaddr; | |
c6d80a15 | 5539 | #endif |
5c5e707a | 5540 | if (!mac) { |
ce5207e1 KM |
5541 | printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); |
5542 | return 1; | |
5543 | } | |
5544 | ||
5545 | if (!strcmp(argv[2], "print-mac-address")) { | |
ce5207e1 KM |
5546 | printf("%02x:%02x:%02x:%02x:%02x:%02x\n", |
5547 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | |
5548 | return 0; | |
5549 | } | |
5550 | ||
5551 | #ifdef CONFIG_E1000_SPI | |
eb4e8ceb AB |
5552 | #ifdef CONFIG_DM_ETH |
5553 | hw = dev_get_priv(dev); | |
5554 | #endif | |
ce5207e1 KM |
5555 | /* Handle the "SPI" subcommand */ |
5556 | if (!strcmp(argv[2], "spi")) | |
5557 | return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); | |
5558 | #endif | |
5559 | ||
5560 | cmd_usage(cmdtp); | |
5561 | return 1; | |
5562 | } | |
5563 | ||
5564 | U_BOOT_CMD( | |
5565 | e1000, 7, 0, do_e1000, | |
5566 | "Intel e1000 controller management", | |
5567 | /* */"<card#> print-mac-address\n" | |
5568 | #ifdef CONFIG_E1000_SPI | |
5569 | "e1000 <card#> spi show [<offset> [<length>]]\n" | |
5570 | "e1000 <card#> spi dump <addr> <offset> <length>\n" | |
5571 | "e1000 <card#> spi program <addr> <offset> <length>\n" | |
5572 | "e1000 <card#> spi checksum [update]\n" | |
5573 | #endif | |
5574 | " - Manage the Intel E1000 PCI device" | |
5575 | ); | |
5576 | #endif /* not CONFIG_CMD_E1000 */ | |
c6d80a15 SG |
5577 | |
5578 | #ifdef CONFIG_DM_ETH | |
5579 | static int e1000_eth_start(struct udevice *dev) | |
5580 | { | |
5581 | struct eth_pdata *plat = dev_get_platdata(dev); | |
5582 | struct e1000_hw *hw = dev_get_priv(dev); | |
5583 | ||
5584 | return _e1000_init(hw, plat->enetaddr); | |
5585 | } | |
5586 | ||
5587 | static void e1000_eth_stop(struct udevice *dev) | |
5588 | { | |
5589 | struct e1000_hw *hw = dev_get_priv(dev); | |
5590 | ||
5591 | _e1000_disable(hw); | |
5592 | } | |
5593 | ||
5594 | static int e1000_eth_send(struct udevice *dev, void *packet, int length) | |
5595 | { | |
5596 | struct e1000_hw *hw = dev_get_priv(dev); | |
5597 | int ret; | |
5598 | ||
5599 | ret = _e1000_transmit(hw, packet, length); | |
5600 | ||
5601 | return ret ? 0 : -ETIMEDOUT; | |
5602 | } | |
5603 | ||
5604 | static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) | |
5605 | { | |
5606 | struct e1000_hw *hw = dev_get_priv(dev); | |
5607 | int len; | |
5608 | ||
5609 | len = _e1000_poll(hw); | |
5610 | if (len) | |
5611 | *packetp = packet; | |
5612 | ||
5613 | return len ? len : -EAGAIN; | |
5614 | } | |
5615 | ||
5616 | static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) | |
5617 | { | |
5618 | struct e1000_hw *hw = dev_get_priv(dev); | |
5619 | ||
5620 | fill_rx(hw); | |
5621 | ||
5622 | return 0; | |
5623 | } | |
5624 | ||
5625 | static int e1000_eth_probe(struct udevice *dev) | |
5626 | { | |
5627 | struct eth_pdata *plat = dev_get_platdata(dev); | |
5628 | struct e1000_hw *hw = dev_get_priv(dev); | |
5629 | int ret; | |
5630 | ||
5631 | hw->name = dev->name; | |
21ccce1b | 5632 | ret = e1000_init_one(hw, trailing_strtol(dev->name), |
81dab9af | 5633 | dev, plat->enetaddr); |
c6d80a15 SG |
5634 | if (ret < 0) { |
5635 | printf(pr_fmt("failed to initialize card: %d\n"), ret); | |
5636 | return ret; | |
5637 | } | |
5638 | ||
5639 | return 0; | |
5640 | } | |
5641 | ||
5642 | static int e1000_eth_bind(struct udevice *dev) | |
5643 | { | |
5644 | char name[20]; | |
5645 | ||
5646 | /* | |
5647 | * A simple way to number the devices. When device tree is used this | |
5648 | * is unnecessary, but when the device is just discovered on the PCI | |
5649 | * bus we need a name. We could instead have the uclass figure out | |
5650 | * which devices are different and number them. | |
5651 | */ | |
5652 | e1000_name(name, num_cards++); | |
5653 | ||
5654 | return device_set_name(dev, name); | |
5655 | } | |
5656 | ||
5657 | static const struct eth_ops e1000_eth_ops = { | |
5658 | .start = e1000_eth_start, | |
5659 | .send = e1000_eth_send, | |
5660 | .recv = e1000_eth_recv, | |
5661 | .stop = e1000_eth_stop, | |
5662 | .free_pkt = e1000_free_pkt, | |
5663 | }; | |
5664 | ||
5665 | static const struct udevice_id e1000_eth_ids[] = { | |
5666 | { .compatible = "intel,e1000" }, | |
5667 | { } | |
5668 | }; | |
5669 | ||
5670 | U_BOOT_DRIVER(eth_e1000) = { | |
5671 | .name = "eth_e1000", | |
5672 | .id = UCLASS_ETH, | |
5673 | .of_match = e1000_eth_ids, | |
5674 | .bind = e1000_eth_bind, | |
5675 | .probe = e1000_eth_probe, | |
5676 | .ops = &e1000_eth_ops, | |
5677 | .priv_auto_alloc_size = sizeof(struct e1000_hw), | |
5678 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
5679 | }; | |
5680 | ||
5681 | U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); | |
5682 | #endif |