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682011ff 1/**************************************************************************
ac3315c2 2Intel Pro 1000 for ppcboot/das-u-boot
682011ff
WD		 3Drivers are port from Intel's Linux driver e1000-4.3.15
4and from Etherboot pro 1000 driver by mrakes at vivato dot net
5tested on both gig copper and gig fiber boards
6***************************************************************************/
7/*******************************************************************************
8
8bde7f77 9
682011ff 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
8bde7f77
WD		 11
12 This program is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published by the Free
14 Software Foundation; either version 2 of the License, or (at your option)
682011ff 15 any later version.
8bde7f77
WD		 16
17 This program is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
682011ff 20 more details.
8bde7f77 21
682011ff 22 You should have received a copy of the GNU General Public License along with
8bde7f77 23 this program; if not, write to the Free Software Foundation, Inc., 59
1aeed8d7 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
8bde7f77 25
682011ff
WD		 26 The full GNU General Public License is included in this distribution in the
27 file called LICENSE.
8bde7f77 28
682011ff
WD		 29 Contact Information:
30 Linux NICS <linux.nics@intel.com>
31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33*******************************************************************************/
34/*
35 * Copyright (C) Archway Digital Solutions.
36 *
37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38 * 2/9/2002
39 *
40 * Copyright (C) Linux Networx.
41 * Massive upgrade to work with the new intel gigabit NICs.
42 * <ebiederman at lnxi dot com>
43 */
44
45#include "e1000.h"
46
682011ff
WD		 47#define TOUT_LOOP 100000
48
49#undef virt_to_bus
50#define virt_to_bus(x) ((unsigned long)x)
51#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
1aeed8d7 52#define mdelay(n) udelay((n)*1000)
682011ff
WD		 53
54#define E1000_DEFAULT_PBA 0x00000030
55
56/* NIC specific static variables go here */
57
58static char tx_pool[128 + 16];
59static char rx_pool[128 + 16];
60static char packet[2096];
61
62static struct e1000_tx_desc *tx_base;
63static struct e1000_rx_desc *rx_base;
64
65static int tx_tail;
66static int rx_tail, rx_last;
67
68static struct pci_device_id supported[] = {
69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
8915f118 78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
682011ff
WD		 79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
ac3315c2 83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
aa3b8bf9 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
1bc43437 85 {}
682011ff
WD		 86};
87
88/* Function forward declarations */
89static int e1000_setup_link(struct eth_device *nic);
90static int e1000_setup_fiber_link(struct eth_device *nic);
91static int e1000_setup_copper_link(struct eth_device *nic);
92static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
93static void e1000_config_collision_dist(struct e1000_hw *hw);
94static int e1000_config_mac_to_phy(struct e1000_hw *hw);
95static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
96static int e1000_check_for_link(struct eth_device *nic);
97static int e1000_wait_autoneg(struct e1000_hw *hw);
98static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
99 uint16_t * duplex);
100static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
101 uint16_t * phy_data);
102static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
103 uint16_t phy_data);
104static void e1000_phy_hw_reset(struct e1000_hw *hw);
105static int e1000_phy_reset(struct e1000_hw *hw);
106static int e1000_detect_gig_phy(struct e1000_hw *hw);
107
108#define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
109#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
110#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
111 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
112#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
8bde7f77 113 readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
682011ff
WD		 114#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
115
7521af1c 116#ifndef CONFIG_AP1000 /* remove for warnings */
682011ff
WD		 117/******************************************************************************
118 * Raises the EEPROM's clock input.
119 *
120 * hw - Struct containing variables accessed by shared code
121 * eecd - EECD's current value
122 *****************************************************************************/
123static void
124e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
125{
126 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
127 * wait 50 microseconds.
128 */
129 *eecd = *eecd | E1000_EECD_SK;
130 E1000_WRITE_REG(hw, EECD, *eecd);
131 E1000_WRITE_FLUSH(hw);
132 udelay(50);
133}
134
135/******************************************************************************
136 * Lowers the EEPROM's clock input.
137 *
8bde7f77 138 * hw - Struct containing variables accessed by shared code
682011ff
WD		 139 * eecd - EECD's current value
140 *****************************************************************************/
141static void
142e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
143{
8bde7f77
WD		 144 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
145 * wait 50 microseconds.
682011ff
WD		 146 */
147 *eecd = *eecd & ~E1000_EECD_SK;
148 E1000_WRITE_REG(hw, EECD, *eecd);
149 E1000_WRITE_FLUSH(hw);
150 udelay(50);
151}
152
153/******************************************************************************
154 * Shift data bits out to the EEPROM.
155 *
156 * hw - Struct containing variables accessed by shared code
157 * data - data to send to the EEPROM
158 * count - number of bits to shift out
159 *****************************************************************************/
160static void
161e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
162{
163 uint32_t eecd;
164 uint32_t mask;
165
166 /* We need to shift "count" bits out to the EEPROM. So, value in the
167 * "data" parameter will be shifted out to the EEPROM one bit at a time.
8bde7f77 168 * In order to do this, "data" must be broken down into bits.
682011ff
WD		 169 */
170 mask = 0x01 << (count - 1);
171 eecd = E1000_READ_REG(hw, EECD);
172 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
173 do {
174 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
175 * and then raising and then lowering the clock (the SK bit controls
176 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
177 * by setting "DI" to "0" and then raising and then lowering the clock.
178 */
179 eecd &= ~E1000_EECD_DI;
180
181 if (data & mask)
182 eecd |= E1000_EECD_DI;
183
184 E1000_WRITE_REG(hw, EECD, eecd);
185 E1000_WRITE_FLUSH(hw);
186
187 udelay(50);
188
189 e1000_raise_ee_clk(hw, &eecd);
190 e1000_lower_ee_clk(hw, &eecd);
191
192 mask = mask >> 1;
193
194 } while (mask);
195
196 /* We leave the "DI" bit set to "0" when we leave this routine. */
197 eecd &= ~E1000_EECD_DI;
198 E1000_WRITE_REG(hw, EECD, eecd);
199}
200
201/******************************************************************************
202 * Shift data bits in from the EEPROM
203 *
204 * hw - Struct containing variables accessed by shared code
205 *****************************************************************************/
206static uint16_t
207e1000_shift_in_ee_bits(struct e1000_hw *hw)
208{
209 uint32_t eecd;
210 uint32_t i;
211 uint16_t data;
212
8bde7f77 213 /* In order to read a register from the EEPROM, we need to shift 16 bits
682011ff
WD		 214 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
215 * the EEPROM (setting the SK bit), and then reading the value of the "DO"
8bde7f77 216 * bit. During this "shifting in" process the "DI" bit should always be
682011ff
WD		 217 * clear..
218 */
219
220 eecd = E1000_READ_REG(hw, EECD);
221
222 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
223 data = 0;
224
225 for (i = 0; i < 16; i++) {
226 data = data << 1;
227 e1000_raise_ee_clk(hw, &eecd);
228
229 eecd = E1000_READ_REG(hw, EECD);
230
231 eecd &= ~(E1000_EECD_DI);
232 if (eecd & E1000_EECD_DO)
233 data |= 1;
234
235 e1000_lower_ee_clk(hw, &eecd);
236 }
237
238 return data;
239}
240
241/******************************************************************************
242 * Prepares EEPROM for access
243 *
244 * hw - Struct containing variables accessed by shared code
245 *
8bde7f77 246 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
682011ff
WD		 247 * function should be called before issuing a command to the EEPROM.
248 *****************************************************************************/
249static void
250e1000_setup_eeprom(struct e1000_hw *hw)
251{
252 uint32_t eecd;
253
254 eecd = E1000_READ_REG(hw, EECD);
255
256 /* Clear SK and DI */
257 eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
258 E1000_WRITE_REG(hw, EECD, eecd);
259
260 /* Set CS */
261 eecd |= E1000_EECD_CS;
262 E1000_WRITE_REG(hw, EECD, eecd);
263}
264
265/******************************************************************************
266 * Returns EEPROM to a "standby" state
8bde7f77 267 *
682011ff
WD		 268 * hw - Struct containing variables accessed by shared code
269 *****************************************************************************/
270static void
271e1000_standby_eeprom(struct e1000_hw *hw)
272{
273 uint32_t eecd;
274
275 eecd = E1000_READ_REG(hw, EECD);
276
277 /* Deselct EEPROM */
278 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
279 E1000_WRITE_REG(hw, EECD, eecd);
280 E1000_WRITE_FLUSH(hw);
281 udelay(50);
282
283 /* Clock high */
284 eecd |= E1000_EECD_SK;
285 E1000_WRITE_REG(hw, EECD, eecd);
286 E1000_WRITE_FLUSH(hw);
287 udelay(50);
288
289 /* Select EEPROM */
290 eecd |= E1000_EECD_CS;
291 E1000_WRITE_REG(hw, EECD, eecd);
292 E1000_WRITE_FLUSH(hw);
293 udelay(50);
294
295 /* Clock low */
296 eecd &= ~E1000_EECD_SK;
297 E1000_WRITE_REG(hw, EECD, eecd);
298 E1000_WRITE_FLUSH(hw);
299 udelay(50);
300}
301
302/******************************************************************************
303 * Reads a 16 bit word from the EEPROM.
304 *
305 * hw - Struct containing variables accessed by shared code
306 * offset - offset of word in the EEPROM to read
8bde7f77 307 * data - word read from the EEPROM
682011ff
WD		 308 *****************************************************************************/
309static int
310e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data)
311{
312 uint32_t eecd;
313 uint32_t i = 0;
314 int large_eeprom = FALSE;
315
316 /* Request EEPROM Access */
317 if (hw->mac_type > e1000_82544) {
318 eecd = E1000_READ_REG(hw, EECD);
319 if (eecd & E1000_EECD_SIZE)
320 large_eeprom = TRUE;
321 eecd |= E1000_EECD_REQ;
322 E1000_WRITE_REG(hw, EECD, eecd);
323 eecd = E1000_READ_REG(hw, EECD);
324 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
325 i++;
326 udelay(10);
327 eecd = E1000_READ_REG(hw, EECD);
328 }
329 if (!(eecd & E1000_EECD_GNT)) {
330 eecd &= ~E1000_EECD_REQ;
331 E1000_WRITE_REG(hw, EECD, eecd);
332 DEBUGOUT("Could not acquire EEPROM grant\n");
333 return -E1000_ERR_EEPROM;
334 }
335 }
336
337 /* Prepare the EEPROM for reading */
338 e1000_setup_eeprom(hw);
339
340 /* Send the READ command (opcode + addr) */
341 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
342 e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6);
343
344 /* Read the data */
345 *data = e1000_shift_in_ee_bits(hw);
346
347 /* End this read operation */
348 e1000_standby_eeprom(hw);
349
350 /* Stop requesting EEPROM access */
351 if (hw->mac_type > e1000_82544) {
352 eecd = E1000_READ_REG(hw, EECD);
353 eecd &= ~E1000_EECD_REQ;
354 E1000_WRITE_REG(hw, EECD, eecd);
355 }
356
357 return 0;
358}
359
360#if 0
361static void
362e1000_eeprom_cleanup(struct e1000_hw *hw)
363{
364 uint32_t eecd;
365
366 eecd = E1000_READ_REG(hw, EECD);
367 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
368 E1000_WRITE_REG(hw, EECD, eecd);
369 e1000_raise_ee_clk(hw, &eecd);
370 e1000_lower_ee_clk(hw, &eecd);
371}
372
373static uint16_t
374e1000_wait_eeprom_done(struct e1000_hw *hw)
375{
376 uint32_t eecd;
377 uint32_t i;
378
379 e1000_standby_eeprom(hw);
380 for (i = 0; i < 200; i++) {
381 eecd = E1000_READ_REG(hw, EECD);
382 if (eecd & E1000_EECD_DO)
383 return (TRUE);
384 udelay(5);
385 }
386 return (FALSE);
387}
388
389static int
390e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data)
391{
392 uint32_t eecd;
393 int large_eeprom = FALSE;
394 int i = 0;
395
396 /* Request EEPROM Access */
397 if (hw->mac_type > e1000_82544) {
398 eecd = E1000_READ_REG(hw, EECD);
399 if (eecd & E1000_EECD_SIZE)
400 large_eeprom = TRUE;
401 eecd |= E1000_EECD_REQ;
402 E1000_WRITE_REG(hw, EECD, eecd);
403 eecd = E1000_READ_REG(hw, EECD);
404 while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
405 i++;
406 udelay(5);
407 eecd = E1000_READ_REG(hw, EECD);
408 }
409 if (!(eecd & E1000_EECD_GNT)) {
410 eecd &= ~E1000_EECD_REQ;
411 E1000_WRITE_REG(hw, EECD, eecd);
412 DEBUGOUT("Could not acquire EEPROM grant\n");
413 return FALSE;
414 }
415 }
416 e1000_setup_eeprom(hw);
417 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5);
418 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4);
419 e1000_standby_eeprom(hw);
420 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3);
421 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6);
422 e1000_shift_out_ee_bits(hw, Data, 16);
423 if (!e1000_wait_eeprom_done(hw)) {
424 return FALSE;
425 }
426 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5);
427 e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4);
428 e1000_eeprom_cleanup(hw);
429
430 /* Stop requesting EEPROM access */
431 if (hw->mac_type > e1000_82544) {
432 eecd = E1000_READ_REG(hw, EECD);
433 eecd &= ~E1000_EECD_REQ;
434 E1000_WRITE_REG(hw, EECD, eecd);
435 }
436 i = 0;
437 eecd = E1000_READ_REG(hw, EECD);
438 while (((eecd & E1000_EECD_GNT)) && (i < 500)) {
439 i++;
440 udelay(10);
441 eecd = E1000_READ_REG(hw, EECD);
442 }
443 if ((eecd & E1000_EECD_GNT)) {
444 DEBUGOUT("Could not release EEPROM grant\n");
445 }
446 return TRUE;
447}
448#endif
449
450/******************************************************************************
451 * Verifies that the EEPROM has a valid checksum
8bde7f77 452 *
682011ff
WD		 453 * hw - Struct containing variables accessed by shared code
454 *
455 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
456 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
457 * valid.
458 *****************************************************************************/
459static int
460e1000_validate_eeprom_checksum(struct eth_device *nic)
461{
462 struct e1000_hw *hw = nic->priv;
463 uint16_t checksum = 0;
464 uint16_t i, eeprom_data;
465
466 DEBUGFUNC();
467
468 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
469 if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
470 DEBUGOUT("EEPROM Read Error\n");
471 return -E1000_ERR_EEPROM;
472 }
473 checksum += eeprom_data;
474 }
8bde7f77 475
682011ff
WD		 476 if (checksum == (uint16_t) EEPROM_SUM) {
477 return 0;
478 } else {
479 DEBUGOUT("EEPROM Checksum Invalid\n");
480 return -E1000_ERR_EEPROM;
481 }
482}
7521af1c 483#endif /* #ifndef CONFIG_AP1000 */
682011ff
WD		 484
485/******************************************************************************
486 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
487 * second function of dual function devices
488 *
489 * nic - Struct containing variables accessed by shared code
490 *****************************************************************************/
491static int
492e1000_read_mac_addr(struct eth_device *nic)
493{
7521af1c 494#ifndef CONFIG_AP1000
682011ff
WD		 495 struct e1000_hw *hw = nic->priv;
496 uint16_t offset;
497 uint16_t eeprom_data;
498 int i;
499
500 DEBUGFUNC();
501
502 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
503 offset = i >> 1;
504 if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
505 DEBUGOUT("EEPROM Read Error\n");
506 return -E1000_ERR_EEPROM;
507 }
508 nic->enetaddr[i] = eeprom_data & 0xff;
509 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
510 }
511 if ((hw->mac_type == e1000_82546) &&
512 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
513 /* Invert the last bit if this is the second device */
514 nic->enetaddr[5] += 1;
515 }
ac3315c2 516#ifdef CONFIG_E1000_FALLBACK_MAC
f2302d44
SR		 517 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
518 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
519
520 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
521 }
ac3315c2 522#endif
7521af1c
WD		 523#else
524 /*
525 * The AP1000's e1000 has no eeprom; the MAC address is stored in the
526 * environment variables. Currently this does not support the addition
527 * of a PMC e1000 card, which is certainly a possibility, so this should
528 * be updated to properly use the env variable only for the onboard e1000
529 */
530
531 int ii;
532 char *s, *e;
533
534 DEBUGFUNC();
535
536 s = getenv ("ethaddr");
f2302d44 537 if (s == NULL) {
7521af1c 538 return -E1000_ERR_EEPROM;
f2302d44 539 } else {
7521af1c
WD		 540 for(ii = 0; ii < 6; ii++) {
541 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
542 if (s){
543 s = (*e) ? e + 1 : e;
544 }
545 }
546 }
547#endif
682011ff
WD		 548 return 0;
549}
550
551/******************************************************************************
552 * Initializes receive address filters.
553 *
8bde7f77 554 * hw - Struct containing variables accessed by shared code
682011ff
WD		 555 *
556 * Places the MAC address in receive address register 0 and clears the rest
557 * of the receive addresss registers. Clears the multicast table. Assumes
558 * the receiver is in reset when the routine is called.
559 *****************************************************************************/
560static void
561e1000_init_rx_addrs(struct eth_device *nic)
562{
563 struct e1000_hw *hw = nic->priv;
564 uint32_t i;
565 uint32_t addr_low;
566 uint32_t addr_high;
567
568 DEBUGFUNC();
569
570 /* Setup the receive address. */
571 DEBUGOUT("Programming MAC Address into RAR[0]\n");
572 addr_low = (nic->enetaddr[0] |
573 (nic->enetaddr[1] << 8) |
574 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
575
576 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
577
578 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
579 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
580
581 /* Zero out the other 15 receive addresses. */
582 DEBUGOUT("Clearing RAR[1-15]\n");
583 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
584 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
585 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
586 }
587}
588
589/******************************************************************************
590 * Clears the VLAN filer table
591 *
592 * hw - Struct containing variables accessed by shared code
593 *****************************************************************************/
594static void
595e1000_clear_vfta(struct e1000_hw *hw)
596{
597 uint32_t offset;
598
599 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
600 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
601}
602
603/******************************************************************************
604 * Set the mac type member in the hw struct.
8bde7f77 605 *
682011ff
WD		 606 * hw - Struct containing variables accessed by shared code
607 *****************************************************************************/
608static int
609e1000_set_mac_type(struct e1000_hw *hw)
610{
611 DEBUGFUNC();
612
613 switch (hw->device_id) {
614 case E1000_DEV_ID_82542:
615 switch (hw->revision_id) {
616 case E1000_82542_2_0_REV_ID:
617 hw->mac_type = e1000_82542_rev2_0;
618 break;
619 case E1000_82542_2_1_REV_ID:
620 hw->mac_type = e1000_82542_rev2_1;
621 break;
622 default:
623 /* Invalid 82542 revision ID */
624 return -E1000_ERR_MAC_TYPE;
625 }
626 break;
627 case E1000_DEV_ID_82543GC_FIBER:
628 case E1000_DEV_ID_82543GC_COPPER:
629 hw->mac_type = e1000_82543;
630 break;
631 case E1000_DEV_ID_82544EI_COPPER:
632 case E1000_DEV_ID_82544EI_FIBER:
633 case E1000_DEV_ID_82544GC_COPPER:
634 case E1000_DEV_ID_82544GC_LOM:
635 hw->mac_type = e1000_82544;
636 break;
637 case E1000_DEV_ID_82540EM:
638 case E1000_DEV_ID_82540EM_LOM:
639 hw->mac_type = e1000_82540;
640 break;
641 case E1000_DEV_ID_82545EM_COPPER:
8915f118 642 case E1000_DEV_ID_82545GM_COPPER:
682011ff
WD		 643 case E1000_DEV_ID_82545EM_FIBER:
644 hw->mac_type = e1000_82545;
645 break;
646 case E1000_DEV_ID_82546EB_COPPER:
647 case E1000_DEV_ID_82546EB_FIBER:
648 hw->mac_type = e1000_82546;
649 break;
ac3315c2 650 case E1000_DEV_ID_82541ER:
aa3b8bf9 651 case E1000_DEV_ID_82541GI_LF:
1aeed8d7
WD		 652 hw->mac_type = e1000_82541_rev_2;
653 break;
682011ff
WD		 654 default:
655 /* Should never have loaded on this device */
656 return -E1000_ERR_MAC_TYPE;
657 }
658 return E1000_SUCCESS;
659}
660
661/******************************************************************************
662 * Reset the transmit and receive units; mask and clear all interrupts.
663 *
664 * hw - Struct containing variables accessed by shared code
665 *****************************************************************************/
666void
667e1000_reset_hw(struct e1000_hw *hw)
668{
669 uint32_t ctrl;
670 uint32_t ctrl_ext;
671 uint32_t icr;
672 uint32_t manc;
673
674 DEBUGFUNC();
675
676 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
677 if (hw->mac_type == e1000_82542_rev2_0) {
678 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
679 pci_write_config_word(hw->pdev, PCI_COMMAND,
680 hw->
681 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
682 }
683
684 /* Clear interrupt mask to stop board from generating interrupts */
685 DEBUGOUT("Masking off all interrupts\n");
686 E1000_WRITE_REG(hw, IMC, 0xffffffff);
687
688 /* Disable the Transmit and Receive units. Then delay to allow
689 * any pending transactions to complete before we hit the MAC with
690 * the global reset.
691 */
692 E1000_WRITE_REG(hw, RCTL, 0);
693 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
694 E1000_WRITE_FLUSH(hw);
695
696 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
697 hw->tbi_compatibility_on = FALSE;
698
699 /* Delay to allow any outstanding PCI transactions to complete before
700 * resetting the device
701 */
702 mdelay(10);
703
704 /* Issue a global reset to the MAC. This will reset the chip's
705 * transmit, receive, DMA, and link units. It will not effect
706 * the current PCI configuration. The global reset bit is self-
707 * clearing, and should clear within a microsecond.
708 */
709 DEBUGOUT("Issuing a global reset to MAC\n");
710 ctrl = E1000_READ_REG(hw, CTRL);
711
712#if 0
713 if (hw->mac_type > e1000_82543)
714 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
715 else
716#endif
717 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
718
719 /* Force a reload from the EEPROM if necessary */
720 if (hw->mac_type < e1000_82540) {
721 /* Wait for reset to complete */
722 udelay(10);
723 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
724 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
725 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
726 E1000_WRITE_FLUSH(hw);
727 /* Wait for EEPROM reload */
728 mdelay(2);
729 } else {
730 /* Wait for EEPROM reload (it happens automatically) */
731 mdelay(4);
732 /* Dissable HW ARPs on ASF enabled adapters */
733 manc = E1000_READ_REG(hw, MANC);
734 manc &= ~(E1000_MANC_ARP_EN);
735 E1000_WRITE_REG(hw, MANC, manc);
736 }
737
738 /* Clear interrupt mask to stop board from generating interrupts */
739 DEBUGOUT("Masking off all interrupts\n");
740 E1000_WRITE_REG(hw, IMC, 0xffffffff);
741
742 /* Clear any pending interrupt events. */
743 icr = E1000_READ_REG(hw, ICR);
744
745 /* If MWI was previously enabled, reenable it. */
746 if (hw->mac_type == e1000_82542_rev2_0) {
747 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
748 }
749}
750
751/******************************************************************************
752 * Performs basic configuration of the adapter.
753 *
754 * hw - Struct containing variables accessed by shared code
8bde7f77
WD		 755 *
756 * Assumes that the controller has previously been reset and is in a
682011ff
WD		 757 * post-reset uninitialized state. Initializes the receive address registers,
758 * multicast table, and VLAN filter table. Calls routines to setup link
759 * configuration and flow control settings. Clears all on-chip counters. Leaves
760 * the transmit and receive units disabled and uninitialized.
761 *****************************************************************************/
762static int
763e1000_init_hw(struct eth_device *nic)
764{
765 struct e1000_hw *hw = nic->priv;
766 uint32_t ctrl, status;
767 uint32_t i;
768 int32_t ret_val;
769 uint16_t pcix_cmd_word;
770 uint16_t pcix_stat_hi_word;
771 uint16_t cmd_mmrbc;
772 uint16_t stat_mmrbc;
773 e1000_bus_type bus_type = e1000_bus_type_unknown;
774
775 DEBUGFUNC();
776#if 0
777 /* Initialize Identification LED */
778 ret_val = e1000_id_led_init(hw);
779 if (ret_val < 0) {
780 DEBUGOUT("Error Initializing Identification LED\n");
781 return ret_val;
782 }
783#endif
784 /* Set the Media Type and exit with error if it is not valid. */
785 if (hw->mac_type != e1000_82543) {
786 /* tbi_compatibility is only valid on 82543 */
787 hw->tbi_compatibility_en = FALSE;
788 }
789
790 if (hw->mac_type >= e1000_82543) {
791 status = E1000_READ_REG(hw, STATUS);
792 if (status & E1000_STATUS_TBIMODE) {
793 hw->media_type = e1000_media_type_fiber;
794 /* tbi_compatibility not valid on fiber */
795 hw->tbi_compatibility_en = FALSE;
796 } else {
797 hw->media_type = e1000_media_type_copper;
798 }
799 } else {
800 /* This is an 82542 (fiber only) */
801 hw->media_type = e1000_media_type_fiber;
802 }
803
804 /* Disabling VLAN filtering. */
805 DEBUGOUT("Initializing the IEEE VLAN\n");
806 E1000_WRITE_REG(hw, VET, 0);
807
808 e1000_clear_vfta(hw);
809
810 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
811 if (hw->mac_type == e1000_82542_rev2_0) {
812 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
813 pci_write_config_word(hw->pdev, PCI_COMMAND,
814 hw->
815 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
816 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
817 E1000_WRITE_FLUSH(hw);
818 mdelay(5);
819 }
820
821 /* Setup the receive address. This involves initializing all of the Receive
822 * Address Registers (RARs 0 - 15).
823 */
824 e1000_init_rx_addrs(nic);
825
826 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
827 if (hw->mac_type == e1000_82542_rev2_0) {
828 E1000_WRITE_REG(hw, RCTL, 0);
829 E1000_WRITE_FLUSH(hw);
830 mdelay(1);
831 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
832 }
833
834 /* Zero out the Multicast HASH table */
835 DEBUGOUT("Zeroing the MTA\n");
836 for (i = 0; i < E1000_MC_TBL_SIZE; i++)
837 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
838
839#if 0
840 /* Set the PCI priority bit correctly in the CTRL register. This
841 * determines if the adapter gives priority to receives, or if it
842 * gives equal priority to transmits and receives.
843 */
844 if (hw->dma_fairness) {
845 ctrl = E1000_READ_REG(hw, CTRL);
846 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
847 }
848#endif
849 if (hw->mac_type >= e1000_82543) {
850 status = E1000_READ_REG(hw, STATUS);
851 bus_type = (status & E1000_STATUS_PCIX_MODE) ?
852 e1000_bus_type_pcix : e1000_bus_type_pci;
853 }
854 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
855 if (bus_type == e1000_bus_type_pcix) {
856 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
857 &pcix_cmd_word);
858 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
859 &pcix_stat_hi_word);
860 cmd_mmrbc =
861 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
862 PCIX_COMMAND_MMRBC_SHIFT;
863 stat_mmrbc =
864 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
865 PCIX_STATUS_HI_MMRBC_SHIFT;
866 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
867 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
868 if (cmd_mmrbc > stat_mmrbc) {
869 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
870 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
871 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
872 pcix_cmd_word);
873 }
874 }
875
876 /* Call a subroutine to configure the link and setup flow control. */
877 ret_val = e1000_setup_link(nic);
878
879 /* Set the transmit descriptor write-back policy */
880 if (hw->mac_type > e1000_82544) {
881 ctrl = E1000_READ_REG(hw, TXDCTL);
882 ctrl =
883 (ctrl & ~E1000_TXDCTL_WTHRESH) |
884 E1000_TXDCTL_FULL_TX_DESC_WB;
885 E1000_WRITE_REG(hw, TXDCTL, ctrl);
886 }
887#if 0
888 /* Clear all of the statistics registers (clear on read). It is
889 * important that we do this after we have tried to establish link
890 * because the symbol error count will increment wildly if there
891 * is no link.
892 */
893 e1000_clear_hw_cntrs(hw);
894#endif
895
896 return ret_val;
897}
898
899/******************************************************************************
900 * Configures flow control and link settings.
8bde7f77 901 *
682011ff 902 * hw - Struct containing variables accessed by shared code
8bde7f77 903 *
682011ff
WD		 904 * Determines which flow control settings to use. Calls the apropriate media-
905 * specific link configuration function. Configures the flow control settings.
906 * Assuming the adapter has a valid link partner, a valid link should be
8bde7f77 907 * established. Assumes the hardware has previously been reset and the
682011ff
WD		 908 * transmitter and receiver are not enabled.
909 *****************************************************************************/
910static int
911e1000_setup_link(struct eth_device *nic)
912{
913 struct e1000_hw *hw = nic->priv;
914 uint32_t ctrl_ext;
915 int32_t ret_val;
916 uint16_t eeprom_data;
917
918 DEBUGFUNC();
919
7521af1c 920#ifndef CONFIG_AP1000
682011ff
WD		 921 /* Read and store word 0x0F of the EEPROM. This word contains bits
922 * that determine the hardware's default PAUSE (flow control) mode,
923 * a bit that determines whether the HW defaults to enabling or
924 * disabling auto-negotiation, and the direction of the
925 * SW defined pins. If there is no SW over-ride of the flow
926 * control setting, then the variable hw->fc will
927 * be initialized based on a value in the EEPROM.
928 */
929 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
930 DEBUGOUT("EEPROM Read Error\n");
931 return -E1000_ERR_EEPROM;
932 }
7521af1c
WD		 933#else
934 /* we have to hardcode the proper value for our hardware. */
935 /* this value is for the 82540EM pci card used for prototyping, and it works. */
936 eeprom_data = 0xb220;
937#endif
682011ff
WD		 938
939 if (hw->fc == e1000_fc_default) {
940 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
941 hw->fc = e1000_fc_none;
942 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
943 EEPROM_WORD0F_ASM_DIR)
944 hw->fc = e1000_fc_tx_pause;
945 else
946 hw->fc = e1000_fc_full;
947 }
948
949 /* We want to save off the original Flow Control configuration just
950 * in case we get disconnected and then reconnected into a different
951 * hub or switch with different Flow Control capabilities.
952 */
953 if (hw->mac_type == e1000_82542_rev2_0)
954 hw->fc &= (~e1000_fc_tx_pause);
955
956 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
957 hw->fc &= (~e1000_fc_rx_pause);
958
959 hw->original_fc = hw->fc;
960
961 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
962
963 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
964 * polarity value for the SW controlled pins, and setup the
965 * Extended Device Control reg with that info.
966 * This is needed because one of the SW controlled pins is used for
967 * signal detection. So this should be done before e1000_setup_pcs_link()
968 * or e1000_phy_setup() is called.
969 */
970 if (hw->mac_type == e1000_82543) {
971 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
972 SWDPIO__EXT_SHIFT);
973 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
974 }
975
976 /* Call the necessary subroutine to configure the link. */
977 ret_val = (hw->media_type == e1000_media_type_fiber) ?
978 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
979 if (ret_val < 0) {
980 return ret_val;
981 }
982
983 /* Initialize the flow control address, type, and PAUSE timer
984 * registers to their default values. This is done even if flow
985 * control is disabled, because it does not hurt anything to
986 * initialize these registers.
987 */
988 DEBUGOUT
989 ("Initializing the Flow Control address, type and timer regs\n");
990
991 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
992 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
993 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
994 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
995
996 /* Set the flow control receive threshold registers. Normally,
997 * these registers will be set to a default threshold that may be
998 * adjusted later by the driver's runtime code. However, if the
999 * ability to transmit pause frames in not enabled, then these
8bde7f77 1000 * registers will be set to 0.
682011ff
WD		 1001 */
1002 if (!(hw->fc & e1000_fc_tx_pause)) {
1003 E1000_WRITE_REG(hw, FCRTL, 0);
1004 E1000_WRITE_REG(hw, FCRTH, 0);
1005 } else {
1006 /* We need to set up the Receive Threshold high and low water marks
1007 * as well as (optionally) enabling the transmission of XON frames.
1008 */
1009 if (hw->fc_send_xon) {
1010 E1000_WRITE_REG(hw, FCRTL,
1011 (hw->fc_low_water | E1000_FCRTL_XONE));
1012 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1013 } else {
1014 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1015 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1016 }
1017 }
1018 return ret_val;
1019}
1020
1021/******************************************************************************
1022 * Sets up link for a fiber based adapter
1023 *
1024 * hw - Struct containing variables accessed by shared code
1025 *
1026 * Manipulates Physical Coding Sublayer functions in order to configure
1027 * link. Assumes the hardware has been previously reset and the transmitter
1028 * and receiver are not enabled.
1029 *****************************************************************************/
1030static int
1031e1000_setup_fiber_link(struct eth_device *nic)
1032{
1033 struct e1000_hw *hw = nic->priv;
1034 uint32_t ctrl;
1035 uint32_t status;
1036 uint32_t txcw = 0;
1037 uint32_t i;
1038 uint32_t signal;
1039 int32_t ret_val;
1040
1041 DEBUGFUNC();
8bde7f77
WD		 1042 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1043 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 1044 * cleared when there is a signal
1045 */
1046 ctrl = E1000_READ_REG(hw, CTRL);
1047 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1048 signal = E1000_CTRL_SWDPIN1;
1049 else
1050 signal = 0;
1051
1052 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1053 ctrl);
1054 /* Take the link out of reset */
1055 ctrl &= ~(E1000_CTRL_LRST);
1056
1057 e1000_config_collision_dist(hw);
1058
1059 /* Check for a software override of the flow control settings, and setup
1060 * the device accordingly. If auto-negotiation is enabled, then software
1061 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1062 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
8bde7f77 1063 * auto-negotiation is disabled, then software will have to manually
682011ff
WD		 1064 * configure the two flow control enable bits in the CTRL register.
1065 *
1066 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 1067 * 0: Flow control is completely disabled
1068 * 1: Rx flow control is enabled (we can receive pause frames, but
1069 * not send pause frames).
1070 * 2: Tx flow control is enabled (we can send pause frames but we do
1071 * not support receiving pause frames).
1072 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff
WD		 1073 */
1074 switch (hw->fc) {
1075 case e1000_fc_none:
1076 /* Flow control is completely disabled by a software over-ride. */
1077 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1078 break;
1079 case e1000_fc_rx_pause:
8bde7f77
WD		 1080 /* RX Flow control is enabled and TX Flow control is disabled by a
1081 * software over-ride. Since there really isn't a way to advertise
682011ff
WD		 1082 * that we are capable of RX Pause ONLY, we will advertise that we
1083 * support both symmetric and asymmetric RX PAUSE. Later, we will
1084 * disable the adapter's ability to send PAUSE frames.
1085 */
1086 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1087 break;
1088 case e1000_fc_tx_pause:
8bde7f77 1089 /* TX Flow control is enabled, and RX Flow control is disabled, by a
682011ff
WD		 1090 * software over-ride.
1091 */
1092 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1093 break;
1094 case e1000_fc_full:
1095 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1096 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1097 break;
1098 default:
1099 DEBUGOUT("Flow control param set incorrectly\n");
1100 return -E1000_ERR_CONFIG;
1101 break;
1102 }
1103
1104 /* Since auto-negotiation is enabled, take the link out of reset (the link
1105 * will be in reset, because we previously reset the chip). This will
1106 * restart auto-negotiation. If auto-neogtiation is successful then the
1107 * link-up status bit will be set and the flow control enable bits (RFCE
1108 * and TFCE) will be set according to their negotiated value.
1109 */
1110 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
1111
1112 E1000_WRITE_REG(hw, TXCW, txcw);
1113 E1000_WRITE_REG(hw, CTRL, ctrl);
1114 E1000_WRITE_FLUSH(hw);
1115
1116 hw->txcw = txcw;
1117 mdelay(1);
1118
1119 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
8bde7f77
WD		 1120 * indication in the Device Status Register. Time-out if a link isn't
1121 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
682011ff
WD		 1122 * less than 500 milliseconds even if the other end is doing it in SW).
1123 */
1124 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1125 DEBUGOUT("Looking for Link\n");
1126 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1127 mdelay(10);
1128 status = E1000_READ_REG(hw, STATUS);
1129 if (status & E1000_STATUS_LU)
1130 break;
1131 }
1132 if (i == (LINK_UP_TIMEOUT / 10)) {
8bde7f77 1133 /* AutoNeg failed to achieve a link, so we'll call
682011ff
WD		 1134 * e1000_check_for_link. This routine will force the link up if we
1135 * detect a signal. This will allow us to communicate with
1136 * non-autonegotiating link partners.
1137 */
1138 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1139 hw->autoneg_failed = 1;
1140 ret_val = e1000_check_for_link(nic);
1141 if (ret_val < 0) {
1142 DEBUGOUT("Error while checking for link\n");
1143 return ret_val;
1144 }
1145 hw->autoneg_failed = 0;
1146 } else {
1147 hw->autoneg_failed = 0;
1148 DEBUGOUT("Valid Link Found\n");
1149 }
1150 } else {
1151 DEBUGOUT("No Signal Detected\n");
1152 return -E1000_ERR_NOLINK;
1153 }
1154 return 0;
1155}
1156
1157/******************************************************************************
1158* Detects which PHY is present and the speed and duplex
1159*
1160* hw - Struct containing variables accessed by shared code
1161******************************************************************************/
1162static int
1163e1000_setup_copper_link(struct eth_device *nic)
1164{
1165 struct e1000_hw *hw = nic->priv;
1166 uint32_t ctrl;
1167 int32_t ret_val;
1168 uint16_t i;
1169 uint16_t phy_data;
1170
1171 DEBUGFUNC();
1172
1173 ctrl = E1000_READ_REG(hw, CTRL);
1174 /* With 82543, we need to force speed and duplex on the MAC equal to what
1175 * the PHY speed and duplex configuration is. In addition, we need to
1176 * perform a hardware reset on the PHY to take it out of reset.
1177 */
1178 if (hw->mac_type > e1000_82543) {
1179 ctrl |= E1000_CTRL_SLU;
1180 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1181 E1000_WRITE_REG(hw, CTRL, ctrl);
1182 } else {
1183 ctrl |=
1184 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1185 E1000_WRITE_REG(hw, CTRL, ctrl);
1186 e1000_phy_hw_reset(hw);
1187 }
1188
1189 /* Make sure we have a valid PHY */
1190 ret_val = e1000_detect_gig_phy(hw);
1191 if (ret_val < 0) {
1192 DEBUGOUT("Error, did not detect valid phy.\n");
1193 return ret_val;
1194 }
1195 DEBUGOUT("Phy ID = %x \n", hw->phy_id);
1196
1197 /* Enable CRS on TX. This must be set for half-duplex operation. */
1198 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
1199 DEBUGOUT("PHY Read Error\n");
1200 return -E1000_ERR_PHY;
1201 }
1202 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1203
1204#if 0
1205 /* Options:
1206 * MDI/MDI-X = 0 (default)
1207 * 0 - Auto for all speeds
1208 * 1 - MDI mode
1209 * 2 - MDI-X mode
1210 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1211 */
1212 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1213 switch (hw->mdix) {
1214 case 1:
1215 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1216 break;
1217 case 2:
1218 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1219 break;
1220 case 3:
1221 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1222 break;
1223 case 0:
1224 default:
1225 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1226 break;
1227 }
1228#else
1229 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1230#endif
1231
1232#if 0
1233 /* Options:
1234 * disable_polarity_correction = 0 (default)
1aeed8d7 1235 * Automatic Correction for Reversed Cable Polarity
682011ff
WD		 1236 * 0 - Disabled
1237 * 1 - Enabled
1238 */
1239 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1240 if (hw->disable_polarity_correction == 1)
1241 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1242#else
1243 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1244#endif
1245 if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
1246 DEBUGOUT("PHY Write Error\n");
1247 return -E1000_ERR_PHY;
1248 }
1249
1250 /* Force TX_CLK in the Extended PHY Specific Control Register
1251 * to 25MHz clock.
1252 */
1253 if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
1254 DEBUGOUT("PHY Read Error\n");
1255 return -E1000_ERR_PHY;
1256 }
1257 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1258 /* Configure Master and Slave downshift values */
1259 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1260 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1261 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1262 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1263 if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
1264 DEBUGOUT("PHY Write Error\n");
1265 return -E1000_ERR_PHY;
1266 }
1267
1268 /* SW Reset the PHY so all changes take effect */
1269 ret_val = e1000_phy_reset(hw);
1270 if (ret_val < 0) {
1271 DEBUGOUT("Error Resetting the PHY\n");
1272 return ret_val;
1273 }
1274
1275 /* Options:
1276 * autoneg = 1 (default)
1aeed8d7
WD		 1277 * PHY will advertise value(s) parsed from
1278 * autoneg_advertised and fc
682011ff 1279 * autoneg = 0
1aeed8d7
WD		 1280 * PHY will be set to 10H, 10F, 100H, or 100F
1281 * depending on value parsed from forced_speed_duplex.
682011ff
WD		 1282 */
1283
1aeed8d7 1284 /* Is autoneg enabled? This is enabled by default or by software override.
682011ff
WD		 1285 * If so, call e1000_phy_setup_autoneg routine to parse the
1286 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
1287 * user should have provided a speed/duplex override. If so, then call
1288 * e1000_phy_force_speed_duplex to parse and set this up.
1289 */
1290 /* Perform some bounds checking on the hw->autoneg_advertised
1291 * parameter. If this variable is zero, then set it to the default.
1292 */
1293 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1294
1295 /* If autoneg_advertised is zero, we assume it was not defaulted
1296 * by the calling code so we set to advertise full capability.
1297 */
1298 if (hw->autoneg_advertised == 0)
1299 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1300
1301 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1302 ret_val = e1000_phy_setup_autoneg(hw);
1303 if (ret_val < 0) {
1304 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1305 return ret_val;
1306 }
1307 DEBUGOUT("Restarting Auto-Neg\n");
1308
1309 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1310 * the Auto Neg Restart bit in the PHY control register.
1311 */
1312 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
1313 DEBUGOUT("PHY Read Error\n");
1314 return -E1000_ERR_PHY;
1315 }
1316 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1317 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
1318 DEBUGOUT("PHY Write Error\n");
1319 return -E1000_ERR_PHY;
1320 }
1321#if 0
1322 /* Does the user want to wait for Auto-Neg to complete here, or
1323 * check at a later time (for example, callback routine).
1324 */
1325 if (hw->wait_autoneg_complete) {
1326 ret_val = e1000_wait_autoneg(hw);
1327 if (ret_val < 0) {
1328 DEBUGOUT
1329 ("Error while waiting for autoneg to complete\n");
1330 return ret_val;
1331 }
1332 }
1333#else
8bde7f77 1334 /* If we do not wait for autonegtation to complete I
682011ff
WD		 1335 * do not see a valid link status.
1336 */
1337 ret_val = e1000_wait_autoneg(hw);
1338 if (ret_val < 0) {
1339 DEBUGOUT("Error while waiting for autoneg to complete\n");
1340 return ret_val;
1341 }
1342#endif
1343
1344 /* Check link status. Wait up to 100 microseconds for link to become
1345 * valid.
1346 */
1347 for (i = 0; i < 10; i++) {
1348 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1349 DEBUGOUT("PHY Read Error\n");
1350 return -E1000_ERR_PHY;
1351 }
1352 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1353 DEBUGOUT("PHY Read Error\n");
1354 return -E1000_ERR_PHY;
1355 }
1356 if (phy_data & MII_SR_LINK_STATUS) {
1357 /* We have link, so we need to finish the config process:
1358 * 1) Set up the MAC to the current PHY speed/duplex
1aeed8d7
WD		 1359 * if we are on 82543. If we
1360 * are on newer silicon, we only need to configure
1361 * collision distance in the Transmit Control Register.
682011ff 1362 * 2) Set up flow control on the MAC to that established with
1aeed8d7 1363 * the link partner.
682011ff
WD		 1364 */
1365 if (hw->mac_type >= e1000_82544) {
1366 e1000_config_collision_dist(hw);
1367 } else {
1368 ret_val = e1000_config_mac_to_phy(hw);
1369 if (ret_val < 0) {
1370 DEBUGOUT
1371 ("Error configuring MAC to PHY settings\n");
1372 return ret_val;
1373 }
1374 }
1375 ret_val = e1000_config_fc_after_link_up(hw);
1376 if (ret_val < 0) {
1377 DEBUGOUT("Error Configuring Flow Control\n");
1378 return ret_val;
1379 }
1380 DEBUGOUT("Valid link established!!!\n");
1381 return 0;
1382 }
1383 udelay(10);
1384 }
1385
1386 DEBUGOUT("Unable to establish link!!!\n");
1387 return -E1000_ERR_NOLINK;
1388}
1389
1390/******************************************************************************
1391* Configures PHY autoneg and flow control advertisement settings
1392*
1393* hw - Struct containing variables accessed by shared code
1394******************************************************************************/
1395static int
1396e1000_phy_setup_autoneg(struct e1000_hw *hw)
1397{
1398 uint16_t mii_autoneg_adv_reg;
1399 uint16_t mii_1000t_ctrl_reg;
1400
1401 DEBUGFUNC();
1402
1403 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1404 if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
1405 DEBUGOUT("PHY Read Error\n");
1406 return -E1000_ERR_PHY;
1407 }
1408
1409 /* Read the MII 1000Base-T Control Register (Address 9). */
1410 if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
1411 DEBUGOUT("PHY Read Error\n");
1412 return -E1000_ERR_PHY;
1413 }
1414
1415 /* Need to parse both autoneg_advertised and fc and set up
1416 * the appropriate PHY registers. First we will parse for
1417 * autoneg_advertised software override. Since we can advertise
1418 * a plethora of combinations, we need to check each bit
1419 * individually.
1420 */
1421
1422 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1423 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1aeed8d7 1424 * the 1000Base-T Control Register (Address 9).
682011ff
WD		 1425 */
1426 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1427 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1428
1429 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
1430
1431 /* Do we want to advertise 10 Mb Half Duplex? */
1432 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1433 DEBUGOUT("Advertise 10mb Half duplex\n");
1434 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1435 }
1436
1437 /* Do we want to advertise 10 Mb Full Duplex? */
1438 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1439 DEBUGOUT("Advertise 10mb Full duplex\n");
1440 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1441 }
1442
1443 /* Do we want to advertise 100 Mb Half Duplex? */
1444 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1445 DEBUGOUT("Advertise 100mb Half duplex\n");
1446 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1447 }
1448
1449 /* Do we want to advertise 100 Mb Full Duplex? */
1450 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1451 DEBUGOUT("Advertise 100mb Full duplex\n");
1452 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1453 }
1454
1455 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1456 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1457 DEBUGOUT
1458 ("Advertise 1000mb Half duplex requested, request denied!\n");
1459 }
1460
1461 /* Do we want to advertise 1000 Mb Full Duplex? */
1462 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1463 DEBUGOUT("Advertise 1000mb Full duplex\n");
1464 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1465 }
1466
1467 /* Check for a software override of the flow control settings, and
1468 * setup the PHY advertisement registers accordingly. If
1469 * auto-negotiation is enabled, then software will have to set the
1470 * "PAUSE" bits to the correct value in the Auto-Negotiation
1471 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1472 *
1473 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 1474 * 0: Flow control is completely disabled
1475 * 1: Rx flow control is enabled (we can receive pause frames
1476 * but not send pause frames).
1477 * 2: Tx flow control is enabled (we can send pause frames
1478 * but we do not support receiving pause frames).
1479 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff 1480 * other: No software override. The flow control configuration
1aeed8d7 1481 * in the EEPROM is used.
682011ff
WD		 1482 */
1483 switch (hw->fc) {
1484 case e1000_fc_none: /* 0 */
1485 /* Flow control (RX & TX) is completely disabled by a
1486 * software over-ride.
1487 */
1488 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1489 break;
1490 case e1000_fc_rx_pause: /* 1 */
1491 /* RX Flow control is enabled, and TX Flow control is
1492 * disabled, by a software over-ride.
1493 */
1494 /* Since there really isn't a way to advertise that we are
1495 * capable of RX Pause ONLY, we will advertise that we
1496 * support both symmetric and asymmetric RX PAUSE. Later
1497 * (in e1000_config_fc_after_link_up) we will disable the
1498 *hw's ability to send PAUSE frames.
1499 */
1500 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1501 break;
1502 case e1000_fc_tx_pause: /* 2 */
1503 /* TX Flow control is enabled, and RX Flow control is
1504 * disabled, by a software over-ride.
1505 */
1506 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1507 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1508 break;
1509 case e1000_fc_full: /* 3 */
1510 /* Flow control (both RX and TX) is enabled by a software
1511 * over-ride.
1512 */
1513 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1514 break;
1515 default:
1516 DEBUGOUT("Flow control param set incorrectly\n");
1517 return -E1000_ERR_CONFIG;
1518 }
1519
1520 if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
1521 DEBUGOUT("PHY Write Error\n");
1522 return -E1000_ERR_PHY;
1523 }
1524
1525 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1526
1527 if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
1528 DEBUGOUT("PHY Write Error\n");
1529 return -E1000_ERR_PHY;
1530 }
1531 return 0;
1532}
1533
1534/******************************************************************************
1535* Sets the collision distance in the Transmit Control register
1536*
1537* hw - Struct containing variables accessed by shared code
1538*
1539* Link should have been established previously. Reads the speed and duplex
1540* information from the Device Status register.
1541******************************************************************************/
1542static void
1543e1000_config_collision_dist(struct e1000_hw *hw)
1544{
1545 uint32_t tctl;
1546
1547 tctl = E1000_READ_REG(hw, TCTL);
1548
1549 tctl &= ~E1000_TCTL_COLD;
1550 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1551
1552 E1000_WRITE_REG(hw, TCTL, tctl);
1553 E1000_WRITE_FLUSH(hw);
1554}
1555
1556/******************************************************************************
1557* Sets MAC speed and duplex settings to reflect the those in the PHY
1558*
1559* hw - Struct containing variables accessed by shared code
1560* mii_reg - data to write to the MII control register
1561*
1562* The contents of the PHY register containing the needed information need to
1563* be passed in.
1564******************************************************************************/
1565static int
1566e1000_config_mac_to_phy(struct e1000_hw *hw)
1567{
1568 uint32_t ctrl;
1569 uint16_t phy_data;
1570
1571 DEBUGFUNC();
1572
1573 /* Read the Device Control Register and set the bits to Force Speed
1574 * and Duplex.
1575 */
1576 ctrl = E1000_READ_REG(hw, CTRL);
1577 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1578 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1579
1580 /* Set up duplex in the Device Control and Transmit Control
1581 * registers depending on negotiated values.
1582 */
1583 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
1584 DEBUGOUT("PHY Read Error\n");
1585 return -E1000_ERR_PHY;
1586 }
1587 if (phy_data & M88E1000_PSSR_DPLX)
1588 ctrl |= E1000_CTRL_FD;
1589 else
1590 ctrl &= ~E1000_CTRL_FD;
1591
1592 e1000_config_collision_dist(hw);
1593
1594 /* Set up speed in the Device Control register depending on
1595 * negotiated values.
1596 */
1597 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1598 ctrl |= E1000_CTRL_SPD_1000;
1599 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1600 ctrl |= E1000_CTRL_SPD_100;
1601 /* Write the configured values back to the Device Control Reg. */
1602 E1000_WRITE_REG(hw, CTRL, ctrl);
1603 return 0;
1604}
1605
1606/******************************************************************************
1607 * Forces the MAC's flow control settings.
8bde7f77 1608 *
682011ff
WD		 1609 * hw - Struct containing variables accessed by shared code
1610 *
1611 * Sets the TFCE and RFCE bits in the device control register to reflect
1612 * the adapter settings. TFCE and RFCE need to be explicitly set by
1613 * software when a Copper PHY is used because autonegotiation is managed
1614 * by the PHY rather than the MAC. Software must also configure these
1615 * bits when link is forced on a fiber connection.
1616 *****************************************************************************/
1617static int
1618e1000_force_mac_fc(struct e1000_hw *hw)
1619{
1620 uint32_t ctrl;
1621
1622 DEBUGFUNC();
1623
1624 /* Get the current configuration of the Device Control Register */
1625 ctrl = E1000_READ_REG(hw, CTRL);
1626
1627 /* Because we didn't get link via the internal auto-negotiation
1628 * mechanism (we either forced link or we got link via PHY
1629 * auto-neg), we have to manually enable/disable transmit an
1630 * receive flow control.
1631 *
1632 * The "Case" statement below enables/disable flow control
1633 * according to the "hw->fc" parameter.
1634 *
1635 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 1636 * 0: Flow control is completely disabled
1637 * 1: Rx flow control is enabled (we can receive pause
1638 * frames but not send pause frames).
1639 * 2: Tx flow control is enabled (we can send pause frames
1640 * frames but we do not receive pause frames).
1641 * 3: Both Rx and TX flow control (symmetric) is enabled.
682011ff
WD		 1642 * other: No other values should be possible at this point.
1643 */
1644
1645 switch (hw->fc) {
1646 case e1000_fc_none:
1647 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1648 break;
1649 case e1000_fc_rx_pause:
1650 ctrl &= (~E1000_CTRL_TFCE);
1651 ctrl |= E1000_CTRL_RFCE;
1652 break;
1653 case e1000_fc_tx_pause:
1654 ctrl &= (~E1000_CTRL_RFCE);
1655 ctrl |= E1000_CTRL_TFCE;
1656 break;
1657 case e1000_fc_full:
1658 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1659 break;
1660 default:
1661 DEBUGOUT("Flow control param set incorrectly\n");
1662 return -E1000_ERR_CONFIG;
1663 }
1664
1665 /* Disable TX Flow Control for 82542 (rev 2.0) */
1666 if (hw->mac_type == e1000_82542_rev2_0)
1667 ctrl &= (~E1000_CTRL_TFCE);
1668
1669 E1000_WRITE_REG(hw, CTRL, ctrl);
1670 return 0;
1671}
1672
1673/******************************************************************************
1674 * Configures flow control settings after link is established
8bde7f77 1675 *
682011ff
WD		 1676 * hw - Struct containing variables accessed by shared code
1677 *
1678 * Should be called immediately after a valid link has been established.
1679 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1680 * and autonegotiation is enabled, the MAC flow control settings will be set
1681 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1682 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1683 *****************************************************************************/
1684static int
1685e1000_config_fc_after_link_up(struct e1000_hw *hw)
1686{
1687 int32_t ret_val;
1688 uint16_t mii_status_reg;
1689 uint16_t mii_nway_adv_reg;
1690 uint16_t mii_nway_lp_ability_reg;
1691 uint16_t speed;
1692 uint16_t duplex;
1693
1694 DEBUGFUNC();
1695
1696 /* Check for the case where we have fiber media and auto-neg failed
1697 * so we had to force link. In this case, we need to force the
1698 * configuration of the MAC to match the "fc" parameter.
1699 */
1700 if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) {
1701 ret_val = e1000_force_mac_fc(hw);
1702 if (ret_val < 0) {
1703 DEBUGOUT("Error forcing flow control settings\n");
1704 return ret_val;
1705 }
1706 }
1707
1708 /* Check for the case where we have copper media and auto-neg is
1709 * enabled. In this case, we need to check and see if Auto-Neg
1710 * has completed, and if so, how the PHY and link partner has
1711 * flow control configured.
1712 */
1713 if (hw->media_type == e1000_media_type_copper) {
1714 /* Read the MII Status Register and check to see if AutoNeg
1715 * has completed. We read this twice because this reg has
1716 * some "sticky" (latched) bits.
1717 */
1718 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1719 DEBUGOUT("PHY Read Error \n");
1720 return -E1000_ERR_PHY;
1721 }
1722 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1723 DEBUGOUT("PHY Read Error \n");
1724 return -E1000_ERR_PHY;
1725 }
1726
1727 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1728 /* The AutoNeg process has completed, so we now need to
1729 * read both the Auto Negotiation Advertisement Register
1730 * (Address 4) and the Auto_Negotiation Base Page Ability
1731 * Register (Address 5) to determine how flow control was
1732 * negotiated.
1733 */
1734 if (e1000_read_phy_reg
1735 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
1736 DEBUGOUT("PHY Read Error\n");
1737 return -E1000_ERR_PHY;
1738 }
1739 if (e1000_read_phy_reg
1740 (hw, PHY_LP_ABILITY,
1741 &mii_nway_lp_ability_reg) < 0) {
1742 DEBUGOUT("PHY Read Error\n");
1743 return -E1000_ERR_PHY;
1744 }
1745
1746 /* Two bits in the Auto Negotiation Advertisement Register
1747 * (Address 4) and two bits in the Auto Negotiation Base
1748 * Page Ability Register (Address 5) determine flow control
1749 * for both the PHY and the link partner. The following
1750 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1751 * 1999, describes these PAUSE resolution bits and how flow
1752 * control is determined based upon these settings.
1753 * NOTE: DC = Don't Care
1754 *
1755 * LOCAL DEVICE | LINK PARTNER
1756 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1757 *-------|---------|-------|---------|--------------------
1aeed8d7
WD		 1758 * 0 | 0 | DC | DC | e1000_fc_none
1759 * 0 | 1 | 0 | DC | e1000_fc_none
1760 * 0 | 1 | 1 | 0 | e1000_fc_none
1761 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1762 * 1 | 0 | 0 | DC | e1000_fc_none
1763 * 1 | DC | 1 | DC | e1000_fc_full
1764 * 1 | 1 | 0 | 0 | e1000_fc_none
1765 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 1766 *
1767 */
1768 /* Are both PAUSE bits set to 1? If so, this implies
1769 * Symmetric Flow Control is enabled at both ends. The
1770 * ASM_DIR bits are irrelevant per the spec.
1771 *
1772 * For Symmetric Flow Control:
1773 *
1774 * LOCAL DEVICE | LINK PARTNER
1775 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1776 *-------|---------|-------|---------|--------------------
1aeed8d7 1777 * 1 | DC | 1 | DC | e1000_fc_full
682011ff
WD		 1778 *
1779 */
1780 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1781 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1782 /* Now we need to check if the user selected RX ONLY
1783 * of pause frames. In this case, we had to advertise
1784 * FULL flow control because we could not advertise RX
1785 * ONLY. Hence, we must now check to see if we need to
1786 * turn OFF the TRANSMISSION of PAUSE frames.
1787 */
1788 if (hw->original_fc == e1000_fc_full) {
1789 hw->fc = e1000_fc_full;
1790 DEBUGOUT("Flow Control = FULL.\r\n");
1791 } else {
1792 hw->fc = e1000_fc_rx_pause;
1793 DEBUGOUT
1794 ("Flow Control = RX PAUSE frames only.\r\n");
1795 }
1796 }
1797 /* For receiving PAUSE frames ONLY.
1798 *
1799 * LOCAL DEVICE | LINK PARTNER
1800 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1801 *-------|---------|-------|---------|--------------------
1aeed8d7 1802 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
682011ff
WD		 1803 *
1804 */
1805 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1806 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1807 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1808 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
1809 {
1810 hw->fc = e1000_fc_tx_pause;
1811 DEBUGOUT
1812 ("Flow Control = TX PAUSE frames only.\r\n");
1813 }
1814 /* For transmitting PAUSE frames ONLY.
1815 *
1816 * LOCAL DEVICE | LINK PARTNER
1817 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1818 *-------|---------|-------|---------|--------------------
1aeed8d7 1819 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 1820 *
1821 */
1822 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1823 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1824 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1825 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
1826 {
1827 hw->fc = e1000_fc_rx_pause;
1828 DEBUGOUT
1829 ("Flow Control = RX PAUSE frames only.\r\n");
1830 }
1831 /* Per the IEEE spec, at this point flow control should be
1832 * disabled. However, we want to consider that we could
1833 * be connected to a legacy switch that doesn't advertise
1834 * desired flow control, but can be forced on the link
1835 * partner. So if we advertised no flow control, that is
1836 * what we will resolve to. If we advertised some kind of
1837 * receive capability (Rx Pause Only or Full Flow Control)
1838 * and the link partner advertised none, we will configure
1839 * ourselves to enable Rx Flow Control only. We can do
1840 * this safely for two reasons: If the link partner really
1841 * didn't want flow control enabled, and we enable Rx, no
1842 * harm done since we won't be receiving any PAUSE frames
1843 * anyway. If the intent on the link partner was to have
1844 * flow control enabled, then by us enabling RX only, we
1845 * can at least receive pause frames and process them.
1846 * This is a good idea because in most cases, since we are
1847 * predominantly a server NIC, more times than not we will
1848 * be asked to delay transmission of packets than asking
1849 * our link partner to pause transmission of frames.
1850 */
1851 else if (hw->original_fc == e1000_fc_none ||
1852 hw->original_fc == e1000_fc_tx_pause) {
1853 hw->fc = e1000_fc_none;
1854 DEBUGOUT("Flow Control = NONE.\r\n");
1855 } else {
1856 hw->fc = e1000_fc_rx_pause;
1857 DEBUGOUT
1858 ("Flow Control = RX PAUSE frames only.\r\n");
1859 }
1860
1aeed8d7 1861 /* Now we need to do one last check... If we auto-
682011ff
WD		 1862 * negotiated to HALF DUPLEX, flow control should not be
1863 * enabled per IEEE 802.3 spec.
1864 */
1865 e1000_get_speed_and_duplex(hw, &speed, &duplex);
1866
1867 if (duplex == HALF_DUPLEX)
1868 hw->fc = e1000_fc_none;
1869
1870 /* Now we call a subroutine to actually force the MAC
1871 * controller to use the correct flow control settings.
1872 */
1873 ret_val = e1000_force_mac_fc(hw);
1874 if (ret_val < 0) {
1875 DEBUGOUT
1876 ("Error forcing flow control settings\n");
1877 return ret_val;
1878 }
1879 } else {
1880 DEBUGOUT
1881 ("Copper PHY and Auto Neg has not completed.\r\n");
1882 }
1883 }
1884 return 0;
1885}
1886
1887/******************************************************************************
1888 * Checks to see if the link status of the hardware has changed.
1889 *
1890 * hw - Struct containing variables accessed by shared code
1891 *
1892 * Called by any function that needs to check the link status of the adapter.
1893 *****************************************************************************/
1894static int
1895e1000_check_for_link(struct eth_device *nic)
1896{
1897 struct e1000_hw *hw = nic->priv;
1898 uint32_t rxcw;
1899 uint32_t ctrl;
1900 uint32_t status;
1901 uint32_t rctl;
1902 uint32_t signal;
1903 int32_t ret_val;
1904 uint16_t phy_data;
1905 uint16_t lp_capability;
1906
1907 DEBUGFUNC();
1908
8bde7f77
WD		 1909 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1910 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 1911 * cleared when there is a signal
1912 */
1913 ctrl = E1000_READ_REG(hw, CTRL);
1914 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1915 signal = E1000_CTRL_SWDPIN1;
1916 else
1917 signal = 0;
1918
1919 status = E1000_READ_REG(hw, STATUS);
1920 rxcw = E1000_READ_REG(hw, RXCW);
1921 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
1922
1923 /* If we have a copper PHY then we only want to go out to the PHY
1924 * registers to see if Auto-Neg has completed and/or if our link
1aeed8d7 1925 * status has changed. The get_link_status flag will be set if we
682011ff
WD		 1926 * receive a Link Status Change interrupt or we have Rx Sequence
1927 * Errors.
1928 */
1929 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1930 /* First we want to see if the MII Status Register reports
1931 * link. If so, then we want to get the current speed/duplex
1932 * of the PHY.
1933 * Read the register twice since the link bit is sticky.
1934 */
1935 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1936 DEBUGOUT("PHY Read Error\n");
1937 return -E1000_ERR_PHY;
1938 }
1939 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1940 DEBUGOUT("PHY Read Error\n");
1941 return -E1000_ERR_PHY;
1942 }
1943
1944 if (phy_data & MII_SR_LINK_STATUS) {
1945 hw->get_link_status = FALSE;
1946 } else {
1947 /* No link detected */
1948 return -E1000_ERR_NOLINK;
1949 }
1950
1951 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
1952 * have Si on board that is 82544 or newer, Auto
1953 * Speed Detection takes care of MAC speed/duplex
1954 * configuration. So we only need to configure Collision
1955 * Distance in the MAC. Otherwise, we need to force
1956 * speed/duplex on the MAC to the current PHY speed/duplex
1957 * settings.
1958 */
1959 if (hw->mac_type >= e1000_82544)
1960 e1000_config_collision_dist(hw);
1961 else {
1962 ret_val = e1000_config_mac_to_phy(hw);
1963 if (ret_val < 0) {
1964 DEBUGOUT
1965 ("Error configuring MAC to PHY settings\n");
1966 return ret_val;
1967 }
1968 }
1969
8bde7f77 1970 /* Configure Flow Control now that Auto-Neg has completed. First, we
682011ff
WD		 1971 * need to restore the desired flow control settings because we may
1972 * have had to re-autoneg with a different link partner.
1973 */
1974 ret_val = e1000_config_fc_after_link_up(hw);
1975 if (ret_val < 0) {
1976 DEBUGOUT("Error configuring flow control\n");
1977 return ret_val;
1978 }
1979
1980 /* At this point we know that we are on copper and we have
1981 * auto-negotiated link. These are conditions for checking the link
1aeed8d7 1982 * parter capability register. We use the link partner capability to
682011ff
WD		 1983 * determine if TBI Compatibility needs to be turned on or off. If
1984 * the link partner advertises any speed in addition to Gigabit, then
1985 * we assume that they are GMII-based, and TBI compatibility is not
1986 * needed. If no other speeds are advertised, we assume the link
1987 * partner is TBI-based, and we turn on TBI Compatibility.
1988 */
1989 if (hw->tbi_compatibility_en) {
1990 if (e1000_read_phy_reg
1991 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
1992 DEBUGOUT("PHY Read Error\n");
1993 return -E1000_ERR_PHY;
1994 }
1995 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
1996 NWAY_LPAR_10T_FD_CAPS |
1997 NWAY_LPAR_100TX_HD_CAPS |
1998 NWAY_LPAR_100TX_FD_CAPS |
1999 NWAY_LPAR_100T4_CAPS)) {
8bde7f77 2000 /* If our link partner advertises anything in addition to
682011ff
WD		 2001 * gigabit, we do not need to enable TBI compatibility.
2002 */
2003 if (hw->tbi_compatibility_on) {
2004 /* If we previously were in the mode, turn it off. */
2005 rctl = E1000_READ_REG(hw, RCTL);
2006 rctl &= ~E1000_RCTL_SBP;
2007 E1000_WRITE_REG(hw, RCTL, rctl);
2008 hw->tbi_compatibility_on = FALSE;
2009 }
2010 } else {
2011 /* If TBI compatibility is was previously off, turn it on. For
2012 * compatibility with a TBI link partner, we will store bad
2013 * packets. Some frames have an additional byte on the end and
2014 * will look like CRC errors to to the hardware.
2015 */
2016 if (!hw->tbi_compatibility_on) {
2017 hw->tbi_compatibility_on = TRUE;
2018 rctl = E1000_READ_REG(hw, RCTL);
2019 rctl |= E1000_RCTL_SBP;
2020 E1000_WRITE_REG(hw, RCTL, rctl);
2021 }
2022 }
2023 }
2024 }
2025 /* If we don't have link (auto-negotiation failed or link partner cannot
2026 * auto-negotiate), the cable is plugged in (we have signal), and our
2027 * link partner is not trying to auto-negotiate with us (we are receiving
2028 * idles or data), we need to force link up. We also need to give
2029 * auto-negotiation time to complete, in case the cable was just plugged
2030 * in. The autoneg_failed flag does this.
2031 */
2032 else if ((hw->media_type == e1000_media_type_fiber) &&
2033 (!(status & E1000_STATUS_LU)) &&
2034 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
2035 (!(rxcw & E1000_RXCW_C))) {
2036 if (hw->autoneg_failed == 0) {
2037 hw->autoneg_failed = 1;
2038 return 0;
2039 }
2040 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2041
2042 /* Disable auto-negotiation in the TXCW register */
2043 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2044
2045 /* Force link-up and also force full-duplex. */
2046 ctrl = E1000_READ_REG(hw, CTRL);
2047 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2048 E1000_WRITE_REG(hw, CTRL, ctrl);
2049
2050 /* Configure Flow Control after forcing link up. */
2051 ret_val = e1000_config_fc_after_link_up(hw);
2052 if (ret_val < 0) {
2053 DEBUGOUT("Error configuring flow control\n");
2054 return ret_val;
2055 }
2056 }
2057 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2058 * auto-negotiation in the TXCW register and disable forced link in the
2059 * Device Control register in an attempt to auto-negotiate with our link
2060 * partner.
2061 */
2062 else if ((hw->media_type == e1000_media_type_fiber) &&
2063 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2064 DEBUGOUT
2065 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2066 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2067 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2068 }
2069 return 0;
2070}
2071
2072/******************************************************************************
2073 * Detects the current speed and duplex settings of the hardware.
2074 *
2075 * hw - Struct containing variables accessed by shared code
2076 * speed - Speed of the connection
2077 * duplex - Duplex setting of the connection
2078 *****************************************************************************/
2079static void
2080e1000_get_speed_and_duplex(struct e1000_hw *hw,
2081 uint16_t * speed, uint16_t * duplex)
2082{
2083 uint32_t status;
2084
2085 DEBUGFUNC();
2086
2087 if (hw->mac_type >= e1000_82543) {
2088 status = E1000_READ_REG(hw, STATUS);
2089 if (status & E1000_STATUS_SPEED_1000) {
2090 *speed = SPEED_1000;
2091 DEBUGOUT("1000 Mbs, ");
2092 } else if (status & E1000_STATUS_SPEED_100) {
2093 *speed = SPEED_100;
2094 DEBUGOUT("100 Mbs, ");
2095 } else {
2096 *speed = SPEED_10;
2097 DEBUGOUT("10 Mbs, ");
2098 }
2099
2100 if (status & E1000_STATUS_FD) {
2101 *duplex = FULL_DUPLEX;
2102 DEBUGOUT("Full Duplex\r\n");
2103 } else {
2104 *duplex = HALF_DUPLEX;
2105 DEBUGOUT(" Half Duplex\r\n");
2106 }
2107 } else {
2108 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2109 *speed = SPEED_1000;
2110 *duplex = FULL_DUPLEX;
2111 }
2112}
2113
2114/******************************************************************************
2115* Blocks until autoneg completes or times out (~4.5 seconds)
2116*
2117* hw - Struct containing variables accessed by shared code
2118******************************************************************************/
2119static int
2120e1000_wait_autoneg(struct e1000_hw *hw)
2121{
2122 uint16_t i;
2123 uint16_t phy_data;
2124
2125 DEBUGFUNC();
2126 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2127
2128 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2129 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2130 /* Read the MII Status Register and wait for Auto-Neg
2131 * Complete bit to be set.
2132 */
2133 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
2134 DEBUGOUT("PHY Read Error\n");
2135 return -E1000_ERR_PHY;
2136 }
2137 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
2138 DEBUGOUT("PHY Read Error\n");
2139 return -E1000_ERR_PHY;
2140 }
2141 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2142 DEBUGOUT("Auto-Neg complete.\n");
2143 return 0;
2144 }
2145 mdelay(100);
2146 }
2147 DEBUGOUT("Auto-Neg timedout.\n");
2148 return -E1000_ERR_TIMEOUT;
2149}
2150
2151/******************************************************************************
2152* Raises the Management Data Clock
2153*
2154* hw - Struct containing variables accessed by shared code
2155* ctrl - Device control register's current value
2156******************************************************************************/
2157static void
2158e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
2159{
2160 /* Raise the clock input to the Management Data Clock (by setting the MDC
2161 * bit), and then delay 2 microseconds.
2162 */
2163 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2164 E1000_WRITE_FLUSH(hw);
2165 udelay(2);
2166}
2167
2168/******************************************************************************
2169* Lowers the Management Data Clock
2170*
2171* hw - Struct containing variables accessed by shared code
2172* ctrl - Device control register's current value
2173******************************************************************************/
2174static void
2175e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
2176{
2177 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2178 * bit), and then delay 2 microseconds.
2179 */
2180 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2181 E1000_WRITE_FLUSH(hw);
2182 udelay(2);
2183}
2184
2185/******************************************************************************
2186* Shifts data bits out to the PHY
2187*
2188* hw - Struct containing variables accessed by shared code
2189* data - Data to send out to the PHY
2190* count - Number of bits to shift out
2191*
2192* Bits are shifted out in MSB to LSB order.
2193******************************************************************************/
2194static void
2195e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
2196{
2197 uint32_t ctrl;
2198 uint32_t mask;
2199
2200 /* We need to shift "count" number of bits out to the PHY. So, the value
8bde7f77 2201 * in the "data" parameter will be shifted out to the PHY one bit at a
682011ff
WD		 2202 * time. In order to do this, "data" must be broken down into bits.
2203 */
2204 mask = 0x01;
2205 mask <<= (count - 1);
2206
2207 ctrl = E1000_READ_REG(hw, CTRL);
2208
2209 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2210 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2211
2212 while (mask) {
2213 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2214 * then raising and lowering the Management Data Clock. A "0" is
2215 * shifted out to the PHY by setting the MDIO bit to "0" and then
2216 * raising and lowering the clock.
2217 */
2218 if (data & mask)
2219 ctrl |= E1000_CTRL_MDIO;
2220 else
2221 ctrl &= ~E1000_CTRL_MDIO;
2222
2223 E1000_WRITE_REG(hw, CTRL, ctrl);
2224 E1000_WRITE_FLUSH(hw);
2225
2226 udelay(2);
2227
2228 e1000_raise_mdi_clk(hw, &ctrl);
2229 e1000_lower_mdi_clk(hw, &ctrl);
2230
2231 mask = mask >> 1;
2232 }
2233}
2234
2235/******************************************************************************
2236* Shifts data bits in from the PHY
2237*
2238* hw - Struct containing variables accessed by shared code
2239*
8bde7f77 2240* Bits are shifted in in MSB to LSB order.
682011ff
WD		 2241******************************************************************************/
2242static uint16_t
2243e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2244{
2245 uint32_t ctrl;
2246 uint16_t data = 0;
2247 uint8_t i;
2248
2249 /* In order to read a register from the PHY, we need to shift in a total
2250 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2251 * to avoid contention on the MDIO pin when a read operation is performed.
2252 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2253 * by raising the input to the Management Data Clock (setting the MDC bit),
2254 * and then reading the value of the MDIO bit.
2255 */
2256 ctrl = E1000_READ_REG(hw, CTRL);
2257
2258 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2259 ctrl &= ~E1000_CTRL_MDIO_DIR;
2260 ctrl &= ~E1000_CTRL_MDIO;
2261
2262 E1000_WRITE_REG(hw, CTRL, ctrl);
2263 E1000_WRITE_FLUSH(hw);
2264
2265 /* Raise and Lower the clock before reading in the data. This accounts for
2266 * the turnaround bits. The first clock occurred when we clocked out the
2267 * last bit of the Register Address.
2268 */
2269 e1000_raise_mdi_clk(hw, &ctrl);
2270 e1000_lower_mdi_clk(hw, &ctrl);
2271
2272 for (data = 0, i = 0; i < 16; i++) {
2273 data = data << 1;
2274 e1000_raise_mdi_clk(hw, &ctrl);
2275 ctrl = E1000_READ_REG(hw, CTRL);
2276 /* Check to see if we shifted in a "1". */
2277 if (ctrl & E1000_CTRL_MDIO)
2278 data |= 1;
2279 e1000_lower_mdi_clk(hw, &ctrl);
2280 }
2281
2282 e1000_raise_mdi_clk(hw, &ctrl);
2283 e1000_lower_mdi_clk(hw, &ctrl);
2284
2285 return data;
2286}
2287
2288/*****************************************************************************
2289* Reads the value from a PHY register
2290*
2291* hw - Struct containing variables accessed by shared code
2292* reg_addr - address of the PHY register to read
2293******************************************************************************/
2294static int
2295e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
2296{
2297 uint32_t i;
2298 uint32_t mdic = 0;
2299 const uint32_t phy_addr = 1;
2300
2301 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2302 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
2303 return -E1000_ERR_PARAM;
2304 }
2305
2306 if (hw->mac_type > e1000_82543) {
2307 /* Set up Op-code, Phy Address, and register address in the MDI
2308 * Control register. The MAC will take care of interfacing with the
2309 * PHY to retrieve the desired data.
2310 */
2311 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2312 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2313 (E1000_MDIC_OP_READ));
2314
2315 E1000_WRITE_REG(hw, MDIC, mdic);
2316
2317 /* Poll the ready bit to see if the MDI read completed */
2318 for (i = 0; i < 64; i++) {
2319 udelay(10);
2320 mdic = E1000_READ_REG(hw, MDIC);
2321 if (mdic & E1000_MDIC_READY)
2322 break;
2323 }
2324 if (!(mdic & E1000_MDIC_READY)) {
2325 DEBUGOUT("MDI Read did not complete\n");
2326 return -E1000_ERR_PHY;
2327 }
2328 if (mdic & E1000_MDIC_ERROR) {
2329 DEBUGOUT("MDI Error\n");
2330 return -E1000_ERR_PHY;
2331 }
2332 *phy_data = (uint16_t) mdic;
2333 } else {
2334 /* We must first send a preamble through the MDIO pin to signal the
2335 * beginning of an MII instruction. This is done by sending 32
2336 * consecutive "1" bits.
2337 */
2338 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2339
2340 /* Now combine the next few fields that are required for a read
2341 * operation. We use this method instead of calling the
2342 * e1000_shift_out_mdi_bits routine five different times. The format of
2343 * a MII read instruction consists of a shift out of 14 bits and is
2344 * defined as follows:
2345 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2346 * followed by a shift in of 18 bits. This first two bits shifted in
2347 * are TurnAround bits used to avoid contention on the MDIO pin when a
2348 * READ operation is performed. These two bits are thrown away
2349 * followed by a shift in of 16 bits which contains the desired data.
2350 */
2351 mdic = ((reg_addr) | (phy_addr << 5) |
2352 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2353
2354 e1000_shift_out_mdi_bits(hw, mdic, 14);
2355
2356 /* Now that we've shifted out the read command to the MII, we need to
2357 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2358 * register address.
2359 */
2360 *phy_data = e1000_shift_in_mdi_bits(hw);
2361 }
2362 return 0;
2363}
2364
2365/******************************************************************************
2366* Writes a value to a PHY register
2367*
2368* hw - Struct containing variables accessed by shared code
2369* reg_addr - address of the PHY register to write
2370* data - data to write to the PHY
2371******************************************************************************/
2372static int
2373e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
2374{
2375 uint32_t i;
2376 uint32_t mdic = 0;
2377 const uint32_t phy_addr = 1;
2378
2379 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2380 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
2381 return -E1000_ERR_PARAM;
2382 }
2383
2384 if (hw->mac_type > e1000_82543) {
2385 /* Set up Op-code, Phy Address, register address, and data intended
2386 * for the PHY register in the MDI Control register. The MAC will take
2387 * care of interfacing with the PHY to send the desired data.
2388 */
2389 mdic = (((uint32_t) phy_data) |
2390 (reg_addr << E1000_MDIC_REG_SHIFT) |
2391 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2392 (E1000_MDIC_OP_WRITE));
2393
2394 E1000_WRITE_REG(hw, MDIC, mdic);
2395
2396 /* Poll the ready bit to see if the MDI read completed */
2397 for (i = 0; i < 64; i++) {
2398 udelay(10);
2399 mdic = E1000_READ_REG(hw, MDIC);
2400 if (mdic & E1000_MDIC_READY)
2401 break;
2402 }
2403 if (!(mdic & E1000_MDIC_READY)) {
2404 DEBUGOUT("MDI Write did not complete\n");
2405 return -E1000_ERR_PHY;
2406 }
2407 } else {
2408 /* We'll need to use the SW defined pins to shift the write command
2409 * out to the PHY. We first send a preamble to the PHY to signal the
8bde7f77 2410 * beginning of the MII instruction. This is done by sending 32
682011ff
WD		 2411 * consecutive "1" bits.
2412 */
2413 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2414
8bde7f77 2415 /* Now combine the remaining required fields that will indicate a
682011ff
WD		 2416 * write operation. We use this method instead of calling the
2417 * e1000_shift_out_mdi_bits routine for each field in the command. The
2418 * format of a MII write instruction is as follows:
2419 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2420 */
2421 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2422 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2423 mdic <<= 16;
2424 mdic |= (uint32_t) phy_data;
2425
2426 e1000_shift_out_mdi_bits(hw, mdic, 32);
2427 }
2428 return 0;
2429}
2430
2431/******************************************************************************
2432* Returns the PHY to the power-on reset state
2433*
2434* hw - Struct containing variables accessed by shared code
2435******************************************************************************/
2436static void
2437e1000_phy_hw_reset(struct e1000_hw *hw)
2438{
2439 uint32_t ctrl;
2440 uint32_t ctrl_ext;
2441
2442 DEBUGFUNC();
2443
2444 DEBUGOUT("Resetting Phy...\n");
2445
2446 if (hw->mac_type > e1000_82543) {
2447 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2448 * bit. Then, take it out of reset.
2449 */
2450 ctrl = E1000_READ_REG(hw, CTRL);
2451 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2452 E1000_WRITE_FLUSH(hw);
2453 mdelay(10);
2454 E1000_WRITE_REG(hw, CTRL, ctrl);
2455 E1000_WRITE_FLUSH(hw);
2456 } else {
2457 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2458 * bit to put the PHY into reset. Then, take it out of reset.
2459 */
2460 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2461 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2462 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2463 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2464 E1000_WRITE_FLUSH(hw);
2465 mdelay(10);
2466 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2467 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2468 E1000_WRITE_FLUSH(hw);
2469 }
2470 udelay(150);
2471}
2472
2473/******************************************************************************
2474* Resets the PHY
2475*
2476* hw - Struct containing variables accessed by shared code
2477*
2478* Sets bit 15 of the MII Control regiser
2479******************************************************************************/
2480static int
2481e1000_phy_reset(struct e1000_hw *hw)
2482{
2483 uint16_t phy_data;
2484
2485 DEBUGFUNC();
2486
2487 if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
2488 DEBUGOUT("PHY Read Error\n");
2489 return -E1000_ERR_PHY;
2490 }
2491 phy_data |= MII_CR_RESET;
2492 if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
2493 DEBUGOUT("PHY Write Error\n");
2494 return -E1000_ERR_PHY;
2495 }
2496 udelay(1);
2497 return 0;
2498}
2499
1aeed8d7 2500static int e1000_set_phy_type (struct e1000_hw *hw)
ac3315c2 2501{
1aeed8d7
WD		 2502 DEBUGFUNC ();
2503
2504 if (hw->mac_type == e1000_undefined)
2505 return -E1000_ERR_PHY_TYPE;
2506
2507 switch (hw->phy_id) {
2508 case M88E1000_E_PHY_ID:
2509 case M88E1000_I_PHY_ID:
2510 case M88E1011_I_PHY_ID:
2511 hw->phy_type = e1000_phy_m88;
2512 break;
2513 case IGP01E1000_I_PHY_ID:
2514 if (hw->mac_type == e1000_82541 ||
2515 hw->mac_type == e1000_82541_rev_2) {
2516 hw->phy_type = e1000_phy_igp;
2517 break;
2518 }
2519 /* Fall Through */
2520 default:
2521 /* Should never have loaded on this device */
2522 hw->phy_type = e1000_phy_undefined;
2523 return -E1000_ERR_PHY_TYPE;
2524 }
2525
2526 return E1000_SUCCESS;
ac3315c2
AS		 2527}
2528
682011ff
WD		 2529/******************************************************************************
2530* Probes the expected PHY address for known PHY IDs
2531*
2532* hw - Struct containing variables accessed by shared code
2533******************************************************************************/
2534static int
2535e1000_detect_gig_phy(struct e1000_hw *hw)
2536{
ac3315c2 2537 int32_t phy_init_status;
682011ff
WD		 2538 uint16_t phy_id_high, phy_id_low;
2539 int match = FALSE;
2540
2541 DEBUGFUNC();
2542
2543 /* Read the PHY ID Registers to identify which PHY is onboard. */
2544 if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
2545 DEBUGOUT("PHY Read Error\n");
2546 return -E1000_ERR_PHY;
2547 }
2548 hw->phy_id = (uint32_t) (phy_id_high << 16);
2549 udelay(2);
2550 if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
2551 DEBUGOUT("PHY Read Error\n");
2552 return -E1000_ERR_PHY;
2553 }
2554 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2555
2556 switch (hw->mac_type) {
2557 case e1000_82543:
2558 if (hw->phy_id == M88E1000_E_PHY_ID)
2559 match = TRUE;
2560 break;
2561 case e1000_82544:
2562 if (hw->phy_id == M88E1000_I_PHY_ID)
2563 match = TRUE;
2564 break;
2565 case e1000_82540:
2566 case e1000_82545:
2567 case e1000_82546:
2568 if (hw->phy_id == M88E1011_I_PHY_ID)
2569 match = TRUE;
2570 break;
ac3315c2
AS		 2571 case e1000_82541_rev_2:
2572 if(hw->phy_id == IGP01E1000_I_PHY_ID)
2573 match = TRUE;
2574
2575 break;
682011ff
WD		 2576 default:
2577 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
2578 return -E1000_ERR_CONFIG;
2579 }
ac3315c2
AS		 2580
2581 phy_init_status = e1000_set_phy_type(hw);
2582
2583 if ((match) && (phy_init_status == E1000_SUCCESS)) {
682011ff
WD		 2584 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
2585 return 0;
2586 }
2587 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
2588 return -E1000_ERR_PHY;
2589}
2590
2591/**
2592 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
2593 *
2594 * e1000_sw_init initializes the Adapter private data structure.
2595 * Fields are initialized based on PCI device information and
2596 * OS network device settings (MTU size).
2597 **/
2598
2599static int
2600e1000_sw_init(struct eth_device *nic, int cardnum)
2601{
2602 struct e1000_hw *hw = (typeof(hw)) nic->priv;
2603 int result;
2604
2605 /* PCI config space info */
2606 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
2607 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
2608 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
2609 &hw->subsystem_vendor_id);
2610 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
2611
2612 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
2613 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
2614
2615 /* identify the MAC */
2616 result = e1000_set_mac_type(hw);
2617 if (result) {
2618 E1000_ERR("Unknown MAC Type\n");
2619 return result;
2620 }
2621
2622 /* lan a vs. lan b settings */
2623 if (hw->mac_type == e1000_82546)
2624 /*this also works w/ multiple 82546 cards */
2625 /*but not if they're intermingled /w other e1000s */
2626 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
2627 else
2628 hw->lan_loc = e1000_lan_a;
2629
2630 /* flow control settings */
2631 hw->fc_high_water = E1000_FC_HIGH_THRESH;
2632 hw->fc_low_water = E1000_FC_LOW_THRESH;
2633 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
2634 hw->fc_send_xon = 1;
2635
2636 /* Media type - copper or fiber */
2637
2638 if (hw->mac_type >= e1000_82543) {
2639 uint32_t status = E1000_READ_REG(hw, STATUS);
2640
2641 if (status & E1000_STATUS_TBIMODE) {
2642 DEBUGOUT("fiber interface\n");
2643 hw->media_type = e1000_media_type_fiber;
2644 } else {
2645 DEBUGOUT("copper interface\n");
2646 hw->media_type = e1000_media_type_copper;
2647 }
2648 } else {
2649 hw->media_type = e1000_media_type_fiber;
2650 }
2651
2652 if (hw->mac_type < e1000_82543)
2653 hw->report_tx_early = 0;
2654 else
2655 hw->report_tx_early = 1;
2656
2657 hw->tbi_compatibility_en = TRUE;
2658#if 0
2659 hw->wait_autoneg_complete = FALSE;
2660 hw->adaptive_ifs = TRUE;
2661
2662 /* Copper options */
2663 if (hw->media_type == e1000_media_type_copper) {
2664 hw->mdix = AUTO_ALL_MODES;
2665 hw->disable_polarity_correction = FALSE;
2666 }
2667#endif
2668 return E1000_SUCCESS;
2669}
2670
2671void
2672fill_rx(struct e1000_hw *hw)
2673{
2674 struct e1000_rx_desc *rd;
2675
2676 rx_last = rx_tail;
2677 rd = rx_base + rx_tail;
2678 rx_tail = (rx_tail + 1) % 8;
2679 memset(rd, 0, 16);
2680 rd->buffer_addr = cpu_to_le64((u32) & packet);
2681 E1000_WRITE_REG(hw, RDT, rx_tail);
2682}
2683
2684/**
2685 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
2686 * @adapter: board private structure
2687 *
2688 * Configure the Tx unit of the MAC after a reset.
2689 **/
2690
2691static void
2692e1000_configure_tx(struct e1000_hw *hw)
2693{
2694 unsigned long ptr;
2695 unsigned long tctl;
2696 unsigned long tipg;
2697
2698 ptr = (u32) tx_pool;
2699 if (ptr & 0xf)
2700 ptr = (ptr + 0x10) & (~0xf);
2701
2702 tx_base = (typeof(tx_base)) ptr;
2703
2704 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
2705 E1000_WRITE_REG(hw, TDBAH, 0);
2706
2707 E1000_WRITE_REG(hw, TDLEN, 128);
2708
2709 /* Setup the HW Tx Head and Tail descriptor pointers */
2710 E1000_WRITE_REG(hw, TDH, 0);
2711 E1000_WRITE_REG(hw, TDT, 0);
2712 tx_tail = 0;
2713
2714 /* Set the default values for the Tx Inter Packet Gap timer */
2715 switch (hw->mac_type) {
2716 case e1000_82542_rev2_0:
2717 case e1000_82542_rev2_1:
2718 tipg = DEFAULT_82542_TIPG_IPGT;
2719 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2720 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2721 break;
2722 default:
2723 if (hw->media_type == e1000_media_type_fiber)
2724 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2725 else
2726 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2727 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2728 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2729 }
2730 E1000_WRITE_REG(hw, TIPG, tipg);
2731#if 0
2732 /* Set the Tx Interrupt Delay register */
2733 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
2734 if (hw->mac_type >= e1000_82540)
2735 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
2736#endif
2737 /* Program the Transmit Control Register */
2738 tctl = E1000_READ_REG(hw, TCTL);
2739 tctl &= ~E1000_TCTL_CT;
2740 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
2741 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2742 E1000_WRITE_REG(hw, TCTL, tctl);
2743
2744 e1000_config_collision_dist(hw);
2745#if 0
2746 /* Setup Transmit Descriptor Settings for this adapter */
2747 adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE;
2748
2749 if (adapter->hw.report_tx_early == 1)
2750 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2751 else
2752 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
2753#endif
2754}
2755
2756/**
2757 * e1000_setup_rctl - configure the receive control register
2758 * @adapter: Board private structure
2759 **/
2760static void
2761e1000_setup_rctl(struct e1000_hw *hw)
2762{
2763 uint32_t rctl;
2764
2765 rctl = E1000_READ_REG(hw, RCTL);
2766
2767 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2768
2769 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* |
2770 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
2771
2772 if (hw->tbi_compatibility_on == 1)
2773 rctl |= E1000_RCTL_SBP;
2774 else
2775 rctl &= ~E1000_RCTL_SBP;
2776
2777 rctl &= ~(E1000_RCTL_SZ_4096);
2778#if 0
2779 switch (adapter->rx_buffer_len) {
2780 case E1000_RXBUFFER_2048:
2781 default:
2782#endif
2783 rctl |= E1000_RCTL_SZ_2048;
2784 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
2785#if 0
2786 break;
2787 case E1000_RXBUFFER_4096:
2788 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2789 break;
2790 case E1000_RXBUFFER_8192:
2791 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2792 break;
2793 case E1000_RXBUFFER_16384:
2794 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2795 break;
2796 }
2797#endif
2798 E1000_WRITE_REG(hw, RCTL, rctl);
2799}
2800
2801/**
2802 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
2803 * @adapter: board private structure
2804 *
2805 * Configure the Rx unit of the MAC after a reset.
2806 **/
2807static void
2808e1000_configure_rx(struct e1000_hw *hw)
2809{
2810 unsigned long ptr;
2811 unsigned long rctl;
2812#if 0
2813 unsigned long rxcsum;
2814#endif
2815 rx_tail = 0;
2816 /* make sure receives are disabled while setting up the descriptors */
2817 rctl = E1000_READ_REG(hw, RCTL);
2818 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
2819#if 0
2820 /* set the Receive Delay Timer Register */
2821
2822 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
2823#endif
2824 if (hw->mac_type >= e1000_82540) {
2825#if 0
2826 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
2827#endif
2828 /* Set the interrupt throttling rate. Value is calculated
2829 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
1aeed8d7
WD		 2830#define MAX_INTS_PER_SEC 8000
2831#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
682011ff
WD		 2832 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
2833 }
2834
2835 /* Setup the Base and Length of the Rx Descriptor Ring */
2836 ptr = (u32) rx_pool;
2837 if (ptr & 0xf)
2838 ptr = (ptr + 0x10) & (~0xf);
2839 rx_base = (typeof(rx_base)) ptr;
2840 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
2841 E1000_WRITE_REG(hw, RDBAH, 0);
2842
2843 E1000_WRITE_REG(hw, RDLEN, 128);
2844
2845 /* Setup the HW Rx Head and Tail Descriptor Pointers */
2846 E1000_WRITE_REG(hw, RDH, 0);
2847 E1000_WRITE_REG(hw, RDT, 0);
2848#if 0
2849 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
2850 if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) {
2851 rxcsum = E1000_READ_REG(hw, RXCSUM);
2852 rxcsum |= E1000_RXCSUM_TUOFL;
2853 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
2854 }
2855#endif
2856 /* Enable Receives */
2857
2858 E1000_WRITE_REG(hw, RCTL, rctl);
2859 fill_rx(hw);
2860}
2861
2862/**************************************************************************
2863POLL - Wait for a frame
2864***************************************************************************/
2865static int
2866e1000_poll(struct eth_device *nic)
2867{
2868 struct e1000_hw *hw = nic->priv;
2869 struct e1000_rx_desc *rd;
2870 /* return true if there's an ethernet packet ready to read */
2871 rd = rx_base + rx_last;
2872 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
2873 return 0;
2874 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
77ddac94 2875 NetReceive((uchar *)packet, le32_to_cpu(rd->length));
682011ff
WD		 2876 fill_rx(hw);
2877 return 1;
2878}
2879
2880/**************************************************************************
2881TRANSMIT - Transmit a frame
2882***************************************************************************/
2883static int
2884e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
2885{
2886 struct e1000_hw *hw = nic->priv;
2887 struct e1000_tx_desc *txp;
2888 int i = 0;
2889
2890 txp = tx_base + tx_tail;
2891 tx_tail = (tx_tail + 1) % 8;
2892
2893 txp->buffer_addr = cpu_to_le64(virt_to_bus(packet));
2894 txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
2895 E1000_TXD_CMD_IFCS | length);
2896 txp->upper.data = 0;
2897 E1000_WRITE_REG(hw, TDT, tx_tail);
2898
2899 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
2900 if (i++ > TOUT_LOOP) {
2901 DEBUGOUT("e1000: tx timeout\n");
2902 return 0;
2903 }
2904 udelay(10); /* give the nic a chance to write to the register */
2905 }
2906 return 1;
2907}
2908
2909/*reset function*/
2910static inline int
2911e1000_reset(struct eth_device *nic)
2912{
2913 struct e1000_hw *hw = nic->priv;
2914
2915 e1000_reset_hw(hw);
2916 if (hw->mac_type >= e1000_82544) {
2917 E1000_WRITE_REG(hw, WUC, 0);
2918 }
2919 return e1000_init_hw(nic);
2920}
2921
2922/**************************************************************************
2923DISABLE - Turn off ethernet interface
2924***************************************************************************/
2925static void
2926e1000_disable(struct eth_device *nic)
2927{
2928 struct e1000_hw *hw = nic->priv;
2929
2930 /* Turn off the ethernet interface */
2931 E1000_WRITE_REG(hw, RCTL, 0);
2932 E1000_WRITE_REG(hw, TCTL, 0);
2933
2934 /* Clear the transmit ring */
2935 E1000_WRITE_REG(hw, TDH, 0);
2936 E1000_WRITE_REG(hw, TDT, 0);
2937
2938 /* Clear the receive ring */
2939 E1000_WRITE_REG(hw, RDH, 0);
2940 E1000_WRITE_REG(hw, RDT, 0);
2941
2942 /* put the card in its initial state */
2943#if 0
2944 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
2945#endif
2946 mdelay(10);
2947
2948}
2949
2950/**************************************************************************
2951INIT - set up ethernet interface(s)
2952***************************************************************************/
2953static int
2954e1000_init(struct eth_device *nic, bd_t * bis)
2955{
2956 struct e1000_hw *hw = nic->priv;
2957 int ret_val = 0;
2958
2959 ret_val = e1000_reset(nic);
2960 if (ret_val < 0) {
2961 if ((ret_val == -E1000_ERR_NOLINK) ||
2962 (ret_val == -E1000_ERR_TIMEOUT)) {
2963 E1000_ERR("Valid Link not detected\n");
2964 } else {
2965 E1000_ERR("Hardware Initialization Failed\n");
2966 }
2967 return 0;
2968 }
2969 e1000_configure_tx(hw);
2970 e1000_setup_rctl(hw);
2971 e1000_configure_rx(hw);
2972 return 1;
2973}
2974
2975/**************************************************************************
2976PROBE - Look for an adapter, this routine's visible to the outside
2977You should omit the last argument struct pci_device * for a non-PCI NIC
2978***************************************************************************/
2979int
2980e1000_initialize(bd_t * bis)
2981{
2982 pci_dev_t devno;
2983 int card_number = 0;
2984 struct eth_device *nic = NULL;
2985 struct e1000_hw *hw = NULL;
2986 u32 iobase;
2987 int idx = 0;
2988 u32 PciCommandWord;
2989
2990 while (1) { /* Find PCI device(s) */
2991 if ((devno = pci_find_devices(supported, idx++)) < 0) {
2992 break;
2993 }
2994
2995 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
2996 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */
2997 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
2998
2999 pci_write_config_dword(devno, PCI_COMMAND,
3000 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3001 /* Check if I/O accesses and Bus Mastering are enabled. */
3002 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
3003 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
3004 printf("Error: Can not enable MEM access.\n");
3005 continue;
3006 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
3007 printf("Error: Can not enable Bus Mastering.\n");
3008 continue;
3009 }
3010
3011 nic = (struct eth_device *) malloc(sizeof (*nic));
3012 hw = (struct e1000_hw *) malloc(sizeof (*hw));
3013 hw->pdev = devno;
3014 nic->priv = hw;
3015 nic->iobase = bus_to_phys(devno, iobase);
3016
3017 sprintf(nic->name, "e1000#%d", card_number);
3018
3019 /* Are these variables needed? */
3020#if 0
3021 hw->fc = e1000_fc_none;
3022 hw->original_fc = e1000_fc_none;
3023#else
3024 hw->fc = e1000_fc_default;
3025 hw->original_fc = e1000_fc_default;
3026#endif
3027 hw->autoneg_failed = 0;
3028 hw->get_link_status = TRUE;
3029 hw->hw_addr = (typeof(hw->hw_addr)) iobase;
3030 hw->mac_type = e1000_undefined;
3031
3032 /* MAC and Phy settings */
3033 if (e1000_sw_init(nic, card_number) < 0) {
3034 free(hw);
3035 free(nic);
3036 return 0;
3037 }
ac3315c2 3038#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
682011ff
WD		 3039 if (e1000_validate_eeprom_checksum(nic) < 0) {
3040 printf("The EEPROM Checksum Is Not Valid\n");
3041 free(hw);
3042 free(nic);
3043 return 0;
3044 }
7521af1c 3045#endif
682011ff
WD		 3046 e1000_read_mac_addr(nic);
3047
3048 E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
3049
3050 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
3051 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
3052 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
3053
3054 nic->init = e1000_init;
3055 nic->recv = e1000_poll;
3056 nic->send = e1000_transmit;
3057 nic->halt = e1000_disable;
3058
3059 eth_register(nic);
3060
3061 card_number++;
3062 }
ad3381cf 3063 return card_number;
682011ff 3064}
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